WO2017143610A1

WO2017143610A1 - Filter tracking circuit, radio frequency front-end module, and communication terminal

Info

Publication number: WO2017143610A1
Application number: PCT/CN2016/074767
Authority: WO
Inventors: 刘荣江; 刘培; 唐样洋
Original assignee: 华为技术有限公司
Priority date: 2016-02-27
Filing date: 2016-02-27
Publication date: 2017-08-31

Abstract

Disclosed in an embodiment of the present invention is a filter tracking circuit, for use in performing filter tracking on a first signal. The filter tracking circuit comprises a multiphase switch capacitor filter and a signal detection and control circuit. The multiphase switch capacitor filter comprises an input end, an output end, and control end. The input end is used for access the first signal. The multiphase switch capacitor filter is used for filtering the first signal to obtain a second signal, and outputting the second signal from the output end. The signal detection and control circuit is electrically connected to the output end and the control end of the multiphase switch capacitor filter, and is used for detecting the strength of the second signal, and controlling the multiphase switch capacitor filter to adjust a filter central frequency and/or a 3dB bandwidth when the strength of the second signal is weaker than a reference signal strength. Also disclosed in the present invention are a radio frequency front-end module and a communication terminal. The filter tracking circuit can flexibly adjust the filter central frequency and the bandwidth.

Description

Tracking filter circuit, RF front-end module and communication terminal

Technical field

The present invention relates to the field of communications technologies, and in particular, to a tracking filter circuit, a radio frequency front end module, and a communication terminal.

Background technique

In the signal receiving process of wireless communication, after the communication terminal receives the signal through the antenna, the received signal is usually filtered to eliminate interference and noise in the signal. There are various wireless communication standards, and each communication standard corresponds to a wireless communication signal having its own characteristics, such as carrier frequency, signal to noise ratio, dynamic range, and linearity. Different wireless communication signals can share a spatial channel. Thus the signal received by the antenna of the communication terminal includes all signals within the frequency range that the antenna can receive. In order to accurately receive wireless communication signals of a specific frequency, a corresponding radio frequency filter needs to be set in the communication terminal. The frequency of the wireless communication signal received by the communication terminal is different, and the filter center frequency of the required RF filter is also different. Especially in the demand of mobile communication, in order to improve the portability and versatility of the communication terminal, it is generally desired that the communication terminal of the same model can be compatible with different communication standards and receive wireless communication signals of different frequency bands.

At present, in a communication terminal such as a mobile phone or a tablet computer, a corresponding radio frequency filter is usually provided for each communication frequency to implement filtering of radio frequency signals compatible with different communication standards. When a communication standard is adopted, the corresponding RF filter is connected to the receiving signal path through the strobe switch. This implementation not only takes up too much area, but also has complex control switches. Another implementation adopts the RF filter with feedback as the principle, but the filtering process will introduce nonlinear interference of the circuit itself, especially when the interference signal is relatively strong, the filter circuit will be saturated and cannot work normally, and the filtering effect is not ideal. In addition, in terms of filter implementation, filtering is currently mainly based on the parallel resonance of the inductor and the capacitor. This implementation has a tradeoff between the filter center frequency bandwidth and the filter quality factor and the complexity of the filter circuit. The change in the filter center frequency is by changing the size of the inductor or capacitor, but the wider center filter frequency span requires a wider range of inductance or capacitance. Due to the parasitic resistance of the inductor and capacitor, excessive capacitance inductance leads to a drop in the filter quality factor. In order to improve the filter The quality factor often uses high-order filters, but the use of higher-order filters will undoubtedly increase circuit complexity.

Summary of the invention

The embodiment of the invention provides a tracking filter circuit, an RF front-end module and a communication terminal, so as to solve the problem that the RF filter circuit in the prior art is too complicated, and the filtering center frequency and the filter bandwidth are inconveniently adjusted, and the RF filter does not need to be changed. The hardware structure of the circuit can easily change the filter center frequency and filter bandwidth, thereby improving the compatibility and flexibility of the RF filter circuit.

A first aspect of the present invention provides a tracking filter circuit for performing tracking filtering on a first signal, where the tracking filter circuit includes a multi-phase switched capacitor filter and a signal detecting and controlling circuit;

The multi-phase switched capacitor filter includes an input end, an output end, and a control end, wherein the input end is configured to input the first signal, and the polyphase switched capacitor filter is configured to filter the first signal to obtain a second signal, and outputting the second signal from the output terminal;

The signal detection and control circuit is electrically connected to the output end and the control end of the multi-phase switched capacitor filter for detecting the intensity of the second signal, and the intensity of the second signal is less than a preset reference At the signal strength, the multiphase switched capacitor filter is controlled to adjust the filter center frequency and/or the 3 dB bandwidth.

The tracking filter circuit provided by the first aspect of the present invention filters the first signal by the polyphase switched capacitor filter to obtain the second signal, and detects the first by the signal detection and control circuit. The strength of the two signals, which in turn compares the intensity of the second signal with a preset reference signal strength, and controls the adjustment of the polyphase switched capacitor filter when the strength of the second signal is less than a preset reference signal strength Filtering the center frequency and/or the 3dB bandwidth to form a closed-loop tracking filter structure, implementing tracking filtering of the first signal without changing the hardware structure of the tracking filter circuit, only by changing the signal detection and control The control signal of the circuit can realize the control of the filtering center frequency and/or the 3dB bandwidth of the multi-phase switched capacitor filter, so that the same set of hardware devices can be compatible with different communication standards, and the RF front-end filter can be effectively reduced. The occupied area in the communication terminal.

With reference to the first aspect, in a first possible implementation manner of the first aspect, the multi-phase switched capacitor filter includes N switches and N capacitors; one ends of the N switches are electrically connected to each other; The other end of the switch is electrically connected to one end of one of the capacitors, and the other of the N capacitors End grounded; where N is an integer greater than zero.

With reference to the first possible implementation manner of the first aspect, in a second possible implementation manner of the first aspect, the signal detection and control circuit includes a signal strength detecting circuit, a comparator, and a logic control circuit that are electrically connected in sequence And a multi-phase signal generating circuit;

The signal strength detecting circuit is electrically connected to the output end of the multi-phase switched capacitor filter for detecting the intensity of the second signal, and outputting the intensity of the second signal to the comparator;

The comparator is configured to compare the intensity of the second signal with the preset reference signal strength, and output a first logic control signal to the station when the strength of the second signal is less than the preset reference signal strength Logic control circuit

The logic control circuit is configured to generate a polyphase characteristic control signal under the control of the first logic control signal, and output the multiphase characteristic control signal to the multiphase signal generation circuit;

The multi-phase signal generating circuit is electrically connected to a control end of the multi-phase switched capacitor filter, and configured to generate a multi-phase clock signal according to the multi-phase characteristic control signal, where the multi-phase clock signal is used to control the The polyphase switched capacitor filter adjusts the filter center frequency and/or 3dB bandwidth.

With reference to the second possible implementation manner of the first aspect, in a third possible implementation manner of the first aspect, the multi-phase signal generating circuit is configured to: preset the frequency to Fs according to the multi-phase characteristic control signal The source signal is subjected to L frequency division processing to obtain a clock signal with a clock period of L/Fs and a frequency of Fs/L, and the clock period L/Fs is equally divided into M sub-cycles to obtain M-phase clocks that do not overlap each other. a signal, the M-phase clock signal is used to control the M switches of the multi-phase switched capacitor filter to be turned on in turn; wherein L is an integer greater than zero, and M is an integer greater than zero and less than or equal to N.

In a third possible implementation manner of the first aspect, the source signal is subjected to L frequency division processing by the multi-phase signal generating circuit to obtain the clock signal, and therefore, the frequency of the source signal is constant. In this case, the frequency and clock period of the clock signal can be easily changed by simply changing the frequency division number L. At the same time, the M-phase clock signal that does not overlap with each other is obtained by performing M-halving processing on the clock cycle of the clock signal, so as to control the M switches to be turned on sequentially, and therefore, by changing the equal fraction M The number of conduction switches in the multi-phase switched capacitor filter can be conveniently controlled. The multi-phase switched capacitor filter can be controlled to change the filter center frequency by changing the frequency of the clock signal without changing the hardware structure of the tracking filter circuit, by changing the multi-phase switched capacitor filter The filter bandwidth of the multi-phase switched capacitor filter can be controlled by the number of switches.

With reference to the third possible implementation manner of the first aspect, in a fourth possible implementation manner of the first aspect, the logic control circuit includes a first control mode and a second control mode; in the first control mode The logic control circuit generates the multi-phase characteristic control signal according to a preset center frequency of the second signal; in the second control mode, the logic control circuit generates a Multiphase characteristic control signals are described.

With reference to the fourth possible implementation manner of the first aspect, in a fifth possible implementation manner of the first aspect, in the first control mode, the logic control circuit stores a center of the second signal a frequency, a bandwidth, and a frequency of the source signal, the logic control circuit generating the polyphase characteristic control signal according to a center frequency, a bandwidth of the second signal, and a frequency of the source signal, thereby passing the multiphase The characteristic control signal controls the multi-phase signal generating circuit to divide the source signal into L, obtain a clock signal having a frequency equal to a center frequency of the second signal, and divide the clock period of the clock signal into M sub- Cycles, obtaining M-phase clock signals that do not overlap each other, and controlling the multi-phase switched capacitor filter to adjust the filter center frequency and bandwidth by the M-phase clock signal.

In the case that the center frequency and the bandwidth of the second signal are known, if the strength of the second signal is less than the preset reference signal strength, the logic may be directly passed by the logic control circuit according to the second signal. The center frequency, the bandwidth, and the frequency of the source signal generate the polyphase characteristic control signal, thereby controlling the multi-phase switched capacitor filter to adjust the filter center frequency and bandwidth.

With reference to the fourth possible implementation manner of the first aspect, in a sixth possible implementation manner of the first aspect, the logic control circuit stores a center frequency of the second signal and a frequency of the source signal, The logic control circuit generates the polyphase characteristic control signal according to a center frequency of the second signal, and further controls the multiphase signal generating circuit to generate a frequency equal to a center of the second signal by using the polyphase characteristic control signal A clock signal of a frequency, and clock cycles of the clock signal are sequentially divided into 1 to M to obtain 1-to M-phase clock signals that do not overlap each other.

If the center frequency of the second signal is known, but the bandwidth of the second signal is unknown, if the filter bandwidth of the polyphase switched capacitor filter is improperly set, the second signal may be caused The intensity is less than the preset reference signal strength. Therefore, by fixing the filter center frequency of the multi-phase switched capacitor filter, the clock cycle of the clock signal is sequentially divided by 1 to M, that is, sequentially changing Decoding the filtering bandwidth of the polyphase switched capacitor filter until the intensity of the second signal is greater than or equal to the preset reference signal strength, thereby being determined by using a bandwidth scan The filtering bandwidth of the polyphase switched capacitor filter.

With reference to the fourth possible implementation manner of the first aspect, in a seventh possible implementation manner of the first aspect, in the second control mode, the logic control circuit controls the device by using the multi-phase characteristic control signal The multiphase signal generating circuit sequentially generates K groups of clock signals of different frequencies, and sequentially divides the clock cycles of each group of clock signals into M equal parts to obtain K groups of M phase clock signals without overlapping each other; wherein K is greater than An integer of zero.

When the center frequency and the bandwidth of the second signal are unknown, the K-group clock signals of different frequencies are sequentially generated by controlling the multi-phase signal generating circuit, and then the clock cycles of each group of clock signals are sequentially M-divided. Obtaining K groups of M-phase clock signals that do not overlap each other, and sequentially controlling the multi-phase switched capacitor filter to change the filter center frequency by the K-group non-overlapping M-phase clock signals, thereby achieving the fixing of the plurality of In the case where the filter bandwidth of the phase-switched capacitor filter is constant, the multi-phase switched capacitor filter is determined to change the filter center frequency by means of frequency scanning.

In conjunction with the fourth possible implementation of the first aspect, in an eighth possible implementation manner of the first aspect, in the second control mode, the logic control circuit controls the device by using the multi-phase characteristic control signal The multi-phase signal generating circuit sequentially generates K groups of clock signals of different frequencies, and sequentially divides the clock cycles of each group of clock signals by 1 to M, to obtain K-groups of non-overlapping 1-to-M-phase clock signals; , K is an integer greater than zero.

When the center frequency and the bandwidth of the second signal are unknown, the filter center frequency of the multi-phase switched capacitor filter is gradually changed by sequentially generating K groups of clock signals of different frequencies, and the clock of each group of frequencies is passed. The signal is sequentially divided into 1 to M, and the filtering bandwidth of the polyphase switched capacitor filter is gradually changed, thereby determining the filtering center frequency and bandwidth of the polyphase switched capacitor filter by means of frequency scanning and bandwidth scanning.

The third possible implementation manner of the first aspect, the fourth possible implementation manner of the first aspect, the fifth possible implementation manner of the first aspect, the sixth possible implementation manner of the first aspect, and the seventh aspect of the first aspect A possible implementation manner, or an eighth possible implementation manner of the first aspect, in the ninth possible implementation manner of the first aspect, in the clock period, each of the switches is only turned on once, and each The on-time of one of the switches is L/(Fs*M); at any one time, only one of the M switches is in an on state.

Combining the third possible implementation manner of the first aspect, the fourth possible implementation manner of the first aspect, The fifth possible implementation manner of the first aspect, the sixth possible implementation manner of the first aspect, the seventh possible implementation manner of the first aspect, the eighth possible implementation manner of the first aspect, or the ninth aspect of the first aspect In a tenth possible implementation manner of the first aspect, the filter center frequency of the transfer function of the polyphase switched capacitor filter is equal to the frequency Fs/L of the clock signal; the multiphase switch The 3 dB bandwidth of the capacitive filter is inversely proportional to the number M of switches that are sequentially turned on in the multi-phase switched capacitor filter.

The second possible implementation manner of the first aspect, the third possible implementation manner of the first aspect, the fourth possible implementation manner of the first aspect, the fifth possible implementation manner of the first aspect, and the sixth aspect of the first aspect Possible implementation manners, the seventh possible implementation manner of the first aspect, the eighth possible implementation manner of the first aspect, the ninth possible implementation manner of the first aspect, or the tenth possible implementation manner of the first aspect, In an eleventh possible implementation manner of the first aspect, when the strength of the second signal is greater than or equal to the preset reference signal strength, the comparator outputs a second logic control signal, where the logic control The circuit keeps the output unchanged under the control of the second logic control signal, the multi-phase signal generating circuit keeps the output unchanged under the control of the logic control circuit, and the multi-phase switched capacitor filter is in the The phase of the filter signal is kept constant under the control of the phase signal generating circuit.

The second possible implementation manner of the first aspect, the third possible implementation manner of the first aspect, the fourth possible implementation manner of the first aspect, the fifth possible implementation manner of the first aspect, and the sixth aspect of the first aspect Possible implementation manners, the seventh possible implementation manner of the first aspect, the eighth possible implementation manner of the first aspect, the ninth possible implementation manner of the first aspect, the tenth possible implementation manner of the first aspect or The eleventh possible implementation manner of the first aspect, in the twelfth possible implementation manner of the first aspect, the tracking filter circuit further includes a low noise amplifier, a down converter, and an intermediate frequency filter that are electrically connected in sequence The low noise amplifier is further electrically connected to an output end of the polyphase switched capacitor filter, an input end of the signal strength detecting circuit and an output end of the polyphase switched capacitor filter, or the low noise The output of the amplifier, or the output of the downconverter or the output of the intermediate frequency filter is electrically connected.

In conjunction with the twelfth possible implementation manner of the first aspect, in the thirteenth possible implementation manner of the first aspect, the signal detection and control circuit further includes a pre-filter circuit and a preamplifier electrically connected in sequence a circuit, an input of the pre-filter circuit and an output of the polyphase switched capacitor filter, or an output of the low noise amplifier, or an output of the downconverter or the intermediate frequency filter The output end of the preamplifier circuit is electrically connected to the input end of the signal strength detecting circuit.

A second aspect of the present invention provides a radio frequency front end module, the radio frequency front end module including the first aspect of the present invention, the first possible implementation manner of the first aspect, the second possible implementation manner of the first aspect, and the first aspect A third possible implementation manner, a fourth possible implementation manner of the first aspect, a fifth possible implementation manner of the first aspect, a sixth possible implementation manner of the first aspect, and a seventh possible implementation of the first aspect The first possible implementation manner of the first aspect, the ninth possible implementation manner of the first aspect, the tenth possible implementation manner of the first aspect, the eleventh possible implementation manner of the first aspect, and the first aspect A twelfth possible implementation or a tracking filter circuit as described in the thirteenth possible implementation of the first aspect.

The tracking filter circuit controls the multi-phase switched capacitor filter to adjust the filter center frequency and bandwidth by setting the multi-phase switched capacitor filter and changing the frequency and phase number of the multi-phase clock signal, and using the same set of hardware devices It can be compatible with different communication standards, and can effectively reduce the occupied area of the radio frequency front-end module in the communication terminal.

A third aspect of the present invention provides a communication terminal, including a radio frequency front end module, the radio frequency front end module including the first aspect of the present invention, the first possible implementation manner of the first aspect, and the second possible implementation manner of the first aspect The third possible implementation manner of the first aspect, the fourth possible implementation manner of the first aspect, the fifth possible implementation manner of the first aspect, the sixth possible implementation manner of the first aspect, and the seventh aspect of the first aspect Possible implementation manners, the eighth possible implementation manner of the first aspect, the ninth possible implementation manner of the first aspect, the tenth possible implementation manner of the first aspect, and the eleventh possible implementation manner of the first aspect The tracking filter circuit of the twelfth possible implementation of the first aspect or the thirteenth possible implementation of the first aspect.

The tracking filter circuit controls the multi-phase switched capacitor filter to adjust the filter center frequency and bandwidth by setting the multi-phase switched capacitor filter and changing the frequency and phase number of the multi-phase clock signal, and using the same set of hardware devices It can be compatible with different communication standards, and can effectively reduce the occupied area of the radio frequency front-end module in the communication terminal, thereby facilitating the reduction of the volume and thickness of the communication terminal, and meeting the ultra-thin development requirements of the communication terminal.

DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly described below.

1 is a schematic structural diagram of a communication terminal according to an embodiment of the present invention;

2 is a schematic structural view of the multi-phase switched capacitor filter shown in FIG. 1;

3 is a schematic structural view of the signal detecting and controlling circuit shown in FIG. 1;

4 is a timing diagram of a multi-phase clock signal generated by the multi-phase signal generating circuit shown in FIG. 3;

5 is a waveform diagram of a frequency domain transfer function of the multi-phase switched capacitor filter shown in FIG. 2;

6 is a schematic structural diagram of a tracking filter circuit according to another embodiment of the present invention;

FIG. 7 is a schematic structural diagram of a signal detection and control circuit according to another embodiment of the present invention.

detailed description

The technical solutions in the embodiments of the present invention will be described below with reference to the accompanying drawings in the embodiments of the present invention.

Referring to FIG. 1, in one embodiment of the present invention, a communication terminal 100 is provided, including an antenna 10, a tracking filter circuit 30, a baseband chip 50, a memory 70, and a user interface 90. The antenna 10 is electrically connected to the baseband chip 50 through the tracking filter circuit 30. The baseband chip 50 is also electrically connected to the memory 70 and the user interface 90. The memory 70 is used to store an operating system, a communication interface program, user data, and the like. The user interface 90 is used to establish an electrical connection relationship between the baseband chip 50 and the receiver 91, the microphone 93, and the touch screen 95. The antenna 10 is configured to receive a first signal Vin. The tracking filter circuit 30 is configured to perform tracking filtering processing on the first signal Vin to obtain a second signal Vout. The second signal Vout is processed by the baseband chip 50 and fed back to the user of the communication terminal 100 through the user interface 90. For example, when the second signal Vout is a voice baseband signal, the baseband chip 50 is configured to restore the voice baseband signal to an analog voice signal, and transmit the signal to the receiver 91 through the user interface 90, thereby passing The receiver 91 plays the analog voice signal. In this embodiment, the communication terminal 100 can be a mobile phone, a tablet computer, or the like.

The tracking filter circuit 30 includes a polyphase switched capacitor filter 31 and a signal detecting and controlling circuit 33. The polyphase switched capacitor filter 31 includes an input terminal 311, an output terminal 313, and a control terminal 315. The input terminal 311 is configured to input the first signal Vin, and the polyphase switched capacitor filter 31 is configured to filter the first signal Vin to obtain a second signal Vout, and output from the output terminal 313. The second signal Vout; the signal detecting and controlling circuit 33 is electrically connected to the output end 313 and the control end 315 of the polyphase switched capacitor filter 31 for detecting the intensity of the second signal Vout, and When the intensity of the second signal Vout is less than the preset reference signal strength Vref, the multi-phase clock signal Vc is outputted to the control terminal 315 to control the multi-phase switched capacitor filter 31 by the multi-phase clock signal Vc. Adjust the filter center frequency and / or 3dB bandwidth.

The first signal may be a radio frequency signal of any frequency in the working frequency band of the antenna 10. It can be understood that in a communication terminal such as a mobile phone or a tablet computer, the working frequency band of the antenna 10 can generally cover a communication frequency band corresponding to multiple communication standards. Therefore, the first signal may include radio frequency signals of a plurality of frequency bands; meanwhile, interference and noise signals may be included in the first signal due to interference and noise that may exist in the communication channel. In view of this, in order to accurately receive the target signal of the specific frequency, the first signal received by the antenna 10 needs to be filtered to replace the other signals included in the first signal except the target signal. The signal is filtered out to obtain the target signal. In this embodiment, the second signal is the target signal of a specific frequency.

Referring to FIG. 2, the multi-phase switched capacitor filter 31 includes N switches S and N capacitors C, and the N switches S are labeled as S1, S2, ..., SN, respectively, and N of the capacitors C are respectively labeled. One ends of the switches S are electrically connected to each other; the other end of each of the switches S is electrically connected to one end of the capacitor C, and the N capacitors C are The other end is grounded. Specifically, one end of the N switches S are electrically connected to the input end 311 and the output end 313; the other end of the switch S1 is electrically connected to one end of the capacitor C1, and the capacitor C1 The other end of the switch S2 is electrically connected to one end of the capacitor C2, and the other end of the capacitor C2 is grounded; and so on, until the other end of the switch SN and one end of the capacitor CN Electrically connected, the other end of the capacitor CN is grounded. The capacitance values of the N capacitors C are the same. Where N is an integer greater than zero. For example, the value of N may be 4, 8, 16, or the like.

Referring to FIG. 3, the signal detection and control circuit 33 includes a signal strength detecting circuit 331, a comparator 333, a logic control circuit 335, and a polyphase signal generating circuit 337 which are electrically connected in sequence. The signal strength detecting circuit 331 is electrically connected to the output end 313 of the polyphase switched capacitor filter 31 for detecting the intensity of the second signal, and outputting the intensity of the second signal to the comparison. 333. The comparator 333 is configured to compare the strength of the second signal with the preset reference signal strength Vref, and output the first logic when the strength of the second signal is less than the preset reference signal strength Vref A control signal is applied to the logic control circuit 335. The logic control circuit 335 is configured to generate a polyphase characteristic control signal under the control of the first logic control signal, and output the polyphase characteristic control signal to the multi-phase signal generation circuit 337. The multi-phase signal generating circuit 337 is electrically connected to the control end 315 of the multi-phase switched capacitor filter 31 for generating a multi-phase clock signal according to the multi-phase characteristic control signal, and the multi-phase clock signal is used for The polyphase switched capacitor filter 31 is controlled to adjust the filter center frequency and/or the 3 dB bandwidth.

Specifically, the reference signal strength Vref may be provided by the baseband chip 50, and the comparator 333 compares the intensity of the second signal with the reference signal strength Vref, and outputs a high level or a low according to the comparison result. The first logic control signal of the level. For example, the comparator 333 may output the first logic control signal of a high level when the intensity of the second signal is greater than or equal to the reference signal strength Vref, and the intensity of the second signal is less than When the reference signal strength Vref is described, a second logic control signal of a low level is output; or the comparator 333 may output a low level when the intensity of the second signal is greater than or equal to the reference signal strength Vref The first logic control signal is described, and when the intensity of the second signal is less than the reference signal strength Vref, a second logic control signal of a high level is output.

The logic control circuit 335 may store a center frequency and a bandwidth of the target signal. When the comparator 333 outputs the first logic control signal, the logic control circuit 335 is configured according to a center frequency of the target signal. A polyphase characteristic control signal corresponding to the bandwidth generation. The multi-phase signal generating circuit 337 is configured to perform frequency division processing on the source signal of the preset frequency Fs according to the multi-phase characteristic control signal to obtain a clock with a clock period T=L/Fs and a frequency F=Fs/L. The signal is divided into M sub-cycles by dividing the clock period T=L/Fs to obtain M-phase clock signals that do not overlap each other, as shown in FIG. 4 . The M-phase clock signal is used to control the M switches of the multi-phase switched capacitor filter to be turned on in sequence. Where L is an integer greater than zero, and M is an integer greater than zero and less than or equal to N. For example, the value of M may be 4, 8, 16, or the like. It can be understood that during the clock cycle, each of the switches is only turned on once, and the on-time of each of the switches is T/M=L/(Fs*M) seconds; at any one moment, M Only one of the switches is in an on state. It can be understood that the source signal with the preset frequency Fs can be provided by the baseband chip 50, and the logic control circuit 335 can also be saved. The frequency Fs of the source signal is stored.

Specifically, the filter center frequency of the multi-phase switched capacitor filter 31 is equal to the frequency F of the clock signal; wherein the waveform of the frequency domain transfer function of the polyphase switched capacitor filter 31 is as shown in FIG. 5, F =Fs/L is the filter center frequency of the polyphase switched capacitor filter 31. The 3 dB bandwidth of the multi-phase switched capacitor filter 31 is inversely proportional to the number M of switches that are sequentially turned on in the multi-phase switched capacitor filter 31. Therefore, by changing the frequency F of the clock signal, the filter center frequency of the multi-phase switched capacitor filter 31 can be adjusted; by changing the number of switches M that are sequentially turned on in the multi-phase switched capacitor filter 31 The 3dB bandwidth of the polyphase switched capacitor filter 31 can be adjusted.

For example, assuming that the frequency Fs of the source signal is 1 GHz and the center frequency of the target signal is 500 MHz, when the filter center frequency of the polyphase switched capacitor filter 31 deviates from 500 MHz, the first signal solution The intensity of the second signal obtained by filtering the multi-phase switched capacitor filter 31 is less than the preset reference signal strength Vref, and the comparator 333 outputs the first logic control signal according to the comparison result, and passes The first logic control signal triggers the logic control circuit 335 to generate a corresponding polyphase characteristic control signal according to a center frequency of the target signal of 500 MHz and a bandwidth, and further controls the generation of the multiphase signal by the multiphase characteristic control signal. The circuit 337 divides the source signal by 2 to obtain a clock signal with a clock period of T=1/500 seconds and a frequency F=500 MHz, and divides the clock period T of the clock signal into M sub-cycles to obtain mutual And overlapping the M-phase clock signals, and then controlling the M switches in the multi-phase switched capacitor filter 31 to be sequentially turned on by the M-phase clock signal, thereby implementing the first letter 500MHz filtering to obtain a second signal, i.e. the target signal. Wherein, the on time of each of the switches is equal to the duration of the sub-cycle, ie T/M seconds. It can be understood that the polyphase characteristic control signal may include a frequency division number L determined according to a center frequency of the second signal and/or an equal fraction M determined according to a bandwidth of the second signal.

In the embodiment, the logic control circuit 335 includes a first control mode and a second control mode. In the first control mode, the logic control circuit 335 generates the polyphase characteristic control signal according to a preset center frequency of the second signal. In the second control mode, the logic control circuit generates the polyphase characteristic control signal according to a preset frequency scanning rule.

Specifically, under the first control mode, if the center frequency and bandwidth of the second signal are known, That is, the logic control circuit 335 stores the center frequency and bandwidth of the second signal and the frequency of the source signal, and then the logic control circuit 335 according to the center frequency and bandwidth of the second signal and the source. The frequency Fs of the signal is generated to generate the polyphase characteristic control signal. The multi-phase characteristic control signal includes a frequency division number L and an equal fraction M. Controlling, by the polyphase characteristic control signal, the multiphase signal generating circuit 337 to divide the source signal into L, obtaining a clock signal having a frequency equal to a center frequency of the second signal, and clocking the clock signal The period is equally divided into M sub-cycles to obtain M-phase clock signals that do not overlap each other, and the multi-phase switched capacitor filter 31 is controlled by the M-phase clock signal to adjust the filter center frequency and bandwidth.

In the first control mode, if the center frequency of the second signal is known, but the bandwidth of the second signal is unknown, that is, the center frequency of the second signal is stored in the logic control circuit 335 And the frequency of the source signal, without storing the bandwidth of the second signal, the logic control circuit 335 generates the polyphase characteristic control signal according to a center frequency of the second signal. The multi-phase characteristic control signal includes a frequency division number L. Controlling, by the polyphase characteristic control signal, the multiphase signal generating circuit 337 to divide the source signal into L to obtain a clock signal having a frequency equal to a center frequency of the second signal, and clock cycle of the clock signal The 1 to M aliquots are sequentially performed to obtain 1- to M-phase clock signals that do not overlap each other. That is, the filter center frequency of the multi-phase switched capacitor filter 31 is fixed, and the filter bandwidth of the multi-phase switched capacitor filter 31 is sequentially changed by sequentially dividing the clock period of the clock signal by 1 to M. Until the intensity of the second signal is greater than or equal to the preset reference signal strength Vref.

In the second control mode, the logic control circuit 335 controls the multi-phase signal generation circuit to sequentially generate K groups of clock signals of different frequencies through the multi-phase characteristic control signal, and clock signals of each group of frequencies M is equally divided to obtain K-phase clock signals in which K groups do not overlap each other; wherein K is an integer greater than zero. That is, the filter bandwidth of the multi-phase switched capacitor filter 31 is fixed, and the filter center frequency of the multi-phase switched capacitor filter 31 is gradually changed until the second signal is gradually generated by sequentially generating K sets of clock signals of different frequencies. The intensity is greater than or equal to the preset reference signal strength Vref.

Alternatively, in the second control mode, the logic control circuit 335 controls the multi-phase signal generation circuit to sequentially generate K groups of clock signals of different frequencies through the multi-phase characteristic control signal, and each group of frequencies The clock signal is sequentially divided into 1 to M, and the K groups are not overlapped with each other to 1 M-phase clock signal; where K is an integer greater than zero. That is, by sequentially generating K groups of clock signals of different frequencies, the filter center frequency of the polyphase switched capacitor filter 31 is gradually changed, and the clock signal of each group of frequencies is sequentially divided by 1 to M, and the said The filtering bandwidth of the polyphase switched capacitor filter 31 is until the intensity of the second signal is greater than or equal to the preset reference signal strength Vref.

It can be understood that when the strength of the second signal is greater than or equal to the preset reference signal strength, the comparator 333 outputs a second logic control signal, and the logic control circuit 335 is at the second logic control signal. The output is kept unchanged under control, the multi-phase signal generating circuit 337 keeps the output unchanged under the control of the logic control circuit, and the polyphase switched capacitor filter 31 is under the control of the multi-phase signal generating circuit 337 Keep the filter center frequency and bandwidth constant.

Referring to FIG. 6, in another embodiment of the present invention, the tracking filter circuit 30 further includes a low noise amplifier 35, a down converter 37, and an intermediate frequency filter 39, which are electrically connected in sequence, and the low noise amplifier 35 is also An output end 313 of the multi-phase switched capacitor filter 31 is electrically connected, and an input end of the signal strength detecting circuit 331 can be connected to an output end of the polyphase switched capacitor filter 31 or the low noise amplifier 35 The output, or the output of the down converter 37 or the output of the intermediate frequency filter 39 is electrically connected. Wherein F _LO is the local oscillator frequency of the down converter 37. After the first signal Vin is filtered by the polyphase switched capacitor filter 31, the signal V1 is output, and the signal V1 enters the low noise amplifier 35 to amplify the output signal V2, and the signal V2 is down-converted. The signal 37 is mixed with the local oscillator frequency F _LO to obtain a signal V3. The signal V3 is further subjected to intermediate frequency filtering processing by the intermediate frequency filter 39 to obtain a second signal Vout.

It can be understood that, in a specific implementation, the processing manners such as amplification, filtering, and mixing may be combined according to the needs of signal adjustment. Therefore, the specific structure of the tracking filter circuit 30 may be different from that shown in FIG. 6, for example, as shown in FIG. The noise amplifier 35, the down converter 37, and the intermediate frequency filter 39 may have only one or a plurality of parallels. The electrical connection position of the input end of the signal detecting and controlling circuit 33 shown in FIG. 6 (ie, the input end of the signal strength detecting circuit 331) is not limited to the intermediate frequency filter 39, and may be located at the The output of the phase switched capacitor filter 31 is 313 or the output of any module located after the output 313. For example, the input of the signal strength detecting circuit 331 can be electrically connected to the output of the low noise amplifier 35 or the output of the down converter 37. In addition, the second signal Vout detected by the signal detection and control circuit 33 can also The input or output signals of other circuit modules are not shown in FIG. 6, such as the output signal of the variable gain amplifier, or may be a digital baseband signal.

Referring to FIG. 7, in another embodiment of the present invention, the signal detecting and controlling circuit 33 further includes a pre-filtering circuit 3301 and a preamplifying circuit 3302 which are electrically connected in sequence, and the input of the pre-filtering circuit 3301 The terminal is electrically connected to the output of the polyphase switched capacitor filter 31, or the output of the low noise amplifier 35, or the output of the down converter 37 or the output of the intermediate frequency filter 39. An output end of the preamplifier circuit 3302 is electrically connected to an input end of the signal strength detecting circuit 331. The pre-filtering circuit 3301 and the pre-amplifying circuit 3302 are configured to further filter and amplify the second signal Vout to improve the accuracy of the intensity detection. It can be understood that, in all embodiments of the present invention, one circuit, module, component or port is electrically connected to another circuit, module, component or port, and may be a direct connection or an indirect connection, wherein the indirect connection It means that there may be other circuits, modules, components or ports between two circuits, modules, components or ports connected to each other.

It can be understood that before the tracking filtering process is performed on the first signal by using the tracking filter circuit 30, it is necessary to perform initial setting on each module of the tracking filter circuit 30. For example, an initial filter center frequency and bandwidth of the polyphase switched capacitor filter 31, a gain of the low noise amplifier 35, a gain of the down converter 37, and a local oscillator frequency, and filtering of the intermediate frequency filter 39 are set. The center frequency and bandwidth, the preset reference signal strength Vref, the control mode of the logic control circuit 335, and the frequency Fs of the source signal, and the like.

In an embodiment of the present invention, a radio frequency front end module is further provided. The radio frequency front end module includes the tracking filter circuit 30 according to the embodiment of the present invention. For the specific function and structure of the tracking filter circuit 30, please refer to FIG. The related description in the embodiment of FIG. 7 will not be repeated here.

The tracking filter circuit 30 described in the embodiment of the present invention controls the multi-phase switched capacitor filter 31 to adjust the filter center by setting the multi-phase switched capacitor filter 31 and changing the frequency and phase number of the multi-phase clock signal. Frequency and bandwidth can be compatible with different communication standards by using the same set of hardware devices, which can effectively reduce the occupied area of the RF front-end module in the communication terminal. At the same time, since the filter center frequency of the multi-phase switched capacitor filter 31 is independent of the filter hardware parameters, the multi-phase clock signal is continuously adjusted without changing the hardware parameters of the multi-phase switched capacitor filter 31 itself. The frequency of the filter can be continuously controlled by the filter center frequency, which can not only filter the specific frequency signal. Processing, it is also possible to achieve continuous scanning of the filter center frequency by continuously changing the frequency of the multi-phase clock signal. In addition, since the tracking filter circuit 30 determines whether the desired filtering effect is achieved by detecting the intensity of the filtered second signal, and the intensity of the second signal is less than the preset reference signal strength The Vref controls the multi-phase switched capacitor filter 31 to adjust the filter center frequency and bandwidth, and forms a closed-loop tracking filter structure as a whole, which can realize dynamic tracking detection and filtering of the received signal, and has better dynamics. Track performance.

The above is only the preferred embodiment of the present invention, and the scope of the present invention is not limited thereto, and those skilled in the art can understand all or part of the process of implementing the above embodiments, and according to the claims of the present invention. Equivalent changes made are still within the scope of the invention.

Claims

A tracking filter circuit for performing tracking filtering on a first signal, wherein the tracking filter circuit comprises a multi-phase switched capacitor filter and a signal detection and control circuit;

The multi-phase switched capacitor filter includes an input end, an output end, and a control end, wherein the input end is configured to input the first signal, and the polyphase switched capacitor filter is configured to filter the first signal to obtain a second signal, and outputting the second signal from the output terminal;

The signal detection and control circuit is electrically connected to the output end and the control end of the multi-phase switched capacitor filter for detecting the intensity of the second signal, and the intensity of the second signal is less than a preset reference At the signal strength, the multiphase switched capacitor filter is controlled to adjust the filter center frequency and/or the 3 dB bandwidth.
The tracking filter circuit according to claim 1, wherein said multi-phase switched capacitor filter comprises N switches and N capacitors; one ends of said N switches are electrically connected to each other; The other end is electrically connected to one end of one of the capacitors, and the other end of the N capacitors is grounded; wherein N is an integer greater than zero.
The tracking filter circuit according to claim 2, wherein the signal detecting and controlling circuit comprises a signal strength detecting circuit, a comparator, a logic control circuit and a multi-phase signal generating circuit which are electrically connected in sequence;

The signal strength detecting circuit is electrically connected to the output end of the multi-phase switched capacitor filter for detecting the intensity of the second signal, and outputting the intensity of the second signal to the comparator;

The comparator is configured to compare the intensity of the second signal with the preset reference signal strength, and output a first logic control signal to the station when the strength of the second signal is less than the preset reference signal strength Logic control circuit

The logic control circuit is configured to generate a polyphase characteristic control signal under the control of the first logic control signal, and output the multiphase characteristic control signal to the multiphase signal generation circuit;

The multi-phase signal generating circuit is electrically connected to the control end of the multi-phase switched capacitor filter for generating a multi-phase clock signal according to the multi-phase characteristic control signal, and the multi-phase clock signal is used for controlling The polyphase switched capacitor filter adjusts the filter center frequency and/or the 3 dB bandwidth.
The tracking filter circuit according to claim 3, wherein the polyphase signal generating circuit is configured to perform a frequency division process on the source signal of the preset frequency Fs according to the multiphase characteristic control signal to obtain a clock cycle. It is a clock signal of L/Fs and frequency Fs/L, and divides the clock period L/Fs into M sub-periods to obtain M-phase clock signals that do not overlap each other, and the M-phase clock signals are used for control. The M switches of the multi-phase switched capacitor filter are sequentially turned on; wherein L is an integer greater than zero, and M is an integer greater than zero and less than or equal to N.
The tracking filter circuit according to claim 4, wherein said logic control circuit comprises a first control mode and a second control mode; and in said first control mode, said logic control circuit is based on a preset The multi-phase characteristic control signal is generated by the center frequency of the second signal; in the second control mode, the logic control circuit generates the multi-phase characteristic control signal according to a preset frequency scanning rule.
A tracking filter circuit according to claim 5, wherein in said first control mode, said logic control circuit controls said multiphase signal generating circuit to generate a frequency equal to said said by said polyphase characteristic control signal A clock signal of a center frequency of the second signal, and clock cycles of the clock signal are sequentially divided by 1 to M to obtain 1-to M-phase clock signals that do not overlap each other.
The tracking filter circuit according to claim 5, wherein in said second control mode, said logic control circuit controls said multiphase signal generating circuit to sequentially generate different K groups by said polyphase characteristic control signal The frequency of the clock signal, and the clock cycles of each group of clock signals are sequentially divided into M, to obtain K groups of M-phase clock signals that do not overlap each other; wherein K is an integer greater than zero.
The tracking filter circuit according to claim 5, wherein in said second control mode, said logic control circuit controls said multiphase signal generating circuit to sequentially generate different K groups by said polyphase characteristic control signal Frequency clock signal, and the clock cycles of each group of clock signals are in turn Performing 1 to M aliquoting, the K-group 1 to M-phase clock signals having no overlap with each other are obtained; wherein K is an integer greater than zero.
A tracking filter circuit according to any one of claims 4-8, characterized in that each of said switches is turned on only once during said clock cycle, and the on-time of each of said switches is L/ (Fs*M); At any one time, only one of the M switches is in an on state.
A tracking filter circuit according to any one of claims 4 to 9, wherein a filter center frequency of a transfer function of said polyphase switched capacitor filter is equal to a frequency Fs/L of said clock signal; said multiphase The 3dB bandwidth of the switched capacitor filter is inversely proportional to the number M of switches that are sequentially turned on in the multiphase switched capacitor filter.
The tracking filter circuit according to any one of claims 3 to 10, wherein when the intensity of the second signal is greater than or equal to the preset reference signal strength, the comparator outputs a second logic control signal The logic control circuit keeps the output unchanged under the control of the second logic control signal, the multi-phase signal generation circuit keeps the output unchanged under the control of the logic control circuit, and the multi-phase switched capacitor filter The filter maintains the filter center frequency unchanged under the control of the polyphase signal generating circuit.
The tracking filter circuit according to any one of claims 3 to 11, wherein the tracking filter circuit further comprises a low noise amplifier, a down converter and an intermediate frequency filter which are electrically connected in sequence, and the low noise amplifier further Electrically connected to an output end of the multi-phase switched capacitor filter, an input end of the signal strength detecting circuit and an output end of the polyphase switched capacitor filter, or an output end of the low noise amplifier, or The output of the frequency converter or the output of the intermediate frequency filter is electrically connected.
The tracking filter circuit according to claim 12, wherein the signal detecting and controlling circuit further comprises a pre-filtering circuit and a pre-amplifying circuit electrically connected in sequence, and the input end of the pre-filtering circuit The output of the polyphase switched capacitor filter, or the input of the low noise amplifier An output terminal or an output end of the down converter or an output end of the intermediate frequency filter is electrically connected, and an output end of the preamplifier circuit is electrically connected to an input end of the signal strength detecting circuit.
A radio frequency front end module, comprising the tracking filter circuit according to any one of claims 1-13.
A communication terminal comprising a radio frequency front end module, characterized in that the radio frequency front end module comprises the tracking filter circuit according to any one of claims 1-13.