WO2017143489A1

WO2017143489A1 - Method, apparatus and system for initializing scrambling code generator

Info

Publication number: WO2017143489A1
Application number: PCT/CN2016/074255
Authority: WO
Inventors: 李强; 冯淑兰; 刘劲楠; 吴毅凌
Original assignee: 华为技术有限公司
Priority date: 2016-02-22
Filing date: 2016-02-22
Publication date: 2017-08-31

Abstract

A method, apparatus and system for initializing a scrambling code generator. For a scenario in which the lengths of subsequences used for generating seed sequences need to be increased, when a scrambling code generator is initialized, the number of bits of all or part of subsequences used for generating seed sequences is decreased, so as to obtain to-be-used subsequences; seed sequences are generated according to the to-be-used subsequences; and a scrambler is scrambled by using the generated seed sequences. In the embodiment, the number of bits of all or part of subsequences used for generating seed sequences is decreased, and seed sequences are generated based on the subsequences the number of which has been decreased, accordingly the number of bits of seed sequences is not increased as the number of bits of subsequences is increased, and a scrambling code generator can be initialized by using the generated seed sequences.

Description

Method, device and system for initializing scrambling code generator

Technical field

The present application relates to the field of wireless communications, and in particular, to a method, an apparatus, and a system for initializing a scrambling code generator.

Background technique

GSM (Global System for Mobile Communication), WCDMA (Wideband Code Division Multiple Access) and LTE (Long Term Evolution) are the current mainstream cellular wireless communication systems in the world. To provide users with voice services and Internet services.

With the expansion of wireless service applications, the Internet of Things (IoT) business has gradually become an important business of wireless communication. The service object of the Internet of Things is “things” rather than “people”. An example of an Internet of Things service is the uploading of monitoring information in a video surveillance system (the communication device is embedded in the surveillance camera, and the monitoring information is periodically uploaded to the network).

In the Internet of Things, on the one hand, the number of terminals in a cell is greatly increased, so the length of the user identification needs to be extended to support a large number of terminals to communicate; on the other hand, the transmission rate of the Internet of Things is low, one frame (English) The length of the frame is longer, and the number of subframes included in one frame is larger. Therefore, the length of the current subframe sequence number needs to be extended to support identification of a large number of subframes in one frame in the Internet of Things. The lengths of the user identifier and the subframe number may be extended at the same time, or only one of them may be extended.

Whether the user identifier or the subframe number, is a component of the seed sequence of the scrambling code generator, and the number of bits of the seed sequence (ie, the length of the seed sequence) is less than or equal to the shift register depth of the scrambling code generator, The shift register depth refers to the number of registers contained in the shift register. If the scrambling code generator initialization method is still adopted according to the current cellular radio communication system such as GSM, WCDMA or LTE, the length of the seed sequence is increased due to the increase of the length of the user identifier and the subframe number, so that the number of bits of the seed sequence is larger than the scrambling code. The shift register depth of the generator, thus Initialization of the scrambling code generator is not possible.

Summary of the invention

The embodiment of the present application provides a method, an apparatus, and a system for initializing a scrambling code generator, and implementing initialization of a scrambling code generator for a scenario in which a length of a subsequence for generating a seed sequence needs to be increased.

The method for initializing a scrambling code generator provided by the embodiment of the present application includes:

The number of bits used to generate all or part of the subsequence of the seed sequence is reduced to obtain a subsequence to be used;

Generating a seed sequence according to the subsequence to be used;

The scrambling code generator is initialized using the seed sequence.

Advantageously, said reducing the number of bits used to generate all or a portion of the subsequence of the seed sequence comprises:

Determining N subsequences to be reduced in number of bits and bits reduced in each of the N subsequences according to a shift register depth of the scrambling code generator and a number of bits of M subsequences for generating a seed sequence Quantity; wherein, M and N are integers greater than or equal to 1, M>=N;

The number of bits of the N subsequences is respectively reduced according to the number of bits reduced for each of the N subsequences.

Preferably, if the number of sub-sequences whose number of bits is reduced is greater than 1, then:

In the subsequence in which the number of bits is reduced, the number of bits used in each subsequence is reduced in the same manner; or, in the subsequence in which the number of bits is reduced, the number of bits used in at least 2 subsequences is reduced by each other. The same, thus providing a variety of reduction methods for flexible selection as needed.

Preferably, the number of bits of a subsequence is reduced by one of the following bit number reduction methods:

Intercepting one or more bits starting from a high bit of a subsequence, the number of bits intercepted being less than the total number of bits of the subsequence;

Intercepting one or more bits from the low bit of a subsequence, the number of bits intercepted is less than the total number of bits of the subsequence. The above method of reducing the number of bits is technically easy to implement and requires less processing overhead.

Preferably, the subsequence whose number of bits is reduced comprises one or more of the following subsequences:

User ID;

Subframe number or frame number;

Cell identification.

Preferably, the obtained to-be-used sub-sequence includes: a user identifier, a subframe sequence number or a frame sequence number, and a cell identifier;

Generating a seed sequence according to the obtained sub-sequence to be used, including:

The user identifier, the subframe number or the frame sequence number, and the cell identifier are cascaded to obtain a seed sequence according to an order from a high bit to a low bit.

Preferably, the total number of bits of the obtained subsequence to be used is less than or equal to the shift register depth of the scrambling code generator, so that the scrambling code generator can be initialized using the generated seed sequence.

A scrambling code generator initializing apparatus provided by the embodiment of the present application includes:

a reduction module, configured to reduce a number of bits used to generate all or a partial subsequence of the seed sequence to obtain a subsequence to be used;

Generating a module, configured to generate a seed sequence according to the sub-sequence to be used obtained by the reduction module;

And an initialization module, configured to initialize the scrambling code generator by using the seed sequence generated by the generating module.

Preferably, the reduction module is specifically configured to:

Determining the N numbers according to the number of bits reduced by each of the N subsequences The number of bits of the subsequence is reduced.

Preferably, if the reduction module performs a bit number reduction on the plurality of sub-sequences, then:

In the subsequence in which the number of bits is reduced, the number of bits used in each subsequence is reduced in the same manner; or

In the subsequence in which the number of bits is reduced, the number of bits used in at least two subsequences is reduced in different ways.

Preferably, the reduction module is specifically configured to:

The number of bits in a subsequence is reduced by one of the following bit number reduction methods:

Intercepting one or more bits from the low bit of a subsequence, the number of bits intercepted is less than the total number of bits of the subsequence.

Preferably, the reduction module reduces the number of bits of one or more of the following subsequences:

User ID;

Subframe number or frame number;

Cell identification.

Preferably, the generating module is specifically configured to: when the obtained sub-sequence to be used includes: a user identifier, a subframe sequence number or a frame sequence number, and a cell identifier, the user is in an order from a high bit to a low bit The identifier, the subframe sequence number or the frame sequence number, and the cell identifier are cascaded to obtain a seed sequence.

Preferably, the total number of bits of the subsequence to be used obtained by the reduction module is less than or equal to the shift register depth of the scrambling code generator.

Another scrambling code generator initializing apparatus provided by the embodiment of the present application includes: a processing unit and a memory;

The processing unit may be configured to perform the scrambling code generator initialization process described in the above embodiments, and the process may include:

The number of bits used to generate all or part of the subsequence of the seed sequence is reduced to obtain Using subsequences;

Generating a seed sequence according to the subsequence to be used;

The scrambling code generator is initialized using the seed sequence.

The embodiment of the present application further provides a scrambling system, including: a scrambling code generator, a scrambling module, and the above scrambling code generator initializing device;

The scrambling code generator initializing means reduces the number of bits used to generate all or part of the subsequence of the seed sequence to obtain a subsequence to be used, generates a seed sequence according to the subsequence to be used, and uses the seed sequence Initializing the scrambling code generator;

The scrambling code generator is configured to generate a scrambling code sequence;

And a scrambling module, configured to scramble the input encoded sequence according to the scrambling code sequence generated by the scrambling code generator.

In the foregoing embodiment of the present application, for the scenario in which the length of the subsequence for generating the seed sequence needs to be increased, when the scrambling code generator is initialized, the number of bits used to generate all or part of the subsequence of the seed sequence is performed. The reduction is performed to obtain a subsequence to be used, a seed sequence is generated according to the obtained subsequence to be used, and the scrambler is initialized using the generated seed sequence. In the above embodiment, since the number of bits used to generate all or part of the subsequence of the seed sequence is reduced, and the seed sequence is generated based on the reduced subsequence, the number of bits of the seed sequence is controllable, and the generated The seed sequence initializes the scrambling code generator.

DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following drawings will be briefly described in the description of the embodiments. It is obvious that the drawings in the following description are only some embodiments of the present application, Those skilled in the art can also obtain other drawings based on these drawings without paying for inventive labor.

1 is a schematic diagram of a coding and scrambling process of a data channel in an LTE system in the prior art;

2 is a schematic diagram of interference randomization of neighboring cells using different scrambling code sequences in the prior art;

3 is a schematic structural diagram of a scrambling code generator in an LTE system in the prior art;

4 is a schematic diagram of a process of initializing a scrambling code generator according to an embodiment of the present application;

FIG. 5 is a schematic structural diagram of an apparatus for initializing a scrambling code generator according to an embodiment of the present disclosure;

FIG. 6 is a schematic structural diagram of an apparatus for initializing a scrambling code generator according to another embodiment of the present disclosure;

FIG. 7 is a schematic structural diagram of a scrambling system according to an embodiment of the present application.

detailed description

The signals transmitted in the LTE system can be roughly divided into control signaling (control information in English) and data (data in English), wherein the data is transmitted through the data channel. Specifically, the downlink data is transmitted in a physical downlink shared channel (Physical Downlink Shared CHannel, abbreviated as PDSCH), and the uplink data is transmitted in a physical uplink shared channel (Physical Uplink Shared CHannel, abbreviated as PUSCH). The data needs to be scrambled (scrambling in English). The so-called scrambling means that the bit sequence after encoding and the scrambling code sequence of the same length are subjected to modulo-addition operation. By scrambling, the interference of signal transmission between adjacent cells can be randomized (in English).

FIG. 1 exemplarily shows a coding and scrambling procedure of a data channel in an LTE system. First, a parity bit is added to the bit sequence of the data to be transmitted, and then subjected to channel coding and rate matching to obtain a coded bit sequence b(i), (i=1, 2, 3, ... N), the bit The length of the sequence is N (ie contains N bits). The scrambling code generator generates a scrambling code sequence c(i), (i = 1, 2, 3, ... N) of the same length as b(i). The scrambling of the bit sequence b(i) is achieved by performing a modulo two-addition operation on the bit sequence b(i) and the scrambling sequence c(i), as shown in the following expression:

among them,

Is the bit sequence after scrambling.

After the mutually interfered signals are scrambled by different scrambling sequences, the mutual interference is randomized to be close to the characteristics of Gaussian white noise. Therefore, signal transmission between adjacent cells that interfere with each other requires different scrambling code sequences for scrambling. As shown in FIG. 2, two adjacent cells use different scrambling code sequences c ₁ (i) and c ₂ (i) to achieve randomization of interference.

The scrambling code sequence is generated by a scrambling code generator. Fig. 3 exemplarily shows the structure of a scrambling code generator. It can be seen that the scrambling code generator is composed of two m-sequence generators (m-sequence generator 1 and m-sequence generator 2 as shown in the figure), and the bit sequences output by the two m-sequence generators are modulo-added. The scrambling code sequence is obtained after the operation. Each m-sequence generator is composed of a shift register having a depth of 31, and the m-sequence is outputted bit by bit by an operation. The shift register depth is represented by the number of bits. For example, the depth of the shift register is 31. It can be understood that 31 bit memory cells are connected in series, and each time data is moved from one memory cell to the next.

In order to generate different scrambling code sequences, in the LTE system, for different cells and different terminals, the scrambling code generator is initialized with different seed sequences, and different scrambling code sequences can be generated based on different seed sequences. Among them, the seed sequence is also called a random seed (initialization seed in English).

The seed sequence of the m sequence generator 1 is fixed, that is, the initial value of the register 0 is set to 1, and the initial value of the remaining registers is set to zero. The seed sequence of the m sequence generator 2 is generated according to the following formula:

among them,

Indicates the cell ID (identification), n _sf indicates the subframe number, q indicates the sequence number of the codeword of the data transmitted this time, n _RNTI indicates the user ID (identification) of the current transmission, and the user ID may be the RNTI allocated to the user. (Radio Network Tempory Identity, wireless network temporary identity). It can be seen that n _RNTI , q , n _sf and in order from high bit to low bit

These subsequences are spliced together to obtain the seed sequence c _init .

It can be seen from the above expression (2) that if the cell IDs are different, the seed sequences are different, and therefore the scrambling code sequences of the neighboring cells are also different. Adjacent cells, if the cell IDs are the same, as long as the RNTIs of the transmission target terminals are different, the seed sequences for different users are different from each other, so the scrambling code sequences used for data transmission of different users are also different. Similarly, for the data transmitted by the same user in different codewords, the seed sequence of the scrambling sequence is also different; for the data transmitted by the same user in different subframes, the seed sequence of the scrambling sequence is also different.

In the LTE system, the length of the RNTI is 16 bits, and 2 ¹⁶ users can be assigned different RNTIs in one cell.

As mentioned above, in the Internet of Things communication, on the one hand, the number of terminals served by one cell is greatly increased, and the number of bits of the existing RNTI needs to be expanded, for example, the RNTI is extended from 16 bits to 20 bits, thereby enabling Support for assigning different RNTIs to 2 ²⁰ users. On the other hand, the number of subframes included in one frame (or superframe) (or the number of frames included in the superframe) is large, so it is necessary to extend the length of the sequence number of the subframe (or frame), for example, now The subframe number length in the LTE system is 4 bits, which needs to be extended to 6 bits in the Internet of Things.

Whether the length of the RNTI is extended or the length of the subframe number is extended, generating the seed sequence according to the above formula (2) causes the number of bits of the generated seed sequence to exceed the shift register depth of the m sequence generator 2, and further This prevents the m sequence generator 2 from being initialized. For example, if the seed sequence is generated using the formula (2) in the Internet of Things, the generated seed sequence is composed of RNTI (20 bits), subframe (frame) number (6 bits), and cell ID (9 bits), for a total of 35 bits. Exceeded the shift register depth (31 bits) of the scrambling code generator. It should be noted that the single stream transmission technology is adopted in the Internet of Things, so the codeword ID is not required when generating the seed sequence.

In order to solve the above problem, the embodiment of the present application provides an initialization scheme of the scrambling code generator for a scenario in which the length of the subsequence for generating the seed sequence needs to be increased. The embodiments of the present application are described in detail below with reference to the accompanying drawings.

The embodiment of the present application is applicable to a scenario in which a length of a subsequence for generating a seed sequence needs to be increased in a wireless communication system. Especially suitable for IoT systems, such as video surveillance systems.

In the embodiment of the present application, a terminal refers to a terminal in a wireless communication system, and can communicate with one or more core networks via a radio access network (Radio Access Network, RAN for short). When the embodiment of the present application is applied to the Internet of Things system, the terminal may be a physical network terminal such as a mobile station (MS), for example, a surveillance camera implanted with a wireless communication device, and implanted. The electric meter of the wireless communication device or the water meter or the like in which the wireless communication device is implanted will not be enumerated here.

In this embodiment of the present application, the base station may be an evolved base station in an LTE system or an Internet of Things system. (Evolutional Node B, referred to as eNB or e-NodeB), macro base station, micro base station (also referred to as "small base station"), pico base station, access point (AP) or transmission point (Transmission Point, Referred to as TP) and so on. This application is not limited thereto. For convenience of description, the following embodiments will be described by taking a base station and a terminal as an example.

FIG. 4 is a schematic diagram of a process of initializing a scrambling code generator according to an embodiment of the present application. As shown, the process can include the following steps:

Step 401: Reduce the number of bits used to generate all or part of the subsequence of the seed sequence to obtain a subsequence to be used. The resulting total number of bits of the subsequence to be used is less than or equal to the shift register depth of the scrambling code generator.

The seed sequence of the scrambling code sequence is generated by M (M is an integer greater than or equal to 1) sub-sequences. In specific implementation, the shift register depth of the scrambling code generator and the M sub-segments used to generate the seed sequence may be used. The number of bits of the sequence, determining N (N is an integer greater than or equal to 1, and M>=N) subsequences to be reduced in number of bits and the number of bits in each of the N subsequences being reduced; and then according to the N The number of bits per subsequence in each subsequence is reduced, and the number of bits of the N subsequences is respectively reduced. Thus, the N subsequences whose number of bits is reduced and the remaining (M-N, ie, M minus N) subsequences constitute the "subsequent to be used".

In some embodiments, if N>1, the number of bits used in each of the N subsequences is reduced in the same manner. In other embodiments, if N>1, the number of bits used in at least two of the N subsequences is reduced in different ways. Which method is used in advance can be pre-agreed.

The number of bits used to generate all or part of the subsequence of the seed sequence is reduced, so that the total number of bits of the obtained subsequence to be used is less than or equal to the shift register depth of the scrambling code generator, so that it can be generated. The seed sequence initializes the scrambling code generator.

A plurality of bit number reduction methods may be used to achieve the above purpose. For example, the number of bits of the sub-sequence may be reduced according to a manner in which the sub-sequence is intercepted according to a set order or a rule, or may be used according to a set operation rule. A part of the bits in the subsequence is operated with another part of the bits (such as an exclusive OR operation), and the obtained result is used as a result of reducing the number of bits in the subsequence.

For example, the number of bits of the sub-sequence is reduced by taking the interception according to the set order or the rule. Specifically, the truncation may be performed from the high-order bit of the sub-sequence, and the truncated bit sequence is used as the sub-sequence after the number of bits is reduced; It can also be intercepted from the low bit of the subsequence, and the truncated bit sequence is used as a subsequence after the number of bits is reduced; it can also be intercepted according to other rules, such as taking the high (or low) bit every 2 bits. The bits are not listed here.

Preferably, in order to simplify the operation, when the number of bits of one subsequence is reduced, one or more bits may be intercepted from the high bit of the subsequence, and the number of bits intercepted is smaller than the total number of bits of the subsequence; One or more bits may also be truncated starting from the lower bits of the subsequence, the number of bits intercepted being less than the total number of bits of the subsequence.

For example, the seed sequence is composed of a user ID, a subframe (or frame) sequence number, and a cell ID. The sub-sequence whose bit number is reduced may include one or more of the following sub-sequences:

- a user ID, such as an RNTI assigned to the user;

a subframe number for identifying a subframe in the radio frame, or a frame sequence number for identifying a frame in the superframe;

a cell ID, such as a PCI (Physical Cell Identifier) of a cell.

Step 402: Generate a seed sequence according to the sub-sequence to be used obtained in step 401.

In a specific implementation, all sub-sequences to be used may be spliced in a set order to obtain a seed sequence. For example, the seed sequence is composed of a user ID, a subframe or a frame number, and a cell ID, and the user ID, the subframe or the frame number, and the cell ID may be cascaded according to the order from the high bit to the low bit. Seed sequence.

Step 403: Initialize the scrambling code generator using the seed sequence generated in step 402. The scrambling code generator is configured to generate a scrambling code sequence, and the generated scrambling code sequence is used to scramble data transmitted on the data channel.

In this step, after the seed sequence is obtained, the shift register of the scrambling code generator can be assigned according to the seed sequence to implement the initialization process of the scrambling code generator. For example, assign the value of bit0 in the seed sequence to the shift register 0 of the scrambling code generator, assign the value of bit1 in the seed sequence to the shift register 1 of the scrambling code generator, and so on, until The value of bit30 in the seed sequence The value is given to the shift register 30 of the scrambling code generator.

As can be seen from the above description, in the foregoing embodiment of the present application, a scenario in which the length of the subsequence for generating the seed sequence needs to be increased, when the scrambling code generator is initialized, will be used to generate all or The number of bits of the partial subsequence is reduced to obtain a subsequence to be used, a seed sequence is generated according to the obtained subsequence to be used, and the scrambler is initialized using the generated seed sequence. In the above embodiment, since the number of bits used to generate all or part of the subsequence of the seed sequence is reduced, and the seed sequence is generated based on the reduced subsequence, the number of the sequence sequence bits is not increased to cause the bit of the seed sequence. The number exceeds the transcoder's shift register depth, which in turn enables the scrambling code generator to be initialized using the generated seed sequence.

The above process will be described below in conjunction with several specific examples. These examples are based on the following scenario: the seed sequence is represented by the user ID (denoted as n _RNTI ), the subframe ID (denoted as n _f ), and the cell ID (represented as

) splicing composition. Where n _RNTI is a 20-bit sequence after being converted into a binary number, and n _f is a 6-bit sequence after being converted into a binary number.

After conversion to binary is a 9-bit sequence. The structure of the scrambling code generator is shown in Figure 3.

As an example, the 16 bits of the low bit of the n _RNTI are truncated in step 401, expressed as:

After interception,

The length (after conversion to a binary number) has changed from 20 bits to 16 bits.

In

step

402, 16 bits are

With other subsequences (6-bit _nf and 9-bit

After combining, you can get the seed sequence:

This seed sequence, after being converted to a binary number, is 31 bits in length and can therefore be used to initialize a scrambling code generator with a shift register depth of 31 bits.

As another example, the 16 bits of the n _RNTI high bit are truncated in step 401, expressed as:

After interception,

In

step

402, 16 bits are

With other subsequences (6-bit _nf and 9-bit

After combining, you can get the seed sequence:

As another example, intercepting in step 401

The 5 bits of the high bit are expressed as:

After interception,

The length (after conversion to a binary number) is changed from 9 bits to 5 bits.

In

step

402, 5 bits are

After combining with other subsequences (20 bits of n _RNTI and 6 bits of n _f ), a seed sequence can be obtained:

As another example, intercepting in step 401

The 5 bits of the low bit are expressed as:

After interception,

In

step

402, 5 bits are

As another example, n _f is taken in step 401 the high bit of 2 bits, is represented as:

After interception,

The length (after conversion to a binary number) is changed from 6 bits to 2 bits.

In

step

402, 2 bits are

With other subsequences (20 bits of n _RNTI and 9 bits)

After combining, you can get the seed sequence:

As another example, in step 401, taken n _f low bits of 2 bits, is represented as:

After interception,

In

step

402, 2 bits are

With other subsequences (20 bits of n _RNTI and 9 bits)

After combining, you can get the seed sequence:

In the embodiment of the present application, the initialization process of the above scrambling code generator may be implemented by a scrambling code generator initializing device. The device may be implemented by hardware or by software, or may be implemented by a combination of hardware and software. The apparatus can reduce the number of bits used to generate all or part of the subsequence of the seed sequence, and generate a seed sequence based on the reduced subsequence, and use the species The subsequence initializes the scrambling code generator.

Based on the same technical concept, the embodiment of the present application further provides a scrambling code generator initializing apparatus.

The scrambling code generator initializing apparatus provided in the embodiment of the present application will be described in detail below with reference to the accompanying drawings.

FIG. 5 is a schematic structural diagram of an apparatus for initializing a scrambling code generator according to an embodiment of the present application. The apparatus can implement the scrambling code generator initialization process described in the foregoing embodiments. The apparatus may include: a reduction module 501, a generation module 502, and an initialization module 503, wherein:

a reduction module 501, configured to reduce a number of bits used to generate all or a partial subsequence of the seed sequence to obtain a subsequence to be used;

a generating module 502, configured to generate a seed sequence according to the sub-sequence to be used obtained by the reducing module 501;

The initialization module 503 is configured to initialize the scrambling code generator using the seed sequence generated by the generating module 502.

In the above apparatus, the reduction module 501 may be specifically used when reducing the number of bits used to generate all or part of the subsequence of the seed sequence, according to the shift register depth of the scrambling code generator and the seed sequence used to generate the seed sequence. The number of bits of the M subsequences, the N subsequences to be reduced in number of bits and the number of bits in which each of the N subsequences is reduced; wherein, M and N are integers greater than or equal to 1, M>= N. The number of bits of the N subsequences is respectively reduced according to the number of bits reduced for each of the N subsequences.

Wherein, if the reduction module 501 performs a bit number reduction on a plurality of (ie, more than one) sub-sequences, the number of bits used in each sub-sequence is reduced in the sub-sequence in which the number of bits is reduced, or In the subsequence in which the number of bits is reduced, the number of bits used in at least two subsequences is reduced in different ways.

In the above apparatus, the reduction module 501 can be specifically used when reducing the number of bits used to generate all or part of the subsequence of the seed sequence:

In the above apparatus, the reduction module 501 can reduce the number of bits of one or more of the following subsequences:

User ID;

Subframe number or frame number;

Cell identification.

In the foregoing apparatus, the generating module 502 may be specifically configured to: when the obtained sub-sequence to be used includes: a user identifier, a subframe sequence number, a frame sequence number, and a cell identifier, according to an order from a high bit to a low bit, The user identifier, the subframe number (or frame number), and the cell identifier are cascaded to obtain a seed sequence.

In the above apparatus, the total number of bits of the subsequence to be used obtained by the reduction module 501 is less than or equal to the shift register depth of the scrambling code generator.

FIG. 6 is a schematic structural diagram of an apparatus for initializing a scrambling code generator according to another embodiment of the present application. The apparatus can implement the scrambling code generator initialization process described in the foregoing embodiments.

As shown, the apparatus can include an interface 601, a processing unit 602, and a memory 603. Processing unit 602 is for controlling the operation of the device; memory 603 can include read only memory and random access memory for providing instructions and data to processing unit 602. A portion of the memory 603 may also include non-volatile line random access memory (NVRAM). The various components of the apparatus are coupled together by a bus system, wherein the bus system 609 includes, in addition to the data bus, a power bus, a control bus, and a status signal bus. However, for clarity of description, various buses are labeled as bus system 609 in the figure.

The process disclosed in the embodiment of the present application may be applied to the processing unit 602, or by the processing unit. 602 implementation. In the implementation process, each step of the flow implemented by the base station may be completed by an integrated logic circuit of hardware in the processing unit 602 or an instruction in the form of software. The processing unit 602 can be a general-purpose processor, a digital signal processor, an application specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or a transistor logic device, and a discrete hardware component, which can be implemented or executed in the embodiment of the present application. Various methods, steps, and logic blocks of the disclosure. A general purpose processor can be a microprocessor or any conventional processor or the like. The steps of the method disclosed in the embodiments of the present application may be directly implemented as a hardware processor, or may be performed by a combination of hardware and software modules in the processor. The software module can be located in a conventional storage medium such as random access memory, flash memory, read only memory, programmable read only memory or electrically erasable programmable memory, registers, and the like. The storage medium is located in the memory 603, and the processing unit 602 reads the information in the memory 603, and completes the steps of the interference indication process implemented by the base station in combination with its hardware.

Specifically, the processing unit 602 may be configured to perform the scrambling code generator initialization process described in the foregoing embodiments, where the process may include:

Generating a seed sequence according to the subsequence to be used;

The scrambling code generator is initialized using the seed sequence.

Preferably, processing unit 602 may reduce the shift register depth of the scrambling code generator and the M subsequences used to generate the seed sequence when reducing the number of bits used to generate all or a portion of the subsequence of the seed sequence a number of bits, determining N subsequences to be reduced in number of bits and a number of bits in which each of the N subsequences is reduced; wherein, M and N are integers greater than or equal to 1, M>=N; The number of bits in each of the N subsequences is reduced, and the number of bits of the N subsequences is respectively reduced.

Preferably, if the processing unit 602 performs bit number reduction on the plurality of sub-sequences, the number of bits used in each sub-sequence is reduced in the sub-sequence in which the number of bits is reduced, or the number of bits is reduced. In the subsequence, the number of bits used in at least two subsequences is reduced in different ways.

Preferably, the processing unit 602 may reduce the number of bits of one subsequence by using one of the following bit number reduction methods:

Preferably, processing unit 602 reduces the number of bits of one or more of the following subsequences:

User ID;

Subframe number or frame number;

Cell identification.

Preferably, the processing unit 602 is specifically configured to: when the obtained sub-sequence to be used includes: a user identifier, a subframe sequence number, a frame sequence number, and a cell identifier, according to an order from a high bit to a low bit, The user identifier, the subframe number (or frame number), and the cell identifier are cascading to obtain a seed sequence.

Preferably, the total number of bits of the obtained subsequence to be used is less than or equal to the shift register depth of the scrambling code generator.

Based on the same technical concept, the embodiment of the present application also provides a scrambling system.

FIG. 7 is a schematic structural diagram of a scrambling system according to an embodiment of the present disclosure. The system may include: a scrambling code generator 701, a scrambling module 702, and a scrambling code generator initializing device 703, wherein the scrambling code generator initializing device 703 The specific structure may be as described in the foregoing embodiment, such as the code generator initialization device described in FIG. 5 or FIG. 6.

In the above system, the scrambling code generator initializing means 703 can reduce the number of bits used to generate all or part of the subsequence of the seed sequence to obtain a subsequence to be used, generate a seed sequence according to the subsequence to be used, and use the The seed sequence initializes the scrambling code generator.

The scrambling code generator 701 can be used to generate a scrambling code sequence. In a specific implementation, the scrambling code generator 701 may generate a scrambling code sequence based on the scrambling code sequence generation algorithm using the encoded sequence.

The scrambling module 702 can be configured to encode the input according to the scrambling code sequence generated by the scrambling code generator 701. The post-sequence is scrambled. In a specific implementation, the scrambling module 702 may perform a modulo two-addition operation on the input bit sequence and the scrambling code sequence to obtain a scrambled bit sequence.

Those skilled in the art will appreciate that embodiments of the present application can be provided as a method, system, or computer program product. Thus, the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment in combination of software and hardware. Moreover, the application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) including computer usable program code.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (system), and computer program products according to embodiments of the present application. It will be understood that each flow and/or block of the flowchart illustrations and/or FIG. The computer program instructions can be provided to a general purpose computer, a special purpose computer, an embedded processor, or a processor of other programmable data processing device such that instructions executed by a processor of the computer or other programmable data processing device can be implemented in a flowchart The function specified in one or more processes and/or block diagrams in one or more blocks.

The computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device. The apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.

These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device. The instructions provide steps for implementing the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.

While the preferred embodiment of the present application has been described, it will be apparent that those skilled in the art can make further changes and modifications to the embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and the modifications and

Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the present disclosure. The spirit and scope of the application. Thus, it is intended that the present invention cover the modifications and variations of the present invention.

Claims

A scrambling code generator initialization method, comprising:

The number of bits used to generate all or part of the subsequence of the seed sequence is reduced to obtain a subsequence to be used;

Generating a seed sequence according to the subsequence to be used;

The scrambling code generator is initialized using the seed sequence.
The method of claim 1 wherein said reducing a number of bits used to generate all or a portion of a subsequence of a seed sequence comprises:

Determining N subsequences to be reduced in number of bits and bits reduced in each of the N subsequences according to a shift register depth of the scrambling code generator and a number of bits of M subsequences for generating a seed sequence Quantity; wherein, M and N are integers greater than or equal to 1, M>=N;

The number of bits of the N subsequences is respectively reduced according to the number of bits reduced for each of the N subsequences.
The method according to claim 1 or 2, wherein if the number of sub-sequences whose number of bits is reduced is greater than 1, then:

In the subsequence in which the number of bits is reduced, the number of bits used in each subsequence is reduced in the same manner; or

In the subsequence in which the number of bits is reduced, the number of bits used in at least two subsequences is reduced in different ways.
The method according to any one of claims 1 to 3, characterized in that the number of bits of a subsequence is reduced by one of the following bit number reduction methods:

Intercepting one or more bits starting from a high bit of a subsequence, the number of bits intercepted being less than the total number of bits of the subsequence;

Intercepting one or more bits from the low bit of a subsequence, the number of bits intercepted is less than the total number of bits of the subsequence.
The method according to any one of claims 1 to 4, wherein the subsequence whose number of bits is reduced comprises one or more of the following subsequences:

User ID;

Subframe number or frame number;

Cell identification.
The method according to any one of claims 1 to 5, wherein the obtained subsequence to be used includes: a user identifier, a subframe number or a frame number, and a cell identifier;

Generating a seed sequence according to the obtained sub-sequence to be used, including:

The user identifier, the subframe number or the frame sequence number, and the cell identifier are cascaded to obtain a seed sequence according to an order from a high bit to a low bit.
The method according to any one of claims 1 to 6, wherein the total number of bits of the obtained subsequence to be used is less than or equal to the shift register depth of the scrambling code generator.
A scrambling code generator initializing device, comprising:

a reduction module, configured to reduce a number of bits used to generate all or a partial subsequence of the seed sequence to obtain a subsequence to be used;

Generating a module, configured to generate a seed sequence according to the sub-sequence to be used obtained by the reduction module;

And an initialization module, configured to initialize the scrambling code generator by using the seed sequence generated by the generating module.
The device according to claim 8, wherein the reduction module is specifically configured to:

Determining N subsequences to be reduced in number of bits and bits reduced in each of the N subsequences according to a shift register depth of the scrambling code generator and a number of bits of M subsequences for generating a seed sequence Quantity; wherein, M and N are integers greater than or equal to 1, M>=N;

The number of bits of the N subsequences is respectively reduced according to the number of bits reduced for each of the N subsequences.
The apparatus according to claim 8 or 9, wherein if said reduction module performs a bit number reduction on a plurality of subsequences, then:

In the subsequence in which the number of bits is reduced, the number of bits used in each subsequence is reduced in the same manner; or

In the subsequence in which the number of bits is reduced, the number of bits used in at least two subsequences is reduced in different ways.
The apparatus according to any one of claims 8 to 10, wherein the reduction module is specifically configured to:

The number of bits in a subsequence is reduced by one of the following bit number reduction methods:

Intercepting one or more bits starting from a high bit of a subsequence, the number of bits intercepted being less than the total number of bits of the subsequence;

Intercepting one or more bits from the low bit of a subsequence, the number of bits intercepted is less than the total number of bits of the subsequence.
The apparatus according to any one of claims 8 to 11, wherein the reduction module reduces the number of bits of one or more of the following subsequences:

User ID;

Subframe number or frame number;

Cell identification.
A device according to any one of claims 8 to 12, wherein

The generating module is specifically configured to: when the obtained sub-sequence to be used includes: a user identifier, a subframe sequence number, a frame sequence number, and a cell identifier, the user identifier and the child are in an order from a high bit to a low bit. The frame sequence number or the frame number and the cell identifier are cascaded to obtain a seed sequence.
The apparatus according to any one of claims 8 to 13, wherein the total number of bits of the subsequence to be used obtained by the reduction module is less than or equal to the shift register depth of the scrambling code generator.
A scrambling system, comprising: a scrambling code generator, a scrambling module, and the scrambling code generator initializing apparatus according to any one of claims 8 to 14;

The scrambling code generator initializing means for generating all or part of the subsequence of the seed sequence The number of bits is reduced, the subsequence to be used is obtained, a seed sequence is generated according to the subsequence to be used, and the scrambling code generator is initialized using the seed sequence;

The scrambling code generator is configured to generate a scrambling code sequence;

And a scrambling module, configured to scramble the input encoded sequence according to the scrambling code sequence generated by the scrambling code generator.