WO2017133100A1 - 发射电极扫描驱动单元、驱动电路、驱动方法以及阵列基板 - Google Patents

发射电极扫描驱动单元、驱动电路、驱动方法以及阵列基板 Download PDF

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Publication number
WO2017133100A1
WO2017133100A1 PCT/CN2016/081206 CN2016081206W WO2017133100A1 WO 2017133100 A1 WO2017133100 A1 WO 2017133100A1 CN 2016081206 W CN2016081206 W CN 2016081206W WO 2017133100 A1 WO2017133100 A1 WO 2017133100A1
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Prior art keywords
level
scan
signal input
signal
clock signal
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Ceased
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PCT/CN2016/081206
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English (en)
French (fr)
Inventor
谭文
邓银
陈佳
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Priority to US15/512,161 priority Critical patent/US10522065B2/en
Publication of WO2017133100A1 publication Critical patent/WO2017133100A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2085—Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination
    • G09G3/2088—Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination with use of a plurality of processors, each processor controlling a number of individual elements of the matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/02—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes by tracing or scanning a light beam on a screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a transmitting electrode scan driving unit, a driving circuit, a driving method, and an array substrate.
  • the embedded touch screen panel (In-Cell TSP) is a trend in the development of TSP technology.
  • a common electrode is typically used as the emitter (TX) electrode.
  • the TX drive signal is applied to the common electrode by an external drive integrated circuit (IC) through a fan-out lead located in the seal area.
  • IC external drive integrated circuit
  • the TX fanout lead is located above or below the array driver on Array (GOA), which easily causes crosstalk between signals applied to the TX electrode and the GOA, thereby reducing the reliability of the touch screen.
  • GOA array driver on Array
  • an emitter electrode scan drive unit that can require a reduced number of fan-out leads for the TX electrode. It is also desirable to provide an emitter electrode scan driving circuit including the emitter electrode scan driving unit, a method of driving the driver circuit, an array substrate including the driver circuit, and a display device including the array substrate.
  • a transmitting electrode scan driving unit including: a shift register unit having a start signal input end, a first clock signal input end, and a scan signal output end; and a plurality of scan drive signal generations And a unit, each having a second clock signal input end, a scan signal input end, a drive signal input end and a scan drive signal output end, wherein the scan signal input end is connected to the scan signal output end of the shift register unit.
  • the shift register unit is adapted to: in response to the first clock signal input being supplied with a first active level and the start signal input being supplied with a start signal having a first level, the scan signal output terminal a first level; in response to the first clock signal input being supplied with the first active level and the start signal input being supplied with a second level that is logically opposite to the first level, the scan signal output is set to a second level; and maintaining the level of the scan signal output unchanged while the input of the first clock signal is supplied with an inactive level.
  • Each of the plurality of scan drive signal generating units is adapted to input in response to a scan signal
  • the terminal is supplied with the first level and the second clock signal input terminal is supplied with the second active level, and the scan driving signal is generated according to the driving signal applied to the input terminal of the driving signal and outputted through the scan driving signal output terminal.
  • the second active level is a first level
  • each of the plurality of scan drive signal generating units includes an AND gate module and a voltage conversion module.
  • the AND gate module is coupled to the second clock signal input end and the scan signal input end, and is adapted to set the first node to be in response to the second clock signal input end and the scan signal input end being supplied with the first level One level.
  • the voltage conversion module is connected to the first node, the driving signal input end and the scan driving signal output end and has a first DC voltage input end and a second DC voltage input end.
  • the voltage conversion module is adapted to set a scan drive signal output to a voltage applied to the first DC voltage input in response to the first node being at the first level and the drive signal input being supplied with the first level, and
  • the scan drive signal output is set to a voltage applied to the second DC voltage input in response to the first node being at the second level or the drive signal input being supplied with the second level.
  • the AND gate module includes a first NAND gate and an inverter.
  • the first NAND gate connects the second clock signal input end and the scan signal input end, and is adapted to set the second node in response to the second clock signal input end and the scan signal input end being supplied with the first level Is the second level.
  • the inverter is coupled to the second node and the first node and is adapted to set the first node to a level that is logically opposite to the level of the second node.
  • the voltage conversion module includes a second NAND gate, a first transistor having a turn-on voltage at a first level, and a second transistor having a turn-on voltage at a second level.
  • the second NAND gate connects the first node and the driving signal input end, and is adapted to respond to the first node being at the first level and the driving signal input end being supplied with the first level, the third node Set to the second level.
  • the first transistor has a gate, a source and a drain, the gate is connected to a third node, one of the source and the drain is connected to the first DC voltage input, and the other is connected to the scan driving signal output end.
  • the second transistor has a gate, a source and a drain, a gate of the second transistor is connected to the third node, and one of a source and a drain of the second transistor is connected to the second DC voltage input. And the other is connected to the scan drive signal output.
  • the shift register unit includes a first pass gate, a second pass gate, a first inverter, a second inverter, a third inverter, and a fourth inverter.
  • the first transmission gate has a first control end, a second control end, an input end, and an output end, and the first control The terminal is connected to the first clock signal input terminal.
  • the second transmission gate has a first control end, a second control end connected to the first clock signal input end, an input end, and an output end connected to the output end of the first transmission gate.
  • the first inverter has an input coupled to the input of the first clock signal and an output coupled to the second control terminal of the first transmission gate and the first control terminal of the second transmission gate.
  • the second inverter has an input connected to the input of the start signal and an output connected to the input of the first transfer gate.
  • the third inverter has an input connected to the output of the second transmission gate and an output connected to the output of the scan signal.
  • the fourth inverter has an input connected to the output of the scan signal and an output connected to the input of the second transfer gate.
  • the emitter electrode scan driving unit includes three scan driving signal generating units.
  • the first level is a high level
  • the second level is a low level
  • the first active level is a high level
  • the second active level is a high level
  • a transmitting electrode scan driving circuit comprising: a plurality of transmitting electrode scan driving units as described above; a first clock signal line; and a plurality of second clock signal lines.
  • the plurality of emitter electrode scan driving units are cascaded with each other such that a scan signal output terminal of the shift register unit of each of the emitter electrode scan driving units is connected to the next one of the emitters other than the last emitter electrode scan driving unit
  • the electrode scans the start signal input of the shift register unit of the drive unit.
  • the first clock signal input terminal of the shift register of the plurality of emitter electrode scan driving units is connected to the first clock signal line.
  • a second clock signal input end of each of the plurality of scan driving signal generating units of each of the transmitting electrode scanning driving units is connected to the plurality of second clock signal lines one to one.
  • a method of driving a emitter electrode scan driving circuit as described above comprising: applying a first clock signal on a first clock signal line.
  • the clock pulse of the first clock signal has a high level that is the first active level.
  • the method also includes applying a start signal pulse at a start signal input of a shift register of the first transmit electrode scan drive unit before one of the clock pulses ends.
  • the start signal pulse is not earlier than the end of the clock pulse and ends no later than the beginning of the next clock pulse.
  • the method also includes applying a respective second clock signal on each of the plurality of second clock signal lines.
  • the clock pulses of the respective second clock signals have a high level of a second active level, each of the second clock signals having a corresponding time interval between two adjacent clock pulses of the first clock signal Clock pulses, and the individual clock pulses do not overlap each other in time.
  • an array substrate including: a substrate; and a emitter electrode scan driving circuit as described above is disclosed.
  • the emitter electrode scan driving circuit is formed on the substrate by patterning.
  • a display device including the array substrate as described above is disclosed.
  • FIG. 1 is a circuit diagram of a transmitting electrode scan driving unit according to an embodiment of the present disclosure
  • FIG. 2 is a timing chart schematically showing an operation of a transmitting electrode scan driving unit according to the embodiment of FIG. 1;
  • FIG. 3 is a circuit diagram of a shift register unit of a transmitting electrode scan driving unit according to the embodiment of FIG. 1;
  • FIG. 4 is a block diagram of a transmitting electrode scan driving circuit in accordance with an embodiment of the present disclosure
  • FIG. 5 is a timing chart schematically showing an operation of a emitter electrode scan driving circuit according to the embodiment of FIG.
  • FIG. 1 is a circuit diagram of a transmitting electrode scan driving unit according to an embodiment of the present disclosure.
  • the emitter electrode scan driving unit includes a shift register unit S/R and three scan driving signal generating units (shown as TX_GEN in the figure).
  • the shift register unit S/R has a start signal input terminal STV and a first clock signal input The input terminal CLK1 and the scan signal output terminal STVOUT.
  • the shift register unit S/R is adapted such that when the level of the first clock signal input terminal CLK1 is at the first active level and the start signal input terminal STV is supplied with the start signal having the first level, The scan signal output terminal STVOUT is set to the first level.
  • the shift register unit S/R is further adapted to scan the signal output terminal STVOUT when the level of the first clock signal input terminal CLK1 is at the first active level and the start signal input terminal STV is supplied with the second level. Set to a second level that is logically opposite to the first level.
  • the shift register unit S/R is also adapted to maintain the level of the scan signal output terminal STVOUT unchanged when the level of the first clock signal input terminal CLK1 is the S/R inactive level.
  • Each of the scan driving signal generating units TX_GEN has a second clock signal input terminal CLK2, a scan signal input terminal STVIN, a drive signal input terminal TXIN, and a scan drive signal output terminal TXOUTx.
  • the scan signal input terminal STVIN is connected to the scan signal output terminal STVOUT of the shift register unit S/R.
  • the second clock signal input terminal CLK2 of the nth TX_GEN is represented as CLK2_n, where n is 1, 2 or 3.
  • the scan drive signal output terminal TXOUTx of the nth TX_GEN is represented as TXOUTx_n, where n is 1, 2 or 3.
  • Each TX_GEN is adapted to generate a scan drive signal and pass the drive signal input from the drive signal input terminal TXIN when the scan signal output terminal STVOUT is supplied with the first level and the second clock signal input terminal is supplied with the second active level. The corresponding scan drive signal output is output.
  • FIG. 2 is a timing chart schematically showing an operation of a transmitting electrode scan driving unit according to the embodiment of FIG. 1. The operation of the emitter electrode scan driving unit will be described below with reference to Figs.
  • the first level is a high level
  • the second level is a low level
  • the first active level is a high level
  • the second active level is a high level
  • a first clock signal is applied to the first clock signal input terminal CLK1.
  • the high level of the clock pulse of the first clock signal is the first active level.
  • a start signal of a high level is applied to the start signal input terminal STV, and the end time of the high level of the start signal is not earlier than the end time of the clock pulse And no later than the start of the next clock pulse.
  • a respective second clock signal is applied to each of the second clock signal inputs (in this example, CLK2_1, CLK2_2, and CLK2_3).
  • the duty cycle of the second clock signal is 1/4.
  • the high level of the clock pulse of each second clock signal is TX_GEN Effective level (second active level).
  • the clock pulses of the respective second clock signals are sequentially supplied such that the clock pulses of any one of the second clock signals do not overlap with the clock pulses of the other second clock signals in time. In the time interval between two adjacent clock pulses of the first clock signal, each of the second clock signals has one clock pulse.
  • the shift register unit S/R When a start signal of a high level is applied to the start signal input terminal STV, since the first clock signal applied to the first clock signal input terminal CLK1 is at a high level, the shift register unit S/R The scan signal output terminal STVOUT is set to a high level. Thereafter, the first clock signal applied to the first clock signal input terminal CLK1 becomes a low level, that is, a level that is inactive to the shift register unit S/R, so that the level of the scan signal output terminal STVOUT is maintained at a high level. level. Until the next clock pulse of the first clock signal arrives, the level of the first clock signal input terminal CLK1 is satisfied to be the first active level and the level of the start signal input terminal STV is low. At this time, the scan signal output terminal STVOUT of the shift register unit S/R is set to a low level.
  • the second clock signal input terminals CLK2_1, CKL2_2, and CLK2_3 of the scan driving signal generating unit TX_GEN are sequentially set to High level.
  • Each TX_GEN is configured to output a scan drive signal when its second clock signal input is at a high level and the output terminal STVOUT of the shift register unit S/R is at a high level.
  • three scan drive signal outputs TXOUTx_1, TXOUTx_2, and TXOUTx_3 of TX_GEN are sequentially outputted with three scan drive signals, as shown in FIG.
  • the three scan driving signals are all outputted at the stage where the scanning signal output terminal STVOUT of the shift register unit S/R is set to a high level, so that the plurality of transmitting electrodes can scan the shift register unit S/R of the driving unit. Cascade, as will be described later.
  • the scan signal output terminals STVOUT of the respective shift register units S/R are sequentially pulled up, so that the respective emitter electrode scan driving units sequentially output the touch scan drive signals.
  • the shift register unit S/R may have a high voltage terminal VGH that is connected to a high voltage and a low voltage terminal VGL that is connected to a low voltage.
  • VGH high voltage terminal
  • VGL low voltage terminal
  • the scan driving signal generating unit TX_GEN includes an AND gate module AND and a voltage conversion module VTR.
  • the AND gate module AND is connected to the second clock signal input terminal CLK2_n (assuming that TX_GEN is the nth TX_GEN) and the scan signal input terminal STVIN. AND gate module AND is used in the When the two clock signal input terminals CLK2_n and the scan signal input terminal STVIN are both at the first level, the first node N1 is set to the first level.
  • the voltage conversion module VTR is connected to the first node N1, the driving signal input terminal TXIN, the scan driving signal output terminal TXOUTx_n, and has a first DC voltage input terminal TXCOM and a second DC voltage input terminal VCOM.
  • the voltage conversion module VTR is configured to set the level of the scan driving signal output terminal TXOUTx_n to the voltage input by the first DC voltage input terminal TXCOM when the first node N1 is at the first level and the driving signal input terminal TXIN is at the first level. And when the first node N1 is at the second level or the driving signal input terminal TXIN is at the second level, the voltage of the scan driving signal output terminal TXOUTx_n is set to the voltage input by the second DC voltage input terminal VCOM.
  • the high and low levels of the output scan drive signal are respectively coincident with the voltages input by the two DC voltage input terminals TXCOM and VCOM described above, so that the scan drive signal satisfies a predetermined drive requirement.
  • the voltage input by the first DC voltage input terminal TXCOM may be the voltage required by the touch detection chip
  • the voltage input by the second DC voltage input terminal VCOM may be the voltage of the common electrode.
  • the AND gate module AND includes a NAND gate 11 (referred to herein as a first NAND gate) and an inverter 21.
  • the first NAND gate 11 is connected to the second clock signal input terminal CLK2_n and the scan signal input terminal STVIN.
  • the first NAND gate 11 is configured to set the second node N2 to the second level when the second clock signal input terminal CLK2_n and the scan signal input terminal STVIN are at the first level.
  • the inverter 21 is connected to the second node N2 and the first node N1.
  • the inverter 21 is for setting the level of the first node N1 to a level that is logically opposite to the level of the second node N2.
  • the voltage conversion module VTR includes a second NAND gate 12, a first transistor T1, a second transistor T2, and has a first DC voltage input terminal TXCOM and a second DC voltage input terminal VCOM.
  • the second NAND gate 12 is connected to the first node N1 and the drive signal input terminal TXIN.
  • the second NAND gate 12 is configured to set the third node N3 to the second level when the first node N1 is at the first level and the driving signal input terminal TXIN is at the first level.
  • the gates of the first transistor T1 and the second transistor T2 are connected to the third node N3.
  • the source of the first transistor T1 is connected to the first DC voltage input terminal TXCOM, and the drain of the first transistor T1 is connected to the scan driving signal output terminal TXOUTx_n.
  • the drain of the second transistor T2 is connected to the scan driving signal output terminal TXOUTx_n, and the source of the second transistor T2 is connected to the second straight Current voltage input terminal VCOM.
  • the turn-on voltage of the first transistor T1 is at a first level
  • the turn-on voltage of the second transistor T2 is at a second level.
  • the source and drain of the first transistor T1 and the second transistor T2 are typically made symmetric, and thus are used interchangeably.
  • FIG. 3 is a circuit diagram of a shift register unit of a transmitting electrode scan driving unit according to the embodiment of FIG. 1.
  • the shift register unit S/R includes a first transfer gate 31, a second transfer gate 32, and four inverters 22, 23, 24, and 25.
  • the first control terminal P of the first transmission gate 31 and the second control terminal N of the second transmission gate 32 are both connected to the first clock signal input terminal CLK1.
  • the first control terminal P of the second transmission gate 32 and the second control terminal N of the first transmission gate 31 are both connected to the output of the first inverter 22.
  • the input of the first inverter 22 is connected to the first clock signal input terminal CLK1.
  • the input end of the second inverter 23 is connected to the start signal input terminal STV, and the output end of the second inverter 23 is connected to the input end of the first transfer gate 31 (in FIG. 3, the left terminal of the first transfer gate 31) Used as an input and the right terminal is used as an output).
  • the output end of the first transfer gate 31 is connected to the output end of the second transfer gate 32 (in FIG.
  • the left terminal of the second transfer gate 32 is used as an output terminal, and the right terminal is used as an input terminal).
  • the input terminal of the third inverter 24 is connected to the output terminal of the second transmission gate 32, and the output terminal of the third inverter 24 is connected to the scan signal output terminal STVOUT.
  • the input terminal of the fourth inverter 25 is connected to the scan signal output terminal STVOUT, and the output terminal of the fourth inverter 25 is connected to the input terminal of the second transfer gate 32.
  • Each of the first transmission gate 31 and the second transmission gate 32 is configured to be turned on when its first control terminal P is at a first level and its second control terminal N is at a second level, thereby being applied to the input The signal at the end is transmitted to the output.
  • the first control terminal P of the first transmission gate 31 is at the first level, and the second control terminal N is at the second level. Therefore, the first transmission gate 31 is turned on, so that when the start signal of the first level is input to the start signal input terminal STV, the input terminal of the first transfer gate 31 is set to the second level, and thus the output terminal is set Is the second level. Further, the third inverter 24 sets the level of the scan signal output terminal STVOUT to the first level.
  • the connection state of the control terminals of the second transmission gate 32 is opposite to the connection state of the first transmission gate 31, so that their operational states are also reversed. Therefore, the second transfer gate 32 is turned off.
  • the first control terminal P of the first transmission gate 31 is at the second level, and the second control terminal N is at the first level. Therefore, the first transfer gate 31 is turned off, and the second transfer gate 32 is turned on. Since the level of the scan signal output terminal STVOUT is the first level, the inverter 25 sets the level of the input terminal of the second transfer gate 32 to the second level. Further, the second transfer gate 32 also sets the level of its output terminal to the second level, and the third inverter 24 sets the level of the scan signal output terminal STVOUT to the first level.
  • the first transfer gate 31 When the level of the clock signal input terminal CLK1 changes to the first level again, the first transfer gate 31 is turned on again, and the second transfer gate 32 is turned off again. However, since the start signal output terminal STV has been set to the second level, the level of the output terminal of the first transfer gate 31 is set to the first level, and thus the third inverter 24 will scan the signal output terminal STVOUT. The level is set to the second level. Thereafter, when the clock signal input terminal CLK1 becomes the second level again, the first transfer gate 31 is turned off, and the second transfer gate 32 is turned on. Since the level of the scan signal output terminal STVOUT is the second level, the input terminal of the second transfer gate 32 is at the first level, and the output terminal of the second transfer gate 32 is also at the first level. Further, the third inverter 24 sets the level of the scan signal output terminal STVOUT to the second level.
  • first transmission gate 31 and the second transmission gate 32 and the respective inverters 22, 23, 24, and 25 generally have a high voltage terminal VGH that is connected to a high voltage and a low voltage terminal VGL that is connected to a low voltage.
  • these high voltage terminals VGH and low voltage terminals VGL are not shown in FIG.
  • FIG. 4 is a block diagram of a transmitting electrode scan driving circuit in accordance with an embodiment of the present disclosure.
  • the emitter electrode scan driving circuit includes a plurality of emitter electrode scan driving units, four clock signal lines L1, L2_1, L2_2, and L2_3, a high voltage line L5, a low voltage line L6, a start signal line L7, and a driving signal. Line L8.
  • Each of the emitter electrode scan driving units may be a transmitter electrode scan driving unit as described above.
  • the three scan drive signal outputs of the xth emitter electrode scan drive unit are denoted as TXOUTx_1, TXOUTx_2 and TXOUTx_3, respectively, where x is an integer greater than or equal to one.
  • the first clock signal input terminal CLK1 is connected to the first clock signal line L1
  • the second clock signal input terminals CLK2_1, CLK2_2 and CLK2_3 are connected to the second clock signal lines L2_1, L2_2 and L2_3 one-to-one.
  • the high voltage terminal VGH is connected to the high voltage line L5
  • the low voltage terminal VGL is connected to the low voltage line L6
  • each driving signal input end TXIN is connected to the drive signal line L8.
  • a plurality of emitter electrode scan drive units are cascaded together. Specifically, in addition to the last emitter electrode scan driving unit, the scan signal output terminal STVOUT of the shift register unit S/R of each of the emitter electrode scan driving units is connected to the shift register unit S/ of the next emitter electrode scan driving unit.
  • the start signal input terminal of R is STV. Further, the start signal input terminal STV of the shift register unit S/R of the first emitter electrode scan driving unit is connected to the start signal line L7.
  • FIG. 5 is a timing chart schematically showing an operation of a emitter electrode scan driving circuit according to the embodiment of FIG.
  • the cascaded emitter electrode scan drive unit of the emitter electrode scan drive circuit is at the corresponding scan drive signal output terminal TXOUT1_1, TXOUY1_2, TXOUT1_3...TXOUTm_2 and TXOUTm_3 (m is the number of transmitting electrode scan driving units) sequentially output touch scan driving signals.
  • a transmitting electrode scan driving unit may provide a plurality of scan driving signals. This makes it possible to disperse the emitter electrode scan driving circuit in the frame region of the array substrate. Thus, it is not necessary to use a large number of fan-out leads to connect the emitter electrode to the edge of the array substrate. Due to the reduction of the fan-out leads, it is also possible to reduce the area of the frame area of the touch device.
  • one transmitting electrode scanning driving unit may include other numbers (such as 7). TX_GEN.
  • one emitter electrode scan driving unit includes seven TX_GENs, eight clock signal lines are required, one of which is connected to the first clock signal input terminal of the shift register unit, and the other clock signal lines are connected one to one by seven TX_GEN The second clock signal input.
  • the emitter electrode scan driving circuit as described above can be fabricated on the array substrate.
  • the array substrate includes a substrate on which the emitter electrode scan driving circuit is formed by patterning.
  • the array substrate can be used to fabricate a display device.
  • the display device here may refer to a mobile phone, a tablet, a navigator, and other products having touch and display functions.

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Abstract

一种发射电极扫描驱动单元，包括：移位寄存器单元，具有起始信号输入端、第一时钟信号输入端和扫描信号输出端；以及多个扫描驱动信号生成单元，每一个具有第二时钟信号输入端、扫描信号输入端、驱动信号输入端和扫描驱动信号输出端。扫描信号输入端与移位寄存器单元的扫描信号输出端相连。还提供了一种驱动电路、驱动方法、阵列基板和显示装置。

Description

发射电极扫描驱动单元、驱动电路、驱动方法以及阵列基板 技术领域
本公开涉及显示技术领域，尤其是涉及一种发射电极扫描驱动单元、驱动电路、驱动方法以及阵列基板。
背景技术
嵌入式触摸屏面板(In-Cell TSP)是TSP技术发展的一个趋势。在In-Cell TSP中，通常使用公共电极作发射(TX)电极。传统设计中，TX驱动信号是由外部驱动集成电路(IC)通过位于封框胶(seal)区域的扇出(fan-out)引线施加到公共电极上的。
随着面板尺寸增大，TX电极数量将增多，并且因此扇出引线的布置需要更多空间。因此，In-Cell技术在大尺寸和窄边框面板上的应用受到限制。另外，TX扇出引线位于阵列基板栅极驱动电路(Gate driver on Array，GOA)上方或下方，这容易造成施加到TX电极和GOA的信号之间的串扰，从而降低触摸屏的可靠性。
发明内容
有利的是实现一种发射电极扫描驱动单元，其可以要求针对TX电极的减少的扇出引线数目。同样期望的是提供一种包括所述发射电极扫描驱动单元的发射电极扫描驱动电路、驱动该驱动电路的方法、包括该驱动电路的阵列基板和包括该阵列基板的显示装置。
根据本公开的一个方面，提供了一种发射电极扫描驱动单元，包括：移位寄存器单元，具有起始信号输入端、第一时钟信号输入端和扫描信号输出端；以及多个扫描驱动信号生成单元，每一个具有第二时钟信号输入端、扫描信号输入端、驱动信号输入端和扫描驱动信号输出端，所述扫描信号输入端与所述移位寄存器单元的扫描信号输出端相连。所述移位寄存器单元被适配成：响应于第一时钟信号输入端被供应第一有效电平且起始信号输入端被供应具有第一电平的起始信号，将扫描信号输出端置为第一电平；响应于第一时钟信号输入端被供应第一有效电平且起始信号输入端被供应与第一电平逻辑上相反的第二电平，将扫描信号输出端置为第二电平；以及响应于第一时钟信号输入端被供应无效电平，维持扫描信号输出端的电平保持不变。所述多个扫描驱动信号生成单元中的每个被适配成响应于扫描信号输入 端被供应第一电平且第二时钟信号输入端被供应第二有效电平，根据施加到驱动信号输入端的驱动信号生成扫描驱动信号并通过扫描驱动信号输出端输出。
在一些实施例中，所述第二有效电平为第一电平，并且所述多个扫描驱动信号生成单元中的每个包括与门模块和电压转换模块。所述与门模块连接第二时钟信号输入端和扫描信号输入端，并且被适配成响应于第二时钟信号输入端和扫描信号输入端被供应第一电平，将第一节点置为第一电平。所述电压转换模块连接第一节点、驱动信号输入端和扫描驱动信号输出端且具有第一直流电压输入端和第二直流电压输入端。所述电压转换模块被适配成响应于第一节点处于第一电平且驱动信号输入端被供应第一电平，将扫描驱动信号输出端置为施加到第一直流电压输入端的电压，并且响应于第一节点处于第二电平或驱动信号输入端被供应第二电平，将扫描驱动信号输出端置为施加到第二直流电压输入端的电压。
在一些实施例中，所述与门模块包括第一与非门和反相器。所述第一与非门连接第二时钟信号输入端和扫描信号输入端，并且被适配成响应于第二时钟信号输入端和扫描信号输入端被供应第一电平，将第二节点置为第二电平。所述反相器连接第二节点和第一节点，并且被适配成将第一节点置为与第二节点的电平逻辑上相反的电平。
在一些实施例中，所述电压转换模块包括第二与非门、具有为第一电平的导通电压的第一晶体管和具有为第二电平的导通电压的第二晶体管。所述第二与非门连接所述第一节点和驱动信号输入端，并且被适配成响应于第一节点处于第一电平且驱动信号输入端被供应第一电平，将第三节点置为第二电平。所述第一晶体管具有栅极、源极和漏极，所述栅极连接第三节点，所述源极和漏极中的一个连接第一直流电压输入端，并且另一个连接扫描驱动信号输出端。所述第二晶体管具有栅极、源极和漏极，所述第二晶体管的栅极连接第三节点，所述第二晶体管的源极和漏极中的一个连接第二直流电压输入端，并且另一个连接扫描驱动信号输出端。
在一些实施例中，所述移位寄存器单元包括第一传输门、第二传输门、第一反相器、第二反相器、第三反相器和第四反相器。第一传输门具有第一控制端、第二控制端、输入端和输出端，所述第一控制 端连接第一时钟信号输入端。第二传输门具有第一控制端、连接第一时钟信号输入端的第二控制端、输入端、以及连接第一传输门的输出端的输出端。第一反相器具有连接第一时钟信号输入端的输入端以及连接第一传输门的第二控制端和第二传输门的第一控制端的输出端。第二反相器具有连接起始信号输入端的输入端和连接第一传输门的输入端的输出端。第三反相器具有连接第二传输门的输出端的输入端和连接扫描信号输出端的输出端。第四反相器具有连接扫描信号输出端的输入端和连接第二传输门的输入端的输出端。
在一些实施例中，所述发射电极扫描驱动单元包括三个扫描驱动信号生成单元。
在一些实施例中，所述第一电平为高电平，第二电平为低电平，第一有效电平为高电平，并且第二有效电平为高电平。
根据本公开的另一方面，公开了一种发射电极扫描驱动电路，包括：多个如上面所述的发射电极扫描驱动单元；第一时钟信号线；以及多条第二时钟信号线。所述多个发射电极扫描驱动单元彼此级联，以使得除最后一个发射电极扫描驱动单元之外所述发射电极扫描驱动单元中的每个的移位寄存器单元的扫描信号输出端连接下一个发射电极扫描驱动单元的移位寄存器单元的起始信号输入端。所述多个发射电极扫描驱动单元的移位寄存器的第一时钟信号输入端连接第一时钟信号线。每个发射电极扫描驱动单元的所述多个扫描驱动信号生成单元的第二时钟信号输入端一对一连接所述多条第二时钟信号线。
根据本公开的又另一方面，公开了一种驱动如上面所述的发射电极扫描驱动电路的方法，包括：在第一时钟信号线上施加第一时钟信号。所述第一时钟信号的时钟脉冲具有为第一有效电平的高电平。所述方法还包括：在所述时钟脉冲之一结束之前，在第一个发射电极扫描驱动单元的移位寄存器的起始信号输入端施加起始信号脉冲。该起始信号脉冲不早于该时钟脉冲的结尾且不晚于下一时钟脉冲的开始结束。所述方法还包括：在所述多条第二时钟信号线中的每个上施加相应的第二时钟信号。各个第二时钟信号的时钟脉冲具有为第二有效电平的高电平，每一个第二时钟信号具有在第一时钟信号的两个时间上相邻的时钟脉冲之间的时间间隔中的相应时钟脉冲，并且各个时钟脉冲在时间上互不重叠。
根据本公开的再另一方面，公开了一种阵列基板，包括：基底；以及如上面所述的发射电极扫描驱动电路。所述发射电极扫描驱动电路通过图案化形成在所述基底上。
根据本公开的再另一方面，公开了一种显示装置，包括如上面所述的阵列基板。
根据在下文中所描述的实施例，本发明的这些和其它方面将是清楚明白的，并且将参考在下文中所描述的实施例而被阐明。
附图说明
通过参考附图会更加清楚的理解本公开的特征信息和优点，附图是示意性的而不应理解为对本公开进行任何限制，在附图中：
图1为根据本公开一实施例的发射电极扫描驱动单元的电路示意图；
图2为示意性示出根据图1的实施例的发射电极扫描驱动单元的操作的时序图；
图3为根据图1的实施例的发射电极扫描驱动单元的移位寄存器单元的电路示意图；
图4为根据本公开一实施例的发射电极扫描驱动电路的框图；并且
图5为示意性示出根据图4的实施例的发射电极扫描驱动电路的操作的时序图。
具体实施方式
为了能够更清楚地理解本公开的上述目的、特征和优点，下面结合附图和具体实施方式对本公开进行进一步的详细描述。需要说明的是，在不冲突的情况下，本申请的实施例及实施例中的特征可以相互组合。
在下面的描述中阐述了很多具体细节以便于充分理解本公开，但是，本公开还可以采用其他不同于在此描述的其他方式来实施。因此，本公开的保护范围并不受下面公开的具体实施例的限制。
图1为根据本公开一实施例的发射电极扫描驱动单元的电路示意图。
参见图1，该发射电极扫描驱动单元包括移位寄存器单元S/R和三个扫描驱动信号生成单元(图中表示为TX_GEN)。
该移位寄存器单元S/R具有起始信号输入端STV、第一时钟信号输 入端CLK1和扫描信号输出端STVOUT。
该移位寄存器单元S/R被适配成在第一时钟信号输入端CLK1的电平为第一有效电平且起始信号输入端STV被供应具有第一电平的起始信号时，将扫描信号输出端STVOUT置为第一电平。
该移位寄存器单元S/R还被适配成在第一时钟信号输入端CLK1的电平为第一有效电平且起始信号输入端STV被供应第二电平时，将扫描信号输出端STVOUT置为与第一电平逻辑上相反的第二电平。
该移位寄存器单元S/R还被适配成在第一时钟信号输入端CLK1的电平为S/R无效电平时，维持扫描信号输出端STVOUT的电平保持不变。
每一个扫描驱动信号生成单元TX_GEN具有第二时钟信号输入端CLK2、扫描信号输入端STVIN、驱动信号输入端TXIN和扫描驱动信号输出端TXOUTx。扫描信号输入端STVIN与移位寄存器单元S/R的扫描信号输出端STVOUT相连。
为了便于区分，将第n个TX_GEN的第二时钟信号输入端CLK2表示为CLK2_n，其中n为1、2或3。而且，将第n个TX_GEN的扫描驱动信号输出端TXOUTx表示为TXOUTx_n，其中n为1、2或3。
每一个TX_GEN被适配成在扫描信号输出端STVOUT被供应第一电平且第二时钟信号输入端被供应第二有效电平时，根据驱动信号输入端TXIN输入的驱动信号生成扫描驱动信号并通过相应的扫描驱动信号输出端输出。
图2为示意性示出根据图1的实施例的发射电极扫描驱动单元的操作的时序图。下面参照图1和2描述发射电极扫描驱动单元的操作。
假设第一电平为高电平，第二电平为低电平，第一有效电平为高电平，并且第二有效电平为高电平。
在第一时钟信号输入端CLK1上施加第一时钟信号。该第一时钟信号的时钟脉冲的高电平为第一有效电平。在第一时钟信号的时钟脉冲之一结束之前，在起始信号输入端STV施加高电平的起始信号，且该起始信号的高电平的结束时刻不早于该时钟脉冲的结束时刻且不晚于下一时钟脉冲的开始时刻。
在各条第二时钟信号输入端(在该示例中，CLK2_1、CLK2_2和CLK2_3)上施加相应的第二时钟信号。在该示例中，第二时钟信号的占空比为1/4。各个第二时钟信号的时钟脉冲的高电平为TX_GEN的有 效电平(第二有效电平)。各个第二时钟信号的时钟脉冲被顺序地提供，使得任意一个第二时钟信号的时钟脉冲与其他第二时钟信号的时钟脉冲在时间上不重叠。在第一时钟信号的两个时间上相邻的时钟脉冲之间的时间间隔中，每一个第二时钟信号均具有一个时钟脉冲。
仍然参见图2，在起始信号输入端STV施加高电平的起始信号时，由于第一时钟信号输入端CLK1上施加的第一时钟信号为高电平，所以移位寄存器单元S/R的扫描信号输出端STVOUT被置为高电平。之后，第一时钟信号输入端CLK1上施加的第一时钟信号变为低电平，也即对于移位寄存器单元S/R无效的电平，使得扫描信号输出端STVOUT的电平维持为高电平。直到第一时钟信号的下一个时钟脉冲到来时，才满足第一时钟信号输入端CLK1的电平为第一有效电平且起始信号输入端STV的电平为低电平。此时，移位寄存器单元S/R的扫描信号输出端STVOUT被置为低电平。
如图2所示，在移位寄存器单元S/R的扫描信号输出端STVOUT输出高电平的间隔内，扫描驱动信号生成单元TX_GEN的第二时钟信号输入端CLK2_1、CKL2_2以及CLK2_3依次被置为高电平。每一个TX_GEN被配置成在其第二时钟信号输入端处于高电平且移位寄存器单元S/R的输出端STVOUT处于高电平时输出一个扫描驱动信号。在该示例中，在TX_GEN的三个扫描驱动信号输出端TXOUTx_1、TXOUTx_2和TXOUTx_3依次输出三个扫描驱动信号，如图2所示的。
三个扫描驱动信号均是在移位寄存器单元S/R的扫描信号输出端STVOUT被置为高电平的阶段输出的，因此可以将多个发射电极扫描驱动单元的移位寄存器单元S/R级联起来，如稍后将描述的。这样，各个移位寄存器单元S/R的扫描信号输出端STVOUT依次被拉高，从而使得各个发射电极扫描驱动单元依次输出触摸扫描驱动信号。
在实际的应用中，移位寄存器单元S/R可以具有接入高电压的高电压端VGH和接入低电压的低电压端VGL。这样的移位寄存器单元S/R在图1中示出。
在一些实施例中，如图1中所示，扫描驱动信号生成单元TX_GEN包括与门模块AND和电压转换模块VTR。
与门模块AND连接第二时钟信号输入端CLK2_n(假设该TX_GEN为第n个TX_GEN)和扫描信号输入端STVIN。与门模块AND用于在第 二时钟信号输入端CLK2_n和扫描信号输入端STVIN均为第一电平时，将第一节点N1置为第一电平。
电压转换模块VTR连接第一节点N1、驱动信号输入端TXIN、扫描驱动信号输出端TXOUTx_n，并具有第一直流电压输入端TXCOM和第二直流电压输入端VCOM。电压转换模块VTR用于在第一节点N1为第一电平且驱动信号输入端TXIN为第一电平时，将扫描驱动信号输出端TXOUTx_n的电平置为第一直流电压输入端TXCOM输入的电压，并且在第一节点N1为第二电平或驱动信号输入端TXIN为第二电平时，将扫描驱动信号输出端TXOUTx_n的电压置为第二直流电压输入端VCOM输入的电压。
这样，输出的扫描驱动信号的高低电平分别与上述的两个直流电压输入端TXCOM和VCOM输入的电压一致，从而使得扫描驱动信号满足预定的驱动要求。具体来说，第一直流电压输入端TXCOM输入的电压可以为触控检测芯片所要求的电压，而第二直流电压输入端VCOM输入的电压可以为公共电极的电压。
在一些实施例中，如图1所示，与门模块AND包括一个与非门11(这里称为第一与非门)和反相器21。
第一与非门11连接第二时钟信号输入端CLK2_n和扫描信号输入端STVIN。第一与非门11用于在第二时钟信号输入端CLK2_n和扫描信号输入端STVIN为第一电平时，将第二节点N2置为第二电平。
反相器21连接第二节点N2和第一节点N1。反相器21用于将第一节点N1的电平置为与第二节点N2的电平逻辑上相反的电平。
在一些实施例中，电压转换模块VTR包括第二与非门12、第一晶体管T1、第二晶体管T2，并具有第一直流电压输入端TXCOM和第二直流电压输入端VCOM。
第二与非门12连接第一节点N1和驱动信号输入端TXIN。第二与非门12用于在第一节点N1为第一电平且驱动信号输入端TXIN为第一电平时，将第三节点N3置为第二电平。
第一晶体管T1和第二晶体管T2的栅极连接第三节点N3。第一晶体管T1的源极连接第一直流电压输入端TXCOM，并且第一晶体管T1的漏极连接扫描驱动信号输出端TXOUTx_n。第二晶体管T2的漏极连接扫描驱动信号输出端TXOUTx_n，并且第二晶体管T2的源极连接第二直 流电压输入端VCOM。第一晶体管T1的导通电压为第一电平，第二晶体管T2的导通电压为第二电平。
应当理解的是，第一晶体管T1和第二晶体管T2的源极和漏极通常被制作为对称的，并且因此可互换地使用。
图3为根据图1的实施例的发射电极扫描驱动单元的移位寄存器单元的电路示意图。
参见图3，该移位寄存器单元S/R包括：第一传输门31、第二传输门32和四个反相器22、23、24和25。
第一传输门31的第一控制端P和第二传输门32的第二控制端N均连接第一时钟信号输入端CLK1。第二传输门32的第一控制端P和第一传输门31的第二控制端N均连接第一反相器22的输出端。第一反相器22的输入端连接第一时钟信号输入端CLK1。第二反相器23的输入端连接起始信号输入端STV，第二反相器23的输出端连接第一传输门31的输入端(在图3中，第一传输门31的左侧端子被用作输入端，并且右侧端子被用作输出端)。第一传输门31的输出端连接第二传输门32的输出端(在图3中，第二传输门32的左侧端子被用作输出端，并且右侧端子被用作输入端)。第三反相器24的输入端连接第二传输门32的输出端，并且第三反相器24的输出端连接扫描信号输出端STVOUT。第四反相器25的输入端连接扫描信号输出端STVOUT，并且第四反相器25的输出端连接第二传输门32的输入端。
第一传输门31和第二传输门32中的每个被配置成在其第一控制端P处于第一电平且其第二控制端N处于第二电平时导通，从而将施加到输入端的信号传输到输出端。
下面参照图2和3描述移位寄存器S/R的操作。
在时钟信号输入端CLK1的电平为第一电平时，第一传输门31的第一控制端P处于第一电平，并且第二控制端N处于第二电平。因此，第一传输门31导通，使得在始信号输入端STV输入第一电平的起始信号时，第一传输门31的输入端被置为第二电平，并且因此输出端被置为第二电平。进一步地，第三反相器24将扫描信号输出端STVOUT的电平置为第一电平。第二传输门32的控制端的连接状态与第一传输门31的连接状态相反，从而它们的工作状态也相反。因此，第二传输门32关断。
当时钟信号输入端CLK1的电平变为第二电平时，第一传输门31的第一控制端P处于第二电平，并且第二控制端N处于第一电平。因此，第一传输门31关断，并且第二传输门32导通。由于扫描信号输出端STVOUT的电平为第一电平，所以反相器25会将第二传输门32的输入端的电平置为第二电平。进一步地，第二传输门32将其输出端的电平也置为第二电平，进而第三反相器24将扫描信号输出端STVOUT的电平置为第一电平。
在时钟信号输入端CLK1的电平再次变为第一电平时，第一传输门31再次导通，并且第二传输门32再次关断。但是，由于起始信号输出端STV已经被置为第二电平，所以第一传输门31的输出端的电平被置为第一电平，进而第三反相器24将扫描信号输出端STVOUT的电平置为第二电平。之后，在时钟信号输入端CLK1再次变为第二电平时，第一传输门31关断，并且第二传输门32导通。由于扫描信号输出端STVOUT的电平为第二电平，所以第二传输门32的输入端为第一电平，并且第二传输门32的输出端也为第一电平。进一步地，第三反相器24将扫描信号输出端STVOUT的电平置为第二电平。
应当理解的是，第一传输门31和第二传输门32以及各个反相器22、23、24和25一般具有接入高电压的高电压端VGH和接入低电压的低电压端VGL。为了简单起见，这些高电压端VGH和低电压端VGL在图3中未示出。
图4为根据本公开一实施例的发射电极扫描驱动电路的框图。
参见图4，该发射电极扫描驱动电路包括多个发射电极扫描驱动单元、4条时钟信号线L1、L2_1、L2_2和L2_3、高电压线L5、低电压线L6、起始信号线L7和驱动信号线L8。每一个发射电极扫描驱动单元可以为如上面所述的发射电极扫描驱动单元。
为了便于区分，将第x个的发射电极扫描驱动单元的三个扫描驱动信号输出端分别表示为TXOUTx_1，TXOUTx_2和TXOUTx_3，其中x为大于等于1的整数。
在每个发射电极扫描驱动单元中，第一时钟信号输入端CLK1连接第一时钟信号线L1，第二时钟信号输入端CLK2_1，CLK2_2和CLK2_3一对一连接第二时钟信号线L2_1、L2_2和L2_3，高电压端VGH连接高电压线L5，低电压端VGL连接低电压线L6，并且各驱动信号输入端 TXIN连接驱动信号线L8。
多个发射电极扫描驱动单元被级联在一起。具体地，除最后一个发射电极扫描驱动单元之外，每个发射电极扫描驱动单元的移位寄存器单元S/R的扫描信号输出端STVOUT连接下一个发射电极扫描驱动单元的移位寄存器单元S/R的起始信号输入端STV。另外，第一个发射电极扫描驱动单元的移位寄存器单元S/R的起始信号输入端STV连接起始信号线L7。
图5为示意性示出根据图4的实施例的发射电极扫描驱动电路的操作的时序图。
与上面结合图2描述的操作类似，在包括经由第一时钟信号输入端CLK1提供的第一时钟信号、经由第二时钟信号输入端CLK2_1、CLK2_2和CLK2_3提供的第二时钟信号、经由起始信号输入端STV提供的起始信号和经由驱动信号输入端TXIN提供的驱动信号的输入信号的激励下，发射电极扫描驱动电路的级联的发射电极扫描驱动单元在相应的扫描驱动信号输出端TXOUT1_1、TXOUY1_2、TXOUT1_3...TXOUTm_2和TXOUTm_3(m为发射电极扫描驱动单元的数目)依次输出触摸扫描驱动信号。
根据本公开实施例的一个发射电极扫描驱动单元可以提供多个扫描驱动信号。这使得将发射电极扫描驱动电路分散制作在阵列基板的边框区域内成为可能。这样，就无需使用大量的扇出引线将发射电极连接到阵列基板的边缘。由于扇出引线的减少，还可能的是降低触控装置的边框区域的面积。
虽然在上面的各个实施例中一个发射电极扫描驱动单元被图示和描述为包括三个扫描驱动信号生成单元TX_GEN，但是在其他实施例中，一个发射电极扫描驱动单元可以包括其他数量(比如7个)的TX_GEN。在一个发射电极扫描驱动单元包括7个TX_GEN的实施例中，需要8条时钟信号线，其中一条连接移位寄存器单元的第一时钟信号输入端，并且其他时钟信号线一对一连接7个TX_GEN的第二时钟信号输入端。
如上面描述的发射电极扫描驱动电路可以制作在阵列基板上。具体地，该阵列基板包括基底，通过图案化在其上形成所述发射电极扫描驱动电路。
进一步地，所述阵列基板可以用于制作显示装置。这里的显示装置可以是指手机、平板电脑、导航仪以及其他具有触控和显示功能的产品。
虽然结合附图描述了本公开的实施方式，但是本领域技术人员可以在不脱离本公开的范围的情况下做出各种修改和变型，这样的修改和变型均落入由所附权利要求所限定的范围之内。

Claims (11)

  1. 一种发射电极扫描驱动单元，包括：
    移位寄存器单元，具有起始信号输入端、第一时钟信号输入端和扫描信号输出端；以及
    多个扫描驱动信号生成单元，每一个扫描驱动信号生成单元具有第二时钟信号输入端、扫描信号输入端、驱动信号输入端和扫描驱动信号输出端，所述扫描信号输入端与所述移位寄存器单元的扫描信号输出端相连，
    其中所述移位寄存器单元被适配成：
    响应于第一时钟信号输入端被供应第一有效电平且起始信号输入端被供应具有第一电平的起始信号，将扫描信号输出端置为第一电平；
    响应于第一时钟信号输入端被供应第一有效电平且起始信号输入端被供应与第一电平逻辑上相反的第二电平，将扫描信号输出端置为第二电平；以及
    响应于第一时钟信号输入端被供应无效电平，维持扫描信号输出端的电平保持不变；并且
    其中所述多个扫描驱动信号生成单元中的每个被适配成响应于扫描信号输入端被供应第一电平且第二时钟信号输入端被供应第二有效电平，根据施加到驱动信号输入端的驱动信号生成扫描驱动信号并通过扫描驱动信号输出端输出。
  2. 如权利要求1所述的发射电极扫描驱动单元，其中所述第二有效电平为第一电平，并且其中所述多个扫描驱动信号生成单元中的每个包括与门模块和电压转换模块，其中：
    所述与门模块连接第二时钟信号输入端和扫描信号输入端，并且被适配成响应于第二时钟信号输入端和扫描信号输入端被供应第一电平，将第一节点置为第一电平；并且
    所述电压转换模块连接第一节点、驱动信号输入端和扫描驱动信号输出端且具有第一直流电压输入端和第二直流电压输入端，所述电压转换模块被适配成响应于第一节点处于第一电平且驱动信号输入端被供应第一电平，将扫描驱动信号输出端置为施加到第一直流电压输入端的电压，并且响应于第一节点处于第二电平或驱动信号输入端被 供应第二电平，将扫描驱动信号输出端置为施加到第二直流电压输入端的电压。
  3. 如权利要求2所述的发射电极扫描驱动单元，其中所述与门模块包括第一与非门和反相器，其中：
    所述第一与非门连接第二时钟信号输入端和扫描信号输入端，并且被适配成响应于第二时钟信号输入端和扫描信号输入端被供应第一电平，将第二节点置为第二电平；并且
    所述反相器连接第二节点和第一节点，并且被适配成将第一节点置为与第二节点的电平逻辑上相反的电平。
  4. 如权利要求2所述的发射电极扫描驱动单元，其中所述电压转换模块包括第二与非门、具有为第一电平的导通电压的第一晶体管和具有为第二电平的导通电压的第二晶体管，其中：
    所述第二与非门连接所述第一节点和驱动信号输入端，并且被适配成响应于第一节点处于第一电平且驱动信号输入端被供应第一电平，将第三节点置为第二电平；
    所述第一晶体管具有栅极、源极和漏极，所述栅极连接第三节点，所述源极和漏极中的一个连接第一直流电压输入端，并且另一个连接扫描驱动信号输出端；并且
    所述第二晶体管具有栅极、源极和漏极，所述第二晶体管的栅极连接第三节点，所述第二晶体管的源极和漏极中的一个连接第二直流电压输入端，并且另一个连接扫描驱动信号输出端。
  5. 如权利要求1所述的发射电极扫描驱动单元，其中所述移位寄存器单元包括第一传输门、第二传输门、第一反相器、第二反相器、第三反相器和第四反相器，其中：
    第一传输门具有第一控制端、第二控制端、输入端和输出端，所述第一控制端连接第一时钟信号输入端；
    第二传输门具有第一控制端、连接第一时钟信号输入端的第二控制端、输入端、以及连接第一传输门的输出端的输出端；
    第一反相器具有连接第一时钟信号输入端的输入端以及连接第一传输门的第二控制端和第二传输门的第一控制端的输出端；
    第二反相器具有连接起始信号输入端的输入端和连接第一传输门的输入端的输出端；
    第三反相器具有连接第二传输门的输出端的输入端和连接扫描信号输出端的输出端；并且
    第四反相器具有连接扫描信号输出端的输入端和连接第二传输门的输入端的输出端。
  6. 如权利要求1所述的发射电极扫描驱动单元，其中所述发射电极扫描驱动单元包括三个扫描驱动信号生成单元。
  7. 如权利要求1-6任一项所述的发射电极扫描驱动单元，其中所述第一电平为高电平，第二电平为低电平，第一有效电平为高电平，并且第二有效电平为高电平。
  8. 一种发射电极扫描驱动电路，包括：
    多个如权利要求1-7任一项所述的发射电极扫描驱动单元；
    第一时钟信号线；以及
    多条第二时钟信号线，
    其中所述多个发射电极扫描驱动单元的移位寄存器彼此级联，以使得除最后一个发射电极扫描驱动单元之外所述发射电极扫描驱动单元中的每个的移位寄存器单元的扫描信号输出端连接下一个发射电极扫描驱动单元的移位寄存器单元的起始信号输入端；
    其中所述多个发射电极扫描驱动单元的移位寄存器的第一时钟信号输入端连接第一时钟信号线；并且
    其中每个发射电极扫描驱动单元的所述多个扫描驱动信号生成单元的第二时钟信号输入端一对一连接所述多条第二时钟信号线。
  9. 一种驱动如权利要求8所述的发射电极扫描驱动电路的方法，包括：
    在第一时钟信号线上施加第一时钟信号，其中所述第一时钟信号的时钟脉冲具有为第一有效电平的高电平；
    在所述时钟脉冲之一结束之前，在第一个发射电极扫描驱动单元的移位寄存器的起始信号输入端施加起始信号脉冲，其中该起始信号脉冲不早于该时钟脉冲的结尾且不晚于下一时钟脉冲的开始结束；以及
    在所述多条第二时钟信号线中的每个上施加相应的第二时钟信号，其中各个第二时钟信号的时钟脉冲具有为第二有效电平的高电平，每一个第二时钟信号具有在第一时钟信号的两个时间上相邻的时钟脉 冲之间的时间间隔中的相应时钟脉冲，并且各个时钟脉冲在时间上互不重叠。
  10. 一种阵列基板，包括：
    基底；以及
    如权利要求8所述的发射电极扫描驱动电路，
    其中所述发射电极扫描驱动电路通过图案化形成在所述基底上。
  11. 一种显示装置，包括如权利要求10所述的阵列基板。
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