WO2017128103A1 - 一种内存访问方法、装置及系统架构 - Google Patents

一种内存访问方法、装置及系统架构 Download PDF

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Publication number
WO2017128103A1
WO2017128103A1 PCT/CN2016/072317 CN2016072317W WO2017128103A1 WO 2017128103 A1 WO2017128103 A1 WO 2017128103A1 CN 2016072317 W CN2016072317 W CN 2016072317W WO 2017128103 A1 WO2017128103 A1 WO 2017128103A1
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Prior art keywords
wireless transceiver
target
transceiver antenna
processing unit
memory
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PCT/CN2016/072317
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English (en)
French (fr)
Inventor
陈少杰
杨伟
赵俊峰
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2016/072317 priority Critical patent/WO2017128103A1/zh
Priority to CN201680070340.9A priority patent/CN108475231B/zh
Publication of WO2017128103A1 publication Critical patent/WO2017128103A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation

Definitions

  • the present invention relates to the field of storage technologies, and in particular, to a memory access method, apparatus, and system architecture.
  • the processing unit and the memory unit are separately integrated.
  • the on-chip architecture of the big data high concurrent application is that the processing unit and the memory unit are separately integrated, and the on-chip architecture is microscopic.
  • each processor core running thread application that is, read the corresponding data from the corresponding memory block of the memory stack layer.
  • the traditional 3D stacking architecture adopts a wired interconnection manner. As shown in FIG. 1 , the architecture includes a core layer Layer 2, a switching layer Layer 1 and a memory stack layer Layer 0.
  • the core layer includes a plurality of processor cores
  • the memory stack layer includes multiple The memory block, the memory data message between the processor core and the memory block is transmitted to the corresponding layer through the vertical direction TSV/TSI, and then transmitted to the corresponding memory block or the processor core by the layer 2D routing path, and the 2D routing path is multi-hopped.
  • Node routing is implemented in which multi-port switch switching in the routing module of each hop node implements packet switching. This wired interconnection is fixed and non-reconfigurable, and the routing complexity is high.
  • the embodiment of the invention provides a memory access method, device and system architecture, which can implement a reconfigurable wireless link between a processing unit and a memory unit, and reduce routing complexity.
  • a first aspect of the present invention provides a memory access method, including:
  • the control target processing unit utilizes the transmission of the memory access request data between the first wireless link and the target memory unit. In this manner, each processing unit communicates with each memory unit by establishing a wireless link, so that it can be reconstructed, and communication between different processing units and memory units can be realized by establishing different wireless links.
  • the routing complexity is low.
  • the target processing is established Before the first wireless link between the first wireless transceiver antenna of the unit and the second wireless transceiver antenna of the target memory unit identified by the target identifier, the method further includes:
  • the second wireless transceiver antenna is not within the current radiation angle range of the first wireless transceiver antenna, adjust the radiation direction of the first wireless transceiver antenna such that the second wireless transceiver antenna is within the radiation angle range of the first wireless transceiver antenna.
  • the method further defines that when establishing the first wireless link, determining whether the second wireless transceiver antenna of the target memory unit is within a range of radiation angles of the first wireless transceiver antenna of the target processing unit, thereby determining different wireless link establishment manners.
  • the antenna beam angle can be queried and the radiation direction of the first wireless transceiver antenna of the target processing unit can be adjusted.
  • the establishment of a wireless link thereby expanding the range of memory units that the target processing unit can access.
  • the target data identified by the first wireless transceiver antenna and the target identifier of the target processing unit is established. Before the first wireless link between the second wireless transceiver antennas of the unit, the method further includes:
  • the first wireless transceiver antenna is selected from the at least two wireless transceiver antennas of the shared antenna pool, wherein all processing units share an antenna pool, and when a target processing unit needs to be performed When the memory data is transmitted, the first wireless transceiver antenna can be selected from the antenna pool, thereby achieving the purpose of improving resource utilization by sharing resources.
  • the selecting, by the target processing unit, the first wireless transceiver antenna from the at least two wireless transceiver antennas includes:
  • the wireless transmitting and receiving antenna with the smallest load is selected from the at least two wireless transmitting and receiving antennas as the first wireless transmitting and receiving antenna.
  • the method when establishing the first wireless link between the first wireless transceiver antenna and the second wireless transceiver antenna, the method may be time division multiplexing, in the target time slot of the first wireless transceiver antenna, and the second A first wireless link is established between the wireless transceiver antennas.
  • the fourth feasible implementation manner of the first aspect further includes: if the load of the first wireless transceiver antenna is greater than a preset first threshold, the method further includes:
  • the control target processing unit performs transmission of the memory access request data between the second wireless link and the target memory unit.
  • the target processing unit selects a third wireless transceiver antenna from the antenna pool, and establishes a third wireless transceiver antenna and a second wireless transceiver antenna. a wireless link, so that the target processing unit can transmit and receive the access request data between the first wireless link and the second wireless link and the target memory unit, thereby reducing the overload phenomenon of the first wireless transceiver antenna and reducing
  • the packet loss rate increases the utilization of idle antennas and balances the bandwidth of each wireless transceiver antenna.
  • determining whether the load of the first wireless transceiver antenna is greater than a preset first threshold including:
  • the load of the first wireless transceiver antenna at the current time is predicted by counting the amount of load data of the first wireless transceiver antenna in the at least one historical time slice, thereby determining whether to allocate the third wireless transceiver antenna to the target processing unit, and the prediction mode is accurate.
  • the processing unit is in one-to-one correspondence with the wireless transceiver antenna, if the load of the first wireless transceiver antenna is greater than the pre- The first threshold is set, and the method further includes:
  • the control target processing unit performs transmission of the memory access request data between the third wireless link and the target memory unit.
  • the method is further defined in the scenario that the processing unit is in one-to-one correspondence with the wireless transceiver antenna. If the load of the first wireless transceiver antenna is greater than a preset first threshold, the target processing unit borrows the fourth wireless transceiver antenna of the auxiliary processing unit. Establishing a third wireless link with the second wireless transceiver antenna, thereby reducing the load of the first wireless transceiver antenna and balancing the amount of load data of each wireless transceiver antenna.
  • the selection of the auxiliary processing unit may include:
  • a second aspect of the present invention provides a memory access device, including:
  • a receiving module configured to receive an access request of the target processing unit, where the access request carries a target identifier of the target memory unit to be accessed by the target processing unit;
  • a control module configured to control, by the target processing unit, the transmission of the memory access request data by using the first wireless link and the target memory unit.
  • each processing unit communicates with each memory unit by establishing a wireless link, so that it can be reconstructed, and communication between different processing units and memory units can be realized by establishing different wireless links.
  • the routing complexity is low.
  • the device further includes:
  • a determining module configured to determine whether the second wireless transceiver antenna is within a current radiation angle range of the first wireless transceiver antenna
  • the adjusting module is configured to adjust a radiation direction of the first wireless transceiver antenna if the second wireless transceiver antenna is not within a current radiation angle range of the first wireless transceiver antenna, so that the second wireless transceiver antenna is in a radiation angle range of the first wireless transceiver antenna Inside.
  • the method further defines that when establishing the first wireless link, determining whether the second wireless transceiver antenna of the target memory unit is within a range of radiation angles of the first wireless transceiver antenna of the target processing unit, thereby determining different wireless link establishment manners.
  • the antenna beam angle can be queried and the radiation direction of the first wireless transceiver antenna of the target processing unit can be adjusted.
  • the establishment of a wireless link thereby expanding the range of memory units that the target processing unit can access.
  • the apparatus further includes:
  • the first selection module is configured to select a first wireless transceiver antenna from the at least two wireless transceiver antennas for the target processing unit, and establish a connection between the first wireless transceiver antenna and the target processing unit.
  • the first wireless transceiver antenna is selected from the at least two wireless transceiver antennas of the shared antenna pool, wherein all processing units share an antenna pool, and when a target processing unit needs to be performed When the memory data is transmitted, the first wireless transceiver antenna can be selected from the antenna pool, thereby achieving the purpose of improving resource utilization by sharing resources.
  • the first selection module is specifically configured to acquire each of the at least two wireless transceiver antennas in the antenna pool. And loading the lowest wireless transceiver antenna from the at least two wireless transceiver antennas as the first wireless transceiver antenna. In this way, the wireless transceiver antenna with the smallest load is selected from the antenna pool as the first wireless transceiver antenna, so that the wireless transceiver antenna resources with relatively small load can be fully utilized, and the antenna resource utilization rate can be improved.
  • the first wireless link may be established between the target time slot of the first wireless transceiver antenna and the second wireless transceiver antenna by means of time division multiplexing.
  • the fourth feasible implementation manner of the second aspect The device further includes: if the load of the first wireless transceiver antenna is greater than a preset first threshold, the apparatus further includes:
  • a second selecting module configured to select a third wireless transceiver antenna from the at least two wireless transceiver antennas for the target processing unit
  • the establishing module is further configured to establish a connection between the target processing unit and the third wireless transceiver antenna, and establish a third wireless transceiver antenna of the target processing unit and a second wireless transceiver antenna of the target memory unit identified by the target identifier. a second wireless link between;
  • the control module is further configured to control, by the target processing unit, the transmission of the memory access request data between the second wireless link and the target memory unit.
  • the target processing unit selects a third wireless transceiver antenna from the antenna pool, and establishes a third wireless transceiver antenna and a second wireless transceiver antenna. a wireless link, so that the target processing unit can transmit and receive the access request data between the first wireless link and the second wireless link and the target memory unit, thereby reducing the overload phenomenon of the first wireless transceiver antenna and reducing
  • the packet loss rate increases the utilization of idle antennas and balances the bandwidth of each wireless transceiver antenna.
  • determining whether the load of the first wireless transceiver antenna is greater than a preset first threshold including:
  • the load of the first wireless transceiver antenna at the current time is predicted by counting the amount of load data of the first wireless transceiver antenna in the at least one historical time slice, thereby determining whether to allocate the third wireless transceiver antenna to the target processing unit, and predicting The method is accurate.
  • the processing unit has a one-to-one correspondence with the wireless transceiver antenna. If the load of the first wireless transceiver antenna is greater than a preset first threshold, the apparatus further includes
  • the establishing module is further configured to establish a connection relationship between the target processing unit and the auxiliary processing unit, and establish a third wireless link between the fourth wireless transceiver antenna and the second wireless transceiver antenna of the auxiliary processing unit;
  • the control module is further configured to control, by the target processing unit, the transmission of the memory access request data between the third wireless link and the target memory unit.
  • the method is further defined in the scenario that the processing unit is in one-to-one correspondence with the wireless transceiver antenna. If the load of the first wireless transceiver antenna is greater than a preset first threshold, the target processing unit borrows the fourth wireless transceiver antenna of the auxiliary processing unit. Establishing a third wireless link with the second wireless transceiver antenna, thereby reducing the load of the first wireless transceiver antenna and balancing the amount of load data of each wireless transceiver antenna.
  • the selection of the auxiliary processing unit may include:
  • a third aspect of the present invention provides a memory access system architecture, including a core layer and a memory stack layer, wherein the core layer and the memory stack layer communicate by wireless signals, and the core layer includes At least two processing units and a global memory controller, the memory stack layer including at least two memory units;
  • the global memory controller establishes a wireless link between a wireless transceiver antenna of the target processing unit and a wireless transceiver antenna of the target memory unit identified by the target identifier;
  • the global memory controller controls the target processing unit to perform transmission of the memory access request data between the wireless link and the target memory unit.
  • each processing unit communicates with each memory unit by establishing a wireless link, so that it can be reconstructed, and communication between different processing units and memory units can be realized by establishing different wireless links.
  • the routing complexity is low.
  • a fourth aspect of the present invention provides a readable medium comprising instructions for executing, when the memory controller executes the execution instruction, the memory controller can perform any one of the possible implementations of the first aspect.
  • a fifth aspect of the present invention provides a memory controller including a processor, a memory, and a bus;
  • the memory is used to store execution instructions, and the processor and the memory are connected by a bus.
  • the processor executes execution instructions stored in the memory, so that the memory controller performs any feasible implementation of the first aspect. the way.
  • an access request of the target processing unit is received, where the access request carries a target identifier of the target memory unit to be accessed by the target processing unit, and the first wireless transceiver antenna of the target processing unit is identified by the target identifier.
  • a first wireless link between the second wireless transceiver antennas of the target memory unit, the control target processing unit uses the first wireless link and the target memory unit to perform transmission of the memory access request data, and the target processing unit
  • the target memory unit performs the transmission of the memory access request data by establishing a wireless link, and has strong reconfigurability, low routing complexity, and small delay.
  • FIG. 1 is a schematic diagram of an on-chip architecture in the prior art according to an embodiment of the present invention
  • FIG. 2 is a schematic flowchart of a memory access method according to an embodiment of the present invention.
  • FIG. 3 is a schematic flowchart diagram of another memory access method according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of a reconfigurable on-chip architecture according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of establishing a wireless link between a processing unit and a wireless transceiver antenna of a memory unit according to an embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of establishing a wireless link between another processing unit and a wireless transceiver antenna of a memory unit according to an embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of an internal structure of an on-chip architecture according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of memory access intensive according to an embodiment of the present invention.
  • FIG. 9 is a schematic diagram of memory access sparseness according to an embodiment of the present invention.
  • FIG. 10 is a schematic diagram of four memory access comparisons according to an embodiment of the present invention.
  • FIG. 11 is a schematic structural diagram of a memory access device according to an embodiment of the present disclosure.
  • FIG. 12 is a schematic structural diagram of another memory controller according to an embodiment of the present invention.
  • the wireless transceiver antenna (for example, the first wireless transceiver antenna, the second wireless transceiver antenna, the third wireless transceiver antenna, and the fourth wireless transceiver antenna) in the embodiment of the present invention may be an antenna or an antenna array.
  • the wireless transceiver antenna of the processing unit may be in the form of an antenna pool, that is, all processing units share multiple wireless transceiver antennas in the antenna pool, when the target processing When the unit needs to access the target memory unit, the first wireless transceiver antenna is selected from the shared antenna pool for communication.
  • the processing unit and the wireless transceiver antenna may have a one-to-one correspondence, that is, one processing unit is provided with a wireless transceiver antenna, and when the target processing unit needs to access the target memory unit, That is, the first wireless transceiver antenna of the target processing unit is used for communication.
  • the memory access method of the embodiment of the present invention may be applied to a multi-core shared memory 3D integrated on-chip architecture, where the on-chip architecture includes a core layer and a memory stack layer, and the core layer includes multiple processing units (eg, a processor core).
  • the global memory controller the memory stack layer includes a plurality of memory units (such as a memory block RAM Cluster), and the core layer and the memory stack layer communicate by wireless signals.
  • the global memory controller is mainly used for scheduling the establishment and deletion of the wireless link between the wireless transceiver antenna of each processing unit and the wireless transceiver antenna of each memory unit, so that any processing unit can implement any memory through the wireless link.
  • the data is transmitted and received between the units, with strong reconfiguration, low routing complexity, and point-to-point data transmission, so the delay is small.
  • the memory access method of the embodiment of the present invention may also be applied to a single-board chassis, where the single-board chassis includes a chassis, and the upper chassis of the chassis includes multiple processing units (for example, a processor or a processor). Core), the lower chassis of the rack includes a plurality of memory units (for example, a memory module), and a wireless link between the wireless transceiver antennas of the respective memory units is established through the wireless transceiver antennas of the respective processing units, thereby passing The wireless link implements transceiving of data accessed between each processing unit and the corresponding memory unit.
  • the single-board chassis includes a chassis
  • the upper chassis of the chassis includes multiple processing units (for example, a processor or a processor).
  • Core the lower chassis of the rack includes a plurality of memory units (for example, a memory module)
  • a wireless link between the wireless transceiver antennas of the respective memory units is established through the wireless transceiver antennas of the respective processing units, thereby passing
  • the wireless link implements trans
  • the applicable scenarios of the memory access method in this embodiment include but are not limited to the foregoing two scenarios, and the foregoing two applicable scenarios are merely examples.
  • FIG. 2 is a schematic flowchart of a memory access method according to an embodiment of the present invention. As shown in the figure, the memory access method in this embodiment includes steps S200-S202;
  • S200 Receive an access request of a target processing unit, where the access request carries a target identifier of a target memory unit to be accessed by the target processing unit.
  • the target processing unit may be a processor or a processor core, and the processor may include a central processing unit (CPU), an image processor, and the like, which are not limited herein.
  • the present invention does not limit the form of existence of the target processing unit.
  • the target processing unit can run various applications and individual threads, and the target processing unit can read data or store data to any one of the target memory units in the memory stack layer.
  • the target memory unit may be a memory block or a memory module of the memory stack layer, which is not limited herein.
  • the target processing unit is provided with a wireless transceiver antenna and a circuit
  • the target memory unit is also provided with a wireless transceiver antenna and circuit, as shown in FIG. 5, which is a target processing unit and target provided by the embodiment of the present invention.
  • FIG. 5 is a target processing unit and target provided by the embodiment of the present invention.
  • Each processor core is provided with a modulation circuit to modulate the memory of the target processor core.
  • the carrier wave is sent to the wireless transceiver antenna of the corresponding memory block through the wireless transceiver antenna, and the wireless transceiver antenna of the target processor core can also receive the response data of the corresponding memory block.
  • the signal transmitted by the target processor core through the wireless transceiver antenna is received through the wireless transceiver antenna of the memory block, and then the received signal is demodulated by the demodulation circuit, thereby obtaining the memory of the target processor core.
  • the data is requested, and finally the corresponding response data is returned for the memory access data, and the return of the response data is also transmitted through the wireless transceiver antenna of the memory block.
  • the transmission of the memory access request data between each processor core and each memory block is based on a wireless link established between the processor core and the memory block, when the target processor core When accessing the target memory block, the first wireless link between the target processor core and the target memory block needs to be established in advance.
  • the transmission of the memory access request data is performed based on the first wireless link, so each processor core can establish a wireless link with any one of the memory blocks to implement point-to-point communication.
  • FIG. 6 another target processing unit and a target memory list according to an embodiment of the present invention are provided.
  • each processor core does not have a one-to-one correspondence with the wireless transceiver antenna, but all processor cores share an antenna pool, and the shared antenna pool and processing The cores are connected through a switching network, and any one of the processor cores can use any one of the antennas in the antenna pool to transmit the access request data.
  • the circuit structure of each wireless transceiver antenna in the antenna pool is the same as that of FIG. 5.
  • the access request is sent to the global memory controller, where the access request carries the target identifier of the target memory unit, and the global memory controller performs the establishment of the wireless link according to the access request and Scheduling.
  • FIG. 4 it is a memory access system architecture diagram provided by an embodiment of the present invention.
  • the global memory controller performs wireless link configuration, and any processing unit (processor core) of the core layer can access the memory stack layer.
  • any processing unit processor core
  • the wireless link is established and scheduled according to the target identifier of the target memory block in the access request.
  • the processing unit of each layer in the memory access system architecture integrates the wireless transceiver antenna and the circuit, and the memory unit of each layer also integrates the wireless transceiver antenna and the circuit, and the interlayer communication is performed wirelessly through the antenna array through the antenna array.
  • the wave speed scanning changes the link direction to form a reconfigurable wireless link, so that each processing unit can directly access several adjacent memory units, and the routing complexity is greatly simplified.
  • the global memory controller establishes a first wireless link between the first wireless transceiver antenna of the target processing unit and the second wireless transceiver antenna of the target memory unit identified by the target identifier, and it should be noted that the first target processing unit is usually
  • the wireless transceiver antenna has a limited range of radiation angles, so it is necessary to further determine whether the second wireless transceiver antenna of the target memory unit is within the current radiation angle range of the first wireless transceiver antenna of the target processing unit.
  • steps S20-S21 may be further included;
  • the current radiation angle of the first wireless transceiver antenna of the target processing unit is usually A plurality of memory units may be included in the range, and the multiple memory units may be all memory units of the system architecture, or may be part of all memory units of the system architecture.
  • the wireless link can be established only when the wireless transceiver antenna of the memory unit is within the current radiation angle range of the processing unit, so before the first wireless link between the first wireless transceiver antenna and the second wireless transceiver antenna is established, Make a judgment.
  • the determining manner may be: whether the second wireless transceiver antenna of the target memory unit identified by the global memory controller querying the target identifier is within a current radiation angle range of the first wireless transceiver antenna of the target processing unit, and is stored in the system architecture.
  • the memory unit of each processing unit's wireless transceiver antenna is in various radiation angle ranges.
  • the target processing unit cannot directly access the target.
  • a memory unit that queries an antenna beam angle and a transmission power between the first wireless transceiver antenna of the target processing unit and the second wireless transceiver antenna of the target memory unit.
  • the global memory controller notifies the antenna array beamforming unit to adjust the radiation direction of the first wireless transceiver antenna of the target processing unit, and adjusts it to the queried antenna beam angle, so that the second wireless transceiver antenna is in the radiation of the first wireless transceiver antenna.
  • the global memory controller notifies the transmitter to adjust the transmit power of the first wireless transmit and receive antenna of the target processing unit, and establishes a second wireless transmit and receive antenna with the target memory unit by using the first wireless transmit and receive antenna of the adjusted target processing unit.
  • the first wireless transceiver antenna and the target of the target processing unit may be directly established. a first wireless link between the second wireless transmit and receive antennas of the memory unit.
  • the target processing unit is controlled to perform transmission of the memory access request data by using the first wireless link and the target memory unit.
  • the global memory controller controls the target processing unit to utilize the first The transmission of the fetched data between the line link and the target memory unit. It should be noted that, before the target processing unit and the target memory unit perform the memory access request data transmission, the global memory controller starts the wireless memory initialization training, and the channel establishment is successful after the training ends.
  • the wireless memory initialization training mode is The first wireless transceiver antenna of the target processing unit always transmits the training data until the second wireless transceiver antenna of the target memory unit receives the data under the specified bit error rate and the sensitivity reaches the threshold value, indicating that the wireless memory initialization training is successful. The channel of the first wireless link is successfully established.
  • the global memory controller controls the target processing unit to send the memory access request data to the target memory unit through the first wireless link, and the target memory unit performs a memory access request and returns data or a response that the target processing unit needs to read. Further, the global memory controller determines whether the first wireless link needs to be closed according to the access frequency of the target memory unit in the historical time slice, thereby reducing energy consumption.
  • the method may further include the following steps S203-S205, or the method may further include the following Steps S206-S207; wherein, steps S203-S205 are balance strategies proposed for the scenario of the shared antenna pool shown in FIG. 6, and steps S206-S207 are for the processing unit shown in FIG. 5 and the wireless transceiver antennas are in one-to-one correspondence.
  • steps S203-S205 are balance strategies proposed for the scenario of the shared antenna pool shown in FIG. 6, and steps S206-S207 are for the processing unit shown in FIG. 5 and the wireless transceiver antennas are in one-to-one correspondence.
  • the determining method for determining whether the load of the first wireless transceiver antenna is greater than a preset first threshold may include the following steps:
  • Step 1 Acquire a load data amount of each historical time slice in the at least one historical time slice of the first wireless transceiver antenna that is closest to the current time;
  • the load data amount of the first wireless transceiver antenna is the data amount of the memory access request data transmission between the first wireless transceiver antenna and the memory unit.
  • the global memory controller acquires the amount of load data of the first wireless transceiver antenna of each historical time slice of the first wireless transceiver antenna in at least one historical time slice closest to the current time.
  • the amount of load data for each wireless transceiver antenna can be monitored by a third party, and the global memory controller can directly obtain the load of each historical time slice of the first wireless transceiver antenna in at least one historical time slice from a third party. The amount of data. As shown in FIG.
  • the first wireless transmitting and receiving antenna may be any one of the wireless transmitting/receiving antenna 1 to the wireless transmitting/receiving antenna 4.
  • Step 2 determining load data of the first wireless transceiver antenna in each of the historical time slices Whether the quantity exceeds the first preset threshold; or the amount of load data of each historical time slice in the historical time slice of the first wireless transceiver antenna exceeding the preset number in the at least one historical time slice is greater than the preset number A threshold.
  • the global memory controller determines whether the load data amount of the first wireless transceiver antenna in each of the counted historical time slices exceeds a preset first threshold. As shown in FIG. 8, the statistics T3 can be selected. The amount of load data of the first wireless transceiver antenna in the four historical time slices of T6 is judged. As shown in the figure, if the first wireless transceiver antenna is the wireless transceiver antenna 2 or the wireless transceiver antenna 3, the load data amount of the first wireless transceiver antenna in the historical time slice T3-T6 is greater than a preset first threshold.
  • the amount of load data of the first wireless transceiver antenna of each historical time slice may not be greater than a preset first threshold, for example, as long as there is more than
  • the amount of load data of the first wireless transceiver antenna of each historical time slice in the preset number of historical time slices may be greater than a preset first threshold. For example, if four historical time slices are counted, only three historical time periods are available.
  • the load data amount of the first wireless transceiver antenna of the slice is greater than a preset first threshold to determine that the load of the first wireless transceiver antenna is greater than a preset first threshold.
  • steps S203-S205 including steps S203-S205;
  • the global memory controller schedules all the wireless transceiver antennas, and selects a third wireless transceiver antenna for the target processing unit from at least two wireless transceiver antennas of the antenna pool, as shown in FIG. 6, where the processing unit is used as a processor core.
  • the processor cores share the wireless transceiver antennas in the antenna pool.
  • the global memory controller processes the target from the shared antenna pool.
  • the unit selects a third wireless transceiver antenna and establishes a connection between the third wireless transceiver antenna and the target memory unit through the switching network.
  • the criteria for selecting the third wireless transceiver antenna may include multiple, for example, The idle antenna is selected as the third wireless transceiver antenna from the shared antenna pool, or the antenna with less memory access request data sent or received in the most recent historical time slices may be selected, or the current load may be selected to be relatively small.
  • the antenna is used as the third wireless transceiver antenna and the like, and is not limited herein.
  • the global memory controller establishes a second wireless link between the third wireless transceiver antenna and the second wireless transceiver antenna of the target memory unit. It should be noted that the third wireless transceiver antenna and the target memory unit are established. When the second wireless link between the second wireless transceiver antennas is also required to determine whether the second wireless transceiver antenna is within the current radiation angle range of the third wireless transceiver antenna, different wireless link establishment manners are adopted, and the specific establishment manner is adopted. The manner of establishing the first wireless link between the first wireless transceiver antenna of the target processing unit and the second wireless transceiver antenna of the target memory unit may be referred to, and details are not described herein again.
  • S205 Control the target processing unit to perform transmission of the memory access request data by using the second wireless link and the target memory unit.
  • the global memory controller controls the target processing unit to perform the transmission of the memory access request data between the second wireless link and the target memory unit.
  • the access request data may be transmitted between the target memory unit by means of frequency division multiplexing, and the second wireless transceiver antenna of the target memory unit. It is an omnidirectional antenna, so it can simultaneously receive the memory access request data of each wireless link.
  • the second wireless transceiver antenna of the target memory unit finally acquires the memory access request data by means of frequency division multiplexing.
  • the steps include steps S206-S207;
  • the processing unit and the wireless transceiver antenna have a one-to-one correspondence, as shown in FIG. 5, that is, a scene in which the processing unit and the wireless transceiver antenna are in one-to-one correspondence.
  • the auxiliary processing unit needs to be selected, and the connection relationship between the target processing unit and the auxiliary processing unit is established, and the auxiliary processing needs to be explained.
  • the invention is not limited. For example, you can choose to minimize the load in all processing units.
  • the processing unit may also be a processing unit that first acquires the load of the wireless transmitting and receiving antenna of each of the processing units and minimizes the load of the wireless transmitting and receiving antenna.
  • the processing unit and the auxiliary processing unit can communicate with each other to complete the routing of the memory access request data.
  • FIG. 7 it is a multi-core provided by the embodiment of the present invention.
  • the processing unit is the processor core
  • the memory unit is the memory block
  • the figure includes eight processor cores and eight memory blocks, as shown in the figure, each processor core There is also a routing path between them, and a connection relationship can be established.
  • the global memory controller dynamically schedules the wireless link bandwidth resources, and the memory data of each processor core is processed by the address decoder, data queue, and request queue of the global memory controller.
  • one channel corresponds to the wireless transceiver antenna of one processor core, as shown in the figure, it is assumed that the processor core 3 is the target processing unit, the memory block 1 is the target memory unit, and the processor core 3 is wireless.
  • the load of the transceiver antenna in the last few historical time slices is greater than the preset first threshold, and the processor core 1 and the processor core 2 may be selected as the auxiliary processor core, and The wireless transceiver antenna of the processor core 1 and the processor core 2 is used as the fourth wireless transceiver antenna, and the third wireless link between the fourth wireless transceiver antenna and the memory block 1 is established, that is, the channel is merged to meet the high bandwidth requirement. .
  • the target processing unit is controlled to perform transmission of the memory access request data by using the third wireless link and the target memory unit.
  • control target processing unit uses the third wireless link and the target memory unit to perform the transmission of the memory access request data.
  • first wireless link and the third wireless link may be The transmission of the memory access request data is performed by means of frequency division multiplexing.
  • the embodiment of the present invention can further improve the low bandwidth utilization by using single channel splitting of the wireless transceiver antenna. For example, if a certain memory unit access is sparse, a wireless transceiver antenna can be channel split. .
  • the target memory unit is taken as an example here, and the global memory controller determines whether the number of accesses of each historical time slice of the target memory unit in each of the most recent historical time slices is lower than a preset threshold.
  • the threshold can be set according to the actual situation. As shown in FIG. 9, the number of accesses of the memory block 2 and the memory block 3 in each historical time slice is relatively small, and the access is sparse. If the target memory unit is memory block 2 or memory block 3, it belongs to memory with sparse access.
  • the unit further selects an alternate memory unit that is adjacent to the target memory unit and has access to sparse access.
  • the target processing unit is the processor core 7
  • the target memory unit is the memory block 6, and the number of accesses of the memory block 6 in the latest historical time slice is relatively small, in order to improve the processor.
  • the memory block 5 and the memory block 7 which are adjacent to the memory block 6 and are relatively sparsely accessed are selected as the candidate memory blocks.
  • the first wireless transceiver antenna of the target processing unit performs single channel splitting to improve low bandwidth utilization
  • the specific splitting manner may be that the transmit beam scanning of the wireless transceiver antenna of the target processing unit is different.
  • the independent time slot and the different memory units perform the transmission of the memory access request data, and the first time between the first wireless transceiver antenna of the target processing unit and the second wireless transceiver antenna of the target memory unit is established in the target time slot.
  • Wireless link Specifically, as shown in FIG.
  • the wireless transceiver antenna of the processor core 7 performs the transmission of the memory access request data between the memory blocks 5 and the memory block 7 in different time slots, wherein, in one time slot, processing A wireless link is established between the wireless transceiver antenna of the core 7 and a memory block for communication.
  • the first wireless transceiver antenna of the target processing unit may also implement communication with different memory units by dividing the antenna array (distribution directivity of each sub-antenna array).
  • an access request of the target processing unit is received, where the access request carries a target identifier of the target memory unit to be accessed by the target processing unit, and the first wireless transceiver antenna of the target processing unit is identified by the target identifier.
  • a first wireless link between the second wireless transceiver antennas of the target memory unit, the control target processing unit uses the first wireless link and the target memory unit to perform transmission of the memory access request data, and the target processing unit
  • the target memory unit performs the transmission of the memory access request data by establishing a wireless link, and has strong reconfigurability, low routing complexity, and small delay.
  • FIG. 3 is a schematic flowchart of another memory access method according to an embodiment of the present invention. As shown in the figure, the memory access method in this embodiment includes:
  • S300 Receive an access request of a target processing unit, where the access request carries a target identifier of a target memory unit to be accessed by the target processing unit.
  • step S300 of the embodiment of the present invention refer to step S200 of the embodiment of FIG. 2, and details are not described herein again.
  • all processing units share an antenna pool, and the antenna pool includes multiple wireless transceiver antennas.
  • the target antenna unit is targeted from at least two wireless transceiver antennas of the shared antenna pool.
  • the processing unit selects the first wireless transceiver antenna and establishes a connection between the first wireless transceiver antenna and the target processing unit. It should be noted that the selection manner of the first wireless transceiver antenna from the shared antenna pool may be various, for example, the idle antenna may be selected from the shared antenna pool as the first wireless transceiver antenna, or may be the shared antenna pool.
  • the antenna with the smallest load is selected as the first wireless transceiver antenna, or one of the plurality of wireless transceiver antennas having a load below a certain threshold is randomly selected as the first wireless transceiver antenna.
  • the selection manner is not limited herein.
  • the selecting the first wireless transceiver antenna from the at least two wireless transceiver antennas for the target processing unit includes the following two steps:
  • Step 1 acquire a load of each of the at least two wireless transceiver antennas
  • Step 2 Select the first wireless transceiver antenna with the smallest load from the at least two wireless transceiver antennas.
  • the antenna with the smallest load is selected from the plurality of wireless transceiver antennas of the antenna pool as the first wireless transceiver antenna, and the first wireless transceiver antenna carries the transmission of other memory access request data, and simultaneously carries the target processing unit.
  • the other memory access request data may be the memory access request data of the other memory unit to the target memory unit, or the memory processing request data of the other memory unit except the target memory unit. . If other processing units access the memory request data of the target memory unit, the embodiment may route the memory access request data of the other processing unit to the target processing unit, and control the first wireless transceiver antenna of the target processing unit to adopt the time division.
  • the multiplexing method separately transmits different memory access request data between different memory units.
  • the target processing unit is controlled to perform transmission of the memory access request data by using the first wireless link and the target memory unit.
  • steps S302-S303 of the embodiment of the present invention refer to steps S201-S202 of the embodiment of FIG. 2, and details are not described herein again.
  • an access request of a target processing unit is received, and the access request carries the item a target identifier of the target memory unit to be accessed by the target processing unit, establishing a first wireless link between the first wireless transceiver antenna of the target processing unit and the second wireless transceiver antenna of the target memory unit identified by the target identifier, the control target
  • the processing unit uses the first wireless link and the target memory unit to perform the transmission of the memory access request data. In this manner, the target processing unit and the target memory unit perform the transmission of the memory access request data by establishing a wireless link. Strong, and the routing complexity is low, and the delay is small.
  • FIG. 11 is a schematic structural diagram of a memory access device according to an embodiment of the present invention. As shown in the figure, a memory access device according to an embodiment of the present invention includes:
  • the receiving module 100 is configured to receive an access request of the target processing unit, where the access request carries a target identifier of the target memory unit to be accessed by the target processing unit;
  • the establishing module 101 is configured to establish a first wireless link between the first wireless transceiver antenna of the target processing unit and the second wireless transceiver antenna of the target memory unit identified by the target identifier;
  • the control module 102 is configured to control the target processing unit to perform transmission of the memory access request data between the first wireless link and the target memory unit.
  • the device may further include a determining module 103 and an adjusting module 104;
  • the determining module 103 is configured to determine whether the second wireless transceiver antenna is within a current radiation angle range of the first wireless transceiver antenna;
  • the adjusting module 104 is configured to adjust a radiation direction of the first wireless transceiver antenna to make the second wireless transceiver antenna if the second wireless transceiver antenna is not within a current radiation angle range of the first wireless transceiver antenna It is within the range of radiation angles of the first wireless transceiver antenna.
  • the device may further include a first selection module 105;
  • the first selection module 105 is configured to select the first wireless transceiver antenna from the at least two wireless transceiver antennas for the target processing unit, and establish a connection between the first wireless transceiver antenna and the target processing unit.
  • the first selection module 105 is specifically configured to acquire a load of each of the at least two wireless transceiver antennas, and select the first wireless with the smallest load from the at least two wireless transceiver antennas. Transceiver antenna.
  • all processing units share an antenna pool, where the antenna pool includes at least two wireless transceiver antennas. If the load of the first wireless transceiver antenna is greater than a preset first threshold, the apparatus further includes a second Selection module 106;
  • the second selecting module 106 is configured to select a third wireless transceiver antenna for the target processing unit from the at least two wireless transceiver antennas;
  • the establishing module 101 is further configured to establish a connection between the target processing unit and the third wireless transceiver antenna, and establish a third wireless transceiver antenna of the target processing unit and a target memory unit identified by the target identifier. a second wireless link between the two wireless transceiver antennas;
  • the control module 102 is further configured to control the target processing unit to perform transmission of the memory access request data between the second wireless link and the target memory unit.
  • the establishing module 101 is further configured to establish the target processing unit and the auxiliary processing. a connection relationship between the units, and establishing a third wireless link between the fourth wireless transceiver antenna of the auxiliary processing unit and the second wireless transceiver antenna;
  • the control module 102 is further configured to control the target processing unit to perform transmission of the memory access request data between the third wireless link and the target memory unit.
  • an access request of the target processing unit is received, where the access request carries a target identifier of the target memory unit to be accessed by the target processing unit, and the first wireless transceiver antenna of the target processing unit is identified by the target identifier.
  • a first wireless link between the second wireless transceiver antennas of the target memory unit, the control target processing unit uses the first wireless link and the target memory unit to perform transmission of the memory access request data, and the target processing unit
  • the target memory unit performs the transmission of the memory access request data by establishing a wireless link, and has strong reconfigurability, low routing complexity, and small delay.
  • the memory controller 40 includes a processor 401, a memory 402, and a bus 403.
  • the processor 401 and the memory 402 are both The bus 403 is connected, the memory is used to store the execution instructions, and the processor 401 calls the execution instructions stored in the memory 402:
  • the processor 401 is configured to receive an access request of the target processing unit, where the access request carries a target identifier of the target memory unit to be accessed by the target processing unit;
  • the processor 401 is further configured to establish a first wireless link between the first wireless transceiver antenna of the target processing unit and the second wireless transceiver antenna of the target memory unit identified by the target identifier;
  • the processor 401 is further configured to control the target processing unit to perform transmission of the memory access request data between the first wireless link and the target memory unit.
  • the processor 401 is further configured to determine whether the second wireless transceiver antenna is within a current radiation angle range of the first wireless transceiver antenna;
  • the second wireless transceiver antenna is not within the current radiation angle range of the first wireless transceiver antenna, adjusting a radiation direction of the first wireless transceiver antenna, so that the second wireless transceiver antenna is in the first wireless The radiation angle of the transceiver antenna is within the range.
  • the processor 401 is further configured to select the first wireless transceiver antenna from the at least two wireless transceiver antennas for the target processing unit, and establish a connection between the first wireless transceiver antenna and the target processing unit.
  • the selecting the first wireless transceiver antenna from the at least two wireless transceiver antennas for the target processing unit includes:
  • the processor 401 is further configured to acquire a load of each of the at least two wireless transceiver antennas;
  • the processor 401 is further configured to select the first wireless transceiver antenna with the smallest load from the at least two wireless transceiver antennas.
  • the processor 401 is further configured to: select, from the at least two wireless transceiver antennas, a third wireless transceiver antenna for the target processing unit, and establish a connection between the target processing unit and the third wireless transceiver antenna;
  • the processor 401 is further configured to establish a second wireless link between the third wireless transceiver antenna of the target processing unit and the second wireless transceiver antenna of the target memory unit identified by the target identifier;
  • the processor 401 is further configured to control, by the target processing unit, the transmission of the memory access request data by using the second wireless link and the target memory unit.
  • the processing unit is in one-to-one correspondence with the wireless transceiver antenna, the load of the first wireless transceiver antenna is greater than a preset first threshold;
  • the processor 401 is further configured to establish a connection relationship between the target processing unit and the auxiliary processing unit, and establish a third wireless chain between the fourth wireless transceiver antenna of the auxiliary processing unit and the second wireless transceiver antenna. road;
  • the processor 401 is further configured to control, by the target processing unit, the transmission of the memory access request data by using the third wireless link and the target memory unit.
  • an access request of the target processing unit is received, where the access request carries a target identifier of the target memory unit to be accessed by the target processing unit, and the first wireless transceiver antenna of the target processing unit is identified by the target identifier.
  • a first wireless link between the second wireless transceiver antennas of the target memory unit, the control target processing unit uses the first wireless link and the target memory unit to perform transmission of the memory access request data, and the target processing unit
  • the target memory unit performs the transmission of the memory access request data by establishing a wireless link, and has strong reconfigurability, low routing complexity, and small delay.
  • FIG. 4 is a structural diagram of a memory access system according to an embodiment of the present invention.
  • the system architecture includes a core layer and a memory stack layer, and the core layer includes multiple processor cores and global memory.
  • the memory block includes eight
  • the core layer Any one of the processor cores can access any one of the eight memory blocks by configuring the wireless link.
  • the following takes an example of the target processor core pre-accessing the target memory block as an example.
  • the global memory controller receives an access request of a target processor core, where the access request carries a target identifier of a target memory block pre-accessed by the target processor core;
  • the global memory controller establishes a wireless link between a wireless transceiver antenna of the target processor core and a wireless transceiver antenna of the target memory block identified by the target identifier;
  • the global memory controller controls the target processor core to perform transmission of the memory access request data between the wireless link and the target memory block.
  • the wireless transceiver antenna of the target processor core communicates with the core5 MEM DIE by transmitting frequency division multiplexing with other idle antennas, and the wireless transceiver antenna of the core5 MEM DIE obtains corresponding information by means of frequency division multiplexing.
  • the memory access request data If there is a localized memory-intensive access in the system architecture, that is, the figure in the upper left corner of FIG. 10, that is, the memory block of only the processor core 5 in all the memory blocks (core5 MEM DIE) If the access is dense, the wireless transceiver antenna of the target processor core communicates with the core5 MEM DIE by transmitting frequency division multiplexing with other idle antennas, and the wireless transceiver antenna of the core5 MEM DIE obtains corresponding information by means of frequency division multiplexing.
  • the memory access request data If there is a localized memory-intensive access in the system architecture, that is, the figure in the upper left corner of FIG. 10, that is, the memory block of only the processor core 5 in all the memory blocks
  • Radio frequency for example, divides the radio cores of the processor core 1, the processor core 2, and the processor core 3 into a group for transmitting frequency division multiplexing access to the core2 MEM DIE; the processor core 2, the processor core 3, and The radio transceiver antennas of the processor core 4 are divided into a group to perform transmission frequency division multiplexing access to the core3 MEM DIE.
  • the space cannot be divided into a group, it needs to be first grouped through the memory block, and then the wireless transceiver antenna of a processor core is used to access the memory block of the group.
  • the core1 MEM DIE is Core2 MEM DIE and core3 MEM DIE are grouped into one group.
  • the wireless transceiver antenna of processor core 1 is used for beam scanning to access each memory block, and core4 MEM DIE, core6 MEM DIE and core7 MEM DIE are grouped into one group.
  • the radio transceiver antenna of the core 7 performs beam scanning to access each memory block.
  • an access request of the target processing unit is received, where the access request carries a target identifier of the target memory unit to be accessed by the target processing unit, and the first wireless transceiver antenna of the target processing unit is identified by the target identifier.
  • a first wireless link between the second wireless transceiver antennas of the target memory unit, the control target processing unit uses the first wireless link and the target memory unit to perform transmission of the memory access request data, and the target processing unit
  • the target memory unit performs the transmission of the memory access request data by establishing a wireless link, and has strong reconfigurability, low routing complexity, and small delay.
  • the storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).
  • the modules in the memory access device of the embodiment of the present invention may be combined, divided, and deleted according to actual needs.

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Abstract

一种内存访问方法、装置及系统架构，该内存访问方法包括：接收目标处理单元的访问请求，所述访问请求携带所述目标处理单元待访问的目标内存单元的目标标识；建立所述目标处理单元的第一无线收发天线与所述目标标识所标识的目标内存单元的第二无线收发天线之间的第一无线链路；控制所述目标处理单元利用所述第一无线链路与所述目标内存单元之间进行访存请求数据的收发。本发明实施例可以实现处理单元与内存单元之间可重构的无线链路，降低路由复杂度。

Description

一种内存访问方法、装置及系统架构 技术领域
本发明涉及存储技术领域，尤其涉及一种内存访问方法、装置及系统架构。
背景技术
在通信技术中，通常为了便于对数据的处理，处理单元与内存单元分开进行集成，例如，大数据高并发应用的片上架构即是处理单元与内存单元分别集成，该片上架构往微观的众核+共享内存3D堆叠的架构发展，每个处理器核运行线程应用时，即从内存堆叠层的相应内存块中读取相应的数据。传统3D堆叠架构采用有线互连的方式，如图1所示，该架构包括众核层Layer2、交换层Layer1以及内存堆叠层Layer0，众核层包括多个处理器核，内存堆叠层包括多个内存块，处理器核与内存块之间的访存数据消息通过垂直方向TSV/TSI传送到对应层，然后由该层2D路由通路传送至相应内存块或者处理器核，2D路由通路由多跳节点路由实现，其中每跳节点的路由模块中的多端口开关切换实现包交换。这种有线互联的方式固定不可重构，路由复杂度高。
发明内容
本发明实施例提供了一种内存访问方法、装置及系统架构，可以实现处理单元与内存单元之间可重构的无线链路，降低路由复杂度。
本发明第一方面提供一种内存访问方法，包括：
接收目标处理单元的访问请求，该访问请求携带目标处理单元待访问的目标内存单元的目标标识；
建立目标处理单元的第一无线收发天线与目标标识所标识的目标内存单元的第二无线收发天线之间的第一无线链路；
控制目标处理单元利用该第一无线链路与目标内存单元之间进行访存请求数据的传输。这种方式中，各个处理单元与各个内存单元之间通过建立无线链路进行通信，因此可以重构，并且可以通过建立不同的无线链路实现不同的处理单元与内存单元之间的通信，因此路由复杂度低。
基于第一方面，在第一方面的第一种可行的实施方式中，在建立目标处理 单元的第一无线收发天线与目标标识所标识的目标内存单元的第二无线收发天线之间的第一无线链路之前，该方法还包括：
判断第二无线收发天线是否在第一无线收发天线当前辐射角度范围内；
若第二无线收发天线不在第一无线收发天线当前辐射角度范围内，则调整第一无线收发天线的辐射方向，使得第二无线收发天线处于第一无线收发天线的辐射角度范围内。
若第二无线收发天线在第一无线收发天线当前辐射角度范围内，则直接建立目标处理单元的第一无线收发天线与目标标识所标识的目标内存单元的第二无线收发天线之间的第一无线链路。这种方式进一步限定在建立第一无线链路时，通过判断目标内存单元的第二无线收发天线是否在目标处理单元的第一无线收发天线辐射角度范围内，从而确定不同的无线链路建立方式，当目标内存单元的第二无线收发天线不在目标处理单元的第一无线收发天线覆盖范围内，则可以通过查询天线波束角度以及调整目标处理单元的第一无线收发天线的辐射方向，从而实现第一无线链路的建立，从而扩大目标处理单元可以访问的内存单元的范围。
基于第一方面或者第一方面的第一种可行的实施方式，在第一方面的第二种可行的实施方式中，在建立目标处理单元的第一无线收发天线与目标标识所标识的目标内存单元的第二无线收发天线之间的第一无线链路之前，该方法还包括：
从至少两个无线收发天线中为目标处理单元选取第一无线收发天线，并建立第一无线收发天线与目标处理单元的连接。
可选的，从共享天线池的至少两个无线收发天线中为目标处理单元选取第一无线收发天线，这种方式中是所有的处理单元都共享一个天线池，当某一个目标处理单元需要进行内存数据的传输时，可以从天线池中选取第一无线收发天线，从而通过共享资源，达到提高资源利用率的目的。
基于第一方面第二种可行的实施方式，在第一方面的第三种可行的实施方式中，从至少两个无线收发天线中为目标处理单元选取第一无线收发天线，包括：
获取天线池中至少两个无线收发天线中每个无线收发天线的负载；
从该至少两个无线收发天线中选取负载最小的无线收发天线作为该第一无线收发天线。通过从天线池中选择负载最小的无线收发天线作为第一无线收发天线，这样可以充分利用负载比较小的无线收发天线资源，提高天线资源利用率。
可选的，在建立第一无线收发天线与第二无线收发天线之间的第一无线链路时，可以是采用时分复用的方式，在第一无线收发天线的目标时隙中与第二无线收发天线之间建立第一无线链路。
基于第一方面或者第一方面第一种可行的实施方式或者第一方面第二种可行的实施方式或者第一方面第三种可行的实施方式，在第一方面的第四种可行的实施方式中，若第一无线收发天线的负载大于预设的第一阈值，则该方法还包括：
从至少两个无线收发天线中为目标处理单元选取第三无线收发天线，并建立该目标处理单元与第三无线收发天线的连接；
建立该目标处理单元的第三无线收发天线与目标标识所标识的目标内存单元的第二无线收发天线之间的第二无线链路；
控制目标处理单元利用该第二无线链路与目标内存单元之间进行访存请求数据的传输。这种方式在第一无线收发天线的负载大于预设的第一阈值时，为目标处理单元从天线池中选取第三无线收发天线，并建立第三无线收发天线与第二无线收发天线的第二无线链路，从而实现目标处理单元可以通过第一无线链路和第二无线链路与目标内存单元之间进行访存请求数据的收发，减小第一无线收发天线的过载现象，减小丢包率，同时提高空闲天线的利用率，平衡各个无线收发天线的带宽。
可选的，判断该第一无线收发天线的负载是否大于预设的第一阈值，包括：
获取该第一无线收发天线在离当前时刻最近的至少一个历史时间片中每一个历史时间片的负载数据量；
判断每一个历史时间片该第一无线收发天线的负载数据量是否均超过预设的第一阈值；或者，判断该至少一个历史时间片中是否超过预设个数的历史时间片中每个历史时间片的负载数据量均大于预设的第一阈值；
若是，则确定该第一无线收发天线的负载大于预设的第一阈值。这种方式 通过统计至少一个历史时间片中该第一无线收发天线的负载数据量来预测当前时刻该第一无线收发天线的负载，从而确定是否为该目标处理单元分配第三无线收发天线，预测方式准确。
基于第一方面或者第一方面第一种可行的实施方式，在第一方面的第五种可行的实施方式中，处理单元与无线收发天线一一对应，若第一无线收发天线的负载大于预设的第一阈值，该方法还包括：
建立目标处理单元与辅助处理单元之间的连接关系，并建立辅助处理单元的第四无线收发天线与第二无线收发天线之间的第三无线链路；
控制目标处理单元利用该第三无线链路与目标内存单元之间进行访存请求数据的传输。这种方式进一步限定在处理单元与无线收发天线一一对应的场景下，若第一无线收发天线的负载大于预设的第一阈值时，目标处理单元通过借用辅助处理单元的第四无线收发天线建立与第二无线收发天线之间的第三无线链路，从而减小第一无线收发天线的负载，平衡各个无线收发天线的负载数据量。
可选的，辅助处理单元的选择方式可以包括：
获取所有处理单元的负载，并将负载最小的处理单元作为辅助处理单元；或者，
获取所有处理单元的天线负载，并将天线负载最小的处理单元作为辅助处理单元。
本发明第二方面提供一种内存访问装置，包括：
接收模块，用于接收目标处理单元的访问请求，该访问请求携带目标处理单元待访问的目标内存单元的目标标识；
建立模块，用于建立目标处理单元的第一无线收发天线与目标标识所标识的目标内存单元的第二无线收发天线之间的第一无线链路；
控制模块，用于控制目标处理单元利用该第一无线链路与目标内存单元之间进行访存请求数据的传输。这种方式中，各个处理单元与各个内存单元之间通过建立无线链路进行通信，因此可以重构，并且可以通过建立不同的无线链路实现不同的处理单元与内存单元之间的通信，因此路由复杂度低。
基于第二方面，在第二方面的第一种可行的实施方式中，该装置还包括：
判断模块，用于判断第二无线收发天线是否在第一无线收发天线当前辐射角度范围内；
调整模块，用于若第二无线收发天线不在第一无线收发天线当前辐射角度范围内，则调整第一无线收发天线的辐射方向，使得第二无线收发天线处于第一无线收发天线的辐射角度范围内。
若第二无线收发天线在第一无线收发天线当前辐射角度范围内，则直接建立目标处理单元的第一无线收发天线与目标标识所标识的目标内存单元的第二无线收发天线之间的第一无线链路。这种方式进一步限定在建立第一无线链路时，通过判断目标内存单元的第二无线收发天线是否在目标处理单元的第一无线收发天线辐射角度范围内，从而确定不同的无线链路建立方式，当目标内存单元的第二无线收发天线不在目标处理单元的第一无线收发天线覆盖范围内，则可以通过查询天线波束角度以及调整目标处理单元的第一无线收发天线的辐射方向，从而实现第一无线链路的建立，从而扩大目标处理单元可以访问的内存单元的范围。
基于第二方面或者第二方面的第一种可行的实施方式，在第二方面的第二种可行的实施方式中，该装置还包括：
第一选取模块，用于从至少两个无线收发天线中为目标处理单元选取第一无线收发天线，并建立第一无线收发天线与目标处理单元的连接。
可选的，从共享天线池的至少两个无线收发天线中为目标处理单元选取第一无线收发天线，这种方式中是所有的处理单元都共享一个天线池，当某一个目标处理单元需要进行内存数据的传输时，可以从天线池中选取第一无线收发天线，从而通过共享资源，达到提高资源利用率的目的。
基于第二方面第二种可行的实施方式，在第二方面的第三种可行的实施方式中，该第一选取模块具体用于获取天线池中至少两个无线收发天线中每个无线收发天线的负载；并从该至少两个无线收发天线中选取负载最小的无线收发天线作为该第一无线收发天线。这种方式通过从天线池中选择负载最小的无线收发天线作为第一无线收发天线，这样可以充分利用负载比较小的无线收发天线资源，提高天线资源利用率。
可选的，在建立第一无线收发天线与第二无线收发天线之间的第一无线链 路时，可以是采用时分复用的方式，在第一无线收发天线的目标时隙中与第二无线收发天线之间建立第一无线链路。
基于第二方面或者第二方面第一种可行的实施方式或者第二方面第二种可行的实施方式或者第二方面第三种可行的实施方式，在第二方面的第四种可行的实施方式中，若所述第一无线收发天线的负载大于预设的第一阈值，该装置还包括：
第二选取模块，用于从至少两个无线收发天线中为目标处理单元选取第三无线收发天线；
建立模块还用于建立所述目标处理单元与所述第三无线收发天线的连接，并建立该目标处理单元的第三无线收发天线与目标标识所标识的目标内存单元的第二无线收发天线之间的第二无线链路；
控制模块还用于控制目标处理单元利用该第二无线链路与目标内存单元之间进行访存请求数据的传输。这种方式在第一无线收发天线的负载大于预设的第一阈值时，为目标处理单元从天线池中选取第三无线收发天线，并建立第三无线收发天线与第二无线收发天线的第二无线链路，从而实现目标处理单元可以通过第一无线链路和第二无线链路与目标内存单元之间进行访存请求数据的收发，减小第一无线收发天线的过载现象，减小丢包率，同时提高空闲天线的利用率，平衡各个无线收发天线的带宽。
可选的，判断该第一无线收发天线的负载是否大于预设的第一阈值，包括：
获取该第一无线收发天线在离当前时刻最近的至少一个历史时间片中每一个历史时间片的负载数据量；
判断每一个历史时间片该第一无线收发天线的负载数据量是否均超过预设的第一阈值；或者，判断该至少一个历史时间片中是否超过预设个数的历史时间片中每个历史时间片的负载数据量均大于预设的第一阈值；
若是，则确定该第一无线收发天线的负载大于预设的第一阈值。这种方式通过统计至少一个历史时间片中该第一无线收发天线的负载数据量来预测当前时刻该第一无线收发天线的负载，从而确定是否为该目标处理单元分配第三无线收发天线，预测方式准确。
基于第二方面或者第二方面第一种可行的实施方式，在第二方面的第五种 可行的实施方式中，处理单元与无线收发天线一一对应，若所述第一无线收发天线的负载大于预设的第一阈值，该装置还包括，
建立模块还用于建立目标处理单元与辅助处理单元之间的连接关系，并建立辅助处理单元的第四无线收发天线与第二无线收发天线之间的第三无线链路；
控制模块还用于控制目标处理单元利用该第三无线链路与目标内存单元之间进行访存请求数据的传输。这种方式进一步限定在处理单元与无线收发天线一一对应的场景下，若第一无线收发天线的负载大于预设的第一阈值时，目标处理单元通过借用辅助处理单元的第四无线收发天线建立与第二无线收发天线之间的第三无线链路，从而减小第一无线收发天线的负载，平衡各个无线收发天线的负载数据量。
可选的，辅助处理单元的选择方式可以包括：
获取所有处理单元的负载，并将负载最小的处理单元作为辅助处理单元；或者，
获取所有处理单元的天线负载，并将天线负载最小的处理单元作为辅助处理单元。
本发明第三方面提供一种内存访问系统架构，该系统架构包括众核层和内存堆叠层，所述众核层和所述内存堆叠层之间通过无线信号进行通信，所述众核层包括至少两个处理单元以及全局内存控制器，所述内存堆叠层包括至少两个内存单元；
所述全局内存控制器接收目标处理单元的访问请求，所述访问请求携带所述目标处理单元待访问的目标内存单元的目标标识；
所述全局内存控制器建立所述目标处理单元的无线收发天线与所述目标标识所标识的目标内存单元的无线收发天线之间的无线链路；
所述全局内存控制器控制所述目标处理单元利用所述无线链路与所述目标内存单元之间进行访存请求数据的传输。这种方式中，各个处理单元与各个内存单元之间通过建立无线链路进行通信，因此可以重构，并且可以通过建立不同的无线链路实现不同的处理单元与内存单元之间的通信，因此路由复杂度低。
本发明第四方面提供一种可读介质，包括执行指令，当内存控制器执行该执行指令时，内存控制器可以执行第一方面的任意一种可行的实施方式。
本发明第五方面提供一种内存控制器，包括处理器、存储器和总线；
该存储器用于存储执行指令，处理器与存储器通过总线连接，当内存控制器运行时，该处理器执行存储器所存储的执行指令，以使内存控制器执行第一方面的任意一种可行的实施方式。
本发明实施例中，接收目标处理单元的访问请求，该访问请求中携带该目标处理单元待访问的目标内存单元的目标标识，建立该目标处理单元的第一无线收发天线与目标标识所标识的目标内存单元的第二无线收发天线之间的第一无线链路，控制目标处理单元利用该第一无线链路与目标内存单元之间进行访存请求数据的传输，这种方式目标处理单元与目标内存单元之间通过建立无线链路进行访存请求数据的传输，重构性强，并且路由复杂度低，延时小。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例提供的一种现有技术中片上架构的示意图；
图2为本发明实施例提供的一种内存访问方法的流程示意图；
图3为本发明实施例提供的另一种内存访问方法的流程示意图；
图4为本发明实施例提供的一种可重构片上架构示意图；
图5为本发明实施例提供的一种处理单元与内存单元的无线收发天线之间建立无线链路的示意图；
图6为本发明实施例提供的另一种处理单元与内存单元的无线收发天线之间建立无线链路的示意图；
图7为本发明实施例提供的一种片上架构的内部结构示意图；
图8为本发明实施例提供的一种内存访问密集示意图；
图9为本发明实施例提供的一种内存访问稀疏示意图；
图10为本发明实施例提供的四种内存访问比较示意图；
图11为本发明实施例提供的一种内存访问装置的结构示意图；
图12为本发明实施例提供的另一种内存控制器的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行描述。
本发明实施例中的无线收发天线(例如第一无线收发天线、第二无线收发天线、第三无线收发天线以及第四无线收发天线)可以是一个天线，也可以是一个天线阵。
本发明实施例中，在一种可选的实施方式中，处理单元的无线收发天线可以是以天线池的形式存在，即是所有处理单元共享天线池中的多个无线收发天线，当目标处理单元需要访问目标内存单元时，即从共享天线池中选取第一无线收发天线进行通信。在另一种可选的实施方式中，处理单元与无线收发天线之间可以是一一对应的关系，即是一个处理单元设置了一个无线收发天线，当目标处理单元需要访问目标内存单元时，即采用目标处理单元的第一无线收发天线进行通信。
可选的，本发明实施例的内存访问方法可以应用于众核-共享内存3D集成片上架构，该片上架构包括众核层以及内存堆叠层，众核层包括多个处理单元(例如处理器核)以及全局内存控制器，内存堆叠层包括多个内存单元(例如内存块RAM Cluster),众核层与内存堆叠层之间通过无线信号进行通信。全局内存控制器主要用于调度各个处理单元的无线收发天线与各个内存单元的无线收发天线之间的无线链路的建立与删除，从而实现任意一个处理单元可以通过无线链路实现与任意一个内存单元之间访存数据的收发，重构性强，路由复杂度低，并且是点到点的数据传输，因此延时小。
可选的，本发明实施例的内存访问方法也可以应用于单板机框，该单板机框包括机架，该机架的上层机框包括多个处理单元(例如：处理器或处理器核)，该机架的下层机框包括多个内存单元(例如：内存条)，通过各个处理单元的无线收发天线建立与各个内存单元的无线收发天线之间的无线链路，从而通过 无线链路实现各个处理单元与相应内存单元之间访存数据的收发。
需要说明的是，本实施例的内存访问方法适用场景包括但不限于上述两种场景，上述两种适用场景仅为举例。
请参照图2，为本发明实施例提供的一种内存访问方法的流程示意图，如图所示，本实施例的内存访问方法包括步骤S200-S202；
S200，接收目标处理单元的访问请求，所述访问请求携带所述目标处理单元待访问的目标内存单元的目标标识；
本发明实施例中，目标处理单元可以是处理器，也可以是处理器核，处理器可以包括中央处理器(Central Processing Unit，CPU)，图像处理器等等，在此不作限定。本发明对于目标处理单元的存在形式不作限定。目标处理单元可以运行各种应用以及各个线程，目标处理单元可以向内存堆叠层中的任意一个目标内存单元读取数据或者存储数据。目标内存单元可以是内存堆叠层的内存块或者内存条，在此不作限定。
在本实施例中，目标处理单元设置了无线收发天线和电路，目标内存单元也设置了无线收发天线和电路，如图5所示，即是本发明实施例提供的一种目标处理单元以及目标内存单元的放大图，如图所示，处理单元以处理器核为例，内存单元以内存块为例，每个处理器核均设置了调制电路，将目标处理器核的访存请求数据调制到载波，并通过无线收发天线将调制信号发送至对应内存块的无线收发天线，同时目标处理器核的无线收发天线也可以接收对应内存块的响应数据。对于每个内存块，首先通过内存块的无线收发天线接收目标处理器核通过无线收发天线发送的信号，然后通过解调电路对所接收的信号进行解调，从而获取目标处理器核的访存请求数据，最后针对访存数据返回对应的响应数据，响应数据的返回同样通过内存块的无线收发天线进行发送。
需要说明的是，如图5所示，各个处理器核与各个内存块之间进行访存请求数据的传输是基于处理器核与内存块之间所建立的无线链路，当目标处理器核需要访问目标内存块时，需要预先建立目标处理器核与目标内存块之间的第一无线链路。基于第一无线链路进行访存请求数据的传输，因此各个处理器核可以建立同任意一个内存块之间的无线链路，实现点到点通信。
如图6所示，为本发明实施例提供的另一种目标处理单元以及目标内存单 元的放大图，同图5的区别是，在图6中每个处理器核并不是与无线收发天线之间一一对应，而是所有处理器核共享一个天线池，该共享天线池与处理器核之间通过交换网络进行连接，任意一个处理器核可以利用天线池中的任意一个无线收发天线与内存单元之间进行访存请求数据的传输。需要说明的是，天线池中每一个无线收发天线的电路结构与图5相同。
本实施例中，当目标处理单元预访问目标内存单元时，向全局内存控制器发送访问请求，该访问请求携带目标内存单元的目标标识，全局内存控制器根据访问请求进行无线链路的建立以及调度。如图4所示，即是本发明实施例提供的一种内存访问系统架构图，全局内存控制器进行无线链路配置，众核层的任意一个处理单元(处理器核)可以访问内存堆叠层中的任意一个内存块，当全局内存控制器接收到目标处理器核的访问请求时，即根据访问请求中目标内存块的目标标识进行无线链路的建立与调度。
S201，建立所述目标处理单元的第一无线收发天线与所述目标标识所标识的目标内存单元的第二无线收发天线之间的第一无线链路；
本发明实施例中，内存访问系统架构中各层的处理单元集成无线收发天线和电路，各层的内存单元也集成无线收发天线以及电路，层间通信通过天线阵以无线方式进行，通过天线阵的波速扫描改变链路方向构成可重构的无线链路，使得每个处理单元可以直接访问若干个相邻内存单元，路由复杂度大幅简化。
全局内存控制器建立目标处理单元的第一无线收发天线与目标标识所标识的目标内存单元的第二无线收发天线之间的第一无线链路，需要说明的是，通常目标处理单元的第一无线收发天线当前辐射角度范围有限，因此需要进一步确定目标内存单元的第二无线收发天线是否在目标处理单元的第一无线收发天线当前辐射角度范围内。
因此，在建立目标处理单元的第一无线收发天线与目标内存单元的第二无线收发天线之间的第一无线链路之前，还可以包括步骤S20-S21；
S20，判断所述第二无线收发天线是否在所述第一无线收发天线当前辐射角度范围内；
本发明实施例中，通常目标处理单元的第一无线收发天线的当前辐射角度 范围内可以包括多个内存单元，该多个内存单元可以是系统架构的所有内存单元，也可以是系统架构的所有内存单元中的部分内存单元。只有内存单元的无线收发天线在处理单元的当前辐射角度范围内时，才可以建立无线链路，因此在建立第一无线收发天线与第二无线收发天线之间的第一无线链路之前，需要进行判断。
具体可选的，判断方式可以是全局内存控制器查询目标标识所标识的目标内存单元的第二无线收发天线是否在目标处理单元的第一无线收发天线的当前辐射角度范围内，系统架构中存储了各个处理单元的无线收发天线在各种辐射角度范围内的内存单元。
S21，若所述第二无线收发天线不在所述第一无线收发天线当前辐射角度范围内，则调整所述第一无线收发天线的辐射方向，以使所述第二无线收发天线处于所述第一无线收发天线的辐射角度范围内。
本发明实施例中，若目标标识所标识的目标内存单元的第二无线收发天线未在目标处理单元的第一无线收发天线的当前辐射角度范围内，则说明该目标处理单元不能直接访问该目标内存单元，查询目标处理单元的第一无线收发天线与该目标内存单元的第二无线收发天线之间的天线波束角度以及发射功率。
全局内存控制器通知天线阵波束形成单元调整目标处理单元的第一无线收发天线辐射方向，并将其调整为所查询得到的天线波束角度，使得第二无线收发天线处于第一无线收发天线的辐射角度范围内，同时全局内存控制器通知发射机调整目标处理单元的第一无线收发天线的发射功率，利用调整后的目标处理单元的第一无线收发天线建立与目标内存单元的第二无线收发天线之间的第一无线链路。
可选的，若目标标识所标识的目标内存单元的第二无线收发天线在目标处理单元的第一无线收发天线当前辐射角度范围内，则可以直接建立目标处理单元的第一无线收发天线与目标内存单元的第二无线收发天线之间的第一无线链路。
S202，控制所述目标处理单元利用所述第一无线链路与所述目标内存单元之间进行访存请求数据的传输。
本发明实施例中，全局内存控制器控制目标处理单元利用所建立的第一无 线链路与目标内存单元之间进行访存数据的传输。需要说明的是，在目标处理单元与目标内存单元进行访存请求数据传输之前，全局内存控制器启动无线内存初始化训练，训练结束后通道建立成功，具体可选的，无线内存初始化训练方式为，目标处理单元的第一无线收发天线一直发射训练数据，直到目标内存单元的第二无线收发天线在指定误码率要求下，且灵敏度达到门限值以上接收数据，则说明无线内存初始化训练成功，第一无线链路的通道建立成功。全局内存控制器控制目标处理单元通过该第一无线链路向目标内存单元发送访存请求数据，目标内存单元执行访存请求，并返回目标处理单元需要读取的数据或响应。进一步的，全局内存控制器根据历史时间片中对目标内存单元的访问频率进行判断是否需要关闭该第一无线链路，从而降低能耗。
可选的，若第一无线收发天线的负载大于预设的第一阈值，则为了能够平衡各个无线收发天线的带宽，则该方法还可以包括以下步骤S203-S205，或者该方法还可以包括以下步骤S206-S207；其中，步骤S203-S205是针对图6所示的共享天线池的场景所提出的平衡策略，步骤S206-S207是针对图5所示的处理单元与无线收发天线一一对应的场景所提出的平衡策略。
需要说明的是，判断第一无线收发天线的负载是否大于预设的第一阈值的判断方法可以包括以下步骤：
步骤一，获取所述第一无线收发天线在离当前时刻最近的至少一个历史时间片中每一个历史时间片的负载数据量；
本发明实施例中，第一无线收发天线的负载数据量即是该第一无线收发天线与内存单元之间进行访存请求数据传输的数据量。全局内存控制器获取第一无线收发天线在离当前时刻最近的至少一个历史时间片中每一个历史时间片的该第一无线收发天线的负载数据量。可选的，对每一个无线收发天线的负载数据量可以由第三方进行监控，全局内存控制器可以直接从第三方获取第一无线收发天线在至少一个历史时间片中每一个历史时间片的负载数据量。如图8所示，即是本发明实施例提供的全局内存控制器所获取的无线收发天线1～无线收发天线4在历史时间片T1～T6的负载数据量的统计图。第一无线收发天线可以是无线收发天线1～无线收发天线4中的任意一个。
步骤二，判断所述第一无线收发天线在每一个所述历史时间片的负载数据 量是否均超过第一预设阈值；或者，该第一无线收发天线在该至少一个历史时间片中超过预设个数的历史时间片中每个历史时间片的负载数据量大于预设的第一阈值。
本发明实施例中，全局内存控制器判断第一无线收发天线在每一个所统计的历史时间片的负载数据量是否均超过预设的第一阈值，如图8所示，可以选择统计T3～T6这四个历史时间片中第一无线收发天线的负载数据量进行判断。如图所示，若第一无线收发天线为无线收发天线二或者无线收发天线三，则该第一无线收发天线在历史时间片T3-T6的负载数据量大于预设的第一阈值。
需要说明的是，在判断过程中，也可以不需要所有历史时间片中每个历史时间片的该第一无线收发天线的负载数据量大于预设的第一阈值，例如，可以是只要有超过预设个数的历史时间片中每个历史时间片的该第一无线收发天线的负载数据量大于预设的第一阈值即可，例如统计4个历史时间片，则只要有3个历史时间片的该第一无线收发天线的负载数据量大于预设的第一阈值即可确定第一无线收发天线的负载大于预设的第一阈值。
应理解，判断第一无线收发天线的负载是否大于预设的第一阈值的方式多种多样，本发明实施例并不对此进行限定。
在一种可选的实施方式中，包括步骤S203-S205；
S203，从至少两个无线收发天线中为所述目标处理单元选取第三无线收发天线，并建立所述目标处理单元与所述第三无线收发天线的连接；
本发明实施例中，若目标处理单元的第一无线收发天线的负载大于预设的第一阈值，为了能够降低该目标处理单元的第一无线收发天线的带宽，平衡各个无线收发天线的带宽，全局内存控制器对所有无线收发天线进行调度，从天线池的至少两个无线收发天线中为目标处理单元选取第三无线收发天线，如图6所示，这里以处理单元为处理器核进行举例说明，所有处理器核共享天线池中的无线收发天线，当目标处理单元的第一无线收发天线的负载大于预设的第一阈值时，则全局内存控制器从共享天线池中为该目标处理单元选取第三无线收发天线，并通过交换网络建立第三无线收发天线与目标内存单元之间的连接。
需要说明的是，选取第三无线收发天线的标准可以包括多个，例如，可以 是从共享天线池中选取空闲天线作为第三无线收发天线，也可以是选取在最近多个历史时间片中发送或者接收的访存请求数据比较少的天线，或者也可以是选取当前负载比较小的天线作为第三无线收发天线等等，在此不作限定。
S204，建立所述目标处理单元的第三无线收发天线与所述目标标识所标识的目标内存单元的第二无线收发天线之间的第二无线链路；
本发明实施例中，全局内存控制器建立第三无线收发天线与目标内存单元的第二无线收发天线之间的第二无线链路，需要说明的是，建立第三无线收发天线与目标内存单元的第二无线收发天线之间的第二无线链路时，也需要判断第二无线收发天线是否在第三无线收发天线当前辐射角度范围内，从而采取不同的无线链路建立方式，具体建立方式可以参照目标处理单元的第一无线收发天线与目标内存单元的第二无线收发天线之间第一无线链路的建立方式，在此不再赘述。
S205，控制所述目标处理单元利用所述第二无线链路与所述目标内存单元之间进行访存请求数据的传输。
本发明实施例中，全局内存控制器控制目标处理单元利用该第二无线链路与目标内存单元之间进行访存请求数据的传输。需要说明的是，第一无线链路与第二无线链路之间可以是采用频分复用的方式与目标内存单元之间进行访存请求数据的传输，目标内存单元的第二无线收发天线为全向天线，因此可以同时接收各个无线链路的访存请求数据。目标内存单元的第二无线收发天线通过解频分复用的方式最终获取访存请求数据。
在另一种可选的实施方式中，包括步骤S206-S207；
S206，建立所述目标处理单元与辅助处理单元之间的连接关系，并建立所述辅助处理单元的第四无线收发天线与所述第二无线收发天线之间的第三无线链路；
本发明实施例中，处理单元与无线收发天线之间一一对应，如图5所示，即是处理单元与无线收发天线一一对应的场景。在目标处理单元的第一无线收发天线的负载大于预设的第一阈值时，则需要选择辅助处理单元，并建立目标处理单元与辅助处理单元之间的连接关系，需要说明的是，辅助处理单元的选择方式有多种，本发明不作限定。例如，可以是选择所有处理单元中负载最小 的处理单元作为辅助处理单元，也可以是先获取所有处理单元中每个处理单元的无线收发天线的负载，并将无线收发天线的负载最小的处理单元作为辅助处理单元。处理单元与辅助处理单元之间可以进行通信，完成访存请求数据的路由。
进一步，建立辅助处理单元的第四无线收发天线与第二无线收发天线之间的第三无线链路，具体可选的，如图7所示，即是本发明实施例提供的一种众核-共享内存3D集成系统架构图，如图所示，处理单元为处理器核，内存单元为内存块，图中包括八个处理器核与八个内存块，如图所示，各个处理器核之间也存在路由通路，可以建立连接关系，全局内存控制器实现动态调度无线链路带宽资源，各个处理器核的访存数据通过全局内存控制器的地址译码器，数据队列以及请求队列处理后，被调度至不同的信道，一个信道对应一个处理器核的无线收发天线，如图所示，假设处理器核3为目标处理单元，内存块1为目标内存单元，处理器核3的无线收发天线在最近几个历史时间片的负载大于预设的第一阈值，则可以选择处理器核1和处理器核2作为辅助处理器核，并利用处理器核1和处理器核2的无线收发天线作为第四无线收发天线，并建立第四无线收发天线与内存块1之间的第三无线链路，即是通过通道合并满足高带宽需求。
S207，控制所述目标处理单元利用所述第三无线链路与所述目标内存单元之间进行访存请求数据的传输。
本发明实施例中，控制目标处理单元利用第三无线链路与目标内存单元之间进行访存请求数据的传输，需要说明的是，第一无线链路与第三无线链路之间可以是通过频分复用的方式进行访存请求数据的传输。
进一步可选的，本发明实施例还可以通过无线收发天线的单通道拆分实现提升低带宽利用率的目的，例如，某几个内存单元访问稀疏，则可以将一个无线收发天线进行通道拆分。具体可选的，这里以目标内存单元为例进行说明，全局内存控制器判断目标内存单元在最近的几个历史时间片中每一个历史时间片的访问次数是否均低于预设阈值，预设阈值可以根据实际情况进行设定，如图9所示，内存块2和内存块3在每个历史时间片的访问次数就比较少，访问比较稀疏。若目标内存单元为内存块2或内存块3，则属于访问稀疏的内存 单元，进一步则选取与目标内存单元相邻且访问稀疏的备选内存单元。
具体可选的，如图7所示，假设目标处理单元为处理器核7，目标内存单元为内存块6，内存块6在最近的历史时间片中访问次数均比较少，为了能够提高处理器核7的无线收发天线的带宽利用率，在本实施例中选取与内存块6相邻且访问比较稀疏的内存块5和内存块7作为备选内存块。
本发明实施例中，将目标处理单元的第一无线收发天线进行单通道拆分提升低带宽利用率，具体的拆分方式可以是，通过目标处理单元的无线收发天线的发射波束扫描，在不同的独立时隙与不同的内存单元之间进行访存请求数据的传输，而在目标时隙中建立目标处理单元的第一无线收发天线与目标内存单元的第二无线收发天线之间的第一无线链路。具体可选的，如图7所示，处理器核7的无线收发天线在不同时隙分别与内存块5～内存块7之间进行访存请求数据的传输，其中，在一个时隙，处理器核7的无线收发天线与一个内存块之间建立无线链路进行通信。
需要说明的是，目标处理单元的第一无线收发天线也可以通过分割天线阵(各子天线阵分散方向性)实现与不同的内存单元之间通信。
本发明实施例中，接收目标处理单元的访问请求，该访问请求中携带该目标处理单元待访问的目标内存单元的目标标识，建立该目标处理单元的第一无线收发天线与目标标识所标识的目标内存单元的第二无线收发天线之间的第一无线链路，控制目标处理单元利用该第一无线链路与目标内存单元之间进行访存请求数据的传输，这种方式目标处理单元与目标内存单元之间通过建立无线链路进行访存请求数据的传输，重构性强，并且路由复杂度低，延时小。
请参照图3，为本发明实施例提供的另一种内存访问方法的流程示意图，如图所示，本实施例的内存访问方法包括：
S300，接收目标处理单元的访问请求，所述访问请求携带所述目标处理单元待访问的目标内存单元的目标标识；
本发明实施例步骤S300请参照图2的实施例步骤S200，在此不再赘述。
S301，从至少两个无线收发天线中为所述目标处理单元选取所述第一无线收发天线，并建立所述第一无线收发天线与所述目标处理单元的连接。
本发明实施例中，所有处理单元共享天线池，该天线池中包括多个无线收发天线，当目标处理单元需要访问目标内存单元时，则从共享天线池的至少两个无线收发天线中为目标处理单元选取第一无线收发天线，并建立第一无线收发天线与目标处理单元之间的连接。需要说明的是，在从共享天线池中选取第一无线收发天线的选取方式可以有多种，例如可以从共享天线池中选取空闲天线作为第一无线收发天线，或者也可以是从共享天线池中选取负载最小的天线作为第一无线收发天线，或者也可以是从负载低于一定阈值的多个无线收发天线中随机选择一个无线收发天线作为第一无线收发天线，选取方式在此不作限定。
可选的，所述从至少两个无线收发天线中为所述目标处理单元选取所述第一无线收发天线，包括以下两个步骤：
步骤一、获取至少两个无线收发天线中每个无线收发天线的负载；
步骤二、从所述至少两个无线收发天线中选取负载最小的所述第一无线收发天线。
具体实施例中，从天线池的多个无线收发天线中选取负载最小的天线作为第一无线收发天线，该第一无线收发天线承载了其它访存请求数据的传输，同时又承载该目标处理单元对目标内存单元之间访存请求数据的传输，其它访存请求数据可以是其它处理单元对该目标内存单元的访存请求数据，或者是其它处理单元对除该目标内存单元的访存请求数据。若是其它处理单元对除该目标内存单元的访存请求数据，则本实施例可以将其它处理单元的访存请求数据路由至该目标处理单元，并控制目标处理单元的第一无线收发天线采用时分复用的方式分别与不同内存单元之间进行不同访存请求数据的传输。
S302，建立所述目标处理单元的第一无线收发天线与所述目标标识所标识的目标内存单元的第二无线收发天线之间的第一无线链路；
S303，控制所述目标处理单元利用所述第一无线链路与所述目标内存单元之间进行访存请求数据的传输。
本发明实施例步骤S302-S303请参照图2的实施例步骤S201-S202，在此不再赘述。
本发明实施例中，接收目标处理单元的访问请求，该访问请求中携带该目 标处理单元待访问的目标内存单元的目标标识，建立该目标处理单元的第一无线收发天线与目标标识所标识的目标内存单元的第二无线收发天线之间的第一无线链路，控制目标处理单元利用该第一无线链路与目标内存单元之间进行访存请求数据的传输，这种方式目标处理单元与目标内存单元之间通过建立无线链路进行访存请求数据的传输，重构性强，并且路由复杂度低，延时小。
请参照图11，为本发明实施例提供的一种内存访问装置的结构示意图，如图所示，本发明实施例的内存访问装置包括：
接收模块100，用于接收目标处理单元的访问请求，所述访问请求携带所述目标处理单元待访问的目标内存单元的目标标识；
建立模块101，用于建立所述目标处理单元的第一无线收发天线与所述目标标识所标识的目标内存单元的第二无线收发天线之间的第一无线链路；
控制模块102，用于控制所述目标处理单元利用所述第一无线链路与所述目标内存单元之间进行访存请求数据的传输。
可选的，该装置还可以包括判断模块103以及调整模块104；
判断模块103，用于判断所述第二无线收发天线是否在所述第一无线收发天线当前辐射角度范围内；
调整模块104，用于若所述第二无线收发天线不在所述第一无线收发天线当前辐射角度范围内，则调整所述第一无线收发天线的辐射方向，以使所述第二无线收发天线处于所述第一无线收发天线的辐射角度范围内。
可选的，该装置还可以包括第一选取模块105；
第一选取模块105，用于从至少两个无线收发天线中为所述目标处理单元选取所述第一无线收发天线，并建立所述第一无线收发天线与所述目标处理单元的连接。
具体可选的，该第一选取模块105具体用于获取至少两个无线收发天线中每个无线收发天线的负载；并从所述至少两个无线收发天线中选取负载最小的所述第一无线收发天线。
可选的，所有处理单元共享天线池，该天线池中包括至少两个无线收发天线，若所述第一无线收发天线的负载大于预设的第一阈值，该装置还包括第二 选取模块106；
第二选取模块106，用于从至少两个无线收发天线中为所述目标处理单元选取第三无线收发天线；
该建立模块101还用于建立所述目标处理单元与所述第三无线收发天线的连接，并建立所述目标处理单元的第三无线收发天线与所述目标标识所标识的目标内存单元的第二无线收发天线之间的第二无线链路；
该控制模块102还用于控制所述目标处理单元利用所述第二无线链路与所述目标内存单元之间进行访存请求数据的传输。
可选的，若处理单元与无线收发天线一一对应，若所述第一无线收发天线的负载大于预设的第一阈值，则该建立模块101还用于建立所述目标处理单元与辅助处理单元之间的连接关系，并建立所述辅助处理单元的第四无线收发天线与所述第二无线收发天线之间的第三无线链路；
该控制模块102还用于控制所述目标处理单元利用所述第三无线链路与所述目标内存单元之间进行访存请求数据的传输。
本发明实施例中，接收目标处理单元的访问请求，该访问请求中携带该目标处理单元待访问的目标内存单元的目标标识，建立该目标处理单元的第一无线收发天线与目标标识所标识的目标内存单元的第二无线收发天线之间的第一无线链路，控制目标处理单元利用该第一无线链路与目标内存单元之间进行访存请求数据的传输，这种方式目标处理单元与目标内存单元之间通过建立无线链路进行访存请求数据的传输，重构性强，并且路由复杂度低，延时小。
可以理解的是，上述内存访问装置中各个模块以及单元的具体实现方式可以进一步参考方法实施例中的相关描述。
请参照图12，为本发明实施例提供的一种内存控制器的结构示意图，如图所示，该内存控制器40包括处理器401、存储器402以及总线403，处理器401、存储器402均与总线403连接，存储器用于存储执行指令，处理器401调用存储器402所存储的执行指令：
处理器401，用于接收目标处理单元的访问请求，所述访问请求携带所述目标处理单元待访问的目标内存单元的目标标识；
处理器401还用于建立所述目标处理单元的第一无线收发天线与所述目标标识所标识的目标内存单元的第二无线收发天线之间的第一无线链路；
处理器401还用于控制所述目标处理单元利用所述第一无线链路与所述目标内存单元之间进行访存请求数据的传输。
可选的，所述建立所述目标处理单元的第一无线收发天线与所述目标标识所标识的目标内存单元的第二无线收发天线之间的第一无线链路之前；
处理器401还用于判断所述第二无线收发天线是否在所述第一无线收发天线当前辐射角度范围内；
若所述第二无线收发天线不在所述第一无线收发天线当前辐射角度范围内，则调整所述第一无线收发天线的辐射方向，以使所述第二无线收发天线处于所述第一无线收发天线的辐射角度范围内。
处理器401还用于从至少两个无线收发天线中为所述目标处理单元选取所述第一无线收发天线，并建立所述第一无线收发天线与所述目标处理单元的连接。
可选的，所述从至少两个无线收发天线中为所述目标处理单元选取所述第一无线收发天线，包括：
处理器401还用于获取至少两个无线收发天线中每个无线收发天线的负载；
处理器401还用于从所述至少两个无线收发天线中选取负载最小的所述第一无线收发天线。
若所述第一无线收发天线的负载大于预设的第一阈值；
处理器401还用于从至少两个无线收发天线中为所述目标处理单元选取第三无线收发天线，并建立所述目标处理单元与所述第三无线收发天线的连接；
处理器401还用于建立所述目标处理单元的第三无线收发天线与所述目标标识所标识的目标内存单元的第二无线收发天线之间的第二无线链路；
处理器401还用于控制所述目标处理单元利用所述第二无线链路与所述目标内存单元之间进行访存请求数据的传输。
若处理单元与无线收发天线一一对应，所述第一无线收发天线的负载大于 预设的第一阈值；
处理器401还用于建立所述目标处理单元与辅助处理单元之间的连接关系，并建立所述辅助处理单元的第四无线收发天线与所述第二无线收发天线之间的第三无线链路；
处理器401还用于控制所述目标处理单元利用所述第三无线链路与所述目标内存单元之间进行访存请求数据的传输。
本发明实施例中，接收目标处理单元的访问请求，该访问请求中携带该目标处理单元待访问的目标内存单元的目标标识，建立该目标处理单元的第一无线收发天线与目标标识所标识的目标内存单元的第二无线收发天线之间的第一无线链路，控制目标处理单元利用该第一无线链路与目标内存单元之间进行访存请求数据的传输，这种方式目标处理单元与目标内存单元之间通过建立无线链路进行访存请求数据的传输，重构性强，并且路由复杂度低，延时小。
请参照图4，为本发明实施例提供的一种内存访问系统架构图，如图所示，该系统架构包括众核层和内存堆叠层，该众核层包括多个处理器核以及全局内存控制器，内存堆叠层包括多个内存块，众核层和内存堆叠层之间通过无线信号进行通信，全局内存控制器对处理器核与内存块之间的无线链路进行配置，从而建立各个处理器核与不同内存块之间的无线链路，处理器核与内存块之间可以通过无线链路进行访存数据的传输，如图所示，若内存块包括8个，则众核层中的任意一个处理器核通过配置无线链路可以访问8个内存块中的任意一个内存块。下面以目标处理器核预访问目标内存块为例进行举例说明。
所述全局内存控制器接收目标处理器核的访问请求，所述访问请求携带所述目标处理器核预访问的目标内存块的目标标识；
所述全局内存控制器建立所述目标处理器核的无线收发天线与所述目标标识所标识的目标内存块的无线收发天线之间的无线链路；
所述全局内存控制器控制所述目标处理器核利用所述无线链路与所述目标内存块之间进行访存请求数据的传输。
可选的，若该系统架构中出现局域性高的内存密集访问，即是如图10的左上角的图，即是所有内存块中只有处理器核5的内存块(core5 MEM DIE) 访问密集，则目标处理器核的无线收发天线通过与其他空闲天线通过发射频分复用的方式与core5 MEM DIE进行无线通信，core5 MEM DIE的无线收发天线通过解频分复用的方式获取相应的访存请求数据。
可选的，若该系统架构中出现离散的内存稀疏访问，即是如图10的右上角的图，即是所有内存块中只有处理器核4的内存块(core4 MEM DIE)、处理器核6的内存块(core6 MEM DIE)以及处理器核7的内存块(core7 MEM DIE)访问稀疏，则可以通过波束扫描(时分复用)的方式实现在不同独立时间片与不同的内存块建立无线链路通信。
可选的，若该系统架构中出现空间离散的内存密集访问，如图10的左下角的图所示，即是所有内存块中有多个内存块均为密集访问，则需要通过分组进行发射频分，例如，将处理器核1、处理器核2以及处理器核3的无线收发天线分为一组进行发射频分复用访问core2 MEM DIE；将处理器核2、处理器核3以及处理器核4的无线收发天线分为一组进行发射频分复用访问core3 MEM DIE。
可选的，若该系统架构中出现空间离散的内存并发访问，如图10的右下角的图所示，即是所有内存块中有多个内存块均为稀疏访问，且多个内存块之间由于空间不相邻等原因不能分为一组，则需要首先通过内存块分组，然后采用一个处理器核的无线收发天线去访问该一个组的内存块，如图所示，将core1 MEM DIE、core2 MEM DIE以及core3 MEM DIE分为一组，采用处理器核1的无线收发天线进行波束扫描访问各个内存块，将core4 MEM DIE、core6 MEM DIE以及core7 MEM DIE分为一组，采用处理器核7的无线收发天线进行波束扫描访问各个内存块。
本发明实施例中，接收目标处理单元的访问请求，该访问请求中携带该目标处理单元待访问的目标内存单元的目标标识，建立该目标处理单元的第一无线收发天线与目标标识所标识的目标内存单元的第二无线收发天线之间的第一无线链路，控制目标处理单元利用该第一无线链路与目标内存单元之间进行访存请求数据的传输，这种方式目标处理单元与目标内存单元之间通过建立无线链路进行访存请求数据的传输，重构性强，并且路由复杂度低，延时小。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程， 是可以通过计算机程序来指令相关的硬件来完成，所述的程序可存储于一计算机可读取存储介质中，该程序在执行时，可包括如上述各方法的实施例的流程。其中，所述的存储介质可为磁碟、光盘、只读存储记忆体(Read-Only Memory，ROM)或随机存储记忆体(Random Access Memory，RAM)等。
本发明实施例方法中的步骤可以根据实际需要进行顺序调整、合并和删减。
本发明实施例内存访问装置中的模块可以根据实际需要进行合并、划分和删减。
以上所揭露的仅为本发明较佳实施例而已，当然不能以此来限定本发明之权利范围，因此依本发明权利要求所作的等同变化，仍属本发明所涵盖的范围。

Claims (15)

  1. 一种内存访问方法，其特征在于，包括：
    接收目标处理单元的访问请求，所述访问请求携带所述目标处理单元待访问的目标内存单元的目标标识；
    建立所述目标处理单元的第一无线收发天线与所述目标标识所标识的目标内存单元的第二无线收发天线之间的第一无线链路；
    控制所述目标处理单元利用所述第一无线链路与所述目标内存单元之间进行访存请求数据的传输。
  2. 如权利要求1所述的方法，其特征在于，所述建立所述目标处理单元的第一无线收发天线与所述目标标识所标识的目标内存单元的第二无线收发天线之间的第一无线链路之前，所述方法还包括：
    判断所述第二无线收发天线是否在所述第一无线收发天线当前辐射角度范围内；
    若所述第二无线收发天线不在所述第一无线收发天线当前辐射角度范围内，则调整所述第一无线收发天线的辐射方向，以使所述第二无线收发天线处于所述第一无线收发天线的辐射角度范围内。
  3. 根据权利要求1或2所述的方法，其特征在于，所述建立所述目标处理单元的第一无线收发天线与所述目标标识所标识的目标内存单元的第二无线收发天线之间的第一无线链路之前，所述方法还包括：
    从至少两个无线收发天线中为所述目标处理单元选取所述第一无线收发天线，并建立所述第一无线收发天线与所述目标处理单元的连接。
  4. 如权利要求3所述的方法，其特征在于，所述从至少两个无线收发天线中为所述目标处理单元选取所述第一无线收发天线，包括：
    获取所述至少两个无线收发天线中每个无线收发天线的负载；
    从所述至少两个无线收发天线中选取负载最小的所述第一无线收发天线。
  5. 根据权利要求1-4任一项所述的方法，其特征在于，若所述第一无线收发天线的负载大于预设的第一阈值，则所述方法还包括：
    从至少两个无线收发天线中为所述目标处理单元选取第三无线收发天线，并建立所述目标处理单元与所述第三无线收发天线的连接；
    建立所述目标处理单元的第三无线收发天线与所述目标标识所标识的目标内存单元的第二无线收发天线之间的第二无线链路；
    控制所述目标处理单元利用所述第二无线链路与所述目标内存单元之间进行访存请求数据的传输。
  6. 根据权利要求1或2所述的方法，其特征在于，处理单元与无线收发天线一一对应，若所述第一无线收发天线的负载大于预设的第一阈值，则所述方法还包括：
    建立所述目标处理单元与辅助处理单元之间的连接关系，并建立所述辅助处理单元的第四无线收发天线与所述第二无线收发天线之间的第三无线链路；
    控制所述目标处理单元利用所述第三无线链路与所述目标内存单元之间进行访存请求数据的传输。
  7. 一种内存访问装置，其特征在于，包括：
    接收模块，用于接收目标处理单元的访问请求，所述访问请求携带所述目标处理单元待访问的目标内存单元的目标标识；
    建立模块，用于建立所述目标处理单元的第一无线收发天线与所述目标标识所标识的目标内存单元的第二无线收发天线之间的第一无线链路；
    控制模块，用于控制所述目标处理单元利用所述第一无线链路与所述目标内存单元之间进行访存请求数据的传输。
  8. 如权利要求7所述的装置，其特征在于，所述装置还包括：
    判断模块，用于判断所述第二无线收发天线是否在所述第一无线收发天线当前辐射角度范围内；
    调整模块，用于若所述第二无线收发天线不在所述第一无线收发天线当前辐射角度范围内，则调整所述第一无线收发天线的辐射方向，以使所述第二无线收发天线处于所述第一无线收发天线的辐射角度范围内。
  9. 如权利要求7或8所述的装置，其特征在于，所述装置还包括：
    第一选取模块，用于从至少两个无线收发天线中为所述目标处理单元选取所述第一无线收发天线，并建立所述第一无线收发天线与所述目标处理单元的连接。
  10. 如权利要求9所述的装置，其特征在于，所述第一选取模块具体用于获取所述至少两个无线收发天线中每个无线收发天线的负载，并从所述至少两个无线收发天线中选取负载最小的所述第一无线收发天线。
  11. 如权利要求7-10任一项所述的装置，其特征在于，若所述第一无线收发天线的负载大于预设的第一阈值，所述装置还包括：
    第二选取模块，用于从至少两个无线收发天线中为所述目标处理单元选取第三无线收发天线；
    所述建立模块还用于建立所述目标处理单元与所述第三无线收发天线的连接，并建立所述目标处理单元的第三无线收发天线与所述目标标识所标识的目标内存单元的第二无线收发天线之间的第二无线链路；
    所述控制模块还用于控制所述目标处理单元利用所述第二无线链路与所述目标内存单元之间进行访存请求数据的传输。
  12. 如权利要求7或8所述的装置，其特征在于，处理单元与无线收发天线一一对应，若所述第一无线收发天线的负载大于预设的第一阈值，则所述建立模块还用于建立所述目标处理单元与辅助处理单元之间的连接关系，并建立所述辅助处理单元的第四无线收发天线与所述第二无线收发天线之间的第三无线链路；
    所述控制模块还用于控制所述目标处理单元利用所述第三无线链路与所 述目标内存单元之间进行访存请求数据的传输。
  13. 一种内存访问系统架构，其特征在于，所述系统架构包括众核层和内存堆叠层，所述众核层和所述内存堆叠层之间通过无线信号进行通信，所述众核层包括至少两个处理单元以及全局内存控制器，所述内存堆叠层包括至少两个内存单元；
    所述全局内存控制器接收目标处理单元的访问请求，所述访问请求携带所述目标处理单元待访问的目标内存单元的目标标识；
    所述全局内存控制器建立所述目标处理单元的无线收发天线与所述目标标识所标识的目标内存单元的无线收发天线之间的无线链路；
    所述全局内存控制器控制所述目标处理单元利用所述无线链路与所述目标内存单元之间进行访存请求数据的传输。
  14. 一种可读介质，其特征在于，包括执行指令，当内存控制器执行所述执行指令时，所述内存控制器执行权利要求1-6任一项所述的方法。
  15. 一种内存控制器，其特征在于，包括：处理器、存储器和总线；
    所述存储器用于存储执行指令，所述处理器与所述存储器通过所述总线连接，当所述内存控制器运行时，所述处理器执行所述存储器存储的所述执行指令，以使所述内存控制器执行权利要求1-6任一项所述的方法。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1839474A (zh) * 2004-01-28 2006-09-27 松下电器产业株式会社 模块及使用它的安装构造体
US20100115528A1 (en) * 2008-10-30 2010-05-06 Nokia Corporation Software Defined Radio
US20120280711A1 (en) * 2011-05-05 2012-11-08 Actel Corporation Fpga ram blocks optimized for use as register files
CN103607428A (zh) * 2013-10-30 2014-02-26 华为技术有限公司 一种访问共享内存的方法和装置
CN103679832A (zh) * 2013-11-25 2014-03-26 无锡市优耐特石化装备有限公司 一种rfid智能考勤系统

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7562190B1 (en) * 2005-06-17 2009-07-14 Sun Microsystems, Inc. Cache protocol enhancements in a proximity communication-based off-chip cache memory architecture

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1839474A (zh) * 2004-01-28 2006-09-27 松下电器产业株式会社 模块及使用它的安装构造体
US20100115528A1 (en) * 2008-10-30 2010-05-06 Nokia Corporation Software Defined Radio
US20120280711A1 (en) * 2011-05-05 2012-11-08 Actel Corporation Fpga ram blocks optimized for use as register files
CN103607428A (zh) * 2013-10-30 2014-02-26 华为技术有限公司 一种访问共享内存的方法和装置
CN103679832A (zh) * 2013-11-25 2014-03-26 无锡市优耐特石化装备有限公司 一种rfid智能考勤系统

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