WO2017127086A1 - Calcul analogique de sous-matrice à partir de matrices d'entrée - Google Patents

Calcul analogique de sous-matrice à partir de matrices d'entrée Download PDF

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Publication number
WO2017127086A1
WO2017127086A1 PCT/US2016/014342 US2016014342W WO2017127086A1 WO 2017127086 A1 WO2017127086 A1 WO 2017127086A1 US 2016014342 W US2016014342 W US 2016014342W WO 2017127086 A1 WO2017127086 A1 WO 2017127086A1
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WIPO (PCT)
Prior art keywords
matrix
cluster
analog
result
sub
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PCT/US2016/014342
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English (en)
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Naveen Muralimanohar
Ben FEINBERG
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Hewlett Packard Enterprise Development Lp
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Priority to PCT/US2016/014342 priority Critical patent/WO2017127086A1/fr
Priority to US16/063,892 priority patent/US10496855B2/en
Publication of WO2017127086A1 publication Critical patent/WO2017127086A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06G—ANALOGUE COMPUTERS
    • G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
    • G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers
    • G06G7/16—Arrangements for performing computing operations, e.g. operational amplifiers for multiplication or division
    • G06G7/161—Arrangements for performing computing operations, e.g. operational amplifiers for multiplication or division with pulse modulation, e.g. modulation of amplitude, width, frequency, phase or form
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06G—ANALOGUE COMPUTERS
    • G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
    • G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers
    • G06G7/14—Arrangements for performing computing operations, e.g. operational amplifiers for addition or subtraction 
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06G—ANALOGUE COMPUTERS
    • G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
    • G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers
    • G06G7/16—Arrangements for performing computing operations, e.g. operational amplifiers for multiplication or division
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
    • G11C11/15—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
    • G06F2207/4802—Special implementations
    • G06F2207/4814—Non-logic devices, e.g. operational amplifiers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
    • G06F2207/4802—Special implementations
    • G06F2207/4828—Negative resistance devices, e.g. tunnel diodes, gunn effect devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G11C2013/0045—Read using current through the cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/77—Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Definitions

  • a resistive memory array can be utilized to perform analog computations that exploit the fundamental relationship between row voltage and column current in a resistive mesh to realize an analog multiply-accumulate unit. Such a unit is not only faster than a pure digital computation, but also consumes significantly lower energy than traditional digital functional units.
  • the memory array is typically organized as a grid of cells interconnected by horizontal and vertical wires, referred to as word lines and bit lines. While it is known that accessing the memory cells involves activating a row followed by reading or writing to bit lines, the effect of row activation signal on bit line voltage/current can also be interpreted as a bitwise AND operation between row signal and cell value. With emerging resistive memories, the above concept can be further developed to build a powerful multiply-accumulate unit within the memory. For instance, the fundamental relationship between a row access voltage and the resulting bit line current can act as an analog multiplier of row voltage and cell conductance. Instead of accessing a single row as performed for loading and storing data, multiple rows can be activated concurrently.
  • FIG. 1 illustrates an example of a circuit for performing analog sub-matrix computations from input matrix values.
  • FIG. 2 illustrates an example of an engine for performing sub-matrix computations.
  • FIG. 3 illustrates an example of a sub-matrix computation derived from portions of an input matrix.
  • FIG. 4 illustrates an example of a circuit that utilizes cluster processing to performing analog sub-matrix computations from input matrix values.
  • FIG. 5 illustrates an example of a method for performing analog sub-matrix computations from input matrix values.
  • This disclosure relates a scalable and configurable circuit to perform analog computing where input matrixes are processed as sub-matrixes.
  • Memristor arrays are employed as computing engines where cell conductance and voltage values perform an analog multiplication between vectors representing the respective values.
  • the vectors from the input matrixes are generally greater than the size of the memristor arrays and thus are broken into smaller units (e.g., clusters operating on sub matrixes) to accommodate the array size and then combined via a parallel pipelined architecture to facilitate computational speed.
  • the circuit can include multiple engines that form clusters to process results received from the input matrix.
  • a first engine can be formed from a first memristor array to compute a first analog multiplication result between vectors of a first sub-matrix.
  • the first sub-matrix can be programmed from a portion of the input matrix.
  • a second engine in the cluster can be formed from a second memristor array (or different portion of first memristor array) to compute a second analog multiplication result between vectors of a second sub-matrix, where the second sub-matrix is programmed from another portion of the input matrix.
  • An analog to digital converter (or converters) generate a digital value for the first and second analog multiplication results computed by the first and second engines. These results are then combined in a pipeline that includes a shifter to shift the digital value of first analog multiplication result a predetermined number of bits to generate a shifted result. An adder then adds the shifted result to the digital value of the second multiplication result to generate a combined multiplication result from the first sub-matrix and the second sub-matrix.
  • a plurality of such clusters can be configured to process the input matrix. Resources such as ADC's can be shared between clusters to conserve power and integrated circuit resources, for example.
  • Various configuration options can be provided to dynamically configure operations of the clusters, digital converters, shift operations, and other aspects of the pipelined architecture.
  • FIG. 1 illustrates an example of a circuit 100 for performing analog sub-matrix computations from input matrix values.
  • the circuit 100 includes an engine 1 10 (or engines) formed from a memristor array to compute an analog multiplication result shown as ANALOG RESULT 1 between vectors of a sub-matrix shown as SUBMATRIX INPUT.
  • the sub-matrix is programmed from a portion of an input matrix.
  • the term input matrix refers to a matrix of values to be multiplied where the respective values are greater than the number of computing elements (e.g.,
  • a sub-matrix represents a computing matrix that computes portions of input vectors from the input matrix as smaller computing values that can be consumed/processed (wholly or in part) within the sub-matrix.
  • An analog to digital converter (ADC) 1 30 (or converters or converter arrays) generates a digital value for the analog multiplication results shown at 140 and 150 as computed by the first and second engines, respectively.
  • the engine 1 10 can be combined with other engines to form a cluster of engines. If a single engine is employed, results can be stored in a holding buffer, shifted, and then added to other results that are processed by the single engine. If multiple engines are employed shift and add operations can occur in parallel across an internal h-tree configuration within a cluster and/or across an external h-tree configuration connecting multiple clusters where cluster results are combined by an external controller (See e.g., FIG. 4).
  • a shifter 160 shifts the digital value of the analog multiplication result 140 a predetermined number of bits to generate a shifted result at 164.
  • An adder 170 adds the shifted result 164 to the digital value of another multiplication result 150 to generate a combined multiplication result from the sub-matrix.
  • a plurality of such engines 1 10 can be combined to form computing clusters that are illustrated and described below with respect to FIG. 4, where each cluster has its respective shifting and adding operations to pipeline results. Outputs from the respective clusters can be combined to form an overall result for the matrixes to be multiplied.
  • the engine 1 10 can be configured to perform a matrix dot product operation between the vectors, in one example.
  • the respective engines can perform a matrix cross product operation between the vectors or a multiply operation between two scalar values, for example.
  • a digital to analog converter (DAC) (not shown) can be provided to generate analog representations of the vectors.
  • a vector buffer (See e.g., FIG. 4) can be provided to store the vectors to be digitized by the DAC (or DACS).
  • the engine 1 1 10 can be combined with at least one other engine and configured as a cluster of engines.
  • the output of each engine in the cluster can be combined to form combined multiplication result representing multiplications from the vectors represented in the input matrix.
  • the engines can communicate across an active h-tree within the cluster of engines where the shift width varies at each level of the h-tree. For example, at one level of the h-tree the shift width may be two digits where at other levels od the h-tree, the shift width may be a number other than two.
  • a configuration register See e.g., FIG.
  • a results buffer (not shown) can also be provided to hold the combined multiplication result from the cluster.
  • At least one other cluster can be provided to process another portion of the matrix. Output from each cluster can be added to form an overall multiplication result for the matrix.
  • ADC analog to digital converter
  • a system controller See e.g., FIG. 4 can be provided to control the ADC array and to aggregate the computation results from the respective clusters.
  • FIG. 2 illustrates an example of an engine 200 for performing sub-matrix computations.
  • the engine 200 includes multiple rows for programming a first part of an N x M matrix as N voltage inputs of the matrix which are multiplied as G column conductance values representing the M vector of the matrix, where N, M, and G are positive integers respectively.
  • the engine 200 can be employed as a basic micro architecture of a dot product engine (DPE) although other types of multiplications are possible.
  • DPE dot product engine
  • Each row can be equipped with a Digital-to-Analog Converter to provide different read voltages determined based on the input vector to be multiplied.
  • every column has a transimpedance amplifier such as shown at 210, which in turn is connected to an Analog-to-Digital Converter (ADC) to digitize the bit-line current from the respective columns.
  • ADC Analog-to-Digital Converter
  • an ADC requires more silicon real estate than an array.
  • an ADC can be operated at higher frequency and time multiplexed across multiple bit lines.
  • a set of configuration registers (not shown) specifies number of valid output bits (No) from the ADC, number of simultaneous rows that can be activated (NR), and bit density of cells (Cb). These configuration registers help tailor the engine 200 to different applications dynamically.
  • the engine 200 has two modes of operation: memory and compute modes.
  • the memory mode is similar to a typical memory - a read operation can leverage ADCs in a DPE to sense a cell content.
  • a write to a cell is accomplished by activating a row followed by the application of write voltage to the selected bit lines.
  • a program and verify circuit can be employed for normal write operations.
  • compute mode based on the configuration register NR, multiple rows are activated, and an ADC is used to convert the resulting bit line current to a fixed point number.
  • each element of matrix B is first programmed to its equivalent analog conductance state of the memristors G.
  • the input vector a is converted to analog input vector voltages Vi by the respective DACs.
  • each element of B can be represented by a memristor cell and the input vector elements can be converted to a single analog value using DACs.
  • the mapping process begins with scanning of matrix elements for the highest (h) and the lowest (I) values. These values typically correspond to the minimum and maximum resistances of a memristor cell. Every other element is then mapped to a resistance according to its ratio with h and I.
  • the actual mapping process can be more complex than the linear mapping mentioned above. For instance, the effect of parasitic such as IR drop, data pattern, location of a cell and so forth can change how a value is mapped to a cell conductance.
  • the output current is collected by the transimpedance amplifier at each column with a reference resistance RS.
  • the output current 10 ⁇ Vi.Gi reflects the corresponding dot-product operation. This value is then digitized using an ADC.
  • ADC bits analog to digital converter specification
  • size of input bits to DAC digital to analog converter specification
  • size of an array are all coupled to each other.
  • NR is the number of rows activated in DPE mode
  • DACb is the input bit width of DAC
  • Mb is the number of bits stored in a memristor cell.
  • Equation 1 specifies ADC and DAC combinations that can be dynamically specified via register settings.
  • FIG. 3 illustrates an example of a sub-matrix computation derived from portions of an input matrix.
  • a 4 x 4 input matrix 310 is broken into smaller sub-matrixes.
  • One such sub-matrix portion is shown at 320 which includes members 2, 7, 3, and 0.
  • the sub-matrix portion 320 is further represented as bit slices 324 and 326 which are multiplied by vector portion represented by members 8 and 6 at 330.
  • the matrices for scientific applications are typically much greater than a single engine can compute. For example, each element utilizes up to 252 bits to represent a floating point number as a fixed point number, whereas a memristor cell can store up to 5 bits, for example.
  • an input matrix is divided into both fewer rows/columns and smaller bit slices.
  • the input matrix 310 is first divided into a set of submats (also referred to as sub-matrixes), where a submat is a contiguous section of the input matrix with dimensions similar to or smaller than the respective engine.
  • submats also referred to as sub-matrixes
  • a submat is a contiguous section of the input matrix with dimensions similar to or smaller than the respective engine.
  • Fig. 3 shows an example 4 x 4 matrix being split into four sub-matrices but other matrix sizes and sub-matrix divisions are possible.
  • each memristor cell in this example can store 2 bits, a sub-matrix such as shown at 320 is further broken into bit slices as shown at 324 and 326.
  • these 7b outputs shown at 340 are shifted by two bits (with shift width being the same as the bit-slice size) and added together at 350 to produce result matrix having members 58 and 24 at 360.
  • DPEs or engines
  • bit-slice results they are combined together by shift and add operations. Similar to the limited storage of memristor cells, on most occasions a digital to analog converter cannot convert an entire element to an analog value. In this case, the vector is also partitioned into bit-slices based on DAC specification (DACb), and their partial results are combined using similar shift and add operations as described herein.
  • DACb DAC specification
  • FIG. 4 illustrates an example of a circuit 400 that utilizes cluster processing to performing analog sub-matrix computations from input matrix values.
  • multiple DPE clusters are shown at 410, 412, 414, and 416 are employed to perform the sub-matrix processing described herein.
  • Two of the clusters 410 and 412 can utilize a common ADC array 420 and two of the clusters 414 and 416 can utilize a common ADC array 424.
  • a system controller 430 and I/O buffer 434 can be provided for managing and aggregating results within the respective clusters.
  • the cluster 410 e.g., first cluster
  • the cluster 412 e.g., second cluster
  • the analog to digital converter (ADC) array 420 digitizes the first and second intermediate results, respectively from the clusters 410 and 412.
  • An example high-level block diagram of a given cluster is shown at 440.
  • Each cluster can include a plurality of engines formed from a memristor array to compute analog multiplication results between vectors of a sub-matrix, where the sub-matrix is programmed from a portion of the input matrix.
  • each cluster shown at 440 can include shifters to shift a digital value of a first cluster analog multiplication result a predetermined number of bits to generate a shifted cluster result. Also, each cluster shown at 440 can include adders to add the shifted cluster result to a digital value of a second cluster multiplication result to generate a combined multiplication result from the first cluster and the second cluster.
  • a set of engines (also referred to as DPEs) and associated circuits used to evaluate a sub-matrix can be referred to as a cluster.
  • a sub-matrix can be sized such that its row and column counts are the same as or less than a given DPE.
  • the number of DPEs in a cluster depends on the capacity of a memristor cell and the size of the matrix elements. If B is the size of fixed point elements in the input matrix, then a cluster needs B/Mb DPEs, where Mb is the number of bits per cell.
  • the DPEs within a cluster operate on the same submat but on different bit slices with each of them generating partial result in parallel.
  • DPEs can be connected together by an active h-tree network in which every joint has a shift and add unit.
  • the h-tree connections are shown in bold at 444.
  • the final result through the h-tree is the product of submat and the corresponding section of the input vector with the respective bits.
  • the ADC can be a high overhead component both in terms of silicon real-estate and energy - a single 8 bit ADC takes 7 times the area of a DPE array and consumes over 90% of DPE cluster power. Rather than having an ADC for every DPE column, a single ADC operating at a higher sample rate can be employed per DPE.
  • each DPE shares its ADC with a neighboring cluster as shown at 420 and 424. Since it is unlikely that all DPE clusters within a system will be active simultaneously (due to peak power constraint), sharing allows area savings at a modest performance cost.
  • a DAC array shown at 450 is another component whose area and power values can be similarly considered.
  • a DAC array can also be shared across clusters to reduce silicon area.
  • Each DPE cluster can operate on a single submat with a common input vector. This input vector is generated using a shared DAC array that fan-outs to all the DPEs within a cluster.
  • the cluster 440 also has a local vector buffer 454 and partial result buffer 460 to store input and buffer intermediate outputs.
  • the local vector buffer 454 stores the part of the input vector that operates on the submat mapped to that cluster. For each iteration (or DPE operation), it provides DACb x DPErows bits of data to the DAC array 450.
  • the partial result buffer 460 is used to store and aggregate partial results due to DAC bit slices. It operates at the same rate as ADC sample rate so that the entire cluster can operate in lock step.
  • Each cluster is highly customizable and can cater to a wide range of applications with different matrix dimensions and accuracy requirements.
  • the DPE specifications such as DAC bits (DACb), cell levels (Mb), ADC output, and shift size can be dynamically configured via registers 464.
  • DACb DAC bits
  • Mb cell levels
  • ADC output ADC output
  • shift size can be dynamically configured via registers 464.
  • Ndpe is the number of DPEs within a cluster
  • Vectorb is the bitwidth of input vector elements
  • the circuit 400 shows one example multiplier/accelerator organization.
  • the circuit 400 has multiple clusters 410-416 to operate on various sub-matrices in parallel. Since the output from each cluster is a complete fixed point value, the clusters are connected using a relatively simple h-tree network. Each joint in the h-tree 444 performs a simple add operation instead of shift-and-add performed within a cluster as shown at 440.
  • the system controller 430 keeps track of various sub-matrices mapped to clusters and collects the aggregated result.
  • the central controller 430 is also leveraged to track and avoid DPEs with permanent cell errors. To minimize cluster latency, the entire multiply operation is pipelined, and the number of clusters that can operate in parallel to cap the total power.
  • the computation pipeline After mapping the input matrix to DPE cells, the computation pipeline begins by sending input vector to NAC clusters using an input h-tree, for example. Each cluster receives the portion of the input vector that operates of its submat, and stores it in the local vector buffer 454. In parallel, a bit slice of input vector is sent to the DAC array 450 to initiate DPE computation. After the DPE generates a result, each ADC output is placed on the first level in the active h-tree. The shift-add unit in each h-tree joint serves as pipeline stage for the values traversing the h-tree. Thus, the entire DPE cluster operates in lockstep with ADC sample rate.
  • the circuit 400 can communicate to a general purpose processor using traditional DDR bus controller, for example (not shown).
  • clusters can be connected through other network topologies such as a grid, for example.
  • the add operation can be performed on outputs of clusters and can be centralized or distributed depending on the topology and area constraint.
  • FIG. 5 illustrates an example of a method 500 for performing analog sub-matrix computations from input matrix values.
  • the method 500 includes computing a first analog multiplication result between vectors of a first sub-matrix (e.g., via Engine 1 10 of FIG. 1 ). The first sub-matrix is programmed from a portion of an input matrix.
  • the method 500 includes computing a second analog multiplication result between vectors of a second sub-matrix (e.g., via Engine 120 of FIG. 1 ). The second sub-matrix is programmed from another portion of the input matrix.
  • the method 500 includes generating a digital value for the first and second analog multiplication results (e.g., via ADC 130 of FIG.
  • the method 500 includes shifting the digital value of first analog multiplication result a predetermined number of bits to generate a shifted result (e.g., via shifter 160 of FIG. 1 ).
  • the method 500 includes adding the shifted result to the digital value of the second multiplication result to generate a combined multiplication result from the first sub-matrix and the second sub-matrix (e.g., via adder 170 of FIG. 1 ).
  • multiple sub-matrixes can be concurrently processed via the method 500 such as via the clustering methods described herein.
  • the method 500 can also include performing a matrix dot product operation between the vectors, performing a matrix cross product operation between the vectors, or performing a multiply operation between two scalar values. While the method 500 includes computing operations within a cluster, multiple clusters can be operated in parallel such as via the h-tree configuration depicted in FIG. 4 where multiple cluster communicate across the h-tree. A system controller can be provided to then aggregate the results from each respective leg of the h-tree operated by a respective cluster.

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Abstract

Selon l'invention, un circuit comprend un moteur pour calculer les résultats de multiplication analogique entre des vecteurs d'une sous-matrice. Un convertisseur analogique vers numérique (CAN) génère une valeur numérique pour les résultats de multiplication analogique calculés par le moteur. Un registre à décalage décale d'un nombre prédéterminé de bits la valeur numérique de résultats de multiplication analogique pour générer un résultat décalé. Un additionneur ajoute le résultat décalé à la valeur numérique d'un second résultat de multiplication pour générer un résultat de multiplication combinée.
PCT/US2016/014342 2016-01-21 2016-01-21 Calcul analogique de sous-matrice à partir de matrices d'entrée WO2017127086A1 (fr)

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US16/063,892 US10496855B2 (en) 2016-01-21 2016-01-21 Analog sub-matrix computing from input matrixes

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