WO2017126493A1

WO2017126493A1 - Signal generation circuit and voltage conversion apparatus

Info

Publication number: WO2017126493A1
Application number: PCT/JP2017/001350
Authority: WO
Inventors: 新太中島
Original assignee: 株式会社オートネットワーク技術研究所; 住友電装株式会社; 住友電気工業株式会社
Priority date: 2016-01-19
Filing date: 2017-01-17
Publication date: 2017-07-27
Also published as: JP2017131009A

Abstract

In the present invention, a signal generation circuit and a voltage conversion apparatus, which output PWM signals to a plurality of objects to be driven on the basis of set target values, are achieved by having a configuration in which the minimum unit of a duty can essentially be set to be less than a predetermined settable value and concentration of heat generation spots can be suppressed. In a signal generation circuit (1), a determination unit determines, when the target values satisfy a prescribed condition, a combination of duties of the PWM signals to be outputted to the objects to be driven, by using a combination of a variety of settable values on the basis of the target values. An allocation unit allocates, each time a combination is determined by the determination unit, the settable values for the determined combination to the objects to be driven, and changes the allocation priority order according to the lapse of time.

Description

Signal generation circuit and voltage converter

The present invention relates to a signal generation circuit and a voltage conversion device.

Conventionally, voltage converters that convert voltage by driving a switching element with a PWM signal have been widely used. This voltage conversion device of the PWM control system calculates a voltage command value based on, for example, a voltage target value, and sets a value corresponding to the calculated voltage command value in a PWM signal generation unit, thereby depending on the target value. A PWM signal with a specified duty is generated.

However, if the minimum unit of the value (settable duty) that can be set in the PWM signal generation unit is relatively large, the duty of the PWM signal cannot be changed smoothly with respect to the change in the target value, and the output voltage Will change stepwise. For example, in the configuration in which the target value to be set in the PWM signal generation unit is calculated as the operation amount in PWM control, when the minimum unit of the settable value (settable duty) is larger than the minimum unit of the target value, There is a problem that the duty of the PWM signal cannot be smoothly changed with respect to the change of the target value and the load fluctuation, and the error of the output voltage becomes large.

On the other hand, in Patent Document 1, when the on / off time of the PWM signal is calculated for each cycle of PWM control, the remainder of the division with the voltage command value as the dividend is rounded down to calculate on / off. A PWM inverter that calculates time and outputs a PWM pulse based on the calculation result is disclosed. The remainder generated by the above calculation corresponds to a voltage command value that is truncated without being reflected in the on / off time.

In this PWM inverter, the remainder that is not reflected in the on / off time in the previous computation is newly added to the next computation by adding the rounded down remainder to the voltage command value in the computation after the next cycle. / It is reflected in the off time, and it is repeated that the remainder at that time is further reflected in the next calculation. For this reason, the average value of the on / off time set for the PWM signal generation unit can be brought close to the target on / off time to be originally set.

Japanese Patent Laid-Open No. 3-98470

However, the technique disclosed in Patent Document 1 does not assume a configuration in which a plurality of PWM signal output paths exist. In particular, the technique of Patent Document 1 is a configuration that corrects a PWM signal of only one output path, and further, a configuration that performs correction by a method that reflects a cumulative value that is rounded down. However, it is difficult to complete the correction in a short time and increase the resolution.

On the other hand, the situation is different in a multiphase converter in which a plurality of PWM signal output paths exist. FIG. 10 illustrates a multiphase converter including four PWM signal generation units. In this example, the resolution in the four PWM signal generation units is 0.1 (%), and the minimum unit of the settable value (settable duty) is 0.1. In such a multiphase converter, when the instruction duty given to each PWM signal generation unit is 50.16 (%), the duty cannot be set with an accuracy of 50.16 (%) in each PWM signal generation unit. A method of setting the PWM signal generation unit at 50.1 (%) close to 50.16 (%) is employed. However, in this method, since it is output with a duty of 50.1 (%), an error from the instruction value of 50.16% becomes large.

On the other hand, the inventors of the present application assumed a configuration as shown in FIG. 11 as a method for solving such a problem. In the method of FIG. 11, 50.16 (%) which is a settable value (settable duty) lower than the instruction value 50.16 (%) is assigned to two PWM signal generation units, 50.16 (% ), Which is a settable value (settable duty) higher than 50.2 (%), is assigned to the remaining PWM signal generation units. According to this method, the average duty of the four PWM signal generation units is 50.15 (%), which is closer to the instruction value of 50.16%.

However, if the minimum unit of duty is substantially reduced by making the duty of some phases relatively low and the duty of other phases relatively high in this way, the duty is set high. There is a concern that in the phase, the amount of current accompanying driving increases, and the heat generation points concentrate.

The present invention has been made based on the above-described circumstances, and a signal generation circuit and a voltage conversion device that output PWM signals to a plurality of driving objects based on a set target value are determined based on predetermined settable values. Another object of the present invention is to realize a configuration that can substantially reduce the minimum unit of duty and that can suppress concentration of heat generation points.

The first invention is
The PWM signal is output to a plurality of driving targets, and the duty of the PWM signal output to each of the plurality of driving targets is selected from a plurality of predetermined settable values based on the set target value. Each of the signal generation circuits to be set,
When the target value satisfies a predetermined condition, a combination of duty of PWM signals output to the plurality of driving targets is determined based on a combination of a plurality of types of the settable values based on the target value, and the settable value Each time the combination is determined, the settable value of each of the determined combinations is assigned to the plurality of driving targets, and a high value is obtained when a plurality of types of the settable values are assigned to the plurality of driving targets. And a control unit that changes the priority order of assigning as time elapses.

As in the first invention, if the combination of the duty ratios of the PWM signals output to a plurality of driving targets is a combination of a plurality of types of settable values, the average value of the duty given to the plurality of driving targets is other than the settable value. Since the value can be a value, the minimum unit of the duty can be substantially smaller than a predetermined settable value. In addition, since the control unit changes the priority order for assigning a high value when assigning a plurality of types of settable values to a plurality of drive targets in accordance with the passage of time, the drive that sets the duty relatively high The bias of the object can be suppressed, and the concentration of heat generation points can be effectively suppressed.

The second invention is
The PWM signal is output to a plurality of driving targets, and the duty of the PWM signal output to each of the plurality of driving targets is selected from a plurality of predetermined settable values based on the set target value. Each of the signal generation circuits to be set,
A temperature detection unit for detecting the temperature of each of the plurality of driving objects;
When the target value satisfies a predetermined condition, a combination of duty of PWM signals output to the plurality of driving targets is determined based on a combination of a plurality of types of the settable values based on the target value, and the settable value Each time the combination is determined, the settable value of each of the determined combinations is assigned to the plurality of driving targets, and a high value is obtained when a plurality of types of the settable values are assigned to the plurality of driving targets. A control unit that determines a priority order for assigning a driving target having a low detection temperature by the temperature detection unit;
Have

If the combination of the duty ratios of the PWM signals output to a plurality of driving targets is a combination of a plurality of settable values as in the second invention, the average value of the duty given to the plurality of driving targets is other than the settable value. Since the value can be a value, the minimum unit of the duty can be substantially smaller than a predetermined settable value. In addition, the control unit determines the priority order for assigning a high value when assigning a plurality of types of settable values to a plurality of driving objects in a manner that prioritizes the driving object having a low temperature detected by the temperature detection unit. A drive target having a lower temperature can be selected as a drive target having a relatively large drive current. Therefore, the concentration of heat generation points can be effectively suppressed.

1 is a block diagram illustrating a configuration example of a voltage conversion device according to a first embodiment. FIG. 3 is a block diagram illustrating a configuration example of a part of the signal generation circuit according to the first embodiment. It is a timing diagram for demonstrating operation | movement of a generation | occurrence | production part. It is explanatory drawing for demonstrating the operation | movement in which the average duty of a PWM signal is decided by m set value for n period. 4 is a flowchart illustrating a processing procedure of a CPU that executes a periodic interrupt process in the signal generation circuit according to the first embodiment. It is a flowchart which shows the process sequence of CPU which concerns on the subroutine of a setting value determination. It is a graph which shows the list of the m setting values for n periods determined according to the target value. It is explanatory drawing explaining the method of switching a priority according to progress of time. FIG. 10 is an explanatory diagram for explaining a method of determining a priority order according to temperature with respect to the signal generation circuit according to the second embodiment. 6 is an explanatory diagram schematically illustrating a configuration of Comparative Example 1. FIG. It is explanatory drawing which illustrates the structure of the comparative example 2 roughly.

The desirable form of invention is illustrated below.
In the present invention, when the target value is within the predetermined range, the control unit sets the combination of the duty ratios of the PWM signals output to the m driving targets to be a minimum value among settable values larger than the target value. 1 duty and a second duty which is the maximum value among settable values smaller than the target value are determined in combination, and m is determined each time a combination of the first duty and the second duty is determined according to the target value. A configuration in which either the first duty or the second duty is assigned to each of the driving targets, and a priority order of the assignment of the first duty in the m driving targets may be changed. .

In this way, the first duty, which is the minimum value among the settable values larger than the target value, and the second duty, which is the maximum value among the settable values smaller than the target value, are set as m driving targets. If each is assigned, the average value of the duty of the PWM signal output to the m driving objects in that period is finely adjusted from the minimum unit of the settable value, and the average value of the duty given to the m driving objects is determined. It becomes easier to get closer to the target value.

Any of the signal generation circuits described above, a plurality of voltage conversion units that convert voltage by switching according to the duty of each PWM signal generated by the signal generation circuit, and an output detection unit that detects an output from the voltage conversion unit And a setting unit that sets a target value based on the detection result of the output detection unit.

According to this configuration, it is possible to apply the signal generation circuit that can substantially reduce the minimum unit of the duty to a predetermined settable value to the voltage conversion device, and the accuracy of the output voltage in the voltage conversion device. Can be increased. Furthermore, in such a voltage converter, concentration of heat generation points can be suppressed.

<Example 1>
Embodiment 1 of the present invention will be described below.
In FIG. 1, reference numeral 100 denotes a voltage converter, and the voltage converter 100 is connected to an external battery 2 and a load 3. The voltage conversion apparatus 100 steps down the DC voltage from the battery 2 and supplies it to the load 3.

The voltage conversion apparatus 100 includes m converters (corresponding to voltage conversion circuits) CV1, CV2,... CVm and converters CV1, CV2,. Drive circuit DC1, DC2,... DCm, a signal generation circuit 1 that generates m PWM signals, a capacitor C1 that smoothes the voltage stepped down by each converter CV1, CV2,. And a current detection circuit 17 for detecting the output current. Output currents from the respective converters CV1, CV2,... CVm are supplied to the load 3 via the current detection circuit 17, and a voltage supplied to the load 3 is supplied to the signal generation circuit 1.

Converters CV1, CV2,... CVm are so-called multiphase converters that are connected in parallel to each other, and may boost DC voltage. One converter CVk (k is a natural number less than or equal to m: the same applies below) includes a switching element (hereinafter simply referred to as a switch) Ska that is an N-channel MOSFET to which a DC voltage supplied from the battery 2 is applied to the drain, One end is connected to the capacitor C1, and an inductor Lk whose other end is connected to the source of the switch Ska and a source-grounded switch Skb whose drain is connected to a connection point between the switch Ska and the inductor Lk are provided. The switches Ska and Skb may be P-channel type MOSFETs or other switching elements such as bipolar transistors.

In this configuration, temperature sensors TH1, TH2,... THm are provided at positions close to the converters CV1, CV2,. Each of the temperature sensors THk has the shortest distance to the corresponding converter CVk component among the converters CV1, CV2,... CVm, and is specifically provided in the vicinity of the switching element of the corresponding converter CVk. It has been. Such a configuration applies to any case where k is a natural number of 1 to m.

The switch Skb can be replaced with a diode whose anode is connected to the ground potential. Here, the switch Skb having a lower on-resistance than the diode performs so-called synchronous rectification, thereby reducing the loss of the converter CVk. . In the case where the current flowing through the inductor Lk reversely flows when the converter CVk is lightly loaded due to synchronous rectification, for example, a resistor is inserted in series with the inductor Lk to detect the current of the inductor Lk, and when the reverse current is detected, the drive circuit DCk The on signal of the switch Skb may be stopped at.

The one drive circuit DCk applies an ON signal for alternately turning on the switches Ska and Skb in each control cycle to the gates of the switches Ska and Skb based on the PWM signal given from the generating unit SGk. The gate of the switch Skb is supplied with an ON signal whose phase is substantially inverted with respect to the ON signal supplied to the gate of the switch Ska and a so-called dead time is ensured.

The signal generation circuit 1 is configured to output a PWM signal to a plurality of driving targets, and based on the set target value, the duty of the PWM signal output to each of the plurality of driving targets is set to a plurality of predetermined settings. It is a circuit that selects and sets each possible value. This signal generation circuit 1 includes generators SG1, SG2,... SGm, and generators SG1, SG2,... SGm that give PWM signals having different phases by 2π / m to the drive circuits DC1, DC2,. And a control unit 10 for setting data in each. The generators SG1, SG2,... SGm may be included in the controller 10. Hereinafter, the phases of the PWM signals generated by the generators SG1, SG2,..., SGm are referred to as first phase, second phase,.

The control unit 10 includes a microcomputer having a CPU 11. The CPU 11 includes a ROM 12 that stores information such as programs, a RAM 13 that stores temporarily generated information, an A / D converter 14 that converts an analog voltage into a digital value, and an interrupt that processes a plurality of interrupt requests. The controller 15 is connected to each other by a bus. Further, generators SG1, SG2,... SGm are connected to the CPU 11 by a bus. The A / D converter 14 is supplied with a detection voltage from the current detection circuit 17 and an output voltage supplied to the load 3. In this configuration, the current detection circuit 17 and the path 18 for inputting a voltage to the A / D converter 14 constitute an output detection unit 19, and output currents from the converters CV1, CV2... CVm (voltage conversion unit) and It functions to detect the output voltage. In the example of FIG. 1, the path 18 is configured to input the voltage of the output-side conductive path 5 to the A / D converter 14, but the voltage of the output-side conductive path 5 is divided to A / D. The structure which inputs into the converter 14 may be sufficient.

As shown in FIG. 2, the ROM 12 may include a setting value storage table 121 that stores a plurality of setting values determined in association with target values to be described later. However, the configuration may not include the set value storage table 121. In this configuration, an example in which the set value storage table 121 is not used will be described as a representative example.

The RAM 13 includes setting

value storage areas

131a and 131b that are duplicated in order to store and read a plurality of setting values at different timings. The set values stored in the set value storage area 131a (or 131b) are sequentially set in the generation units SG1, SG2,... SGm in an interrupt process to be described later controlled by the interrupt controller 15. Yes.

The generator SG1 includes a register buffer 161 in which set values are set, a duty register 162 in which the contents of the register buffer 161 are periodically loaded, and a PWM signal that generates a PWM signal with a duty corresponding to the contents of the duty register 162 A generation unit 163. The PWM signal generation unit 163 gives a load signal for loading the contents of the register buffer 161 to the duty register 162. The same applies to the other generators SG2, SG3,.

The PWM signal generation unit 163 generates a PWM signal having an on time that is an integral multiple of the period of the internal clock, based on an internal clock (not shown) and the contents of the duty register 162. The PWM signal generated by the PWM signal generation unit 163 is supplied to the drive circuit DC1 and is also supplied to the interrupt controller 15 as one of interrupt requests. The same applies to the PWM signal generators 163 of the other generators SG2, SG3,.

Returning to FIG. 1, when any of the above interrupt requests is received, the interrupt controller 15 gives a signal (so-called INT signal) for requesting an interrupt to the CPU 11, and the CPU 11 receives an acknowledge signal (so-called INTA signal). ) Is sent, the interrupt vector corresponding to each interrupt request is sent to the bus. When the interrupt vector sent to the bus is read by the CPU 11, the CPU 11 executes an interrupt process corresponding to each interrupt request.

The current detection circuit 17 includes a resistor R1 and a differential amplifier DA1. The voltage drop generated in the resistor R1 due to the output current is amplified by the differential amplifier DA1 to become a detection voltage corresponding to the output current, and is converted into a digital value by the A / D converter 14.

In the above-described configuration, the currents flowing from the battery 2 to the inductors L1, L2,... Lm are switches S1a, S2a,... Sma with a phase difference of 2π / m from the drive circuits DC1, DC2,. .., Sma, and the currents flowing through the inductors L1, L2,... Lm return to the switches S1b, S2b,... Smb during the OFF period of each of the switches S1a, S2a,.

In this way, currents flowing with a phase difference of 2π / m from one end of each inductor L1, L2,... Lm to the load 3 are added, so that each converter CV1, CV2,. The output power is added. An ON signal given to each switch S1a, S2a,... Sma with a phase difference of 2π / m, and a current flowing through each inductor L1, L2,. A timing diagram showing the time relationship is detailed in Japanese Patent Application Laid-Open No. 2013-46541.

Now, the CPU 11 of the signal generation circuit 1 controls the voltage supplied to the load 3 by, for example, a current mode control system that executes voltage loop control and current loop control in parallel. In the voltage loop control, the CPU 11 performs an operation to obtain a target current value in the subsequent current loop control based on a deviation obtained by subtracting the digital value obtained by A / D converting the output voltage supplied to the load 3 from the target voltage value. Calculate the quantity. In this voltage loop control, the voltage output from each converter CV1, CV2,... CVm is the control amount.

In the current loop control, the CPU 11 performs m generation units SG1 based on a deviation obtained by subtracting the digital value obtained by A / D converting the output current supplied to the load 3 from the target current value from the previous voltage loop control. , SG2... SGm is calculated as a target value. In this configuration, the control unit 10 (specifically, the CPU 11) corresponds to an example of a setting unit that sets a target value. The CPU 11 further determines a settable value that can be set in each of the generating units SG1, SG2,... SGm according to the calculated target value. As described above, in this configuration, the duty of the PWM signal output from each of the generators SG1, SG2,... SGm is selected from a plurality of predetermined settable values and set.

The settable value here refers to a value that is an integral multiple of the minimum unit (minimum increment) that is reflected in the change in the output PWM signal when each generator SG1, SG2,... SGm is set. That is, the duty of the PWM signal output from each of the generators SG1, SG2,... SGm is selected from a value (settable value) that is an integral multiple of the minimum unit. Hereinafter, for the sake of simplicity, the settable values determined to be set in each of the generating units SG1, SG2,. The generators SG1, SG2,... SGm generate a PWM signal having a duty corresponding to the set value when the determined set value is set. In this current loop control, the current output from each converter CV1, CV2,... CVm is the controlled variable.

Here, when the output voltage and output current of the voltage converter 100 fluctuate relatively gently in time, the control cycle of the voltage loop control and current loop control is n times the PWM cycle (n is a natural number of 1 or more). ) Is sufficient. Therefore, in this configuration, the set values for n cycles for m generators SG1, SG2,... SGm are determined collectively every n cycles of the PWM cycle and stored in the set

value storage area

131a or 131b. Each of the m set values is sequentially set in the generators SG1, SG2,..., SGm for each cycle in the interrupt process generated in the PWM cycle, and this is repeated over n cycles.

In the following, m = n = 3 for simplicity, but is not limited thereto, and m may be 2 or 4 or more. n may be a natural number other than 3, may be 2 or more, and may be 1. Moreover, m and n may be different. The m set values do not necessarily have to be set for all the generation units SG1, SG2,... SGm every cycle, and the set values change when the set values change between a certain cycle and the next cycle. You may make it set only with respect to a generation | occurrence | production part.

Next, a mechanism in which the PWM signal generation unit 163 generates a PWM signal corresponding to the contents of the duty register 162 will be described by taking the generation unit SG1 that generates the first phase PWM signal as an example. FIG. 3 is a timing chart for explaining the operation of the generation unit SG1. The five timing charts shown in FIG. 3 all have the same time axis as the horizontal axis. The vertical axis corresponds to the signal level of the first phase PWM signal and the first phase PWM signal from the top of the figure. The execution state of the interrupt processing to be executed, the contents of the register buffer 161 of the generator SG1, the on / off state of the load signal for loading the contents of the register buffer 161 into the duty register 162, and the duty register of the generator SG1 The contents of 162 are shown.

Regarding the PWM signal of each phase, each of the period from time t21 to t22, from time t22 to t23, and from time t23 to t31 is the first period, the second period, and the third period in the n period (n = 3). Yes, from time t13 to t21 is the third period in the previous n period. The timing when the first phase PWM signal rises coincides with the start time of each cycle. The timing when the PWM signal rises in each of the second phase, the third phase, ..., the m-th phase, and the timing related to processing, signals, etc. are 2π / m, 2π × 2 / m · with respect to the timing shown in FIG. .. The phase is delayed by 2π × (m−1) / m.

The falling edge when the signal level in each cycle of the PWM signal changes from H to L is accepted as an interrupt request to the interrupt controller 15 and the interrupt process is executed once. Specifically, the interrupt process is executed when the on-time T13, T21, T22, and T23 in each cycle has elapsed from time t13, t21, t22, and t23. In each interrupt process, the set value for the next PWM cycle is read from the set

value storage area

131a or 131b included in the RAM 13 and set in the register buffer 161.

The setting value is stored in the setting value storage area 131a (or 131b) for n cycles during which reading from the setting value storage area 131b (or 131a) is performed and from the setting value storage area 131a (or 131b). Is carried out during n cycles preceding the cycle in which reading is started. For example, the setting values read from the setting value storage area 131a (or 131b) in the third period, the first period, and the second period that are continuous from the time t13 are the third period, the first period that is continuous before the time t13, It is calculated during the period and the second period and is stored in the set value storage area 131a (or 131b).

The m set values for the first period, the second period, and the third period stored in the set value storage area 131a (or 131b) are the third period that continues after each set value is stored, The data are sequentially read out by the interrupt processing for each phase in the first cycle and the second cycle, and set in the register buffer 161 of the corresponding generation unit. Thus, in the interrupt processing for each phase in the third period, the first period, and the second period, the contents of the register buffer 161 of the corresponding generation unit are the first period, the second period, and the third period. It is rewritten to the set value.

On the other hand, at the rise when the signal level of the PWM signal changes from L to H, that is, at times t13, t21, t22, t23, and t31, the contents of the register buffer 161 are transferred from the PWM signal generation unit 163 to the duty register 162. A load signal for loading is provided. Thereby, during each of the first period, the second period, and the third period, the contents of the duty register 162 are held at the set values for the first period, the second period, and the third period. The duty of the PWM signal in each of the first period, the second period, and the third period is determined by these set values.

Next, a specific example in which set values corresponding to target values are set in the generating units SG1, SG2, and SG3 will be described.
FIG. 4 is an explanatory diagram for explaining an operation in which an average duty of a PWM signal is determined by m set values for n cycles. In the figure, the horizontal axis represents time, and the vertical axis represents the signal levels of the PWM signals of the first phase, the second phase, and the third phase. FIG. 4 shows how the PWM signals from the first phase to the third phase in each of the first cycle, the second cycle, and the third cycle of the PWM cycle change on / off for two consecutive n cycles. is there. Again, for simplicity, m = n = 3.

In the first embodiment, the period of the PWM signal generated by each of the generating units SG1, SG2, and SG3 is 10 μs, and the minimum unit (that is, the minimum increment) of the set value that can be set in each of the generating units SG1, SG2, and SG3 is 1. The minimum unit of 1 corresponds to 1% of the duty of the PWM signal (that is, the ON time of 0.1 μs). In other words, the duty of the PWM signal generated by each of the generating units SG1, SG2, and SG3 can be set in increments of 1%. On the other hand, the minimum unit of the target duty calculated by the CPU 11 by the PID calculation is smaller than that, for example, 0.1%.

Suppose that the total operation amount as a result of the PID calculation in the previous n cycles is 67.2% at the timing shown in FIG. This means that the added value of the target value to be set for each of the generating units SG1, SG2, and SG3 is 67.2. That is, the target value is 22.4 (= 67.2 / 3). The set value that can be set in each of the generating portions SG1, SG2, and SG3 is determined to be 22 or 23 that is close to the target value 22.4 (= 67.2 / 3). However, when the set values of the generators SG1, SG2, and SG3 are set to 22 only or 23 only, the set values deviate from the target value 22.4.

Therefore, in this configuration, when the target value X is within a predetermined range, the combination of the duty ratios of the PWM signals output to the m driving targets (that is, the combination of the set values) is a settable value larger than the target value X. The first duty, which is the minimum value, and the second duty, which is the maximum value among the settable values smaller than the target value X, are determined. For example, when the target value X is 22.4, a combination of setting values (duty of PWM signals output to three driving targets) set in the generators SG1, SG2, and SG3 is set to be larger than 22.4. It is determined by combining 23 (first duty), which is the minimum value among possible values, and 22 (second duty), which is the maximum value among settable values smaller than 22.4.

Specifically, 202 is specified as a settable value closest to a value obtained by multiplying the target value 22.4 by n × m (22.4 × 3 × 3 = 201.6), and the specified 202 is set to n × m. All settable values are allocated as evenly as possible to determine m set values for the next n cycles. The settable value specified here may be, for example, 201 that is the second closest value to the value obtained by multiplying the target value by n × m or other values, but is preferably specified to the closest 202. Specifically, out of n × m = 9 setting values, 4 setting values are 23 (corresponding to 23% duty), and 5 setting values are 22 (corresponding to 22% duty). And decide.

A method for allocating the set values in each cycle will be described later. For example, the set values in the generators SG1, SG2, and SG3 in the first cycle, the second cycle, and the third cycle of the next n cycles are 23, 23, respectively. , 23, 23, 22, 22 and 22, 22, 22, the average value of the duty of the PWM signal from the first phase to the third phase in each of the first period, the second period, and the third period is 22 .4, which approaches the target value as an average.

By determining m set values for n cycles in this way, the average value of the n cycles of the set values set for each of the generating units SG1, SG2, and SG3 is set to the minimum unit of settable values ( It is possible to change in units smaller than 1%).

Hereinafter, the operation of the signal generation circuit 1 that determines the combination of m set values for the above-described n periods will be described with reference to the flowcharts of FIGS. The following processing is executed by the CPU 11 in accordance with a control program stored in advance in the ROM 12.

The cycle number J in FIG. 5, information indicating which of the set

value storage areas

131 a and 131 b is for storage (or read-out), and the phase counter K and the cycle counter L in FIG. 6 are stored in the RAM 13. The The initial value of the cycle number J is n. The m set values for the n periods determined in the process of FIG. 6 are stored in the set

value storage area

131a or 131b in the order of addresses. The periodic interrupt that triggers the periodic interrupt process shown in FIG. 5 occurs at the start of each period included in the n period. For example, a periodic interrupt may be generated at the rising edge of the first phase PWM signal generated by the generator SG1.

When a periodic interrupt occurs and the control of the CPU 11 shifts to the processing of FIG. 5, the CPU 11 determines whether or not the periodic number J is n (here, 3) (S10), and when it is n ( (S10: YES), J is set to 1 (S11), and the setting

value storage areas

131a and 131b are switched between storing and reading (S12). For example, if the set value storage area 131b (or 131a) is for storage before the process of step S12, the set value storage area 131a (or 131b) is switched for storage in the process of step S12 to store the set value. The area 131b (or 131a) is switched for reading.

The set value storage area 131a (or 131b) switched for storage in step S12 is an area in which m set values for n cycles determined in the set value determination subroutine are stored. On the other hand, the setting value storage area 131b (or 131a) switched for reading is an area where setting values are read when setting values are assigned in each cycle.

Thereafter, the CPU 11 takes in an output voltage value obtained by converting the output voltage supplied to the load 3 by the A / D converter 14 (S13), and performs an operation related to voltage loop control based on the taken-in voltage value and the target voltage value. (S14) to calculate the target voltage value.

Next, the CPU 11 captures an output current value obtained by converting the detection voltage of the current detection circuit 17 by the A / D converter 14 (S15), and performs an operation related to current loop control based on the captured current value and the target current value. Execute (S16) and calculate the target duty for each phase. In order to omit the current loop control, steps S15 and S16 may not be executed. When steps S15 and S16 are not executed, the target duty of each phase is determined based on the value calculated in step S14.

Next, the CPU 11 calculates the target value by dividing the target duty by the duty corresponding to the minimum unit of the settable value (S17). In the example shown in FIG. 4, the target duty is 0.224, the minimum unit of the settable value is 1, and 1 of the minimum unit corresponds to 1% (= 0.01) of the duty of the PWM signal. Therefore, the target value is calculated as 0.224 / 0.01 = 22.4.

After that, the CPU 11 calls and executes a subroutine related to setting value determination (S18), and then returns to the interrupted routine. On the other hand, if J is not n in step S10 (S10: NO), the CPU 11 increments J by 1 (S19), and then returns to the interrupted routine. That is, every time a periodic interrupt occurs n times, the processing from steps S11 to S18 is executed once, and m set values for n periods are determined.

Moving to FIG. 6, when a subroutine related to setting value determination is called from the periodic interrupt processing, the CPU 11 multiplies the target value by m × n to calculate a total of n target values for n periods, A settable value closest to the calculated sum total of n cycles is specified (S21). In the example shown in FIG. 4, since the target value is 22.4, the total sum of m target values for n cycles is calculated as 22.4 × 3 × 3 = 201.6, and the nearest settable value is 202. Identified.

Next, the CPU 11 calculates the quotient Q and the remainder R by dividing the specified settable value by the number of driving targets (number of phases) m × (number of periods) n (S22). In the example shown in FIG. 4, the settable value 202 is divided by 3 × 3, the quotient Q is calculated as 22, and the remainder R is calculated as 4.

Next, the CPU 11 temporarily stores all the m set values for n cycles as Q in the set

value storage area

131a or 131b (S23). Here, Q corresponds to a reference value for n cycles of m settable values. Which of the set

value storage areas

131a and 131b is for storage is specified by the switching process in step S12 shown in FIG. Thereafter, the CPU 11 initializes the phase counter K to 1 (S24), and further initializes the period counter L to 1 (S25).

Next, the CPU 11 determines whether or not the remainder R calculated in step S22 (R as a calculation result in step S31 when step S31 described later is executed) is 0 (S26). If so (S26: YES), the process returns to the called routine. The fact that R is 0 means that the process of dividing the remainder R of the division result into the minimum unit of the settable value and adding it to a part of the reference value is completed, or the remainder R to be divided into the minimum unit is from the beginning. It means 0.

When R is not 0 (S26: NO), the CPU 11 determines whether or not the phase counter K is m + 1, that is, whether or not the phase counter K has overflowed (S27). When the phase counter K is m + 1 (S27: YES), the CPU 11 initializes the phase counter K to 1 (S28) and increments the period counter L by 1 (S29).

When the phase counter K is not m + 1 (S27: NO), or when the process of step S29 is completed, the CPU 11 sets the set value for generating the Lth period K-phase PWM signal as the quotient Q. The value is added to the minimum unit of possible values (S30), and the setting value (Q) already stored in the setting

value storage area

131a or 131b is overwritten. In the example shown in FIG. 4, since the minimum unit of the settable value is 1, the process in step S30 can be replaced with a process of incrementing the set value stored in the set

value storage area

131a or 131b by 1. .

After that, the CPU 11 newly sets a value obtained by subtracting the minimum unit of settable values from R as R (S31), increments the phase counter K by 1 (S32), and moves the process to step S26. By repeating the above-described processing from step S26 to S32, when the remainder R calculated in step S22 is not 0, the remainder R is divided into the minimum units of settable values, and one or more set values are set. Sequentially added to the reference value.

Next, a specific example of m set values for n cycles determined as described above will be described with a plurality of examples. FIG. 7 is a chart showing a list of m set values for n periods determined according to the target value. The target value is expressed by a numerical value of one or two decimal places. Note that the overlap between the boundaries of the target value ranges in adjacent rows means that the set value shown in any row is determined when the target value matches the boundary value. In FIG. 7, a combination of m set values for n cycles is shown in the same row for each target value range. However, how m set values for n cycles are allocated is only described. It is an example. A method for determining which phase is preferentially assigned a high set value for each cycle will be described in detail later.

For example, when the target value is in the range of 9.95 to 10.06, the first phase and the second phase are equal to three periods of three set values, that is, the first period, the second period, and the third period, respectively. , The combination of set values for generating the third phase PWM signal is determined as 10, 10, 10, 10, 10, 10, 10, 10, 10. In this case, the average value of the target values over the n periods of the m phase is 10.00. When the target value is within the range of 10.06 to 10.17, the combination of m set values for n cycles is determined as 11, 10, 10, 10, 10, 10, 10, 10, 10. . In this case, the average value of the target values over the n periods of the m phase is 10.11. Further, when the target value is within the range of 22.39 to 22.50 as in the example of 22.4% described above, m set values for n cycles are 23, 23, 23, 23, 22, 22, 22, 22, and 22. In this case, the average value over the n cycles of the added value of the set values for each cycle is 22.44.

In this configuration, a combination of m set values for n cycles is determined by such a method, and the CPU 11 functioning as the center of the control unit 10 has m (= 3) generation units SG1, SG2, and SG3. A set value that can be set for each of the m generation units SG1, SG2, and SG3 is determined and set according to a target value that should be set for each. More specifically, the CPU 11 sets a settable value closest to the sum total of n cycles of the target value for every n (for example, 3) cycles of the PWM signal generated by each of the m generators SG1, SG2, and SG3. Based on the quotient Q and remainder R obtained by specifying and dividing the specified settable value by the product of m and n, m set values for n periods are determined. Further, the quotient Q of the above-mentioned division result is specified as a reference value for all m settable values for n cycles, and the remainder R of the above-described division result is set to the minimum unit (that is, the minimum increment) of the settable value. = 1), and the divided minimum unit value is added to a part of the m reference values for n periods, respectively, to determine m set values for n periods.

Then, when the target value satisfies the predetermined condition, the control unit 10 determines the combination of the duty ratios of the PWM signals to be output to a plurality of driving targets by combining a plurality of types of settable values based on the target value. Function. The case where the target value satisfies the predetermined condition is a case where the remainder R described above does not become 0, and a case where all combinations of m set values for n cycles do not have the same value. Note that the drive circuit DCk and the converter CVk correspond to an example of the drive target, and m drive targets are provided in this configuration.

The combinations are determined in this way, and the m set values for the n cycles stored in the set value storage area 131a (or 131b) are assigned as the set values for the n cycles continuously performed after the storage. It is decided. The set values determined to be assigned in this way are sequentially read out by phase-specific interrupt processing in each of the n cycles, and set in the corresponding register buffer 161 of the generation unit.

For example, in the case of n = 3 and m = 3, after the combination of three set values for three cycles is determined, setting value assignment in the first cycle, the second cycle, and the third cycle performed thereafter (that is, , Allocation of three set values in each cycle). When setting a set value for n cycles, for example, the assignment is performed by an assignment method in which a larger set value is set to an earlier cycle. In this case, when m set values for n cycles are determined to be 23, 23, 23, 23, 22, 22, 22, 22, 22, 22, the combination of the set values of the first cycle is (23, 23, 23), the combination of the set values of the second period is (23, 22, 22), and the combination of the set values of the third period is (22, 22, 22). In this configuration, this method is a representative example. Note that the assignment is not limited to this method. For example, the assignment may be performed by an assignment method in which a smaller setting value is set in an earlier cycle. In this case, when m set values for n cycles are determined to be 23, 23, 23, 23, 22, 22, 22, 22, 22, 22, the combination of the set values of the first cycle is (22, 22, 22), the combination of the setting values of the second period is (22, 22, 23), and the combination of the setting values of the third period is (23, 23, 23).

When assigning m set values in each cycle, follow the assignment table as shown in FIG. The assignment table in FIG. 8 is a table that includes a plurality of setting information that defines the priority for each phase in assigning a higher setting value in a combination of m setting values set for each period. Regardless of which setting in the allocation table is selected, higher setting values are allocated in order from the phase with the higher priority order (smaller number).

In the assignment table of FIG. 8, setting 1 is a setting in which the priority of the first phase is 1, the priority of the second phase is 2, and the priority of the third phase is 3. That is, when the first phase set value is D1, the first phase set value is D2, and the third phase set value is D3, D1 ≧ D2 ≧ D3. The setting 2 is a setting in which the priority of the first phase is 3, the priority of the second phase is 1, and the priority of the third phase is 2, so that D2 ≧ D3 ≧ D1. Setting 3 is a setting in which the priority of the first phase is 2, the priority of the second phase is 3, and the priority of the third phase is 1, and D3 ≧ D1 ≧ D2.

In the control unit 10, by switching which setting in the assignment setting table of FIG. 8 is used at predetermined time intervals (for example, every second), a plurality of types of setting values (can be set) for a plurality of driving targets. The priority for assigning a higher value when assigning (value) is changed over time.

For example, when the target value is 22.4%, m set values for n cycles are 23, 23, 23, 23, 22, 22, 22, 22, 22, by the above-described combination determination process. It is determined. Of the n periods, the combination of the set values of the first period is (23, 23, 23), the combination of the set values of the second period is (23, 22, 22), and the combination of the set values of the third period Is determined to be (22, 22, 22). In this case, if the time period of the second period that is a combination (23, 22, 22) of a plurality of types of setting values is the time period Ta1 in which the setting 1 is used, the value from the larger value of the combinations The first phase, the second phase, and the third phase are set in order. That is, 23 is set for the first phase, and 22 is set for the second phase and the third phase.

On the other hand, when the target value is set as 22.4%, if the time period of the second period that is a combination of a plurality of types of setting values (23, 22, 22) is the time period Ta2 in which the setting 2 is used. The second phase, the third phase, and the first phase are set in descending order of the combination values. That is, 23 is set for the second phase, and 22 is set for the first phase and the third phase.

In the case of another target value, the concept is the same. When the target value is 20.1%, m set values for n cycles are set to 21, 20, 20, 20 by the above-described combination determination process. , 20, 20, 20, 20, 20 are determined. Of the n periods, the combination of the setting values of the first period is (21, 20, 20), the combination of the setting values of the second period is (20, 20, 20), and the combination of the setting values of the third period Is determined as (20, 20, 20). In this case, if the time zone of the first period set with the combination (21, 20, 20) of a plurality of types of setting values is the time zone Ta3 in which the setting 3 is used, the value of the combination is large. The third phase, the first phase, and the second phase are set in order from the value. That is, 21 is set for the third phase, and 20 is set for the second and third phases.

As described above, in this configuration, a combination of m setting values is determined for each period. Which phase is assigned the highest setting value and which phase is assigned the lowest setting value depends on the time zone. Become.

If the combination of the duty ratios of PWM signals output to a plurality of driving targets is a combination of a plurality of settable values as in this configuration, the average value of the duty given to the plurality of driving targets is set to a value other than the settable value. Therefore, the minimum unit of duty can be made substantially smaller than a predetermined settable value. In addition, since the assigning unit changes the priority order for assigning a high value when assigning a plurality of types of settable values to a plurality of drive targets according to the passage of time, the drive for setting the duty relatively high The bias of the object can be suppressed, and the concentration of heat generation points can be effectively suppressed.

As in this configuration, when the target value is within a predetermined range, the first duty that is the minimum value among the settable values larger than the target value and the maximum value among the settable values smaller than the target value If a certain second duty is assigned to each of the m driving objects, the average value of the duty of the PWM signal output to the m driving objects in the cycle is finely adjusted from the minimum unit of the settable value, The duty given to m driving objects can be made closer to the target value. And if it is the structure which changes the priority of allocation of a relatively high duty (1st duty), concentration of a heat_generation | fever location can be suppressed reliably.

<Example 2>
Next, Example 2 will be described.
The signal generation circuit and the voltage conversion apparatus according to the second embodiment have the same hardware configuration as that of the first embodiment, and the contents described with reference to FIGS. 1 to 7 are the same as those of the first embodiment. Therefore, reference will be made to FIGS. Further, in this configuration, only the allocation method after the combination of m set values for n cycles is determined is different from that in the first embodiment, and therefore only the differences will be described in detail below.

Also in the voltage conversion apparatus 100 according to the second embodiment having the same hardware configuration as that in FIG. 1, a combination of m set values for n cycles is determined every n cycles, and the determination is as shown in FIGS. 5 and 6. Do in the flow. Then, after the combination of m set values for n cycles is determined, the assignment is performed as follows.

In this configuration, the temperature sensors TH1, TH2,... THm shown in FIG. 1 correspond to an example of a temperature detection unit, and corresponding driving objects (driving circuit DCk and converter CVk (where k is a natural number of 1 to m)). ) Function to detect each temperature. Specifically, the control unit 10 acquires the detected temperature from the temperature sensors TH1, TH2,... THm at regular intervals, and determines the priority for each time period so that a higher set value is assigned to a phase with a lower temperature. .

For example, in the case of n = 3 and m = 3, as shown in FIG. 9, the temperature detected by the temperature sensor TH1 corresponding to the first phase at the timing of the start of the time zone Tb1 is 90 ° C., and the second phase When the temperature detected by the temperature sensor TH2 corresponding to is 82 ° C. and the temperature detected by the temperature sensor TH3 corresponding to the second phase is 89 ° C., the priority of the first phase is 3 in the time zone Tb1. The setting A is adopted in which the priority of the second phase is 1 and the priority of the third phase is 2. In this setting, if the first phase setting value is D1, the first phase setting value is D2, and the third phase setting value is D3, then D2 ≧ D3 ≧ D1. In addition, the temperature detected by the temperature sensor TH1 corresponding to the first phase at the timing of the start of the time zone Tb2 is 90 ° C., the temperature detected by the temperature sensor TH2 corresponding to the second phase is 88 ° C., When the temperature detected by the temperature sensor TH3 corresponding to the two phases is 87 ° C., the priority of the first phase is 3, the priority of the second phase is 2, and the priority of the third phase is the time zone Tb2. A setting B of 1 is adopted. In this setting, D3 ≧ D2 ≧ D1. The detected temperature at the temperature sensor TH1 corresponding to the first phase at the timing of the start of the time zone Tb3 is 90 ° C., the detected temperature at the temperature sensor TH2 corresponding to the second phase is 92 ° C., and the third phase When the temperature detected by the temperature sensor TH3 corresponding to is 89 ° C., the priority of the first phase is 2, the priority of the second phase is 3, and the priority of the third phase is 1 in the time zone Tb2. The setting C to be used is adopted. In this setting, D3 ≧ D1 ≧ D2.

As a specific example, for example, when the target value is 22.4%, m set values for n cycles are 23, 23, 23, 23, 22, 22, 22, 22, and 22 are determined. Of the n periods, the combination of the set values of the first period is (23, 23, 23), the combination of the set values of the second period is (23, 22, 22), and the combination of the set values of the third period Is determined to be (22, 22, 22). In this case, if the time period of the second period, which is a combination (23, 22, 22) of a plurality of types of setting values, is the time period Tb1 in which the setting A is used depending on the temperature state, The second phase, the third phase, and the first phase are set in order from the largest value. That is, 23 is set for the second phase having the lowest temperature, and 22 is set for the first phase and the third phase.

On the other hand, when the target value is set as 22.4%, if the time period of the second cycle that is a combination of a plurality of types of setting values (23, 22, 22) is the time period Tb2 in which the setting B is used. In the combination values, the third phase, the second phase, and the first phase are set in descending order. That is, 23 is set for the third phase having the lowest temperature, and 22 is set for the first phase and the second phase.

In the case of another target value, the concept is the same. When the target value is 20.1%, m set values for n cycles are set to 21, 20, 20, 20 when the combination determination process described above is performed. , 20, 20, 20, 20, 20 are determined. Of the n periods, the combination of the setting values of the first period is (21, 20, 20), the combination of the setting values of the second period is (20, 20, 20), and the combination of the setting values of the third period Is determined as (20, 20, 20). In this case, if the time zone of the first period set with the combination (21, 20, 20) of a plurality of types of setting values is the time zone Tb3 in which the setting C is used, the combination value is large. The third phase, the first phase, and the second phase are set in order from the value. That is, 21 is set for the third phase at the lowest temperature, and 20 is set for the second phase and the third phase.

As described above, in this configuration, a combination of m setting values is determined for each cycle, and which phase is assigned the highest setting value and which phase is assigned the lowest setting value depends on the temperature state. Become.

As described above, also in this configuration, when the target value satisfies the predetermined condition, the control unit 10 can set a plurality of types of settable values based on the target value for the combination of the duty ratios of the PWM signals output to the plurality of driving targets. Each time a combination of settable values is determined, each settable value of the determined combination is assigned to a plurality of driving targets. And the control part 10 determines the priority which allocates the high value when assigning a multiple types of settable value with respect to several drive object by the system which gives priority to the drive object with low temperature detection by a temperature detection part.

Even in this configuration, the minimum unit of duty can be substantially smaller than a predetermined settable value. In addition, the control unit 10 determines the priority order for assigning a high value when assigning a plurality of types of settable values to a plurality of drive targets in a manner that gives priority to a drive target having a low temperature detected by the temperature detection unit. A drive target having a lower temperature can be selected as a drive target having a relatively large drive current. Therefore, the concentration of heat generation points can be effectively suppressed.

<Other embodiments>
The present invention is not limited to the embodiments described with reference to the above description and drawings. For example, the following embodiments are also included in the technical scope of the present invention.
(1) In the first and second embodiments, the step-down type multi-phase converter is typically exemplified, but a step-up type multi-phase converter or a step-up / step-down type multi-phase converter may be used. Moreover, although the multiphase converter whose output direction is one direction was illustrated, a bidirectional type multiphase converter may be used.
(2) The battery 2 and the load 3 in the first and second embodiments are merely examples, and various devices and electronic components can be connected to the input side conductive path and the output side conductive path.
(3) In the first and second embodiments, the combination of m set values for n cycles is determined by arithmetic processing, temporarily stored in the set

value storage area

131a or 131b, and then read. It may be determined from the contents stored in advance in the set value storage table 121 included in the ROM 12. That is, in the setting value storage table 121, combinations of m setting values for n cycles are determined for each target value range, and each time the target value is determined, the setting value storage table 121 is referred to and the target value is handled. You may make it determine the combination of the m setting value for the attached n period.

DESCRIPTION OF SYMBOLS 1 ... Signal generation circuit 10 ... Control part (setting part)
19 ... Output detection unit 100 ... Voltage converters TH1, TH2 ... Thm ... Temperature sensor (temperature detection unit)
CV1, CV2 ... CVm ... Converter (voltage converter)

Claims

The PWM signal is output to a plurality of driving targets, and the duty of the PWM signal output to each of the plurality of driving targets is selected from a plurality of predetermined settable values based on the set target value. Each of the signal generation circuits to be set,
When the target value satisfies a predetermined condition, a combination of duty of PWM signals output to the plurality of driving targets is determined based on a combination of a plurality of types of the settable values based on the target value, and the settable value Each time the combination is determined, the settable value of each of the determined combinations is assigned to the plurality of driving targets, and a high value is obtained when a plurality of types of the settable values are assigned to the plurality of driving targets. The signal generation circuit which has a control part which changes the priority which allocates according to time passage.
The PWM signal is output to a plurality of driving targets, and the duty of the PWM signal output to each of the plurality of driving targets is selected from a plurality of predetermined settable values based on the set target value. Each of the signal generation circuits to be set,
A temperature detection unit for detecting the temperature of each of the plurality of driving objects;
When the target value satisfies a predetermined condition, a combination of duty of PWM signals output to the plurality of driving targets is determined based on a combination of a plurality of types of the settable values based on the target value, and the settable value Each time the combination is determined, the settable value of each of the determined combinations is assigned to the plurality of driving targets, and a high value is obtained when a plurality of types of the settable values are assigned to the plurality of driving targets. A control unit that determines a priority order for assigning a driving target having a low detection temperature by the temperature detection unit;
A signal generating circuit.
When the target value is within a predetermined range, the control unit sets a duty combination of PWM signals to be output to m driving targets to a minimum value among the settable values larger than the target value. 1 duty and a second duty which is the maximum value among the settable values smaller than the target value are determined in combination, and a combination of the first duty and the second duty is determined according to the target value Each of the m driving objects is assigned with either the first duty or the second duty, and the first duty is assigned to the m driving objects. The signal generation circuit according to claim 1, wherein the signal generation circuit is configured to change the signal.
A signal generation circuit according to any one of claims 1 to 3,
A plurality of voltage converters for converting a voltage by switching according to the duty of each PWM signal generated by the signal generation circuit;
An output detection unit for detecting an output from the voltage conversion unit;
A setting unit that sets the target value based on a detection result of the output detection unit;
A voltage conversion device comprising: