WO2017125795A1 - Transistor et dispositif d'imagerie - Google Patents

Transistor et dispositif d'imagerie Download PDF

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Publication number
WO2017125795A1
WO2017125795A1 PCT/IB2016/052924 IB2016052924W WO2017125795A1 WO 2017125795 A1 WO2017125795 A1 WO 2017125795A1 IB 2016052924 W IB2016052924 W IB 2016052924W WO 2017125795 A1 WO2017125795 A1 WO 2017125795A1
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Prior art keywords
transistor
film
oxide
oxide semiconductor
region
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PCT/IB2016/052924
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English (en)
Japanese (ja)
Inventor
山崎舜平
津吹将志
堅石李甫
広瀬篤志
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株式会社半導体エネルギー研究所
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Publication of WO2017125795A1 publication Critical patent/WO2017125795A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors

Definitions

  • One embodiment of the present invention relates to a transistor including an oxide semiconductor and an imaging device.
  • one embodiment of the present invention is not limited to the above technical field.
  • the technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method.
  • one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter). Therefore, the technical field of one embodiment of the present invention disclosed in this specification more specifically includes a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, a power storage device, a memory device, an imaging device, A driving method or a manufacturing method thereof can be given as an example.
  • a semiconductor device refers to any device that can function by utilizing semiconductor characteristics.
  • a transistor and a semiconductor circuit are one embodiment of a semiconductor device.
  • a memory device, a display device, an imaging device, and an electronic device may include a semiconductor device.
  • a technique for forming a transistor using a semiconductor thin film formed over a substrate having an insulating surface has attracted attention.
  • the transistor is applied to a wide range of electronic devices such as an integrated circuit (IC) and a display device.
  • IC integrated circuit
  • a silicon-based semiconductor is widely known as a semiconductor material applicable to a transistor, but an oxide semiconductor has attracted attention as another material.
  • MOSFETs using silicon semiconductors have been miniaturized in order to improve element characteristics.
  • the cut-off frequency f is improved, so that the operation speed can be improved.
  • the degree of integration of the MOSFET is improved.
  • the gate electrode layer can be brought closer to the channel region, so that the control of the channel region by the gate electrode is strengthened, and the short channel effect can be suppressed. Therefore, thinning the gate insulating film that suppresses the short channel effect is used as an effective technique in MOSFETs.
  • a countermeasure called channel doping is also taken in which a small amount of an impurity element such as phosphorus or boron is added to the entire channel formation region of the MOSFET in a shallow amount (see, for example, Patent Document 7).
  • the above-described channel dope has a drawback that the carrier mobility is hindered by the impurity element intentionally added, and the carrier mobility is greatly reduced. As a result, there is a problem that the field effect mobility of the MOSFET is significantly reduced.
  • Patent Documents 1 and 2 a technique for manufacturing a transistor using zinc oxide or an In—Ga—Zn-based oxide semiconductor as an oxide semiconductor is disclosed (see Patent Documents 1 and 2).
  • a transistor using an oxide semiconductor the short channel effect as described above is not likely to be a problem.
  • Patent Document 3 a transistor having an oxide semiconductor with extremely low off-state current is used as a part of a pixel circuit, and a transistor including silicon capable of manufacturing a CMOS (Complementary Metal Oxide Semiconductor) circuit is used as a peripheral circuit.
  • CMOS Complementary Metal Oxide Semiconductor
  • Patent Document 4 discloses an imaging device in which a transistor including silicon, a transistor including an oxide semiconductor, and a photodiode including a crystalline silicon layer are stacked.
  • JP 2007-123861 A JP 2007-96055 A JP 2011-119711 A JP2013-243355A JP 2001-274378 A JP 2006-253440 A JP-A-4-206971
  • the pixel circuit of the imaging device has a function of converting incident light into an electrical signal.
  • an object of one embodiment of the present invention is to provide a transistor with low noise. Another object is to provide an imaging device capable of converting incident light into an appropriate electrical signal. Another object is to provide an imaging device including a transistor with low noise. Another object is to provide an imaging device suitable for high-speed operation. Another object is to provide an imaging device with high resolution. Another object is to provide an imaging device with high integration. Another object is to provide an imaging device with low power consumption. Another object is to provide an imaging device capable of imaging under low illuminance. Another object is to provide an imaging device with a wide dynamic range. Another object is to provide an imaging device that can be used in a wide temperature range. Another object is to provide an imaging device with a high aperture ratio. Another object is to provide a highly reliable imaging device. Another object is to provide a novel imaging device or the like. Another object is to provide a novel semiconductor device or the like.
  • One embodiment of the present invention relates to an imaging device including a transistor formed using an oxide semiconductor.
  • One embodiment of the present invention is a field-effect transistor including an oxide semiconductor and having 1 / f noise smaller than that of an n-ch MOS transistor including silicon in a channel region. Further, the field effect transistor is characterized in that 1 / f noise has a characteristic that is equal to or lower than a p-ch MOS transistor having silicon in a channel region.
  • an oxide semiconductor is used, and 1 / f noise is smaller than that of a p-ch MOS transistor including silicon in a channel region at an operating frequency of 1 Hz to 10 Hz. It is a field effect transistor characterized by this.
  • a field effect transistor having an oxide semiconductor and having a characteristic that 1 / f noise having silicon in a channel region is smaller than that of a p-ch MOS transistor in a region of 60% or more of an operating frequency region It is.
  • Another embodiment of the present invention includes a first oxide semiconductor, a second oxide semiconductor, a third oxide semiconductor, a gate insulating film, and a gate electrode.
  • the transistor has a composition in the vicinity thereof, and the second oxide semiconductor has a crystal structure.
  • the channel length of the transistor may be greater than or equal to 10 nm and less than or equal to 3 ⁇ m. Further, the channel length of the transistor may be 10 nm to 100 nm. In one embodiment of the present invention, the channel width of the transistor may be 10 nm to 3 ⁇ m. Further, the channel width of the transistor may be 10 nm to 100 nm.
  • the oxide semiconductor may have a crystal structure, and the crystal structure may include a region having c-axis orientation.
  • An oxide semiconductor has a crystal structure, and the crystal structure may have c-axis alignment.
  • the gate insulating film preferably includes a portion with a thickness of greater than or equal to 1 nm and less than or equal to 100 nm. More preferably, the gate insulating film has a thickness of 3 nm to 15 nm.
  • the third oxide semiconductor may have a region in contact with the gate insulating film.
  • the top surface of the third oxide semiconductor may have a region in contact with the gate insulating film.
  • the first electrode includes the transistor according to one embodiment of the present invention, the first electrode, the second electrode, and the photoelectric conversion layer between the first electrode and the second electrode.
  • an imaging device in which one of the second electrodes is electrically connected to the transistor is also one embodiment of the present invention.
  • the imaging device according to one embodiment of the present invention includes a second transistor, and a channel region of the second transistor may include silicon.
  • a transistor with low noise can be provided.
  • an imaging device that can convert incident light into an appropriate electrical signal can be provided.
  • an imaging device including a transistor with low noise can be provided.
  • an imaging device suitable for high-speed operation can be provided.
  • an imaging device with high resolution can be provided.
  • an imaging device with a high degree of integration can be provided.
  • an imaging device with low power consumption can be provided.
  • an imaging device capable of imaging under low illuminance can be provided.
  • an imaging device with a wide dynamic range can be provided.
  • an imaging device that can be used in a wide temperature range can be provided.
  • an imaging device with a high aperture ratio can be provided.
  • a highly reliable imaging device can be provided.
  • a novel imaging device or the like can be provided.
  • a novel semiconductor device or the like can be provided.
  • one embodiment of the present invention is not limited to these effects.
  • one embodiment of the present invention may have effects other than these effects depending on circumstances or circumstances.
  • one embodiment of the present invention may not have these effects depending on circumstances or circumstances.
  • 1A and 1B are a top view and a cross-sectional view illustrating an imaging device.
  • 2A and 2B are diagrams illustrating circuits included in the imaging device.
  • 3A to 3F are cross-sectional views illustrating connection forms of photoelectric conversion elements.
  • 4A and 4B are cross-sectional views illustrating the imaging device.
  • 5A to 5F are cross-sectional views illustrating a connection form of photoelectric conversion elements.
  • FIG. 6 is a cross-sectional view illustrating the imaging apparatus.
  • 7A and 7B are cross-sectional views illustrating the imaging device.
  • 8A to 8D are cross-sectional views illustrating the configuration of the imaging device.
  • 9A1, 9A2, 9A3, 9B1, 9B2, and 9B3 show curved imaging devices.
  • 10A and 10B illustrate the configuration of the pixel circuit.
  • 11A to 11C are timing charts for explaining the operation of the pixel circuit.
  • 12A and 12B illustrate the configuration of the pixel circuit.
  • the configuration of the pixel circuit in FIGS. 13A and 13B will be described.
  • 14A and 14B illustrate the configuration of the pixel circuit.
  • FIG. 15 illustrates the configuration of a pixel circuit.
  • FIG. 16 illustrates the configuration of the pixel circuit.
  • FIG. 17 illustrates the configuration of a pixel circuit.
  • FIG. 18 illustrates the configuration of a pixel circuit.
  • 19A and 19B are timing charts for explaining operations of the global shutter method and the rolling shutter method.
  • 20A to 20C illustrate a top view and a cross-sectional structure of a transistor according to an embodiment.
  • 21A to 21C illustrate a top view and a cross-sectional structure of a transistor according to an embodiment.
  • 22A to 22C illustrate a top view and a cross-sectional structure of a transistor according to an embodiment.
  • 23A to 23C illustrate a top view and a cross-sectional structure of a transistor according to an embodiment.
  • 24A to 24C illustrate a top view and a cross-sectional structure of a transistor according to an embodiment.
  • 25A to 25C illustrate a top view and a cross-sectional structure of a transistor according to an embodiment.
  • 26A to 26C illustrate a top view and a cross-sectional structure of a transistor according to an embodiment.
  • 27A to 27F illustrate an electronic device.
  • 28A to 28E illustrate a manufacturing process of a photoelectric conversion element.
  • 29A and 29B show the measurement results of 1 / f noise.
  • 30A to 30C illustrate cross-sectional structures of the transistor according to the embodiment.
  • 31A and 31B are top views of a semiconductor wafer according to one embodiment of the present invention.
  • 32A and 32B are a flowchart and a perspective schematic view illustrating an example of a manufacturing process of an electronic component.
  • FIG. 33 shows data comparing 1 / f noise characteristics.
  • 34A to 34C illustrate cross-sectional structures of the transistor according to the embodiment.
  • 35A to 35C show a cross-sectional TEM image and a cross-sectional HR-TEM image of the metal oxide film.
  • 36A to 36C show a cross-sectional TEM image and a cross-sectional HR-TEM image of the metal oxide film.
  • FIG. 37A to 37C show a cross-sectional TEM image and a cross-sectional HR-TEM image of the metal oxide film.
  • 38A to 38C show the XRD measurement results and electron beam diffraction pattern of the metal oxide film.
  • 39A to 39C show the XRD measurement results and electron diffraction pattern of the metal oxide film.
  • 40A to 40C show the XRD measurement results and electron diffraction pattern of the metal oxide film.
  • 41A and 41B show electron beam diffraction patterns.
  • FIG. 42 illustrates a line profile of an electron diffraction pattern.
  • FIG. 43 is a conceptual diagram illustrating the luminance profile of the electron beam diffraction pattern, the relative luminance R of the luminance profile, and the half-value width of the profile.
  • 44A1, 44A2, 44B1, and 44B2 show an electron diffraction pattern and a luminance profile.
  • 45A1 and 45A2 show an electron diffraction pattern and a luminance profile.
  • FIG. 46 shows the relative luminance estimated from the electron diffraction pattern of the metal oxide film.
  • 47A and 47B show a cross-sectional TEM image of the metal oxide film and a cross-sectional TEM image after image analysis.
  • 48A and 48B show a cross-sectional TEM image of the metal oxide film and a cross-sectional TEM image after image analysis.
  • 49A and 49B show a cross-sectional TEM image of the metal oxide film and a cross-sectional TEM image after image analysis.
  • 50A to 50C show SIMS measurement results of the metal oxide film.
  • FIG. 51 shows the Id-Vg characteristic.
  • FIG. 52 shows the Id-Vg characteristic.
  • FIG. 53 shows the calculation result of the interface state density.
  • 54A and 54B show the Id-Vg characteristics.
  • FIG. 55 shows the calculation result of the defect level density.
  • 56A to 56D illustrate a deposition mechanism of an oxide semiconductor film.
  • 57A to 57C illustrate the range of the atomic ratio of the oxide semiconductor film.
  • FIG. 58 illustrates a crystal of InMZnO 4 .
  • FIG. 59 illustrates an energy band in a transistor in which an oxide semiconductor film is used for a channel region.
  • FIG. 60 shows the measurement result of the XRD spectrum of the sample.
  • 61A to 61L show a TEM image and an electron beam diffraction pattern of the sample.
  • 62 (A) to 62 (C) show the EDX mapping of the sample.
  • X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).
  • an element that enables electrical connection between X and Y for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display, etc.
  • Element, light emitting element, load, etc. are not connected between X and Y
  • elements for example, switches, transistors, capacitive elements, inductors
  • resistor element for example, a diode, a display element, a light emitting element, a load, or the like.
  • an element for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, a display, etc.
  • the switch has a function of controlling on / off. That is, the switch is in a conductive state (on state) or a non-conductive state (off state), and has a function of controlling whether or not to pass a current. Alternatively, the switch has a function of selecting and switching a path through which a current flows.
  • the case where X and Y are electrically connected includes the case where X and Y are directly connected.
  • a circuit for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, etc.) that enables a functional connection between X and Y, signal conversion, etc.
  • Circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), level shifter circuit that changes signal potential level, etc.), voltage source, current source, switching Circuit, amplifier circuit (circuit that can increase signal amplitude or current amount, operational amplifier, differential amplifier circuit, source follower circuit, buffer circuit, etc.), signal generation circuit, memory circuit, control circuit, etc.)
  • a circuit for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, etc.) that enables a functional connection between X and Y, signal conversion, etc.
  • Circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down
  • X and Y are functionally connected.
  • the case where X and Y are functionally connected includes the case where X and Y are directly connected and the case where X and Y are electrically connected.
  • the source (or the first terminal) of the transistor is electrically connected to X through (or not through) Z1, and the drain (or the second terminal or the like) of the transistor is connected to Z2.
  • Y is electrically connected, or the source (or the first terminal, etc.) of the transistor is directly connected to a part of Z1, and another part of Z1 Is directly connected to X, and the drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2, and another part of Z2 is directly connected to Y.
  • X and Y, and the source (or the first terminal or the like) and the drain (or the second terminal or the like) of the transistor are electrically connected to each other.
  • the drain of the transistor (or the second terminal, etc.) and the Y are electrically connected in this order.
  • the source (or the first terminal or the like) of the transistor is electrically connected to X
  • the drain (or the second terminal or the like) of the transistor is electrically connected to Y
  • X or the source ( Or the first terminal or the like, the drain of the transistor (or the second terminal, or the like) and Y are electrically connected in this order.
  • X is electrically connected to Y through the source (or the first terminal) and the drain (or the second terminal) of the transistor, and X is the source of the transistor (or the first terminal). Terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are provided in this connection order.
  • Terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are provided in this connection order.
  • a source (or a first terminal or the like of a transistor) is electrically connected to X through at least a first connection path, and the first connection path is The second connection path does not have a second connection path, and the second connection path includes a transistor source (or first terminal or the like) and a transistor drain (or second terminal or the like) through the transistor.
  • the first connection path is a path through Z1
  • the drain (or the second terminal, etc.) of the transistor is electrically connected to Y through at least the third connection path.
  • the third connection path is connected and does not have the second connection path, and the third connection path is a path through Z2.
  • the source (or the first terminal or the like) of the transistor is electrically connected to X via Z1 by at least a first connection path, and the first connection path is a second connection path.
  • the second connection path has a connection path through the transistor, and the drain (or the second terminal, etc.) of the transistor is at least connected to Z2 by the third connection path.
  • Y, and the third connection path does not have the second connection path.
  • the source of the transistor (or the first terminal or the like) is electrically connected to X through Z1 by at least a first electrical path, and the first electrical path is a second electrical path Does not have an electrical path, and the second electrical path is an electrical path from the source (or first terminal or the like) of the transistor to the drain (or second terminal or the like) of the transistor;
  • the drain (or the second terminal or the like) of the transistor is electrically connected to Y through Z2 by at least a third electrical path, and the third electrical path is a fourth electrical path.
  • the fourth electrical path is an electrical path from the drain (or second terminal or the like) of the transistor to the source (or first terminal or the like) of the transistor.
  • X, Y, Z1, and Z2 are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, and the like).
  • the term “electrically connected” in this specification includes in its category such a case where one conductive film has functions of a plurality of components.
  • film and “layer” can be interchanged with each other depending on the case or circumstances.
  • conductive layer may be changed to the term “conductive film”.
  • insulating film may be changed to the term “insulating layer” in some cases.
  • FIG. 1A is a top view illustrating a pixel of an imaging device of one embodiment of the present invention, and specific connection forms of the photoelectric conversion element 60, the transistor 51, the transistor 52, the transistor 53, and the transistor 54 in the pixel circuit illustrated in FIG. 2A. An example is shown.
  • FIG. 1B is a cross-sectional view taken along A1-A2 in FIG. 1A. In the drawings, some elements are omitted for clarity.
  • each wiring, each electrode, and the conductor 81 are illustrated as individual elements in the drawing, those that are electrically connected may be provided as the same element.
  • insulating layers 41 and 42 having a function as an interlayer insulating film or a planarizing film are provided between the elements.
  • the insulating layers 41 and 42 can be an inorganic insulating film such as a silicon oxide film or a silicon oxynitride film.
  • an organic insulating film such as an acrylic resin or a polyimide resin may be used.
  • the top surfaces of the insulating layers 41 and 42 are preferably subjected to a planarization process by a CMP (Chemical Mechanical Polishing) method or the like.
  • one of the source electrode and the drain electrode of the transistor 51 is electrically connected to the one electrode 66 of the photoelectric conversion element 60.
  • the other of the source electrode and the drain electrode of the transistor 51 is electrically connected to the gate electrode of the transistor 52.
  • the other of the source electrode and the drain electrode of the transistor 51 is electrically connected to one of the source electrode and the drain electrode of the transistor 53.
  • one of the source electrode and the drain electrode of the transistor 52 is electrically connected to one of the source electrode and the drain electrode of the transistor 54.
  • the other of the source and the drain of the transistor 51 may be electrically connected to one electrode of the capacitor 58 as illustrated in FIG. 2A.
  • the source electrode or the drain electrode of each transistor can function as a wiring.
  • one of the wiring 71 and the wiring 79 can function as a power supply line and the other as an output line.
  • the wiring 72 can function as a power supply line.
  • the wiring 77 can function as a power supply line (low potential).
  • the wirings 75, 76, and 78 can function as signal lines for controlling on / off of the transistors.
  • the wiring 74 can function as a connection wiring.
  • the transistor 51 can function as a transfer transistor for controlling the potential of the charge storage portion (FD) in accordance with the output of the photoelectric conversion element 60.
  • the transistor 52 can function as an amplifying transistor that performs output in accordance with the potential of the charge accumulation portion (FD).
  • the transistor 53 can function as a reset transistor that initializes the potential of the charge accumulation portion (FD).
  • the transistor 54 can function as a selection transistor for selecting a pixel.
  • transistors 51 to 54 transistors whose active layers are formed using an oxide semiconductor (hereinafter referred to as OS transistors) can be used.
  • a MOSFET using silicon causes a short channel effect as it is miniaturized. Therefore, when the gate insulating film is thinned, the gate electrode layer can be brought close to the channel region, so that the control of the channel region by the gate electrode layer is strengthened, and the short channel effect can be suppressed. Therefore, the thinning of the gate insulating film that improves the operation speed and integration degree of the MOSFET and suppresses the short channel effect is used as an effective technique in the MOSFET.
  • a tunnel current passing through the gate insulating film is generated.
  • a gate insulating film such as an insulating film containing silicon oxide (a silicon oxide film or a silicon oxide film containing nitrogen) is thinned.
  • a high-k material for example, a relative dielectric constant of 20
  • an insulating film containing silicon oxide for example, a relative dielectric constant of 3.8 to 4.1
  • the oxide film included in the oxide stacked film has few minority carriers. Therefore, in a MOSFET using an oxide stacked film, a depletion layer is likely to spread greatly. Therefore, without using a high-k material having a high dielectric constant for the gate insulating film, it is possible to use an insulating film with a thickness of 1 nm to 100 nm, preferably 3 nm to 15 nm, as converted to a silicon oxide film. Even when an insulating film with the above-mentioned equivalent film thickness is used, the depletion layer of the oxide multilayer film expands greatly, so that high-speed operation of the MOSFET is possible, and since no tunnel current is generated, no leakage current is generated and high reliability is achieved. Can be achieved. Further, since it is possible to suppress shape defects such as coating defects due to thinning of the gate insulating film, it is possible to suppress yield and characteristic variations.
  • a so-called buried channel transistor in which a channel is formed in the oxide film can be obtained.
  • a buried channel transistor is a surface channel transistor because carriers move through the oxide film without moving through the interface between the oxide stacked film and the gate insulating film, so that there is no decrease in carrier mobility due to surface scattering. High field effect mobility can be obtained.
  • the channel doping step necessary for the MOSFET using silicon is unnecessary.
  • impurities such as hydrogen and silicon are reduced in the oxide stacked film. Accordingly, it is possible to prevent the carrier movement from being hindered, so that the field-effect mobility of the MOSFET using the oxide stacked film can be improved.
  • the oxide semiconductor film has an energy gap of 2.8 eV to 3.2 eV, which is much larger than the energy gap of silicon, 1.1 eV. Since a transistor using a stack of oxide semiconductor films hardly causes avalanche breakdown, it can be said that the resistance to hot carrier deterioration is higher than that of a transistor using silicon. Therefore, the LDD structure is not necessarily formed in the oxide stacked film.
  • the dynamic range of imaging can be expanded.
  • the potential of the charge storage portion (FD) decreases when the intensity of light incident on the photoelectric conversion element 60 is large. Since a transistor including an oxide semiconductor has an extremely low off-state current, a current corresponding to the gate potential can be accurately output even when the gate potential is extremely small. Therefore, the range of illuminance that can be detected, that is, the dynamic range can be expanded.
  • the period in which charge can be held in the charge accumulation portion (FD) can be extremely long. Therefore, it is possible to apply a global shutter system in which charge accumulation operation is simultaneously performed in all pixels without complicating a circuit configuration and an operation method. Therefore, even if the subject is a moving object, an image with small distortion can be easily obtained.
  • the OS transistor can be used in a very wide temperature range because the temperature dependence of variation in electrical characteristics is smaller than that of a transistor using silicon as a channel formation region (hereinafter, Si transistor). Therefore, an imaging device and a semiconductor device having an OS transistor are suitable for mounting on automobiles, aircraft, spacecrafts, and the like.
  • the OS transistor has a higher drain breakdown voltage than the Si transistor.
  • a photoelectric conversion element using a selenium-based material as a photoelectric conversion layer it is preferable to apply a relatively high voltage (for example, 10 V or more) so that an avalanche phenomenon easily occurs. Therefore, by combining an OS transistor and a photoelectric conversion element using a selenium-based material as a photoelectric conversion layer, an imaging device with high reliability can be obtained.
  • a transistor electrically connected to a photoelectric conversion layer including a selenium-based material may be an OS transistor, and another imaging device may include a Si transistor.
  • An imaging device in which an OS transistor and a Si transistor are mixedly mounted can enjoy the advantages of each.
  • the main factor of noise is 1 / f noise, there is regularity with respect to frequency.
  • a carrier number fluctuation model caused by trapping and re-emission of carriers due to trap levels and a mobility fluctuation model caused by phonon scattering have been proposed.
  • a carrier number fluctuation model by carrier capture and re-emission can be applied to an n-channel transistor having silicon in a channel region.
  • the OS transistor is not easily captured and re-emitted.
  • a mobility fluctuation model by phonon scattering or the like can be applied to a p-ch type Si transistor.
  • the present invention can be similarly applied to an n-channel OS transistor.
  • S Id Drain, Current Spectral Density in a range of frequencies (Frequency)
  • S Id Drain, Current Spectral Density in a range of frequencies (Frequency)
  • S Id normalized by Id has also properties that is proportional to Id. This means that when Id is small, the noise is relatively small. This is an advantage that the OS transistor operates at a low current compared to a Si transistor or the like. This property can help to realize a high-performance image sensor or memory with less noise.
  • 29A and 29B are data comparing 1 / f noise characteristics of OS transistors and Si transistors (n-ch type, p-ch type).
  • the OS transistor for explaining the characteristics is a TGSA FET described later.
  • the vertical axis is S ID / Id 2 ⁇ L ⁇ W [m 2 / Hz], which is a value obtained by normalizing the spectral density of the drain current by the drain current and the channel size of the transistor, and measured in the frequency range of 1 Hz to 10 kHz. Is going.
  • L is the channel length of the transistor
  • W is the channel width of the transistor
  • L / W 0.8 ⁇ m / 10 ⁇ m for the Si transistor. is there.
  • an IGZO target In—Ga—Zn oxide target
  • L / W 30 nm / 60 nm
  • the 1 / f noise of the OS transistor is smaller than that of the n-ch type Si transistor.
  • the result is small in the range of 1 Hz to 10 Hz, and large at a frequency higher than 100 Hz.
  • the 1 / f noise of the OS transistor is smaller than that of the n-ch type Si transistor. Furthermore, when compared with a p-ch type Si transistor, it is small in the range of 1 Hz to 500 Hz, and almost the same result at frequencies higher than 500 Hz. That is, it can be said that the 1 / f noise is smaller in the OS transistor than in the p-ch type Si transistor in the range of 1 Hz or more and 10 kHz or less of the frequency logarithmic axis in FIG. 29B.
  • An oxide semiconductor layer formed by a sputtering method using an IGZO target can improve the electrical characteristics of the transistor by appropriately controlling the film formation method. Specifically, it is preferable that the substrate temperature at the time of sputtering film formation is relatively low, and the oxygen concentration in the sputtering gas is not increased more than necessary.
  • An OS made using In: Ga: Zn 4: 2: 4.1 (atomic ratio) as the IGZO target, with an oxygen flow rate of 30% and a substrate temperature of 170 ° C. in the total flow rate of the sputtering gas (Ar + O 2 ). Comparison is made with an OS transistor manufactured with oxygen flow rate of 10% and substrate temperature of room temperature, 50 ° C., 70 ° C., 100 ° C., and 130 ° C. based on the transistor.
  • the oxide semiconductor layer of the reference OS transistor is manufactured under the same conditions as the oxide semiconductor layer of the OS transistor illustrated in FIG. 29B, and the transistor using the oxide semiconductor layer also has 1 / f noise smaller than that of the Si transistor. Show the characteristics. Further, by setting the substrate temperature during sputtering film formation to room temperature to 130 ° C. and the oxygen flow rate of the sputtering gas to 10%, 1 / f noise is further reduced.
  • the substrate temperature during sputtering film formation is 130 ° C. or lower, preferably 70 ° C. or lower, more preferably room temperature or its
  • an oxide semiconductor layer formed at a temperature close to that a transistor having 1 / f noise sufficiently smaller than that of a Si transistor can be formed.
  • a second oxide semiconductor layer (S2) with a thickness of 15 nm manufactured using an IGZO target with In: Ga: Zn 4: 2: 4.1 (atomic ratio), and In: Ga:
  • Each semiconductor layer has a composition in the vicinity of the composition of the target.
  • the gate insulating film is a silicon oxynitride film having a thickness of 10 nm
  • the gate electrode includes titanium nitride having a thickness of 10 nm and tungsten having a thickness of 50 nm thereon.
  • the channel length of the transistor is preferably 10 nm to 3 ⁇ m, particularly preferably 10 nm to 100 nm, and the channel width is preferably 10 nm to 3 ⁇ m, particularly preferably 10 nm to 100 nm.
  • the thickness of the gate insulating film is preferably 1 nm to 100 nm, particularly preferably 3 nm to 15 nm.
  • the transistor noise In the pixel circuit shown in FIGS. 2A and 2B, in order to appropriately set the potential of the gate of the transistor 52 (the potential of the node FD), it is important to reduce the noise of the transistor (eg, the transistor 51) to a certain value or less. . In other words, the transistor noise must be small so as to satisfy the circuit specifications. Except for the case of operating at a high frequency, the noise when operating the pixel circuit is predominantly 1 / f noise.
  • the noise of the circuit needs to be lower than the potential difference of one gradation at a minimum.
  • the noise is as small as 1/10 times ( ⁇ 10 dB), preferably 1/100 times ( ⁇ 20 dB), more preferably 1/1000 times ( ⁇ 30 dB) of the potential difference of one gradation. It is desirable to approach 0.
  • the gradation error due to noise can be considered to be sufficiently close to 0 in consideration of the presence of an error in electrical characteristics that affects the device size and factors of several percent to 10 percent.
  • the gradation error is 2560 mV.
  • ⁇ 0.1 250 mV (25 gradations).
  • the gradation error due to 1 / f noise is about 1/100 to 1/1000, which is sufficiently small.
  • the cause of noise between elements constituting the circuit it is preferable to improve the cause of noise between elements constituting the circuit. For example, when there is a noise generation factor in one of the source electrode or the drain electrode of the transistor 51 through which a low current flows and the electrical connection portion of the photoelectric conversion element 60, the charge in the charge storage portion (FD) is accurately discharged. I can't. The same problem occurs when there is a cause of noise at the connection portion between the other of the source electrode or the drain electrode of the transistor 51 and the charge storage portion (FD).
  • one region where electrical connection is made between the elements it is preferable to use one region where electrical connection is made between the elements. This is because when there are a plurality of regions where electrical connection is performed, different noises are generated in each region. Therefore, it is preferable to suppress the generation of many types of noise by using one region where electrical connection is made between the elements.
  • the amount of noise is proportional to the area of the region where electrical connection between the elements is performed, it is preferable that the area of the region is small within an allowable range.
  • the shape viewed from the upper surface of the region is a substantially rectangular shape or a substantially circular shape, and one side or the diameter thereof is a length that does not exceed the wiring design rule.
  • the electrical connection between the elements is made up of a plurality of openings in the insulating film in contact with the electrode of the element. And a contact plug or wiring is provided in the opening.
  • one of the source electrode and the drain electrode of the transistor 51 and the one electrode of the photoelectric conversion element 60 are electrically connected in one opening 31. Is going.
  • the opening 31 is provided in an insulating layer formed between one of the source electrode and the drain electrode of the transistor 51 and one electrode of the photoelectric conversion element 60.
  • the other of the source electrode or the drain electrode of the transistor 51 and the gate electrode of the transistor 52 are electrically connected in one opening 32.
  • the opening 32 is provided in an insulating layer provided between the other of the source electrode and the drain electrode of the transistor 51 and the gate electrode of the transistor 52.
  • the insulating layer functions as a gate insulating film of each transistor.
  • the source electrode and the drain electrode can form a favorable contact interface with the oxide semiconductor layer and can function as a wiring. Therefore, a circuit including an OS transistor can be configured to generate less noise between elements forming the circuit than a circuit including a transistor having silicon in a channel region.
  • the pixel circuit of the imaging device can accurately convert incident light into an electrical signal.
  • a transistor including an oxide semiconductor may be used for a region other than the pixel circuit, and an oxide semiconductor may be used for a transistor included in a driver circuit of the imaging device.
  • noise can be reduced; therefore, for accurate operation of the imaging device, it is useful to use an oxide semiconductor for a transistor included in a driver circuit of the imaging device.
  • Electrode 66 for example, gold, titanium nitride, molybdenum, tungsten, aluminum, titanium, or the like can be used. Further, for example, a stack in which aluminum is sandwiched between titanium can be used.
  • the electrode 66 can be formed by sputtering or plasma CVD. Note that the electrode 66 may be formed over the substrate, or may be formed over the driving transistor formed in the substrate or formed over the substrate.
  • the electrode 66 illustrated in FIG. 1B preferably has high flatness in order to prevent a short circuit with the electrode 62 due to poor coverage of the photoelectric conversion layer 61 or the like. Note that when the flatness of the electrode 66 described above is improved, the adhesion to the photoelectric conversion layer 61 may be improved. Furthermore, when the flatness of the electrode 66 is high, it contributes to the improvement of the flatness of the upper surface of the photoelectric conversion layer 62.
  • a selenium-based material can be used for the photoelectric conversion layer 61.
  • a photoelectric conversion element using a selenium-based material has a high external quantum efficiency with respect to visible light.
  • the photoelectric conversion efficiency can be increased by performing multiplication of carriers generated by incident light using the charge multiplication effect due to the avalanche phenomenon.
  • Crystalline selenium can be used for the photoelectric conversion layer 61.
  • selenium include single crystal selenium, polycrystalline selenium, microcrystalline selenium, and amorphous selenium (amorphous selenium).
  • single crystal selenium, polycrystalline selenium, and microcrystalline selenium are classified as crystalline selenium.
  • a selenium layer in which crystalline selenium and amorphous selenium are mixed may be used.
  • the crystalline selenium layer can be obtained by heat treatment after forming an amorphous selenium layer.
  • a crystalline selenium layer when used for the photoelectric conversion layer 61, variation in characteristics of each pixel can be reduced by making the grain size of selenium crystals contained in the layer smaller than the pixel pitch.
  • a crystalline selenium layer has characteristics of higher spectral sensitivity to visible light and light absorption coefficient than an amorphous selenium layer. Therefore, it is suitable for imaging in a low illumination environment.
  • FIG. 28A is a diagram illustrating a state in which the electrode 66 is formed on the insulating layer 41.
  • an amorphous selenium layer 61 a is formed on the electrode 66.
  • FIG. 28B is a diagram illustrating a state in which an amorphous selenium layer 61 a is formed on the electrode 66.
  • the plate 121 is placed on the amorphous selenium layer 61a.
  • FIG. 28C is a diagram illustrating a state where the plate 121 is placed on the amorphous selenium layer 61a.
  • the plate 121 is placed for the purpose of applying a predetermined pressure to the amorphous selenium layer 61a.
  • the plate 121 is formed by applying pressure during the step of crystallizing the amorphous selenium layer 61a. It has a function of flattening the upper surface.
  • FIG. 28D is a diagram illustrating a state in which the photoelectric conversion layer 61 is formed on the electrode 66.
  • As the plate 121 a sapphire substrate, a quartz substrate, or a glass substrate can be used.
  • the surface of the plate 121 that contacts the amorphous selenium layer 61 a is preferably flatter than the upper surface of the formed photoelectric conversion layer 61.
  • the amorphous selenium layer 61a may be crystallized without placing the plate 121.
  • the photoelectric conversion layer 61 may be a layer containing a compound of copper, indium, and selenium (CIS).
  • a layer containing a compound of copper, indium, gallium, and selenium (CIGS) may be used.
  • CIS and CIGS a photoelectric conversion element that can utilize an avalanche phenomenon as in the case of a single selenium can be formed.
  • CIS and CIGS are p-type semiconductors, and n-type semiconductors such as cadmium sulfide and zinc sulfide may be provided in contact with each other in order to form a junction. In order to generate the avalanche phenomenon, it is required to apply a relatively high voltage (for example, 10 V or more) to the photoelectric conversion element.
  • the electrode 62 includes, for example, indium tin oxide (ITO), indium tin oxide containing silicon, indium oxide containing zinc, zinc oxide, zinc oxide containing gallium, zinc oxide containing aluminum, tin oxide, and oxide containing fluorine. Tin, tin oxide containing antimony, graphene, or the like can be used, but indium tin oxide and indium tin oxide containing silicon are particularly preferable.
  • the electrode 62 is not limited to a single layer, and may be a stack of different films. Note that indium tin oxide includes In, Sn, and O.
  • the electrode 62 preferably has a high light transmittance so that the light reaches the photoelectric conversion layer 61.
  • the area occupied by one pixel is extremely small, and the area that can be used for light reception is extremely small, so that light transmission becomes more important.
  • the electrode 62 can be formed by a sputtering method or a plasma CVD method.
  • FIG. 28E A state in which the electrode 62 is formed is shown in FIG. 28E. Thus, the photoelectric conversion element 60 is formed.
  • the photoelectric conversion element may further include a hole injection blocking layer 91 between the photoelectric conversion layer 61 and the electrode 62 as shown in FIG. 3F.
  • the hole injection blocking layer 91 is a layer having a function of suppressing injection of holes from the electrode 62 to the photoelectric conversion layer 61.
  • a photoelectric conversion element using a selenium-based material for the photoelectric conversion layer 61 has a large dark current when an electric field is applied.
  • one of the causes of dark current is that charge injection from the electrode to the photoelectric conversion layer 61 could not be suppressed. Therefore, in order to suppress charge injection into the photoelectric conversion layer 61, a hole injection blocking layer 91 made of gallium oxide may be provided between the photoelectric conversion layer 61 and the electrode 62.
  • the layer needs to have a certain thickness or more.
  • the film thickness is preferably 5 nm to 1 ⁇ m, and more preferably 10 nm to 500 nm.
  • a material whose film thickness is easier to control than gallium oxide can be used for the hole injection blocking layer 91.
  • an oxide material can be used for the hole injection blocking layer 91.
  • the oxide material used for the hole injection blocking layer 91 include indium oxide, tin oxide, zinc oxide, In—Zn oxide, Sn—Zn oxide, Al—Zn oxide, Zn—Mg oxide, Sn— Mg oxide, In—Mg oxide, In—Ga oxide, In—Ga—Zn oxide, In—Al—Zn oxide, In—Sn—Zn oxide, Sn—Ga—Zn oxide, Al— Ga-Zn oxide, Sn-Al-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In-Ce-Zn oxide, In-Pr-Zn oxide, In-Nd- Zn oxide, In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide , In-Er-
  • an In—Ga—Zn oxide means an oxide containing In, Ga, and Zn as its main components. Moreover, metal elements other than In, Ga, and Zn may be contained.
  • a film formed using an In—Ga—Zn oxide is also referred to as an IGZO film.
  • an In—Ga—Zn oxide is useful as the oxide used for the hole injection blocking layer 91.
  • An In—Ga—Zn oxide tends to be a film having a CAAC (C Axis aligned Crystalline) structure or a microcrystalline oxide film, and an In—Ga—Zn oxide is formed on the hole injection blocking layer 91. When it is used, it becomes a film having crystallinity, which is preferable because it is compatible with the photoelectric conversion layer 61 having crystallinity.
  • the In—Ga—Zn oxide includes at least In, Ga, Zn, and O. Note that a material using Al, Sn, Y, Hf, or Zr instead of Ga is also useful as a material that can exhibit the CAAC structure of the In—Ga—Zn oxide.
  • a film having a CAAC structure has high crystallinity as described later.
  • the photoelectric conversion layer 61 is a selenium layer having crystallinity
  • the hole injection blocking layer 91 and the This is preferable because a film having a CAAC structure is easily formed and the adhesion at the interface is increased.
  • the photoelectric conversion element may include an electron injection blocking layer 92 between the electrode 66 and the photoelectric conversion layer 61 as illustrated in FIG. 3F.
  • the electron injection blocking layer 92 is a layer having a function of suppressing injection of electrons from the electrode 66 to the photoelectric conversion layer 61, and can be provided between the electrode 66 and the photoelectric conversion layer 61.
  • the electron injection blocking layer 92 may be provided with nickel oxide or antimony sulfide.
  • the photoelectric conversion layer 61 and the electrode 62 are not separated between pixels, but may be separated between circuits as shown in the cross-sectional view of FIG. 3A.
  • the partition 67 may not be provided.
  • the electrode 62 and the wiring 77 may be in direct contact with each other.
  • the insulating layer 42 may not be planarized.
  • the partition 67 can be formed using an inorganic insulator, an insulating organic resin, or the like. Further, the partition wall 67 may be colored black or the like for shielding light from the transistor or the like and / or for determining the area of the light receiving portion per pixel.
  • the photoelectric conversion element 60 can be a diode element in which a pn-type or pin-type junction is formed in a silicon substrate.
  • a pin-type diode element using an amorphous silicon film, a microcrystalline silicon film, or the like may be used.
  • FIG. 4A shows an example in which a pin-type thin film photodiode is used for the photoelectric conversion element 60.
  • the photodiode has a configuration in which an n-type semiconductor layer 65, an i-type semiconductor layer 64, and a p-type semiconductor layer 63 are sequentially stacked.
  • Amorphous silicon is preferably used for the i-type semiconductor layer 64.
  • amorphous silicon or microcrystalline silicon containing a dopant imparting each conductivity type can be used.
  • a photodiode using amorphous silicon as a photoelectric conversion layer has high sensitivity in the wavelength region of visible light and can easily detect weak visible light.
  • the n-type semiconductor layer 65 acting as a cathode has an electrical connection with an electrode layer having an electrical connection with the transistor 53.
  • the p-type semiconductor layer 63 acting as an anode has an electrical connection with the wiring 77.
  • the photoelectric conversion element 60 is preferably formed so that the p-type semiconductor layer 63 serves as a light receiving surface. By using the p-type semiconductor layer 63 as the light receiving surface, the output current of the photoelectric conversion element 60 can be increased.
  • the configuration of the photoelectric conversion element 60 in the form of a pin-type thin film photodiode and the connection form of the photoelectric conversion element 60, the transistor 53, and the wiring may be the examples shown in FIGS. 5A to 5F. Note that the configuration of the photoelectric conversion element 60, the connection form of the photoelectric conversion element 60 and the wiring, and the connection form of the transistor 53 and the wiring are not limited to these, and may be other forms.
  • FIG. 5A shows a configuration in which an electrode 62 in contact with the p-type semiconductor layer 63 of the photoelectric conversion element 60 is provided.
  • the electrode 62 acts as an electrode and can increase the output current of the photoelectric conversion element 60.
  • Examples of the electrode 62 include indium tin oxide, indium tin oxide containing silicon, indium oxide containing zinc, zinc oxide, zinc oxide containing gallium, zinc oxide containing aluminum, tin oxide, and tin oxide containing fluorine. Tin oxide containing antimony, graphene, or the like can be used.
  • the electrode 62 is not limited to a single layer, and may be a stack of different films.
  • FIG. 5B shows a configuration in which the p-type semiconductor layer 63 of the photoelectric conversion element 60 and the wiring 74 are connected.
  • FIG. 5C shows a configuration in which an electrode 62 in contact with the p-type semiconductor layer 63 of the photoelectric conversion element 60 is provided, and the wiring 74 and the electrode 62 are connected.
  • FIG. 5D shows a structure in which an opening for exposing the p-type semiconductor layer 63 is provided in the insulating layer covering the photoelectric conversion element 60, and the electrode 62 and the wiring 74 covering the opening have electrical connection.
  • FIG. 5E shows a configuration in which a conductor 81 that penetrates the photoelectric conversion element 60 is provided.
  • the wiring 77 is electrically connected to the p-type semiconductor layer 63 through the conductor 81.
  • the wiring 77 and the electrode 66 are apparently conducted through the n-type semiconductor layer 65.
  • the photoelectric conversion element 60 can have diode characteristics without causing a short circuit between the anode and the cathode.
  • FIG. 5F shows a configuration in which an electrode 62 in contact with the p-type semiconductor layer 63 is provided to the photoelectric conversion element 60 in FIG. 5E.
  • the photoelectric conversion element 60 illustrated in FIGS. 5D to 5F has an advantage that a wide light receiving area can be secured because the light receiving region and the wiring do not overlap.
  • the structure which the insulating layers 41 and 42 are a multilayer may be sufficient.
  • the conductor 81 has a step.
  • the insulating layer 42 includes the insulating layer 42a and the insulating layer 42b.
  • a photodiode having the silicon substrate 40 as a photoelectric conversion layer can be used for the photoelectric conversion element 60.
  • the photoelectric conversion element 60 formed using the above-described selenium-based material, amorphous silicon, or the like can be manufactured using a general semiconductor manufacturing process such as a film formation process, a lithography process, or an etching process.
  • the selenium-based material has a high resistance, and as illustrated in FIG. 1B, the photoelectric conversion layer 61 may be configured not to be separated between circuits. Therefore, the imaging device of one embodiment of the present invention can be manufactured with high yield and low cost.
  • a process with a high degree of difficulty such as a polishing process or a bonding process is required.
  • the imaging device of one embodiment of the present invention may have a multilayer structure including the silicon substrate 40 over which a circuit is formed. For example, as shown in FIGS. 7A and 7B, a transistor 55 and a transistor 56 having an active region on the silicon substrate 40 may overlap with the pixel circuit.
  • the circuit formed on the silicon substrate 40 can have a function of reading a signal output from the pixel circuit, a function of performing a process of converting the signal, and the like, and can include a CMOS inverter.
  • the gates of the transistor 55 (n-ch type) and the transistor 56 (p-ch type) are electrically connected.
  • one of the source and the drain of one transistor is electrically connected to one of the source and the drain of the other transistor.
  • the other of the source or the drain of both transistors is electrically connected to another wiring.
  • the silicon substrate 40 is not limited to a bulk silicon substrate, and a substrate made of germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor can also be used.
  • the transistor 55 and the transistor 56 may be transistors having an active layer 59 of a silicon thin film.
  • the active layer 59 can be made of polycrystalline silicon or SOI (Silicon on Insulator) single crystal silicon.
  • the insulating layer 80 is provided between the layer including the transistors 55 and 56 and the layer including the transistors 51 and 52.
  • Hydrogen in the insulating layer provided in the vicinity of the active regions of the transistors 55 and 56 terminates dangling bonds of silicon. Therefore, the hydrogen has an effect of improving the reliability of the transistor 55 and the transistor 56.
  • hydrogen in the insulating layer provided in the vicinity of the oxide semiconductor layer which is an active layer of the transistor 51 or the like becomes one of the factors for generating carriers in the oxide semiconductor. Therefore, the hydrogen may be a factor that decreases the reliability of the transistor 51 and the like. Therefore, in the case where one layer having a transistor using a silicon-based semiconductor material and the other layer having a transistor using an oxide semiconductor are stacked, the insulating layer 80 has a function of preventing hydrogen diffusion therebetween. Is preferably provided. The reliability of the transistors 55 and 56 can be improved by confining hydrogen in one layer by the insulating layer 80. In addition, since the diffusion of hydrogen from one layer to the other layer is suppressed, the reliability of the transistor 51 and the like can be improved.
  • the insulating layer 80 for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), or the like can be used.
  • aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), or the like can be used.
  • a circuit for example, a drive circuit formed on the silicon substrate 40, the transistor 51, and the photoelectric conversion element 60 can be formed so as to overlap with each other.
  • the degree of pixel integration can be increased. That is, the resolution of the imaging device can be increased. For example, it is suitable for use in an imaging device having the number of pixels of 4k2k, 8k4k, or 16k8k.
  • the imaging device illustrated in FIG. 7A has a configuration in which no photoelectric conversion element is provided on the silicon substrate 40. Therefore, an optical path to the photoelectric conversion element 60 can be secured without being affected by various transistors and wirings, and a pixel with a high aperture ratio can be formed.
  • any one or more of the transistors 51 to 54 can be formed of a transistor having silicon or the like in an active region or an active layer.
  • both or one of the transistor 55 and the transistor 56 can be a transistor having an oxide semiconductor layer as an active layer.
  • FIG. 8A is a cross-sectional view of an example in which a color filter or the like is added to the imaging device shown in FIGS. 1A and 1B.
  • the cross-sectional view shows a part of a region having a pixel circuit for three pixels.
  • An insulating layer 1500 is formed over the region 1400 where the photoelectric conversion element 60 is formed.
  • the insulating layer 1500 can be formed using a silicon oxide film having high light-transmitting property with respect to visible light.
  • a silicon nitride film may be stacked as the passivation film.
  • a dielectric film such as hafnium oxide may be stacked as the antireflection film.
  • a light shielding layer 1510 is formed over the insulating layer 1500.
  • the light shielding layer 1510 has a function of preventing color mixture of light passing through the upper color filter.
  • a structure in which a metal layer such as aluminum or tungsten, or a dielectric film having a function as an antireflection film is stacked can be used.
  • an organic resin layer 1520 is formed as a planarization film.
  • a color filter 1530a, a color filter 1530b, and a color filter 1530c are formed for each pixel.
  • a color image can be obtained by assigning colors such as R (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta) to each of the color filters. it can.
  • a microlens array 1540 is provided over the color filter 1530a, the color filter 1530b, and the color filter 1530c. Therefore, light passing through each lens included in the microlens array 1540 passes through the color filter directly below and is irradiated to the photoelectric conversion element. Note that the microlens array 1540 may be omitted.
  • an optical conversion layer 1550 may be used instead of the color filter 1530a, the color filter 1530b, and the color filter 1530c. With such a configuration, an imaging device capable of obtaining images in various wavelength regions can be obtained.
  • an infrared imaging device when a filter that blocks light having a wavelength shorter than or equal to that of visible light is used for the optical conversion layer 1550, an infrared imaging device can be obtained. If a filter that blocks light having an infrared wavelength or less is used for the optical conversion layer 1550, a far-infrared imaging device can be obtained. When a filter that blocks light having a wavelength longer than or equal to that of visible light is used for the optical conversion layer 1550, an ultraviolet imaging device can be obtained.
  • an imaging apparatus that can be used for an X-ray imaging apparatus or the like to obtain an image that visualizes the intensity of radiation can be obtained.
  • radiation such as X-rays transmitted through the subject
  • light fluorescence
  • photoluminescence a phenomenon called photoluminescence
  • image data is acquired by detecting the light with the photoelectric conversion element 60.
  • the imaging device having the configuration may be used for a radiation detector or the like.
  • the scintillator is made of a substance that absorbs energy and emits visible light or ultraviolet light when irradiated with radiation such as X-rays or gamma rays, or a material containing the substance.
  • Gd 2 O 2 S Tb
  • Gd 2 O 2 S Pr
  • Gd 2 O 2 S Eu
  • BaFCl Eu
  • NaI, CsI, CaF 2 , BaF 2 , CeF 3 LiF, LiI, ZnO, etc.
  • Materials and materials in which they are dispersed in resins and ceramics are known.
  • the photoelectric conversion element 60 using a selenium-based material can directly convert radiation such as X-rays into electric charges, and thus can be configured to eliminate a scintillator.
  • the imaging device of one embodiment of the present invention may include a region 1300 in which an OS transistor is provided below the region 1400 as illustrated in FIG. 8C.
  • the configurations of the region 1300 and the region 1400 may be, for example, the configurations illustrated in FIGS. 1A and 1B, FIGS. 4A and 4B, and FIG.
  • the imaging device of one embodiment of the present invention includes a region 1300 in which an OS transistor is provided below the region 1400, and a region 1200 in which an Si transistor is provided below the region 1300. You may have.
  • the configuration of the region 1200, the region 1300, and the region 1400 can be, for example, the configuration illustrated in FIGS. 7A and 7B.
  • FIG. 9A1 shows a state in which the imaging device is bent in the direction of a two-dot chain line X1-X2.
  • 9A2 is a cross-sectional view of a portion indicated by two-dot chain line X1-X2 in FIG. 9A1.
  • 9A3 is a cross-sectional view of a portion indicated by two-dot chain line Y1-Y2 in FIG. 9A1.
  • FIG. 9B1 shows a state in which the imaging device is curved in the direction of a two-dot chain line X3-X4 in the drawing and in the direction of a two-dot chain line Y3-Y4 in the drawing.
  • 9B2 is a cross-sectional view of a portion indicated by two-dot chain line X3-X4 in FIG. 9B1.
  • 9B3 is a cross-sectional view of a portion indicated by two-dot chain line Y3-Y4 in FIG. 9B1.
  • the imaging device By curving the imaging device, field curvature and astigmatism can be reduced. Therefore, optical design of a lens or the like used in combination with the imaging device can be facilitated. For example, since the number of lenses for aberration correction can be reduced, it is possible to easily reduce the size and weight of a semiconductor device using an imaging device. In addition, the quality of the captured image can be improved.
  • one embodiment of the present invention is described in this embodiment. Alternatively, in another embodiment, one embodiment of the present invention will be described. Note that one embodiment of the present invention is not limited thereto. For example, although an example in which the present invention is applied to an imaging device is shown as one embodiment of the present invention, one embodiment of the present invention is not limited thereto. In some cases or depending on circumstances, one embodiment of the present invention may not be applied to an imaging device. For example, one embodiment of the present invention may be applied to a semiconductor device having another function.
  • Embodiment 2 In this embodiment, the pixel circuit described in Embodiment 1 is described.
  • FIG. 10A shows details of the connection form between the pixel circuit and each wiring shown in FIG. 2A.
  • the circuit illustrated in FIG. 10A includes a photoelectric conversion element 60, a transistor 51, a transistor 52, a transistor 53, and a transistor 54.
  • the anode of the photoelectric conversion element 60 is connected to the wiring 316, and the cathode is connected to one of the source and the drain of the transistor 51.
  • the other of the source and the drain of the transistor 51 is connected to the charge accumulation portion (FD), and the gate is connected to the wiring 312 (TX).
  • One of a source and a drain of the transistor 52 is connected to the wiring 314 (GND), the other of the source and the drain is connected to one of the source and the drain of the transistor 54, and a gate is connected to the charge accumulation portion (FD).
  • One of a source and a drain of the transistor 53 is connected to the charge accumulation portion (FD), the other of the source and the drain is connected to the wiring 317, and a gate is connected to the wiring 311 (RS).
  • the other of the source and the drain of the transistor 54 is connected to the wiring 315 (OUT), and the gate is connected to the wiring 313 (SE). All the above connections are electrical connections.
  • a potential such as GND, VSS, or VDD may be supplied to the wiring 314.
  • the potential and voltage are relative. Therefore, the magnitude of the potential of GND is not necessarily 0 volts.
  • the photoelectric conversion element 60 is a light receiving element, and has a function of generating a current corresponding to light incident on the pixel circuit.
  • the transistor 53 has a function of controlling charge accumulation in the charge accumulation unit (FD) by the photoelectric conversion element 60.
  • the transistor 54 has a function of outputting a signal corresponding to the potential of the charge accumulation portion (FD).
  • the transistor 56 has a function of resetting the potential of the charge accumulation portion (FD).
  • the transistor 56 has a function of controlling selection of the pixel circuit at the time of reading.
  • the charge storage portion (FD) is a charge holding node, and holds charges that change according to the amount of light received by the photoelectric conversion element 60.
  • the transistor 52 and the transistor 54 may be connected in series between the wiring 315 and the wiring 314. Therefore, the wiring 314, the transistor 52, the transistor 54, and the wiring 315 may be arranged in this order, or the wiring 314, the transistor 54, the transistor 52, and the wiring 315 may be arranged in this order.
  • the wiring 311 functions as a signal line for controlling the transistor 53.
  • the wiring 312 functions as a signal line for controlling the transistor 51.
  • the wiring 313 functions as a signal line for controlling the transistor 54.
  • the wiring 314 functions as a signal line for setting a reference potential (for example, GND).
  • the wiring 315 functions as a signal line for reading a signal output from the transistor 52.
  • the wiring 316 functions as a signal line for outputting charges from the charge accumulation portion (FD) via the photoelectric conversion element 60, and is a low potential line in the circuit of FIG. 10A.
  • the wiring 317 functions as a signal line for resetting the potential of the charge accumulation portion (FD), and is a high potential line in the circuit of FIG. 10A.
  • the wiring 76 corresponds to the wiring 311 (RS).
  • the wiring 75 corresponds to the wiring 312 (TX).
  • the wiring 78 corresponds to the wiring 313 (SE).
  • the wiring 79 corresponds to the wiring 314 (GND).
  • the wiring 71 corresponds to the wiring 315 (OUT).
  • the wiring 77 corresponds to the wiring 316.
  • the pixel circuit of one embodiment of the present invention may have a structure illustrated in FIG. 10B.
  • the circuit shown in FIG. 10B has the same components as the circuit shown in FIG. 10A, but the anode of the photoelectric conversion element 60 is electrically connected to one of the source and drain of the transistor 51, and the cathode of the photoelectric conversion element 60 is It differs in that it is electrically connected to the wiring 316.
  • the wiring 316 functions as a signal line for supplying a charge to the charge accumulation portion (FD) through the photoelectric conversion element 60, and is a high potential line in the circuit of FIG. 10B.
  • the wiring 317 is a low potential line.
  • an element formed of a selenium-based material and a conductive layer, or an element in which a pin-type junction is formed by a silicon layer can be used.
  • the transistor 51, the transistor 52, the transistor 53, and the transistor 54 can be formed using a silicon semiconductor such as amorphous silicon, microcrystalline silicon, polycrystalline silicon, or single crystal silicon; It is preferable to use the transistor used.
  • a transistor in which a channel formation region is formed using an oxide semiconductor has a characteristic of extremely low off-state current.
  • transistors 52 and 54 if the leakage current is large, unnecessary charge is output to the wiring 314 or the wiring 315. Therefore, transistors in which a channel formation region is formed using an oxide semiconductor are used as these transistors. It is preferable.
  • FIG. 10A An example of operation of the circuit in FIG. 10A will be described with reference to a timing chart shown in FIG. 11A.
  • each wiring is given as a signal that changes in binary.
  • each potential is an analog signal, actually, it can take various values without being limited to binary values depending on the situation.
  • the signal 701 shown in the figure is the potential of the wiring 311 (RS)
  • the signal 702 is the potential of the wiring 312 (TX)
  • the signal 703 is the potential of the wiring 313 (SE)
  • the signal 704 is the potential of the charge accumulation portion (FD)
  • a signal 705 corresponds to the potential of the wiring 315 (OUT).
  • the potential of the wiring 316 is always “Low”, and the potential of the wiring 317 is always “High”.
  • the potential of the wiring 311 (signal 701) is “High” and the potential of the wiring 312 (signal 702) is “High”
  • the potential of the charge accumulation portion (FD) (signal 704) is the potential of the wiring 317 (signal 704). It is initialized to “High”) and the reset operation is started. Note that the potential of the wiring 315 (signal 705) is precharged to “High”.
  • the charge distribution storage unit (FD) (signal 704) starts to decrease due to the reverse current. Since the reverse current increases when the photoelectric conversion element 60 is irradiated with light, the rate of decrease of the potential (signal 704) of the charge storage portion (FD) changes according to the amount of the irradiated light. That is, the channel resistance between the source and the drain of the transistor 54 changes in accordance with the amount of light with which the photoelectric conversion element 60 is irradiated.
  • the potential of the wiring 312 (signal 702) is set to “Low”, the accumulation operation ends, and the potential of the charge accumulation portion (FD) (signal 704) becomes constant.
  • the potential is determined by the amount of charge generated by the photoelectric conversion element 60 during the accumulation operation. That is, it changes according to the amount of light that has been applied to the photoelectric conversion element.
  • the transistor 51 and the transistor 53 are formed using a transistor in which a channel formation region is formed using an oxide film semiconductor layer and have an extremely low off-state current, the charge accumulation unit (FD) is used until a subsequent selection operation (read operation) is performed. ) Can be kept constant.
  • the transistor 54 is turned on to start a selection operation, and the wiring 314 and the wiring 315 are turned on through the transistor 52 and the transistor 54. Then, the potential of the wiring 315 (signal 705) decreases. Note that the precharge of the wiring 315 may be completed before the time D.
  • the speed at which the potential of the wiring 315 (the signal 705) decreases depends on the current between the source and the drain of the transistor 52. That is, it changes according to the amount of light irradiated to the photoelectric conversion element 60 during the accumulation operation.
  • the potential of the wiring 313 (signal 703) is set to “Low”, the transistor 54 is cut off, the selection operation is finished, and the potential of the wiring 315 (signal 705) becomes a constant value.
  • the value which becomes a constant value changes in accordance with the amount of light applied to the photoelectric conversion element 60. Therefore, by acquiring the potential of the wiring 315, the amount of light applied to the photoelectric conversion element 60 during the accumulation operation can be known.
  • the potential of the charge storage portion (FD), that is, the gate voltage of the transistor 52 is decreased. Therefore, the current flowing between the source and the drain of the transistor 52 becomes small, and the potential of the wiring 315 (signal 705) is slowly decreased. Accordingly, a relatively high potential can be read from the wiring 315.
  • the description of the timing chart in FIG. 11A can be referred to.
  • the potential of the wiring 315 is acquired, so that the photoelectric conversion element 60 is irradiated during the accumulation operation. You can know the amount.
  • the pixel circuit illustrated in FIG. 10A may have a mode in which the transistor 5254 is shared by a plurality of pixels as illustrated in FIG.
  • FIG. 15 illustrates a configuration in which the transistor 5254 is shared by a plurality of pixels in the vertical direction; however, the transistor 5254 may be shared by a plurality of pixels in the horizontal direction or the horizontal and vertical directions. With such a structure, the number of transistors included in one pixel can be reduced. Note that although FIG. 15 illustrates a mode in which the transistor 5254 is shared by four pixels, the transistor 5254 may be shared by two, three, or five or more pixels. Further, the pixel circuit illustrated in FIG. 10B can have a similar structure.
  • the pixel circuit of one embodiment of the present invention may have a structure illustrated in FIGS. 12A and 12B.
  • the circuit illustrated in FIG. 12A has a configuration in which the transistor 53, the wiring 316, and the wiring 317 are omitted from the configuration of the circuit illustrated in FIG. 10A, and the wiring 311 (RS) is electrically connected to the anode of the photoelectric conversion element 60.
  • Other configurations are the same as those of the circuit shown in FIG. 10A.
  • 12B has the same components as the circuit shown in FIG. 12A, but the anode of the photoelectric conversion element 60 is electrically connected to one of the source and the drain of the transistor 52, and the cathode of the photoelectric conversion element 60 is It differs in that it is electrically connected to the wiring 311 (RS).
  • the circuit in FIG. 12A can be operated with the timing chart shown in FIG. 11A in the same manner as the circuit in FIG. 10A.
  • the description of the circuit operation in FIG. 10A can be referred to.
  • the photoelectric conversion element 60 is irradiated during the accumulation operation. You can know the amount.
  • the circuit in FIG. 12B can be operated with the timing chart shown in FIG. 11C.
  • the description of the circuit operation in FIG. 10A can be referred to.
  • the photoelectric conversion element 60 is irradiated during the accumulation operation. You can know the amount.
  • the pixel circuit illustrated in FIG. 12A may have a configuration in which the transistor 52 and the transistor 54 are shared by a plurality of pixels as illustrated in FIG.
  • FIG. 16 illustrates a configuration in which the transistor 52 and the transistor 54 are shared by a plurality of pixels in the vertical direction, but the transistor 52 and the transistor 54 may be shared by a plurality of pixels in the horizontal direction or the horizontal and vertical directions.
  • FIG. 16 illustrates a mode in which the transistor 52 and the transistor 54 are shared by four pixels, but two, three, or five or more pixels may be shared.
  • the pixel circuit illustrated in FIG. 12B can have a similar structure.
  • FIGS. 12A and 12B illustrate examples in which the transistor 51 is provided; however, one embodiment of the present invention is not limited thereto. As shown in FIGS. 13A and 13B, the transistor 51 can be omitted.
  • the transistor used in the pixel circuit may have a structure in which a back gate is provided in the transistor 51, the transistor 52, and the transistor 54 as illustrated in FIG. 14A or 14B.
  • FIG. 14A shows a configuration in which a constant potential is applied to the back gate, and the threshold voltage can be controlled.
  • FIG. 14B shows a configuration in which the same potential as that of the front gate is applied to the back gate, and the on-current can be increased.
  • 14A illustrates the structure in which the back gate is electrically connected to the wiring 314 (GND); however, the back gate may be electrically connected to another wiring to which a constant potential is supplied.
  • 14A and 14B show an example in which a back gate is provided in a transistor in the circuit shown in FIG. 12A.
  • FIGS. 10A and 10B, FIGS. 12B, 13A and 13B You can also.
  • a configuration in which the same potential as that of the front gate is applied to the back gate, a configuration in which a constant potential is applied to the back gate, or a configuration in which no back gate is provided for a transistor included in one circuit is arbitrarily selected as necessary.
  • a combined circuit configuration may be used.
  • the transistor 52 and the transistor 54 may be shared by a plurality of pixels as illustrated in FIG.
  • the pixel circuit illustrated in FIG. 14B may have a configuration in which the transistor 52 and the transistor 54 are shared by a plurality of pixels as illustrated in FIG.
  • the operation of the pixel circuit is a repetition of the reset operation, the accumulation operation, and the selection operation.
  • an imaging method for controlling the entire pixel matrix a global shutter method and a rolling shutter method are known.
  • FIG. 19A is a timing chart in the global shutter system. Note that FIG. 19A is an example of an imaging device having a plurality of pixel circuits in a matrix, and the pixel circuit having the circuit of FIG. 10A. The first to nth rows (n is a natural number of 3 or more). The operation of the pixel circuit will be described. The following description of the operation can also be applied to the circuits shown in FIGS. 10B, 12A and 12B, and FIGS. 13A and 13B.
  • a signal 501, a signal 502, and a signal 503 are signals input to the wiring 311 (RS) connected to the pixel circuits in the first row, the second row, and the n-th row.
  • the signal 504, the signal 505, and the signal 506 are signals input to the wiring 312 (TX) connected to the pixel circuits in the first row, the second row, and the n-th row.
  • the signal 507, the signal 508, and the signal 509 are signals input to the wiring 313 (SE) connected to the pixel circuits in the first row, the second row, and the n-th row.
  • a period 510 is a period required for one imaging.
  • a period 511 is a period in which the pixel circuits in each row perform the reset operation at the same time.
  • a period 520 is a period in which the pixel circuits in each row perform the accumulation operation simultaneously. Note that the selection operation is sequentially performed in the pixel circuits in each row.
  • the period 531 is a period in which the pixel circuit in the first row is performing a selection operation. As described above, in the global shutter system, after the reset operation is performed almost simultaneously in all the pixel circuits, the accumulation operation is performed almost simultaneously in all the pixel circuits, and the read operation is sequentially performed for each row.
  • FIG. 19B is a timing chart when the rolling shutter method is used. Note that the description of FIG. 19A can be referred to for the signals 501 to 509.
  • a period 610 is a period required for one imaging.
  • a period 611, a period 612, and a period 613 are reset periods for the first row, the second row, and the n-th row, respectively.
  • a period 621, a period 622, and a period 623 are accumulation operation periods of the first row, the second row, and the n-th row, respectively.
  • a period 631 is a period in which the pixel circuit in the first row is performing a selection operation.
  • the accumulation operation is not performed simultaneously in all the pixel circuits, but is sequentially performed for each row, so that the synchronization of imaging in the pixel circuits in each row is not ensured. Therefore, since the imaging timing is different between the first line and the last line, when the moving object is a subject, an image with a large distortion is obtained.
  • a global shutter system can be easily realized by using a transistor in which a channel formation region is formed using an oxide semiconductor in a pixel circuit.
  • FIG. 20A to 20C are a top view and cross-sectional views of a transistor according to one embodiment of the present invention.
  • 20A is a top view
  • FIG. 20B is a cross-sectional view corresponding to the alternate long and short dash line X1-X2 shown in FIG. 20A
  • FIG. 20C is a cross-sectional view corresponding to the alternate long and short dash line Y1-Y2. Note that in the top view of FIG. 20A, some elements are omitted for clarity of illustration.
  • the transistor 200 includes a conductor 205 (a conductor 205a and a conductor 205b) that functions as a gate electrode, a conductor 260, an insulator 220 that functions as a gate insulating layer, an insulator 222, an insulator 224, and an insulator. 250, an oxide 230 having a region where a channel is formed (oxide 230a, oxide 230b, and oxide 230c), a conductor 240a functioning as one of a source or a drain, and functioning as the other of a source or a drain And an insulator 280 having excess oxygen and an insulator 282 having a barrier property.
  • the oxide 230 includes an oxide 230a, an oxide 230b over the oxide 230a, and an oxide 230c over the oxide 230b. Note that when the transistor 200 is turned on, a current flows mainly in the oxide 230b (a channel is formed). On the other hand, in the oxide 230a and the oxide 230c, a current may flow at the interface with the oxide 230b and in the vicinity thereof (may be a mixed region), but other regions function as an insulator. There is.
  • the oxide 230c is preferably provided so as to cover the side surfaces of the oxide 230a and the oxide 230b.
  • impurities such as hydrogen, water, and halogen are transferred from the insulator 280 to the oxide 230b. Diffusion can be suppressed.
  • the conductor 205 includes a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing any of the above elements as a component (tantalum nitride, nitride).
  • a titanium film, a molybdenum nitride film, a tungsten nitride film, or the like can be used.
  • a metal nitride film such as tantalum nitride is preferable because it has a barrier property against hydrogen or oxygen and is difficult to oxidize (high oxidation resistance).
  • indium tin oxide indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon oxide added It is also possible to apply a conductive material such as indium tin oxide.
  • 20A to 20C illustrate a two-layer structure of the conductor 205a and the conductor 205b; however, the structure is not limited thereto, and may be a single layer or a stacked structure including three or more layers.
  • a conductor having a high barrier property and a conductor having a high barrier property may be formed between a conductor having a barrier property and a conductor having a high conductivity.
  • the insulator 220 and the insulator 224 are preferably insulators containing oxygen such as a silicon oxide film or a silicon oxynitride film.
  • an insulator containing excess oxygen (containing oxygen in excess of the stoichiometric composition) is preferably used. By providing such an insulator containing excess oxygen in contact with the oxide included in the transistor 200, oxygen vacancies in the oxide can be compensated.
  • the insulator 222 and the insulator 224 are not necessarily made of the same material.
  • the insulator 222 is formed of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ), or (Ba,
  • An insulator containing a so-called high-k material such as Sr) TiO 3 (BST) is preferably used in a single layer or a stacked layer.
  • an insulating film having a barrier property against oxygen and hydrogen, such as aluminum oxide and hafnium oxide is preferably used. In the case of using such a material, it functions as a layer which prevents release of oxygen from the oxide 230 and entry of impurities such as hydrogen from the outside.
  • aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators.
  • these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the above insulator.
  • the insulator 220, the insulator 222, and the insulator 224 may have a stacked structure of two or more layers. In that case, it is not limited to the laminated structure which consists of the same material, The laminated structure which consists of a different material may be sufficient.
  • the insulator 222 By including the insulator 222 including a high-k material between the insulator 220 and the insulator 224, the insulator 222 can capture electrons under a specific condition and increase the threshold voltage. That is, the insulator 222 may be negatively charged.
  • the operating temperature of the semiconductor device Or under a temperature higher than the storage temperature (eg, 125 ° C. or higher and 450 ° C. or lower, typically 150 ° C. or higher and 300 ° C. or lower), the potential of the conductor 205 is higher than the potential of the source electrode or the drain electrode.
  • the potential of the conductor 205 is higher than the potential of the source electrode or the drain electrode.
  • the threshold voltage of the transistor that captures an amount of electrons necessary for the electron trap level of the insulator 222 is shifted to the positive side. Note that the amount of electrons captured can be controlled by controlling the voltage of the conductor 205, and the threshold voltage can be controlled accordingly.
  • the transistor 200 is a normally-off transistor that is non-conductive (also referred to as an off state) even when the gate voltage is 0 V.
  • the process for capturing electrons may be performed in the manufacturing process of the transistor. For example, after the formation of the conductor connected to the source electrode or drain electrode of the transistor, after the completion of the previous process (wafer processing), after the wafer dicing process, after packaging, etc., at any stage before factory shipment It is good to do.
  • the threshold voltage can be controlled by appropriately adjusting the film thicknesses of the insulator 220, the insulator 222, and the insulator 224.
  • the total thickness of the insulator 220, the insulator 222, and the insulator 224 is 65 nm or less, preferably 20 nm or less.
  • a transistor with small leakage current when non-conducting it is possible to provide a transistor with small leakage current when non-conducting.
  • a transistor having stable electrical characteristics can be provided.
  • a transistor with high on-state current can be provided.
  • a transistor with a small subthreshold swing value can be provided.
  • a highly reliable transistor can be provided.
  • the oxide 230a, the oxide 230b, and the oxide 230c are formed using a metal oxide such as an In-M-Zn oxide (M is Al, Ga, Y, or Sn). Further, as the oxide 230, an In—Ga oxide or an In—Zn oxide may be used.
  • the insulator 250 is formed of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ), or (Ba,
  • An insulator containing a so-called high-k material such as Sr) TiO 3 (BST) can be used as a single layer or a stacked layer.
  • aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators.
  • these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the above insulator.
  • the insulator 250 is preferably formed using an oxide insulator containing oxygen in excess of the stoichiometric composition, like the insulator 224. By providing such an insulator containing excess oxygen in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced.
  • the insulator 250 has a barrier property against oxygen and hydrogen such as aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, and silicon nitride.
  • An insulating film can be used.
  • the insulator 250 is formed using such a material, it functions as a layer which prevents release of oxygen from the oxide 230 and entry of impurities such as hydrogen from the outside.
  • the insulator 250 may have a stacked structure similar to that of the insulator 220, the insulator 222, and the insulator 224.
  • the transistor 200 can shift the threshold voltage to the plus side.
  • the transistor 200 is a normally-off transistor that is non-conductive (also referred to as an off state) even when the gate voltage is 0 V.
  • a barrier film may be provided between the oxide 230 and the conductor 260 in addition to the insulator 250.
  • the oxide 230c having a barrier property may be used.
  • oxygen may be in a state in which the oxide substantially matches the stoichiometric composition or in a stoichiometric composition. Many supersaturated states can be obtained. In addition, entry of impurities such as hydrogen into the oxide 230 can be prevented.
  • One of the conductor 240a and the conductor 240b functions as a source electrode, and the other functions as a drain electrode.
  • a metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or an alloy containing the same as a main component can be used.
  • a metal nitride film such as tantalum nitride is preferable because it has a barrier property against hydrogen or oxygen and has high oxidation resistance.
  • a stacked structure of two or more layers may be used.
  • a tantalum nitride and tungsten film may be stacked.
  • a titanium film and an aluminum film are preferably stacked.
  • a two-layer structure in which an aluminum film is stacked on a tungsten film a two-layer structure in which a copper film is stacked on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is stacked on a titanium film, and a tungsten film A two-layer structure in which copper films are stacked may be used.
  • a three-layer structure in which an aluminum film or a copper film is stacked over the film and the molybdenum film or the molybdenum nitride film, and a molybdenum film or a molybdenum nitride film is stacked thereover may be used.
  • a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.
  • the conductor 260 having a function as a gate electrode is, for example, a metal selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, an alloy containing the above-described metal as a component, or a combination of the above-described metals. It can be formed by using an alloy or the like.
  • a metal nitride film such as tantalum nitride is preferable because it has a barrier property against hydrogen or oxygen and has high oxidation resistance.
  • a metal selected from one or more of manganese and zirconium may be used.
  • a semiconductor typified by polycrystalline silicon doped with an impurity element such as phosphorus, or silicide such as nickel silicide may be used.
  • an impurity element such as phosphorus
  • silicide such as nickel silicide
  • a two-layer structure in which a titanium film is stacked over an aluminum film is preferable.
  • a two-layer structure in which a titanium film is stacked on a titanium nitride film, a two-layer structure in which a tungsten film is stacked on a titanium nitride film, and a two-layer structure in which a tungsten film is stacked on a tantalum nitride film or a tungsten nitride film are used. Also good.
  • a three-layer structure in which a titanium film and an aluminum film are stacked over the titanium film and a titanium film is stacked thereover may be used.
  • an alloy film or a nitride film in which one or more metals selected from aluminum, titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium are combined may be used.
  • the conductor 260 includes indium tin oxide, indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, indium tin oxide including titanium oxide, and indium zinc oxide.
  • a light-transmitting conductive material such as indium tin oxide to which silicon oxide is added can be used.
  • a stacked structure of the above light-transmitting conductive material and the above metal can be used.
  • an insulator 280 and an insulator 282 are provided over the transistor 200.
  • the insulator 280 an insulator containing more oxygen than that in the stoichiometric composition is preferably used. That is, the insulator 280 is preferably formed with a region where oxygen is present in excess of the stoichiometric composition (hereinafter also referred to as an excess oxygen region).
  • an insulator having an excess oxygen region is provided as an interlayer film or the like in the vicinity of the transistor 200 so that oxygen vacancies in the transistor 200 are reduced, so that reliability can be improved. .
  • an oxide material from which part of oxygen is released by heating is preferably used as the insulator having an excess oxygen region.
  • the oxide which desorbs oxygen by heating means that the amount of desorbed oxygen converted to oxygen atoms is 1.0 ⁇ 10 18 atoms / cm 3 or more, preferably 3.0 ⁇ 10 20 in TDS analysis.
  • An oxide film having atoms / cm 3 or more. The surface temperature of the film at the time of the TDS analysis is preferably in the range of 100 ° C. to 700 ° C., or 100 ° C. to 500 ° C.
  • a material containing silicon oxide or silicon oxynitride is preferably used.
  • a metal oxide can be used. Note that in this specification, silicon oxynitride refers to a material with a higher oxygen content than nitrogen, and silicon nitride oxide refers to a material with a higher nitrogen content than oxygen.
  • the insulator 280 that covers the transistor 200 may function as a planarization film that covers the uneven shape below the transistor 200.
  • the insulator 282 is preferably formed using an insulating film having a barrier property against oxygen and hydrogen, such as aluminum oxide and hafnium oxide. In the case of using such a material, the insulator 282 functions as a layer which prevents release of oxygen from the oxide 230 and entry of impurities such as hydrogen from the outside.
  • a transistor including an oxide semiconductor with high on-state current can be provided.
  • a transistor including an oxide semiconductor with low off-state current can be provided.
  • variation in electrical characteristics of the semiconductor device can be suppressed and reliability can be improved.
  • a semiconductor device with reduced power consumption can be provided.
  • FIGS. 21A to 21C illustrate examples of structures applicable to the transistor 200.
  • FIGS. FIG. 21A shows the top surface of the transistor 200. Note that some films are omitted in FIG. 21A for clarity.
  • 21B is a cross-sectional view corresponding to the alternate long and short dash line X1-X2 shown in FIG. 21A
  • FIG. 21C is a cross-sectional view corresponding to Y1-Y2.
  • the structure having the same function as the structure of the transistor 200 illustrated in FIGS. 20A to 20C is denoted by the same reference numeral.
  • the conductor 260 is provided in a two-layer structure (the conductor 260a and the conductor 260b).
  • the same material may be stacked.
  • the conductor 260a is formed using a thermal CVD method, an MOCVD method, or an ALD method.
  • damage during film formation on the insulator 250 can be reduced.
  • the conductor 260b is formed by a sputtering method.
  • the conductor 260 a by including the conductor 260 a over the insulator 250, it is possible to prevent the damage on the insulator 250 from being damaged when the conductor 260 b is formed. Further, since the sputtering method has a higher film formation rate than the ALD method, the yield is high and the productivity can be improved.
  • an insulator 270 is provided so as to cover the conductor 260.
  • the insulator 270 is formed using a substance having a barrier property against oxygen in order to prevent the conductor 260b from being oxidized by the released oxygen. .
  • the insulator 270 can be formed using a metal oxide such as aluminum oxide.
  • the insulator 270 only needs to be provided with a thickness that prevents the conductor 260 from being oxidized.
  • the thickness of the insulator 270 is 1 nm to 10 nm, preferably 3 nm to 7 nm.
  • the range of material selection for the conductor 260 can be increased.
  • a material having low conductivity while having low oxidation resistance such as aluminum can be used.
  • a conductor that can be easily formed or processed can be used.
  • oxidation of the conductor 260 can be suppressed, and oxygen released from the insulator 280 can be efficiently supplied to the oxide 230.
  • the transistor 200 with low power consumption can be provided.
  • FIG. 22A to 22C illustrate examples of structures applicable to the transistor 200.
  • FIG. FIG. 22A shows the top surface of the transistor 200. Note that some films are omitted in FIG. 22A for clarity.
  • 22B is a cross-sectional view corresponding to the alternate long and short dash line X1-X2 shown in FIG. 22A
  • FIG. 22C is a cross-sectional view corresponding to Y1-Y2.
  • the conductor 260 functioning as a gate electrode includes a conductor 260a, a conductor 260b, and a conductor 260c.
  • the oxide 230c only needs to cover the side surface of the oxide 230b, and may be cut on the insulator 224.
  • the conductor 260a is formed using a thermal CVD method, an MOCVD method, or an ALD method. In particular, it is preferable to form using the ALD method. By forming by the ALD method or the like, damage to the insulator 250 due to plasma can be reduced. Further, it is preferable because the coverage of the conductor 260a can be improved. Therefore, the transistor 200 with high reliability can be provided.
  • the conductor 260b is formed using a highly conductive material such as tantalum, tungsten, copper, or aluminum. Further, the conductor 260c formed over the conductor 260b is preferably formed using a conductor having high oxidation resistance such as tungsten nitride.
  • a conductor having high oxidation resistance is used for the conductor 260c having a large area in contact with the insulator 280 having an excess oxygen region, thereby preventing excess oxygen from It is possible to suppress the desorbed oxygen from being absorbed by the conductor 260. Further, oxidation of the conductor 260 can be suppressed, and oxygen released from the insulator 280 can be efficiently supplied to the oxide 230. In addition, by using a highly conductive conductor for the conductor 260b, the transistor 200 with low power consumption can be provided.
  • the oxide 230b is covered with the conductor 260 in the channel width direction.
  • the insulator 224 has a protrusion
  • the side surface of the oxide 230 b can be covered with the conductor 260.
  • the shape of the protrusion of the insulator 224 be adjusted so that the bottom surface of the conductor 260 is closer to the substrate side than the bottom surface of the oxide 230b on the side surface of the oxide 230b. That is, the transistor 200 has a structure in which the oxide 230 b can be electrically surrounded by the electric field of the conductor 260.
  • the structure of the transistor that electrically surrounds the oxide 230b by the electric field of the conductor is referred to as a surrounded channel (s-channel) structure.
  • a channel can be formed in the entire oxide 230b (bulk).
  • the drain current of the transistor can be increased and a larger on-current can be obtained.
  • the entire region of the channel formation region formed in the oxide 230b can be depleted by the electric field of the conductor 260. Therefore, in the s-channel structure, the off-state current of the transistor can be further reduced. Note that by reducing the channel width, the effect of increasing the on-current, the effect of reducing the off-current, and the like due to the s-channel structure can be enhanced.
  • FIGS. 23A to 23C illustrate an example of a structure applicable to the transistor 200.
  • FIGS. FIG. 23A shows the top surface of the transistor 200. Note that some films are omitted in FIG. 23A for clarity.
  • 23B is a cross-sectional view corresponding to the alternate long and short dash line X1-X2 shown in FIG. 23A
  • FIG. 23C is a cross-sectional view corresponding to Y1-Y2.
  • a conductor functioning as a source or a drain has a stacked structure.
  • the conductor 240a and the conductor 240b are preferably formed using a conductor that has high adhesion to the oxide 230b, and the conductor 241a and the conductor 241b are preferably formed using a material having high conductivity.
  • the conductor 240a and the conductor 240b are preferably formed using an ALD method. By forming by ALD method or the like, the coverage can be improved.
  • the transistor 200 with high reliability and low power consumption can be provided.
  • the oxide 230b is surrounded by the conductor 205 and the conductor 260 in the channel width direction.
  • the insulator 222 has a convex portion, the side surface of the oxide 230 b can be covered with the conductor 260.
  • the dielectric constant of the insulator 222 is large, so that the equivalent SiO 2 film thickness (EOT: Equivalent Oxide Thickness) can be reduced. . Therefore, the distance between the conductor 205 and the oxide 230 can be increased by the physical thickness of the insulator 222 without weakening the influence of the electric field from the conductor 205 on the oxide 230. Therefore, the distance between the conductor 205 and the oxide 230 can be adjusted by the thickness of the insulator 222.
  • EOT Equivalent Oxide Thickness
  • the shape of the protrusion of the insulator 224 be adjusted so that the bottom surface of the conductor 260 is closer to the substrate side than the bottom surface of the oxide 230b on the side surface of the oxide 230b. That is, the transistor 200 has a structure in which the oxide 230 b can be electrically surrounded by the electric field of the conductor 260. In this manner, the structure of the transistor that electrically surrounds the oxide 230b by the electric field of the conductor is referred to as a surrounded channel (s-channel) structure. In the transistor 200 having an s-channel structure, a channel can be formed in the entire oxide 230b (bulk).
  • the drain current of the transistor can be increased and a larger on-current can be obtained. Further, the entire region of the channel formation region formed in the oxide 230b can be depleted by the electric field of the conductor 260. Therefore, in the s-channel structure, the off-state current of the transistor can be further reduced. Note that by reducing the channel width, the effect of increasing the on-current, the effect of reducing the off-current, and the like due to the s-channel structure can be enhanced.
  • FIG. 24A to 24C illustrate an example of a structure that can be applied to the transistor 200.
  • FIG. FIG. 24A shows the top surface of the transistor 200. Note that some films are omitted in FIG. 24A for clarity.
  • 24B is a cross-sectional view corresponding to the alternate long and short dash line X1-X2 shown in FIG. 24A
  • FIG. 24C is a cross-sectional view corresponding to Y1-Y2.
  • an oxide 230 c, an insulator 250, and a conductor 260 are formed in an opening formed in the insulator 280.
  • a transistor having a structure in which the arrangement of the conductive film functioning as a gate electrode is determined by self-alignment includes SA s-channel FET (Self Align S-channel FET), trench gate s-channel FET, and TGSA FET ( It can also be called Trench Gate Self Align FET.
  • SA s-channel FET Self Align S-channel FET
  • trench gate s-channel FET trench gate s-channel FET
  • TGSA FET It can also be called Trench Gate Self Align FET.
  • one end portion of the conductor 240a and the conductor 240b and the end portion of the opening formed in the insulator 280 coincide with each other.
  • the three ends of the conductors 240 a and 240 b coincide with part of the ends of the oxide 230. Therefore, the conductor 240a and the conductor 240b can be formed at the same time by providing an opening in the insulator 280 after the oxide 230 is formed. Therefore, masks and processes can be reduced. In addition, yield and productivity can be improved.
  • the conductor 240a, the conductor 240b, the oxide 230a, and the oxide 230b are in contact with the insulator 280 having an excess oxygen region through the oxide 230d. Therefore, the oxide 230d is interposed between the insulator 280 and the oxide 230b having a region where a channel is formed, so that impurities such as hydrogen, water, and halogen can be extracted from the insulator 280. It is possible to suppress diffusion to 230b.
  • the transistor 200 illustrated in FIGS. 24A to 24C has a structure in which the conductors 240a and 240b and the conductor 260 hardly overlap with each other, so that the parasitic capacitance applied to the conductor 260 can be reduced. That is, the transistor 200 having a high operating frequency can be provided.
  • FIGS. 25A to 25C illustrate examples of structures applicable to the transistor 200.
  • FIGS. FIG. 25A shows the top surface of the transistor 200. Note that some films are omitted in FIG. 25A for clarity.
  • 25B is a cross-sectional view corresponding to the alternate long and short dash line X1-X2 shown in FIG. 25A
  • FIG. 25C is a cross-sectional view corresponding to Y1-Y2.
  • An insulator 285 and an insulator 286 are formed over the insulator 282.
  • An oxide 230c, an insulator 250, and a conductor 260 are formed in openings formed in the insulator 280, the insulator 282, and the insulator 285.
  • one end portion of the conductor 240a and the conductor 240b and the end portion of the opening formed in the insulator 280 coincide with each other.
  • the three ends of the conductor 240a and the conductor 240b coincide with part of the ends of the oxide 230a and the oxide 230b. Therefore, the conductor 240a and the conductor 240b can be formed at the same time as the oxide 230a and the oxide 230b or the opening of the insulator 280. Therefore, masks and processes can be reduced. In addition, yield and productivity can be improved.
  • the conductor 240a, the conductor 240b, the oxide 230a, and the oxide 230b are in contact with the insulator 280 having an excess oxygen region through the oxide 230d. Therefore, the oxide 230d is interposed between the insulator 280 and the oxide 230b having a region where a channel is formed, so that impurities such as hydrogen, water, and halogen can be extracted from the insulator 280. It is possible to suppress diffusion to 230b.
  • 25A to 25C can increase the on-state current of the transistor 200 because a high-resistance offset region is not formed.
  • FIGS. 26A to 26C illustrate examples of structures applicable to the transistor 200.
  • FIGS. FIG. 26A shows the top surface of the transistor 200. Note that some films are omitted in FIG. 26A for clarity.
  • 26B is a cross-sectional view corresponding to the alternate long and short dash line X1-X2 shown in FIG. 26A
  • FIG. 26C is a cross-sectional view corresponding to Y1-Y2.
  • the transistor 200 illustrated in FIGS. 26A to 26C has a structure without the oxide 230d.
  • the oxide 230d is not necessarily provided. Therefore, masks and processes can be reduced. In addition, yield and productivity can be improved.
  • the insulator 224 may be provided only in a region overlapping with the oxide 230a and the oxide 230b. In this case, the oxide 230a, the oxide 230b, and the insulator 224 can be processed using the insulator 222 as an etching stopper. Therefore, yield and productivity can be increased.
  • the transistor 200 illustrated in FIGS. 26A to 26C has a structure in which the conductors 240a and 240b and the conductor 260 hardly overlap with each other, so that the parasitic capacitance applied to the conductor 260 can be reduced. That is, the transistor 200 having a high operating frequency can be provided.
  • ⁇ Transistor structure 8> 30A to 30C illustrate examples of structures applicable to the transistor 200.
  • FIG. 30A to 30C illustrate examples of structures applicable to the transistor 200.
  • the structure having the same function as the structure of the transistor 200 illustrated in FIGS. 20A to 20C is denoted by the same reference numeral.
  • a transistor 200 illustrated in FIG. 30A is a cross-sectional view of a channel-etched transistor having a bottom gate structure.
  • a transistor 200 illustrated in FIG. 30B is a cross-sectional view of a channel-protective transistor having a bottom-gate structure.
  • FIG. 30C is a cross-sectional view of a transistor having a top-gate structure.
  • the oxide 230 is a single layer, but may have a three-layer structure of the oxide 230a, the oxide 230b, and the oxide 230c. In any structure, the number of layers constituting the stacked structure is small. Therefore, the transistor 200 with high productivity can be provided.
  • the transistors illustrated in FIGS. 30A to 30C may each have a back gate.
  • the back gate can control the threshold value of the transistor.
  • the mobility of the transistor can be improved.
  • a cross-sectional structure of a transistor having a back gate is illustrated in FIGS. 34A to 34C.
  • a transistor 200 illustrated in FIG. 34A is a cross-sectional view of a channel-etched transistor having a bottom gate structure.
  • a transistor 200 illustrated in FIG. 34B is a cross-sectional view of a channel-protective transistor having a bottom-gate structure.
  • FIG. 34C is a cross-sectional view of a transistor having a top-gate structure.
  • Each of the transistors illustrated in any of the drawings includes a conductive film 248 that can function as a back gate.
  • the oxide 230 is a single layer, but a three-layer structure of the oxide 230a, the oxide 230b, and the oxide 230c may be used. In any structure, the number of layers constituting the stacked structure is small. Therefore, the transistor 200 with high productivity can be provided.
  • An imaging device and a semiconductor device including the imaging device can reproduce a recording medium such as a display device, a personal computer, and a recording medium (typically, a DVD: Digital Versatile Disc). , A device having a display capable of displaying the image).
  • a recording medium such as a display device, a personal computer, and a recording medium (typically, a DVD: Digital Versatile Disc).
  • an electronic device that can use the imaging device according to one embodiment of the present invention and the semiconductor device including the imaging device, a mobile phone, a portable game machine, a portable data terminal, an electronic book, a video camera, a digital Still cameras and other cameras, goggle type displays (head-mounted displays), navigation systems, sound playback devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, multifunction printers, automatic teller machines (ATMs) And vending machines.
  • FIGS. 27A to 27F Specific examples of these electronic devices are illustrated in FIGS. 27A to 27F.
  • FIG. 27A illustrates a portable game machine, which includes a housing 901, a housing 902, a display portion 903, a display portion 904, a microphone 905, speakers 906, operation keys 907, a stylus 908, a camera 909, and the like. Note that although the portable game machine illustrated in FIG. 27A includes two display portions 903 and 904, the number of display portions included in the portable game device is not limited thereto.
  • the imaging device of one embodiment of the present invention can be used for the camera 909.
  • FIG. 27B illustrates a portable data terminal, which includes a first housing 911, a display portion 912, a camera 919, and the like. Information can be input and output by a touch panel function of the display portion 912.
  • the imaging device of one embodiment of the present invention can be used for the camera 919.
  • FIG. 27C illustrates a digital camera, which includes a housing 921, a shutter button 922, a microphone 923, a light emitting unit 927, a lens 925, and the like.
  • the imaging device of one embodiment of the present invention can be provided at a position where the lens 925 becomes a focal point.
  • FIG. 27D illustrates a wristwatch-type information terminal, which includes a housing 931, a display portion 932, a wristband 933, a camera 939, and the like.
  • the display unit 932 may be a touch panel.
  • the imaging device of one embodiment of the present invention can be used for the camera 939.
  • FIG. 27E illustrates a video camera, which includes a first housing 941, a second housing 942, a display portion 943, operation keys 944, a lens 945, a connection portion 946, and the like.
  • the operation key 944 and the lens 945 are provided in the first housing 941, and the display portion 943 is provided in the second housing 942.
  • the first housing 941 and the second housing 942 are connected by a connection portion 946, and the angle between the first housing 941 and the second housing 942 can be changed by the connection portion 946. is there.
  • the video on the display portion 943 may be switched according to the angle between the first housing 941 and the second housing 942 in the connection portion 946.
  • the imaging device of one embodiment of the present invention can be provided at a position where the lens 945 is focused.
  • FIG. 27F illustrates a mobile phone which includes a housing 951, a display portion 952, a microphone 957, a speaker 954, a camera 959, an input / output terminal 956, an operation button 955, and the like.
  • the imaging device of one embodiment of the present invention can be used for the camera 959.
  • FIG. 31A shows a top view of the substrate 711 before the dicing process is performed.
  • a semiconductor substrate also referred to as a “semiconductor wafer”
  • a plurality of circuit regions 712 are provided on the substrate 711.
  • a transistor according to one embodiment of the present invention a CPU, an RF tag, an imaging device, or the like can be provided.
  • Each of the plurality of circuit regions 712 is surrounded by the isolation region 713.
  • a separation line (also referred to as “dicing line”) 714 is set at a position overlapping with the separation region 713. By cutting the substrate 711 along the separation line 714, the chip 715 including the circuit region 712 can be cut out from the substrate 711.
  • FIG. 31B shows an enlarged view of the chip 715.
  • a conductive layer or a semiconductor layer may be provided in the separation region 713.
  • ESD that can occur in the dicing process can be reduced, and a reduction in yield due to the dicing process can be prevented.
  • the dicing step is performed while supplying pure water having a specific resistance lowered by dissolving carbon dioxide gas or the like for the purpose of cooling the substrate, removing shavings, and preventing charging.
  • the amount of pure water used can be reduced.
  • the productivity of the semiconductor device can be increased.
  • FIGS. 32A and 32B An example of an electronic component using the chip 715 will be described with reference to FIGS. 32A and 32B.
  • the electronic component is also referred to as a semiconductor package or an IC package.
  • Electronic components are completed by combining the semiconductor device described in the above embodiment and components other than the semiconductor device in an assembly process (post-process).
  • a “back surface grinding step” of grinding the back surface (the surface where the semiconductor device or the like is not formed) of the substrate 711 is performed (step S721). .
  • the electronic component can be downsized.
  • a “dicing process” for separating the substrate 711 into a plurality of chips 715 is performed (step S722).
  • a “die bonding step” is performed in which the separated chip 715 is bonded onto each lead frame (step S723).
  • a suitable method is appropriately selected according to the product, such as bonding with a resin or bonding with a tape. Note that a chip may be bonded on the interposer instead of the lead frame.
  • a “wire bonding process” is performed in which the lead of the lead frame and the electrode on the chip are electrically connected by a thin metal wire (wire) (step S724).
  • a silver wire or a gold wire can be used as the metal thin wire.
  • ball bonding or wedge bonding can be used.
  • the wire-bonded chip is subjected to a “sealing process (molding process)” that is sealed with an epoxy resin or the like (step S725).
  • a sealing process molding process
  • the inside of the electronic component is filled with resin, and the circuit part built in the chip and the wire connecting the chip and the lead can be protected from mechanical external force, and characteristics due to moisture and dust Degradation (decrease in reliability) can be reduced.
  • a “lead plating process” for plating the leads of the lead frame is performed (step S726).
  • the plating process prevents rusting of the lead, and soldering when mounted on a printed circuit board later can be performed more reliably.
  • a “shaping step” for cutting and shaping the lead is performed (step S727).
  • a “marking process” is performed in which a printing process (marking) is performed on the surface of the package (step S728).
  • An electronic component is completed through an “inspection process” (step S729) for checking the appearance shape and the presence or absence of malfunction.
  • FIG. 32B shows a schematic perspective view of the completed electronic component.
  • FIG. 32B shows a schematic perspective view of a QFP (Quad Flat Package) as an example of an electronic component.
  • An electronic component 750 shown in FIG. 32B shows a lead 755 and a chip 715.
  • the electronic component 750 may have a plurality of chips 715.
  • An electronic component 750 illustrated in FIG. 32B is mounted on, for example, a printed circuit board 752.
  • a plurality of such electronic components 750 are combined and each is electrically connected on the printed circuit board 752 to complete a substrate (mounting substrate 754) on which the electronic components are mounted.
  • the completed mounting board 754 is used for an electronic device or the like.
  • a metal oxide film including two types of crystal parts is used for the oxide semiconductor included in the transistor of one embodiment of the present invention.
  • One of the crystal parts also referred to as the first crystal part
  • has orientation in the thickness direction of the film also referred to as a film surface direction, a film formation surface, or a direction perpendicular to the film surface
  • c It is a crystal part having axial orientation.
  • Another of the crystal parts (also referred to as a second crystal part) is a crystal part that does not have c-axis orientation and is oriented in various directions.
  • the metal oxide film used for the oxide semiconductor included in the transistor of one embodiment of the present invention includes such two kinds of crystal parts.
  • the crystal part having c-axis orientation is described separately from the first crystal part, and the crystal part not having c-axis orientation is described separately from the second crystal part.
  • these may not be distinguished because there is no difference in crystallinity and crystal size. That is, the metal oxide film used for the oxide semiconductor included in the transistor of one embodiment of the present invention can be expressed without distinction.
  • the metal oxide film has a plurality of crystal parts, and at least one of the crystal parts in the film may have c-axis orientation. Further, among the crystal parts present in the film, the ratio of the crystal parts not having c-axis orientation may be larger than the ratio of the crystal parts having c-axis orientation.
  • the metal oxide film a plurality of crystal parts are observed in an observation image by a transmission electron microscope in a cross section in the film thickness direction, and the c-axis orientation is not included in the plurality of crystal parts. There are cases where more second crystal parts are observed than the first crystal parts having c-axis orientation. In other words, the metal oxide film has a large proportion of the second crystal part having no c-axis orientation.
  • the second crystal part having no c-axis orientation can serve as an oxygen diffusion path. Therefore, when there is a sufficient oxygen supply source in the vicinity of the metal oxide film, oxygen is supplied to the first crystal part having c-axis orientation through the second crystal part having no c-axis orientation. Can be supplied. Therefore, the amount of oxygen vacancies in the metal oxide film can be reduced. By applying such a metal oxide film to a semiconductor film of a transistor, high reliability and high field effect mobility can be obtained. In this way, the second crystal part having no c-axis orientation serves as an oxygen diffusion path, and oxygen can be supplied to the first crystal part having the c-axis orientation.
  • a metal oxide film including a first crystal part having a second crystal part and a second crystal part having no c-axis orientation is referred to as an oxygen-deficient metal oxide film or an oxygen-deficient oxide semiconductor film. There is a case.
  • a specific crystal plane has orientation with respect to the thickness direction of the film. Therefore, when X-ray diffraction (XRD) measurement is performed on the metal oxide film including the first crystal part in a direction substantially perpendicular to the upper surface of the film, the first diffraction crystal is obtained at a predetermined diffraction angle (2 ⁇ ). A diffraction peak derived from the crystal part 1 is confirmed. On the other hand, even if the metal oxide film has the first crystal part, a diffraction peak may not be sufficiently confirmed due to scattering of X-rays by the support substrate or an increase in background. Note that the height (intensity) of the diffraction peak increases in accordance with the presence ratio of the first crystal portion included in the metal oxide film, and can be an index for estimating the crystallinity of the metal oxide film.
  • XRD X-ray diffraction
  • electron diffraction can be given. For example, when an electron beam diffraction measurement is performed on a cross section and an electron beam diffraction pattern of the metal oxide film is observed, the first region having a diffraction spot due to the first crystal part and the second crystal part are observed. A second region having the resulting diffraction spot is observed.
  • the first region having a diffraction spot due to the first crystal part is derived from the crystal part having c-axis orientation.
  • the second region having a diffraction spot due to the second crystal part is derived from a crystal part having no orientation or a crystal part that is disorderly oriented in any direction. Therefore, different patterns may be observed depending on the beam diameter of the electron beam used for electron beam diffraction, that is, the area of the region to be observed.
  • electron beam diffraction in which the beam diameter of an electron beam is measured from 1 nm ⁇ to 100 nm ⁇ is referred to as nano beam electron diffraction (NBED: Nano Beam Electron Diffraction).
  • the crystallinity of the metal oxide film may be evaluated by a method different from that of NBED.
  • Examples of the method for evaluating the crystallinity of the metal oxide film include electron diffraction, X-ray diffraction, and neutron diffraction.
  • electron diffractions in addition to the NBED shown above, transmission electron microscope (TEM: Transmission Electron Microscopy), scanning electron microscope (SEM: Scanning Electron Microscopy), convergent electron diffraction (CBED: Convergent Electron Limit) Field electron diffraction (SAED: Selected Area Electron Diffraction) or the like can be suitably used.
  • a ring-shaped pattern is observed in the nanobeam electron diffraction pattern under the condition that the beam diameter of the electron beam is increased (for example, 25 nm ⁇ to 100 nm ⁇ or 50 nm ⁇ to 100 nm ⁇ ).
  • the ring-shaped pattern may have a luminance distribution in the radial direction.
  • in NBED in an electron beam diffraction pattern under a condition that the beam diameter of the electron beam is sufficiently small (for example, 1 nm ⁇ to 10 nm ⁇ ), distribution is performed in the circumferential direction (also referred to as ⁇ direction) at the position of the ring-shaped pattern. Multiple spots may be observed. That is, a ring-shaped pattern that can be seen under the condition that the beam diameter of the electron beam is increased is formed by an aggregate of the plurality of spots.
  • Sample A1 is a sample in which a metal oxide film having a thickness of about 100 nm is formed on a glass substrate.
  • the metal oxide film includes indium, gallium, and zinc.
  • the ratio of the oxygen flow rate to the total gas flow rate described above may be referred to as an oxygen flow rate ratio. Note that the oxygen flow rate ratio in the production conditions of the sample A1 is 30%.
  • Sample A2 is a sample in which a metal oxide film having a thickness of about 100 nm is formed on a glass substrate.
  • the substrate was heated to 130 ° C., and argon gas having a flow rate of 180 sccm and oxygen gas having a flow rate of 20 sccm were introduced into the chamber of the sputtering apparatus.
  • the oxygen flow rate ratio under the production conditions of sample A2 is 10%.
  • the conditions other than the substrate temperature and the oxygen flow rate ratio were the same as those of the sample A1 described above.
  • Sample A3 is a sample in which a metal oxide film having a thickness of about 100 nm is formed on a glass substrate.
  • the substrate was set to room temperature (RT), and argon gas having a flow rate of 180 sccm and oxygen gas having a flow rate of 20 sccm were introduced into the chamber of the sputtering apparatus.
  • the oxygen flow rate ratio under the production conditions of sample A3 is 10%.
  • the conditions other than the substrate temperature and the oxygen flow rate ratio were the same as those of the sample A1 described above.
  • Table 1 shows conditions for preparing Samples A1 to A3.
  • FIGS. 35A to 35C, FIGS. 36A to 36C, and FIGS. 37A to 37C show cross-sectional TEM observation results of samples A1 to A3.
  • 35A and 35B are cross-sectional TEM images of the sample A1
  • FIGS. 36A and 36B are cross-sectional TEM images of the sample A2
  • FIGS. 37A and 37B are cross-sectional TEM images of the sample A3.
  • 35C is a high-resolution transmission electron microscope (HR-TEM) image of the cross section of the sample A1
  • FIG. 36C is a cross-sectional HR-TEM image of the sample A2
  • FIG. 37C is the sample A3. It is a cross-sectional HR-TEM image.
  • a spherical aberration correction function may be used for observation of the cross-sectional HR-TEM image.
  • a high-resolution TEM image using the spherical aberration correction function is particularly referred to as a Cs-corrected high-resolution TEM image.
  • the Cs-corrected high resolution TEM image can be observed, for example, with an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.
  • FIG. 38A shows the XRD measurement result of sample A1
  • FIG. 39A shows the XRD measurement result of sample A2
  • FIG. 40A shows the XRD measurement result of sample A3.
  • a powder method (also referred to as a ⁇ -2 ⁇ method) which is a kind of out-of-plane method was used.
  • the ⁇ -2 ⁇ method is a method of measuring the X-ray diffraction intensity by changing the incident angle of the X-ray and setting the angle of the detector provided facing the X-ray source to be the same as the incident angle.
  • GIXRD Gram-Incidence XRD
  • GIXRD is a kind of out-of-plane method in which X-rays are incident from the film surface at an angle of about 0.40 ° and the X-ray diffraction intensity is measured by changing the angle of the detector.
  • Method also referred to as a thin film method or a Seemann-Bohlin method
  • 38A, 39A, and 40A the vertical axis indicates the diffraction intensity in arbitrary units, and the horizontal axis indicates the angle 2 ⁇ .
  • the thickness of the sample in the depth direction is, for example, 10 nm to 100 nm, typically 10 nm to 50 nm.
  • FIGS. 38B and 38C show the electron diffraction pattern of the sample A1
  • FIGS. 39B and 39C show the electron diffraction pattern of the sample A2
  • FIGS. 40B and 40C show the electron diffraction pattern of the sample A3, respectively.
  • the electron beam diffraction patterns shown in FIGS. 38B and 38C, FIGS. 39B and 39C, and FIGS. 40B and 40C are image data in which the contrast is adjusted so that the electron beam diffraction patterns are clear.
  • the brightest bright spot at the center is due to the incident electron beam, and the center of the electron diffraction pattern (both direct spot or transmitted wave). Say).
  • FIG. 38B when the beam diameter of the incident electron beam is 1 nm ⁇ , a plurality of spots distributed circumferentially are seen, so that the metal oxide film is extremely minute and has a plane orientation. It can be seen that a plurality of crystal parts oriented in all directions are mixed.
  • FIG. 38C when the beam diameter of the incident electron beam is 100 nm ⁇ , the diffraction spots from the plurality of crystal parts are connected, and the luminance is averaged to form a ring-shaped diffraction pattern. I can confirm. In FIG. 38C, two ring-shaped diffraction patterns having different radii can be observed.
  • the first ring and the second ring are referred to from the diffraction pattern having a small diameter. It can be confirmed that the brightness of the first ring is higher than that of the second ring. In addition, two spots (first areas) with high luminance are confirmed at positions overlapping the first ring.
  • the radial distance from the center of the first ring substantially coincides with the radial distance from the center of the diffraction spot on the (009) plane in the structural model of single crystal InGaZnO 4 . Further, the first region is a diffraction spot due to the c-axis orientation.
  • c-axis orientation which is oriented in any direction is included in the metal oxide film. It can also be said that there is a crystal part or a second crystal part).
  • the two first regions are symmetrically arranged with respect to the center point of the electron beam diffraction pattern and have the same brightness, so that it is assumed that the two first regions have a two-fold symmetry.
  • the direction of the straight line connecting the two first regions and the center is the direction of the c-axis of the crystal part. Match.
  • the vertical direction is the film thickness direction, it can be seen that there is a crystal part in which the c-axis is oriented in the film thickness direction in the metal oxide film.
  • the metal oxide film of the sample A1 is a film in which a crystal part having c-axis orientation and a crystal part not having c-axis orientation are mixed.
  • the electron diffraction patterns shown in FIGS. 39B and 39C and FIGS. 40B and 40C are almost the same as the electron diffraction patterns shown in FIGS. 38B and 38C.
  • the brightness of the two spots (first region) due to the c-axis orientation is the brightest in the sample A1, darker in the order of the sample A2 and the sample A3, and the proportion of crystal parts having c-axis orientation.
  • sample A1 is the highest, and decreases in the order of sample A2 and sample A3.
  • FIG. 41A is an electron beam diffraction pattern measured with a beam diameter of 100 nm with respect to a metal oxide film having a thickness of 100 nm
  • FIG. 41B is a diagram in which contrast is adjusted for the electron beam diffraction pattern shown in FIG. It is the electron beam diffraction pattern obtained by (1).
  • first regions two clear spots
  • These two spots (first regions) are caused by diffraction spots corresponding to the (001) plane in the structural model of InGaZnO 4 , that is, crystal parts having c-axis orientation.
  • a ring-like pattern (second region) with low luminance appears to overlap with the first region approximately concentrically. This is because the spot due to the structure of the crystal part (second crystal part) having no c-axis orientation is averaged and formed into a ring shape by setting the electron beam diameter to 100 nm.
  • the crystallinity of the metal oxide film can be quantified by acquiring and comparing the line profile including the first region and the line profile including the second region.
  • FIG. 42 shows a region AA ′, a region BB ′, and a region CC ′ in a simulation pattern of electron beam diffraction obtained when the (100) plane of the structural model of InGaZnO 4 is irradiated with an electron beam. It is the figure which attached the auxiliary line of.
  • Region A-A ′ shown in FIG. 42 includes a straight line passing through two diffraction spots caused by the first crystal part having c-axis orientation and a direct spot.
  • the region BB ′ and the region CC ′ illustrated in FIG. 42 each include a straight line passing through a region where a diffraction spot due to the first crystal part having c-axis orientation is not observed and a direct spot.
  • the angle at which the region AA ′ and the region BB ′ or the region CC ′ intersect is around 34 °, specifically, 30 ° to 38 °, preferably 32 ° to 36 °, More preferably, the angle may be not less than 33 ° and not more than 35 °.
  • FIG. 43 shows an image diagram of a line profile for each structure, a relative luminance R, and a diagram explaining a half width of a spectrum (FWHM: Full Width at Half Maximum) resulting from the c-axis orientation obtained from the electron diffraction pattern. .
  • the relative luminance R shown in FIG. 43 is a value obtained by dividing the integral intensity of luminance in the area AA ′ by the integral intensity of luminance in the area BB ′ or the integral intensity of luminance in the area CC ′. is there.
  • the integrated intensity of luminance in the areas AA ′, BB ′, and CC ′ is obtained by removing the direct spot appearing at the center position and the background caused by the direct spot. It is.
  • the strength of the c-axis orientation can be defined quantitatively. For example, as shown in FIG. 43, in the single crystal metal oxide film, the peak intensity of the diffraction spot due to the first crystal part having the c-axis orientation in the region AA ′ is high, and the region BB Since the diffraction spot due to the first crystal part having the c-axis orientation is not seen in 'and the region CC', the relative luminance R exceeds 1 and becomes extremely large.
  • the relative luminance R is highest in the single crystal metal oxide film, and decreases in the order of CAAC + nanocrystal, nanocrystal, and amorphous metal oxide film only in CAAC (details of CAAC will be described later).
  • the relative luminance R is 1 in a nanocrystal that does not have a specific orientation and an amorphous metal oxide film.
  • the full width at half maximum of the single-crystal metal oxide film is the smallest, the full width at half maximum increases in the order of CAAC only, CAAC + nanocrystal, and nanocrystal metal oxide film.
  • the intensity ratio of the integrated intensity of the luminance in the first region to the integrated intensity of the luminance in the second region is important information in estimating the existence ratio of the crystal part having orientation.
  • FIGS. 44A1 and 44A2 show the analysis results using the line profile of the sample A1
  • FIGS. 44B1 and 44B2 show the analysis results using the line profile of the sample A2
  • FIGS. 45A1 and 45A2 show the analysis results using the line profile of the sample A3. , Respectively.
  • FIG. 44A1 is an electron beam diffraction pattern in which the region AA ′, the region BB ′, and the region CC ′ are described in the electron beam diffraction pattern illustrated in FIG. 38C.
  • FIG. 44B1 is illustrated in FIG. 45A1 is an electron beam diffraction pattern in which a region AA ′, a region BB ′, and a region CC ′ are described in the electron beam diffraction pattern shown, and FIG. 45A1 shows the region A ⁇ in the electron beam diffraction pattern shown in FIG. It is the electron beam diffraction pattern which described A ', area
  • region A-A ′, the region B-B ′, and the region C-C ′ can be obtained by normalizing with the brightness of the direct spot appearing at the center position of the electron beam diffraction pattern. This also allows a relative comparison between the samples.
  • the background luminance may be calculated by linear approximation. For example, a region located on the lower luminance side than a straight line drawn along the skirts on both sides of the target peak can be subtracted as the background.
  • the integrated intensity of luminance in the region A-A ′, the region B-B ′, and the region C-C ′ was calculated from the data obtained by subtracting the background by the above-described method.
  • a value obtained by dividing the integrated luminance intensity in the region A-A ′ by the integrated luminance intensity in the region B-B ′ or the integrated luminance intensity in the region C-C ′ was obtained as the relative luminance R.
  • FIG. 46 shows the relative luminance R of the samples A1 to A3.
  • the integrated intensity of the luminance in the region AA ′ is the luminance in the region BB ′ at the peaks located on the left and right of the direct spot in the luminance profiles shown in FIGS. 44A2, 44B2, and 45A2.
  • the relative luminance R of the samples A1 to A3 is as shown below.
  • -Relative luminance R of sample A1 25.00
  • -Relative luminance R of the sample A2 3.04
  • -Relative luminance R of sample A3 1.05
  • the relative luminance R described above is an average value at four positions. As described above, the relative luminance R is highest in the sample A1, and decreases in the order of the sample A2 and the sample A3.
  • the relative luminance R is more than 1 and 40 or less, preferably more than 1 and 10 or less, more preferably It is preferable to use a metal oxide film that exceeds 1 and is 3 or less.
  • Presence ratio of crystal part The existence ratio of the crystal part in the metal oxide film can be estimated by analyzing the cross-sectional TEM image.
  • a two-dimensional fast Fourier transform (FFT: Fast Fourier Transform) process is performed on a TEM image captured at a high resolution to obtain an FFT image.
  • FFT Fast Fourier Transform
  • the obtained FFT image is subjected to a mask process that leaves a range having periodicity and removes the rest.
  • the masked FFT image is then subjected to a two-dimensional inverse Fourier transform (IFFT: Inverse Fast Fourier Transform) to obtain an FFT filtered image.
  • IFFT Inverse Fast Fourier Transform
  • the existence ratio of the crystal part can be estimated from the ratio of the area of the remaining image. Further, by subtracting the area of the remaining image from the area of the region used for the calculation (also referred to as the area of the original image), it is possible to estimate the existence ratio of the portion other than the crystal part.
  • FIG. 47A shows a cross-sectional TEM image of sample A1
  • FIG. 47B shows an image obtained after image analysis of the cross-sectional TEM image of sample A1.
  • FIG. 48A shows a cross-sectional TEM image of sample A2
  • FIG. 48B shows an image obtained after image analysis of the cross-sectional TEM image of sample A2.
  • FIG. 49A shows a cross-sectional TEM image of sample A3, and FIG. 49B shows an image obtained after image analysis of the cross-sectional TEM image of sample A3.
  • the white area in the metal oxide film corresponds to the area including the crystal part having orientation, and the black area does not have orientation. This corresponds to a crystal part or a region including a crystal part oriented in various directions.
  • the ratio of the portion excluding the region including the crystal portion having orientation in the sample A1 was about 43.1%. Further, from the result shown in FIG. 48B, the ratio of the portion excluding the region including the crystal part having orientation in the sample A2 is about 61.7%. From the result shown in FIG. 49B, the ratio of the portion excluding the region including the crystal part having orientation in the sample A3 was about 89.5%.
  • the metal oxide film is a film having extremely high crystallinity. It is preferable because oxygen vacancies are difficult to make and electrical characteristics are very stable.
  • the ratio of the portion excluding the crystal part having orientation in the metal oxide film is 40% or more and less than 100%, preferably 60% or more and 90% or less, the metal oxide film has orientation.
  • the crystal part which has and the crystal part which does not have orientation coexist in a moderate ratio, and it can make electrical characteristics stable and high mobility compatible.
  • LGBR Lateral Growth Buffer Region
  • samples B1 to B3 were produced.
  • a metal oxide film having a thickness of about 50 nm was formed on a glass substrate by a method similar to that of the sample A1 described above. Subsequently, a silicon oxynitride film having a thickness of about 30 nm, a silicon oxynitride film having a thickness of about 100 nm, and a silicon oxynitride film having a thickness of about 20 nm are stacked over the metal oxide film by a plasma CVD method.
  • a metal oxide film may be described as OS and a silicon oxynitride film may be described as GI.
  • an In—Sn—Si oxide film having a thickness of 5 nm was formed by a sputtering method.
  • oxygen addition treatment was performed on the silicon oxynitride film.
  • oxygen addition conditions using an ashing apparatus, a substrate temperature of 40 ° C., and an oxygen gas (16 O) of the flow rate 150 sccm, and a flow rate 100sccm oxygen gas (18 O) is introduced into the chamber, 15 Pa pressure Then, RF power of 4500 W was supplied for 600 seconds between parallel plate electrodes installed in the ashing device so that a bias was applied to the substrate side. Note that oxygen gas ( 16 O) was contained in the silicon oxynitride film at a main component level, and thus oxygen gas ( 18 O) was used to accurately measure the oxygen added by the oxygen addition treatment. .
  • a silicon nitride film having a thickness of about 100 nm was formed by a plasma CVD method.
  • Sample B2 is a sample manufactured by changing the film formation conditions of the metal oxide film from Sample B1.
  • a metal oxide film having a thickness of about 50 nm was formed by a method similar to that for Sample A2 described above.
  • Sample B3 is a sample manufactured by making the film formation conditions of the metal oxide film different from those of Sample B1.
  • a metal oxide film with a thickness of about 50 nm was formed by a method similar to that for Sample A3 described above.
  • Samples B1 to B3 were manufactured through the above steps.
  • SIMS analysis For samples B1 to B3, the concentration of 18 O was measured by SIMS (Secondary Ion Mass Spectrometry) analysis. Note that in SIMS analysis, the above-prepared samples B1 to B3 were not subjected to heat treatment, the samples B1 to B3 were subjected to heat treatment at 350 ° C. for 1 hour in a nitrogen atmosphere, and the samples B1 to B3 were subjected to nitrogen atmosphere. Under these conditions, the following three conditions were set: 450 ° C. and 1 hour heat treatment.
  • 50A to 50C show SIMS measurement results.
  • 50A to 50C show analysis results of a region including GI and OS.
  • 50A to 50C show the results of analysis from the substrate side (also referred to as SSDP (Substrate Side Depth Profile) -SIMS).
  • substrate side also referred to as SSDP (Substrate Side Depth Profile) -SIMS.
  • the gray broken line is a profile under conditions where heat treatment is not performed
  • the black broken line is a profile under conditions where heat treatment is performed at 350 ° C.
  • the black solid line is subjected to heat treatment at 450 ° C. It is a profile of the condition.
  • a metal oxide film in which a crystal part having orientation and a crystal part not having orientation are mixed and the ratio of the crystal part having orientation is low is a film that easily transmits oxygen, in other words, It can be confirmed that the film easily diffuses oxygen. Moreover, it can be confirmed that oxygen in the GI film diffuses into the OS by performing heat treatment at 350 ° C. and 450 ° C.
  • LGBR regions other than crystal parts
  • LGBR cross-sectional observation image
  • oxygen released from the oxide film diffuses in the thickness direction of the metal oxide film due to LGBR. Then, oxygen can be supplied from the lateral direction to the crystal part having orientation through the LGBR. Thereby, oxygen is sufficiently distributed to the crystal part having the orientation of the metal oxide film and other regions, and oxygen vacancies in the film can be effectively reduced.
  • the side surface of the crystal part having orientation Active oxygen (atomic oxygen) is bound to.
  • a metal such as In, M, or Zn is bonded to the bonded active oxygen.
  • the active oxygen and a metal such as In, M, or Zn are repeatedly bonded to each other so that solid phase growth occurs laterally from the side surface of the crystal part having orientation. Lateral growth of crystal parts having such orientation can also be called self-organization.
  • a hydrogen atom that is not bonded to a metal atom is present in the metal oxide film, this may be bonded to an oxygen atom to form OH and be fixed. Therefore, the oxygen deficiency of the metal oxide film by depositing a low temperature fixed amount state where hydrogen atoms are trapped (referred to as V O H) to (V O) (for example, about 1 ⁇ 10 17 cm -3) By forming, OH is suppressed from being formed.
  • V O H generates carriers, a certain amount of carriers are present in the metal oxide film. Thereby, a metal oxide film with an increased carrier density can be formed.
  • oxygen vacancies are simultaneously formed during film formation, but the oxygen vacancies can be reduced by introducing oxygen through LGBR as described above. By such a method, a metal oxide film having a relatively high carrier density and sufficiently reduced oxygen vacancies can be formed.
  • the region other than the crystal part having orientation forms a very fine crystal part having no orientation during film formation, no clear crystal grain boundary is observed in the metal oxide film.
  • the extremely fine crystal part is located between a plurality of crystal parts having orientation.
  • the fine crystal part grows in the lateral direction by heat at the time of film formation, and is bonded to an adjacent crystal part having orientation.
  • the fine crystal part also functions as a region for generating carriers. Accordingly, it is considered that the field-effect mobility of the metal oxide film having such a structure can be remarkably improved by being applied to a transistor.
  • oxygen permeability is improved by using a metal oxide film formed under conditions of a low temperature and a low oxygen flow rate. For this reason, for example, an increase in the amount of oxygen diffused during the manufacturing process of the transistor may reduce defects such as oxygen vacancies in the metal oxide film and at the interface between the metal oxide film and the insulating film. Guessed. It is suggested that the on-state current of the transistor is remarkably increased as a result of reducing the defect level density by such an effect.
  • the transistor with improved on-state current can be suitably used for a switch that can charge and discharge a capacitor at high speed.
  • it can be suitably used for a demultiplexer circuit or the like.
  • etching treatment in an oxygen atmosphere after forming a metal oxide film and forming an oxide insulating film such as a silicon oxide film thereon.
  • Such treatment can reduce the hydrogen concentration in addition to supplying oxygen into the film.
  • fluorine remaining in the chamber may be doped into the metal oxide film at the same time. Fluorine exists as a negatively charged fluorine atom, and is combined with a positively charged hydrogen atom by Coulomb force to generate HF. HF is released out of the metal oxide film during the plasma treatment, and as a result, the hydrogen concentration in the metal oxide film can be reduced.
  • oxygen atoms and hydrogen may be combined and released as H 2 O out of the film.
  • a structure in which a silicon oxide film (or silicon oxynitride film) is stacked on a metal oxide film is considered. Since fluorine in the silicon oxide film is bonded to hydrogen in the film and can exist as electrically neutral HF, it does not affect the electrical characteristics of the metal oxide film. In addition, although Si-F bond may arise, this also becomes electrically neutral. Further, it is considered that HF in the silicon oxide film does not affect oxygen diffusion.
  • Samples C1 to C3 are transistors having a channel length L of 6 ⁇ m and a channel width W of 50 ⁇ m.
  • a titanium film with a thickness of 10 nm and a copper film with a thickness of 100 nm were formed on a glass substrate using a sputtering apparatus. Subsequently, the conductive film was processed by a photolithography method.
  • insulating films were stacked over the substrate and the conductive film.
  • the insulating film was continuously formed in a vacuum using a plasma enhanced chemical vapor deposition (PECVD) apparatus.
  • PECVD plasma enhanced chemical vapor deposition
  • a silicon nitride film with a thickness of 50 nm, a silicon nitride film with a thickness of 300 nm, a silicon nitride film with a thickness of 50 nm, and a silicon oxynitride film with a thickness of 50 nm were used from the bottom.
  • an oxide semiconductor film was formed over the insulating film, and the oxide semiconductor film was processed into an island shape, whereby a semiconductor layer was formed.
  • an oxide semiconductor film with a thickness of 40 nm was formed.
  • an insulating film was formed over the insulating film and the semiconductor layer.
  • a 150 nm thick silicon oxynitride film was formed using a PECVD apparatus.
  • heat treatment was performed.
  • heat treatment was performed at 350 ° C. for 1 hour in a mixed gas atmosphere of nitrogen and oxygen.
  • an opening was formed in a desired region of the insulating film.
  • a dry etching method was used as a method for forming the opening.
  • a conductive film was formed over the insulating film so as to cover the opening, and the conductive film was processed to form an island-shaped conductive film. Further, after the island-shaped conductive film was formed, the island-shaped insulating film was formed by processing the insulating film in contact with the lower side of the conductive film.
  • an oxide semiconductor film having a thickness of 10 nm, a titanium nitride film having a thickness of 50 nm, and a copper film having a thickness of 100 nm were sequentially formed.
  • the titanium nitride film and the copper film were formed using a sputtering apparatus.
  • plasma treatment was performed over the oxide semiconductor film, the insulating film, and the conductive film.
  • the plasma treatment was performed using a PECVD apparatus at a substrate temperature of 220 ° C. in a mixed gas atmosphere of argon gas and nitrogen gas.
  • an insulating film was formed over the oxide semiconductor film, the insulating film, and the conductive film.
  • a silicon nitride film with a thickness of 100 nm and a silicon oxynitride film with a thickness of 300 nm were stacked using a PECVD apparatus.
  • a mask was formed over the formed insulating film, and an opening was formed in the insulating film using the mask.
  • a conductive film was formed so as to fill the opening, and the conductive film was processed into an island shape, so that a conductive film to be a source electrode and a drain electrode was formed.
  • a titanium film with a thickness of 10 nm and a copper film with a thickness of 100 nm were formed using a sputtering apparatus, respectively.
  • an insulating film was formed over the insulating film and the conductive film.
  • an acrylic photosensitive resin film having a thickness of 1.5 ⁇ m was used as the insulating film.
  • the shallow defect level of metal oxide (hereinafter also referred to as sDOS) can be estimated from the electrical characteristics of a transistor using the metal oxide film as a semiconductor film.
  • the following evaluates the density of interface state of the transistor, in addition to the density of the interface states, when considering the number of electrons N trap trapped in interface states, a method for predicting the subthreshold leakage current .
  • the number of electrons trapped in the interface state N trap is, for example, a comparison between the measured value of the drain current-gate voltage (Id-Vg) characteristic of the transistor and the calculated value of the drain current-gate voltage (Id-Vg) characteristic. By doing so, it can be evaluated.
  • the source voltage Vs 0 V
  • the change of the drain current Id with respect to the gate voltage Vg becomes gentle. This is presumably because electrons were trapped in a shallow interface state located near the energy (denoted Ec) at the bottom of the conduction band.
  • the density N it of the interface state is estimated more strictly by considering the number of traps N trap (per unit area and unit energy) trapped in the shallow interface state. Can do.
  • FIG. A broken line shows an ideal Id-Vg characteristic without a trap level obtained by calculation.
  • the solid line indicates the actually measured Id-Vg characteristic.
  • the change in the gate voltage Vg when the drain current changes from Id1 to Id2 is represented by ⁇ V ex . Drain current Id1, the potentials at the target to the interface when the Id2 phi it1, and phi it2, to the change amount of [Delta] [phi it.
  • C tg is the combined capacitance of the insulator and semiconductor per area.
  • ⁇ Q trap can also be expressed by Equation (2) using the trapped number of electrons N trap (per unit area, unit energy). Note that q is an elementary electric quantity.
  • Formula (3) can be obtained by combining Formula (1) and Formula (2).
  • formula (4) can be obtained by taking the limit ⁇ it ⁇ 0 of formula (3).
  • the number of trapped electrons N trap at the interface can be estimated using the ideal Id-Vg characteristic, the actually measured Id-Vg characteristic, and Equation (4). Note that the relationship between the drain current and the potential at the interface can be obtained by the above-described calculation.
  • Equation (5) the unit area, the density N it the number of electrons N trap and interface state per unit energy are related as Equation (5).
  • f (E) is a Fermi distribution function.
  • N is a Fermi distribution function.
  • the N trap obtained from equation (4) By fitting the formula (5), N it is determined.
  • the calculation using a device simulator set the N it, it is possible to obtain a transfer characteristic containing an Id ⁇ 0.1 pA.
  • Equation (4) the result of extracting N trap by applying Equation (4) to the actually measured Id-Vg characteristic shown in FIG. 51 is shown by white circles in FIG.
  • the vertical axis in FIG. 53 represents Fermi energy Ef from the conduction band lower end Ec of the semiconductor. Looking at the broken line, the maximum value is found at a position just below Ec.
  • FIGS. 54A and 54B show the results of back-calculating the Id-Vg characteristics by feeding back the obtained interface state fitting curve to the calculation using the device simulator.
  • FIG. 54A shows an Id-Vg characteristic obtained by calculation when the drain voltage Vd is 0.1 V and 1.8 V, and an actually measured Id-Vg in the transistor when the drain voltage Vd is 0.1 V and 1.8 V. Characteristics.
  • FIG. 54B is a graph in which the drain current Id of FIG. 54A is logarithmic.
  • FIG. 55 shows the result of calculating the average value of the shallow defect level densities of the two sets of samples C1 to C3.
  • the peak value of the shallow defect level density is less than 2.5 ⁇ 10 12 cm ⁇ 2 eV ⁇ 1 , indicating that the sample has a very low shallow defect level density.
  • the peak value of the shallow defect level density in the metal oxide film is less than 2.5 ⁇ 10 12 cm ⁇ 2 eV ⁇ 1 , preferably less than 1.75 ⁇ 10 12 cm ⁇ 2 eV ⁇ 1 , and more.
  • it is less than 1.5 * 10 ⁇ 12 > cm ⁇ -2 > eV ⁇ -1 >, More preferably, it is less than 7.5 * 10 ⁇ 11 > cm ⁇ -2 > eV- 1 .
  • Samples C1 to C3 are transistors in which a metal oxide film with a low density of defect states is formed. This is because a metal oxide film formed under the conditions of a low temperature and a low oxygen flow rate improves oxygen permeability and increases the amount of oxygen diffused during the manufacturing process of the transistor, thereby increasing the amount of oxygen in the metal oxide film. This suggests that defects such as oxygen vacancies at the interface between the metal oxide film and the insulating film are reduced.
  • the metal oxide film can be formed by a sputtering method in an atmosphere containing oxygen.
  • the substrate temperature during film formation is preferably a temperature of room temperature to 150 ° C., preferably 50 ° C. to 150 ° C., more preferably 100 ° C. to 150 ° C., typically 130 ° C.
  • the substrate temperature is preferably a temperature of room temperature to 150 ° C., preferably 50 ° C. to 150 ° C., more preferably 100 ° C. to 150 ° C., typically 130 ° C.
  • the flow rate ratio of oxygen during film formation is 0% to less than 50%, preferably 0% to 30%, more preferably 0% to 20%, and even more preferably 0% to 15%. % Or less, typically 10%.
  • oxygen partial pressure is 0% to less than 50%, preferably 0% to 30%, more preferably 0% to 20%, and even more preferably 0% to 15%. % Or less, typically 10%.
  • a metal oxide film in which a crystal part having orientation and a crystal part having no orientation are mixed can be obtained. Obtainable.
  • the substrate temperature and the oxygen flow rate within the above ranges, it is possible to control the existence ratio of the crystal part having orientation and the crystal part having no orientation.
  • An oxide target that can be used for forming a metal oxide film is not limited to an In—Ga—Zn-based oxide, and includes, for example, an In—M—Zn-based oxide (M is Al, Ga, Y). Or Sn) can be applied.
  • a metal oxide film including a crystal part is formed using a sputtering target including a polycrystalline oxide having a plurality of crystal grains, compared to a case where a sputtering target not including a polycrystalline oxide is used, A metal oxide film having crystallinity is easily obtained.
  • the sputtering target has a plurality of crystal grains and the crystal grains have a layered structure, and there is an interface that is easily cleaved, the ions are allowed to collide with the sputtering target.
  • the crystal grains are cleaved.
  • the sputtering target is, for example, as shown in FIG. 58 described later, and includes a layered structure including In, M (M is Al, Ga, Y, or Sn), and Zn, and oriented in the c-axis direction. It shall have a structure.
  • the crystal grains are tabular or pellet-like clusters, and can also be referred to as nanoclusters.
  • the nanoclusters 20 cleaved from the target are flat, and thus are easily deposited with the plane side facing the surface of the substrate 28.
  • the particles 23 ejected from the target reach the surface of the substrate 28.
  • the particle 23 has an aggregate of one atom or several atoms. Therefore, the particles 23 can also be referred to as atomic particles.
  • the nanocluster has a layered structure oriented in the c-axis direction, including In, M (M is Al, Ga, Y, or Sn), and Zn, as shown in FIG. 58 described later.
  • M is Al, Ga, Y, or Sn
  • Zn as shown in FIG. 58 described later.
  • the particles 23 are more easily bonded to the side surfaces than the upper surface of the nanocluster 20. Accordingly, the particles 23 preferentially adhere to the side surfaces of the nanoclusters 20 so as to fill the regions where the nanoclusters 20 are not formed.
  • the particles 23 are chemically connected to the nanoclusters 20 when the bond is in an active state to form the laterally grown portions 22 (see FIG. 56A). It can also be said that the particles 23 enter the region between the nanocluster
  • the lateral growth part 22 grows in the lateral direction so as to fill the region 26 between the nanoclusters 20 (the region 26 can also be referred to as Lateral Growth Buffer Region (LGBR)) (also referred to as lateral growth).
  • LGBR Lateral Growth Buffer Region
  • the lateral direction refers to a direction perpendicular to the c-axis in the nanocluster 20, for example.
  • the particles 23 adhere to the laterally grown portions 22 of the nanoclusters 20, oxygen diffused via LGBR adheres to the particles 23, and the particles 23 again.
  • the reaction of adhering in the same manner is likely to occur. It is presumed that the solid-phase growth in the horizontal direction is caused by this repetition.
  • Such lateral growth of nanoclusters can also be called self-organization.
  • the lateral growth part 22 collides with each other because the lateral growth part 22 grows laterally.
  • Adjacent nanoclusters 20 are connected with a portion where the laterally growing portion 22 collides as a connecting portion 27 (see FIG. 56B). That is, the connecting portion 27 is formed in the region 26.
  • the particles 23 form the lateral growth portions 22 on the side surfaces of the nanoclusters 20 and the lateral growth portions 22 grow in the lateral direction, thereby filling the regions 26 between the nanoclusters 20. . In this manner, the lateral growth portion 22 is formed until the region where the nanocluster 20 is not formed is filled.
  • the gap between the nanoclusters 20 and the nanoclusters 20 is filled while the particles 23 are laterally grown, so that a clear crystal grain boundary is not formed.
  • the particles 23 are smoothly connected (anchored) between the nanoclusters 20, different crystal structures are formed in the connecting portion 27 from both single crystals and polycrystals.
  • a crystal structure having a strain is formed at the connecting portion 27 between the nanoclusters 20.
  • the crystal structure whose upper surface has a hexagonal shape may be deformed into a pentagon or heptagon.
  • new nanoclusters 20 are formed with the planar side facing the surface of the substrate 28.
  • the particles 23 are deposited so as to fill the region where the nanoclusters 20 are not formed, thereby forming the lateral growth portion 22 (see FIG. 56C).
  • the particles 23 adhere to the side surfaces of the nanoclusters 20 and the laterally grown portions 22 grow laterally, thereby connecting the nanoclusters 20 in the second layer (see FIG. 56D).
  • Film formation continues until the m-th layer (m is an integer of 2 or more) is formed, and a metal oxide film having a stacked body is formed.
  • the bonding or rearrangement of the nanoclusters 20 proceeds on the substrate surface, so that a metal oxide film including a crystal part having orientation is easily formed.
  • the method for forming a metal oxide film of one embodiment of the present invention is not limited to this, and for example, a pulse laser deposition (PLD) method, a plasma enhanced chemical vapor deposition (PECVD) method, thermal CVD (Chemical Vapor Deposition)
  • PLD pulse laser deposition
  • PECVD plasma enhanced chemical vapor deposition
  • thermal CVD Thermal Vapor Deposition
  • an ALD Atomic Layer Deposition
  • a vacuum deposition method may be used.
  • An example of the thermal CVD method is a MOCVD (Metal Organic Chemical Vapor Deposition) method.
  • a metal oxide film can be applied to a semiconductor device such as a transistor.
  • a metal oxide film having semiconductor characteristics hereinafter referred to as an oxide semiconductor film
  • the oxide semiconductor film includes indium (In), M (M represents Al, Ga, Y, or Sn), and Zn (zinc).
  • the element M is aluminum, gallium, yttrium, or tin.
  • boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, Cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like may be used.
  • a plurality of the aforementioned elements may be combined.
  • FIGS. 57A to 57C do not describe the atomic ratio of oxygen.
  • the terms of the atomic ratio of indium, element M, and zinc included in the oxide semiconductor film are [In], [M], and [Zn].
  • 57A and 57B illustrate an example of a preferable range of the atomic ratio of indium, the element M, and zinc included in the oxide semiconductor film of one embodiment of the present invention.
  • FIG. 58 shows a crystal structure of InMZnO 4 when observed from a direction parallel to the b-axis.
  • a metal element in a layer containing M, Zn, and oxygen hereinafter referred to as an (M, Zn) layer
  • the element M or zinc represents the element M or zinc.
  • the ratio of the element M and zinc shall be equal.
  • the element M and zinc can be substituted and the arrangement is irregular.
  • Indium and element M can be substituted for each other. Therefore, the element M in the (M, Zn) layer can be replaced with indium and expressed as an (In, M, Zn) layer. In that case, a layered structure in which the In layer is 1 and the (In, M, Zn) layer is 2 is employed.
  • the element M in the MZnO 2 layer can be substituted with indium, and can be expressed as an In ⁇ M 1- ⁇ ZnO 2 layer (0 ⁇ ⁇ 1). In that case, a layered structure in which the InO 2 layer is 1 and the In ⁇ M 1- ⁇ ZnO 2 layer is 2 is adopted. Further, indium in the InO 2 layer can be replaced with the element M, and can be expressed as an In 1- ⁇ M ⁇ O 2 layer (0 ⁇ ⁇ 1). In that case, the In 1- ⁇ M ⁇ O 2 layer is 1 and the MZnO 2 layer is 2.
  • the In layer when the In layer is 1 and the (M, Zn) layer is non-integer, the In layer has 1 and the (M, Zn) layer has an integer of multiple layers.
  • the In layer has 1 and the (M, Zn) layer has an integer of multiple layers.
  • a film with an atomic ratio that deviates from the atomic ratio of the target is formed.
  • [Zn] of the film may be smaller than [Zn] of the target.
  • a plurality of phases may coexist in the oxide semiconductor film (two-phase coexistence, three-phase coexistence, and the like).
  • a grain boundary also referred to as a grain boundary
  • a grain boundary may be formed between different crystal structures.
  • the carrier mobility (electron mobility) of the oxide semiconductor film can be increased. This is because, in an oxide semiconductor film containing indium, element M, and zinc, the s orbital of heavy metal mainly contributes to carrier conduction, and by increasing the indium content, the region where the s orbital overlaps becomes larger. Therefore, an oxide semiconductor film with a high indium content has higher carrier mobility than an oxide semiconductor film with a low indium content.
  • the oxide semiconductor film of one embodiment of the present invention preferably has an atomic ratio shown by a region A in FIG. 57A which has a high carrier mobility and a layered structure with few grain boundaries.
  • An oxide semiconductor film having an atomic ratio represented by the region B is an excellent oxide semiconductor film that has particularly high crystallinity and high carrier mobility.
  • the conditions under which the oxide semiconductor film forms a layered structure are not uniquely determined by the atomic ratio. Depending on the atomic ratio, there is a difference in difficulty for forming a layered structure. On the other hand, even if the atomic ratio is the same, there may be a layered structure or a layered structure depending on the formation conditions. Therefore, the region illustrated in the drawing is a region exhibiting an atomic ratio in which the oxide semiconductor film has a layered structure, and the boundaries between the regions A to C are not strict.
  • Metal oxide film structure Next, the structure of the metal oxide film (hereinafter referred to as an oxide semiconductor) is described.
  • An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor.
  • a non-single-crystal oxide semiconductor a CAAC-OS (c-axis-aligned crystal oxide semiconductor), a polycrystalline oxide semiconductor, an nc-OS (nanocrystalline oxide semiconductor), a pseudo-amorphous oxide semiconductor (a-like oxide OS) : Amorphous-like oxide semiconductor) and amorphous oxide semiconductor.
  • oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxide semiconductors.
  • a crystalline oxide semiconductor include a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, and an nc-OS.
  • Amorphous structures are generally isotropic, have no heterogeneous structure, are metastable, have no fixed atomic arrangement, have a flexible bond angle, have short-range order, but long-range order It is said that it does not have.
  • a stable oxide semiconductor cannot be called a complete amorphous oxide semiconductor.
  • an oxide semiconductor that is not isotropic (for example, has a periodic structure in a minute region) cannot be called a complete amorphous oxide semiconductor.
  • an a-like OS is not isotropic but has an unstable structure having a void (also referred to as a void). In terms of being unstable, a-like OS is physically similar to an amorphous oxide semiconductor.
  • CAAC-OS First, the CAAC-OS will be described.
  • a CAAC-OS is a kind of oxide semiconductor having a plurality of c-axis aligned crystal parts (also referred to as pellets).
  • the CAAC-OS is an oxide semiconductor with high crystallinity. Since the crystallinity of an oxide semiconductor may be deteriorated by entry of impurities, generation of defects, or the like, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies).
  • the impurity means an element other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, or a transition metal element.
  • an element such as silicon which has a stronger bonding force with oxygen than a metal element included in an oxide semiconductor, disturbs the atomic arrangement of the oxide semiconductor by depriving the oxide semiconductor of oxygen, thereby reducing crystallinity. It becomes a factor.
  • heavy metals such as iron and nickel, argon, carbon dioxide, and the like have large atomic radii (or molecular radii), which disturbs the atomic arrangement of the oxide semiconductor and decreases crystallinity.
  • nc-OS is analyzed by XRD.
  • XRD X-ray diffraction
  • the nc-OS is an oxide semiconductor that has higher regularity than an amorphous oxide semiconductor. Therefore, the nc-OS has a lower density of defect states than an a-like OS or an amorphous oxide semiconductor. Note that the nc-OS does not have regularity in crystal orientation between different pellets. Therefore, the nc-OS may have a higher density of defect states than the CAAC-OS.
  • the a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor.
  • the a-like OS has a void or a low density region. Since the a-like OS has a void, it has an unstable structure.
  • An a-like OS has a lower density than an nc-OS and a CAAC-OS because it has a void.
  • the density of the a-like OS is 78.6% or more and less than 92.3% of the density of the single crystal having the same composition.
  • the density of the nc-OS and the density of the CAAC-OS are 92.3% or more and less than 100% of the density of the single crystal having the same composition.
  • An oxide semiconductor having a density of less than 78% of the single crystal is difficult to form.
  • the density of single crystal InGaZnO 4 having a rhombohedral structure is 6.357 g / cm 3 .
  • the density of a-like OS is 5.0 g / cm 3 or more and less than 5.9 g / cm 3.
  • the density of the nc-OS and the density of the CAAC-OS are 5.9 g / cm 3 or more and 6.3 g / cm. less than cm 3 .
  • oxide semiconductors have various structures and various properties.
  • the oxide semiconductor may be a stacked film including two or more of an amorphous oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS, for example.
  • an oxide semiconductor film for a transistor for example, carrier scattering at a crystal grain boundary can be reduced as compared with a transistor using polycrystalline silicon for a channel region.
  • a transistor can be realized.
  • a highly reliable transistor can be realized.
  • the oxide semiconductor film of one embodiment of the present invention is a film in which a crystal part having orientation and a crystal part not having orientation are mixed. By using such an oxide semiconductor film having crystallinity, a transistor having both high field-effect mobility and high reliability can be realized.
  • Carrier density of metal oxide film The carrier density of the metal oxide film (hereinafter referred to as an oxide semiconductor film) will be described below.
  • oxygen vacancies (Vo) in the oxide semiconductor film As a factor that affects the carrier density of the oxide semiconductor film, oxygen vacancies (Vo) in the oxide semiconductor film, impurities in the oxide semiconductor film, and the like can be given.
  • the density of defect states is increased when hydrogen is bonded to the oxygen vacancies (this state is also referred to as VoH).
  • the carrier density of the oxide semiconductor film can be controlled by controlling the density of defect states in the oxide semiconductor film.
  • the object is to suppress a negative shift in the threshold voltage of the transistor or to reduce the off-state current of the transistor, it is preferable to reduce the carrier density of the oxide semiconductor film.
  • the impurity concentration in the oxide semiconductor film may be decreased and the defect level density may be decreased.
  • a low impurity concentration and a low density of defect states are referred to as high purity intrinsic or substantially high purity intrinsic.
  • the carrier density of the high-purity intrinsic oxide semiconductor film is less than 8 ⁇ 10 15 cm ⁇ 3 , preferably less than 1 ⁇ 10 11 cm ⁇ 3 , more preferably less than 1 ⁇ 10 10 cm ⁇ 3 , and 1 ⁇ What is necessary is just to set it as 10 ⁇ -9 > cm ⁇ -3 > or more.
  • the carrier density of the oxide semiconductor film for the purpose of improving the on-state current of the transistor or improving the field-effect mobility of the transistor, it is preferable to increase the carrier density of the oxide semiconductor film.
  • the impurity concentration of the oxide semiconductor film may be slightly increased or the defect state density of the oxide semiconductor film may be slightly increased.
  • the band gap of the oxide semiconductor film is preferably made smaller.
  • an oxide semiconductor film with a slightly high impurity concentration or a slightly high defect state density within a range where the on / off ratio of the Id-Vg characteristics of the transistor can be obtained can be regarded as substantially intrinsic.
  • the oxide semiconductor film in which the carrier density is increased is slightly n-type. Therefore, an oxide semiconductor film with an increased carrier density may be referred to as “Slightly-n”.
  • the carrier density of the substantially intrinsic oxide semiconductor film is preferably 1 ⁇ 10 5 cm ⁇ 3 or more and less than 1 ⁇ 10 18 cm ⁇ 3 , preferably 1 ⁇ 10 7 cm ⁇ 3 or more and 1 ⁇ 10 17 cm ⁇ 3 or less. More preferably, it is 1 ⁇ 10 9 cm ⁇ 3 or more and 5 ⁇ 10 16 cm ⁇ 3 or less, more preferably 1 ⁇ 10 10 cm ⁇ 3 or more and 1 ⁇ 10 16 cm ⁇ 3 or less, and further preferably 1 ⁇ 10 11 cm ⁇ 3. More preferably, it is 1 ⁇ 10 15 cm ⁇ 3 or less.
  • FIG. 59 illustrates energy bands in a transistor in which an oxide semiconductor film is used for a channel region.
  • FIG. 59 GE represents a gate electrode, GI represents a gate insulating film, OS represents an oxide semiconductor film, and SD represents a source electrode or a drain electrode. That is, FIG. 59 illustrates an example of the energy band of the gate electrode, the gate insulating film, the oxide semiconductor film, and the source or drain electrode in contact with the oxide semiconductor film.
  • a silicon oxide film is used as the gate insulating film and an In—Ga—Zn oxide is used as the oxide semiconductor film.
  • the transition level ( ⁇ f) of defects that can be formed in the silicon oxide film is formed at a position away from the conduction band of the gate insulating film by 3.1 eV, and the oxide when the gate voltage (Vg) is 30V.
  • the Fermi level (Ef) of the silicon oxide film at the interface between the semiconductor film and the silicon oxide film is set to 3.6 eV from the conduction band of the gate insulating film. Note that the Fermi level of the silicon oxide film varies depending on the gate voltage.
  • the Fermi level (Ef) of the silicon oxide film at the interface between the oxide semiconductor film and the silicon oxide film is lowered.
  • white circles in FIG. 59 represent electrons (carriers), and X in FIG. 59 represents a defect level in the silicon oxide film.
  • the carrier when a carrier is thermally excited in a state where a gate voltage is applied, the carrier is trapped at a defect level (X in the figure), and from a plus (“+”) to a neutral (“0”). ”), The charge state of the defect level changes. That is, when the value obtained by adding the above-described thermal excitation energy to the Fermi level (Ef) of the silicon oxide film becomes higher than the defect transition level ( ⁇ f), the charge state of the defect level in the silicon oxide film is positive. From this state, the transistor becomes neutral, and the threshold voltage of the transistor fluctuates in the positive direction.
  • the depth at which the Fermi level at the interface between the gate insulating film and the oxide semiconductor film is formed may be different.
  • the conduction band of the gate insulating film moves upward at and near the interface between the gate insulating film and the oxide semiconductor.
  • the energy difference between the Fermi level at the interface between the gate insulating film and the oxide semiconductor film increases.
  • the charge trapped in the gate insulating film is reduced.
  • the change in the charge state of the defect level that can be formed in the above-described silicon oxide film is reduced, and the gate bias heat ( The variation of the threshold voltage of the transistor under stress can be reduced under stress (Gate Bias Temperature: GBT).
  • the charge trapped in the defect level of the oxide semiconductor film takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor in which a channel region is formed in an oxide semiconductor film with a high defect level density may have unstable electrical characteristics.
  • Impurities include hydrogen, nitrogen, alkali metal, alkaline earth metal, iron, nickel, silicon, and the like.
  • the concentrations of silicon and carbon in the oxide semiconductor film, and the concentrations of silicon and carbon in and near the interface of the oxide semiconductor film Is 2 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 17 atoms / cm 3 or less.
  • the concentration of alkali metal or alkaline earth metal in the oxide semiconductor film obtained by SIMS is set to 1 ⁇ 10 18 atoms / cm 3 or lower, preferably 2 ⁇ 10 16 atoms / cm 3 or lower.
  • the nitrogen in the oxide semiconductor film is preferably reduced as much as possible.
  • the nitrogen concentration in the oxide semiconductor film obtained by SIMS is less than 5 ⁇ 10 19 atoms / cm 3 , preferably 5 ⁇ 10 18 atoms / cm 3 or less, more preferably 1 ⁇ 10 18 atoms / cm 3 or less, and even more preferably 5 ⁇ 10 17 atoms / cm 3 or less.
  • hydrogen contained in the oxide semiconductor film reacts with oxygen bonded to a metal atom to become water, so that an oxygen vacancy may be formed in some cases.
  • oxygen vacancy may be formed in some cases.
  • electrons serving as carriers may be generated.
  • a part of hydrogen may be combined with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor including an oxide semiconductor film containing hydrogen is likely to be normally on. For this reason, it is preferable that hydrogen in the oxide semiconductor film be reduced as much as possible.
  • the hydrogen concentration obtained by SIMS is less than 1 ⁇ 10 20 atoms / cm 3 , preferably less than 1 ⁇ 10 19 atoms / cm 3 , more preferably 5 ⁇ 10 18 atoms / cm 3. Less than cm 3 , more preferably less than 1 ⁇ 10 18 atoms / cm 3 .
  • the oxide semiconductor film preferably has an energy gap of 2 eV or more, or 2.5 eV or more.
  • the thickness of the oxide semiconductor film is 3 nm to 200 nm, preferably 3 nm to 100 nm, more preferably 3 nm to 60 nm.
  • the oxide semiconductor film is an In-M-Zn oxide
  • the CAC is one structure of a material in which an element included in an oxide semiconductor is unevenly distributed with a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or the vicinity thereof. Note that in the following, in an oxide semiconductor, one or more metal elements are unevenly distributed, and a region including the metal element has a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or the vicinity thereof.
  • the state mixed with is also referred to as a mosaic or patch.
  • CAC-IGZO in an In—Ga—Zn oxide is indium oxide (hereinafter referred to as InO X1 (X1 is a real number greater than 0)) or indium zinc oxide.
  • InO X1 X1 is a real number greater than 0
  • objects hereinafter, in X2 Zn Y2 O Z2 ( X2, Y2, and Z2 is larger real) than 0.
  • gallium oxide hereeinafter, GaO X3 (X3 is a large real number) than 0.
  • Or gallium zinc oxide hereinafter referred to as Ga X4 Zn Y4 O Z4 (X4, Y4, and Z4 are real numbers greater than 0)
  • InO X1 or In X2 Zn Y2 O Z2 is uniformly distributed in the film (hereinafter also referred to as cloud shape).
  • CAC-IGZO has a region GaO X3 is the main component, and In X2 Zn Y2 O Z2, or InO X1 is the main component region is a composite oxide semiconductor having a structure that is mixed.
  • the first region indicates that the atomic ratio of In to the element M in the first region is larger than the atomic ratio of In to the element M in the second region. It is assumed that the concentration of In is higher than that in the second region.
  • IGZO is a common name and may refer to one compound of In, Ga, Zn, and O.
  • ZnO ZnO
  • the crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure.
  • the CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected without being oriented in the ab plane.
  • CAC relates to a material structure.
  • CAC is a material structure containing In, Ga, Zn, and O, and is a region that is observed in a part of nanoparticles mainly composed of Ga, and a part of nanoparticles composed mainly of In.
  • the observed region is a configuration in which the regions are randomly dispersed in a mosaic pattern. Therefore, in CAC, the crystal structure is a secondary element.
  • CAC does not include a stacked structure of two or more kinds of films having different compositions.
  • a structure composed of two layers of a film mainly containing In and a film mainly containing Ga is not included.
  • a region GaO X3 is the main component, and In X2 Zn Y2 O Z2 or InO X1 is the main component region, in some cases clear boundary can not be observed.
  • Sample structure and production method >> In the following, nine samples according to one embodiment of the present invention are described. Each sample is manufactured under different conditions for the substrate temperature and the oxygen gas flow rate when the oxide semiconductor film is formed. Note that the sample has a structure including a substrate and an oxide semiconductor over the substrate.
  • a glass substrate is used as the substrate.
  • an In—Ga—Zn oxide with a thickness of 100 nm is formed as an oxide semiconductor over the glass substrate with a sputtering apparatus.
  • 2500 W AC power is supplied to the oxide target installed in the sputtering apparatus.
  • the substrate temperature was set to a temperature at which heating was not performed intentionally (hereinafter also referred to as RT), 130 ° C., or 170 ° C.
  • RT temperature at which heating was not performed intentionally
  • oxygen gas flow rate ratio nine samples are manufactured by setting the flow rate ratio of oxygen gas to the mixed gas of Ar and oxygen (hereinafter also referred to as oxygen gas flow rate ratio) to 10%, 30%, or 100%.
  • FIG. 60 shows the results of measuring the XRD spectrum using the out-of-plane method.
  • the upper part shows the measurement result for the sample whose substrate temperature condition during film formation is 170 ° C.
  • the middle part shows the measurement result for the sample whose substrate temperature condition during film formation is 130 ° C.
  • the lower part shows the measurement result during film formation.
  • the measurement result in the sample is shown.
  • the left column shows the measurement results for the sample with an oxygen gas flow ratio of 10%
  • the center column shows the measurement results for a sample with an oxygen gas flow ratio of 30%
  • the right column shows the oxygen gas flow rate.
  • the measurement result in the sample whose ratio condition is 100% is shown.
  • planar TEM image a planar image acquired by HAADF-STEM
  • sectional image a sectional image
  • the TEM image was observed using a spherical aberration correction function.
  • the HAADF-STEM image was taken by irradiating an electron beam with an acceleration voltage of 200 kV and a beam diameter of about 0.1 nm ⁇ using an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.
  • FIG. 61A shows the substrate temperature R.D. T.A. , And a plane TEM image of a sample fabricated at an oxygen gas flow rate ratio of 10%.
  • FIG. 61B shows the substrate temperature R.D. T.A. And a cross-sectional TEM image of a sample manufactured at an oxygen gas flow rate ratio of 10%.
  • FIG. 61A the substrate temperature R.D. T.A. , And an electron beam diffraction pattern indicated by black spots a1, black spots a2, black spots a3, black spots a4, and black spots a5 in a planar TEM image of a sample prepared at an oxygen gas flow rate ratio of 10%.
  • the observation of the electron beam diffraction pattern is performed while moving at a constant speed from the 0 second position to the 35 second position while irradiating the electron beam.
  • FIG. 61C shows the result of black point a1
  • FIG. 61D shows the result of black point a2
  • FIG. 61E shows the result of black point a3
  • FIG. 61F shows the result of black point a4, and
  • FIG. 61G shows the result of black point a5.
  • FIG. T.A In the cross-sectional TEM image of the sample manufactured at an oxygen gas flow rate ratio of 10%, the electron beam diffraction pattern indicated by black spot b1, black spot b2, black spot b3, black spot b4, and black spot b5 is observed.
  • FIG. 61H shows the result of black point b1
  • FIG. 61I shows the result of black point b2
  • FIG. 61J shows the result of black point b3
  • FIG. 61K shows the result of black point b4
  • FIG. 61L shows the result of black point b5.
  • a high luminance region in a ring shape can be observed.
  • a plurality of spots can be observed in the ring-shaped region.
  • nc-OS oxide semiconductor having a microcrystal
  • a simple diffraction pattern is observed.
  • nanobeam electron diffraction is performed on the nc-OS using an electron beam with a small probe diameter (for example, less than 50 nm)
  • bright spots are observed.
  • nanobeam electron diffraction is performed on the nc-OS, a region with high luminance may be observed so as to draw a circle (in a ring shape). In addition, a plurality of bright spots may be observed in the ring-shaped region.
  • Substrate temperature R.D. T.A The electron beam diffraction pattern of a sample manufactured at an oxygen gas flow rate ratio of 10% has a ring-like high luminance region and a plurality of bright spots in the ring region. Therefore, the substrate temperature R.D. T.A. And the sample manufactured at an oxygen gas flow rate ratio of 10% has an electron beam diffraction pattern of nc-OS and has no orientation in the plane direction and the cross-sectional direction.
  • an oxide semiconductor with a low substrate temperature or a low oxygen gas flow ratio during deposition has properties that are clearly different from those of an amorphous oxide semiconductor film and a single crystal oxide semiconductor film. Can be estimated.
  • each point in the analysis target region of the sample is irradiated with an electron beam, and the characteristic X-ray energy and the number of occurrences of the sample generated thereby are measured to obtain an EDX spectrum corresponding to each point.
  • the peak of the EDX spectrum at each point is represented by the electron transition from the In atom to the L shell, the electron transition from the Ga atom to the K shell, the electron transition from the Zn atom to the K shell, and the K shell from the O atom.
  • the ratio of each atom at each point is calculated.
  • FIG. 62A to 62C show the substrate temperature R.D. T.A. And EDX mapping in a cross section of a sample fabricated at an oxygen gas flow rate ratio of 10%.
  • FIG. 62A is an EDX mapping of Ga atoms (the ratio of Ga atoms to all atoms is in the range of 1.18 to 18.64 [atomic%]).
  • FIG. 62B is EDX mapping of In atoms (the ratio of In atoms to all atoms is in the range of 9.28 to 33.74 [atomic%]).
  • FIG. 62C is an EDX mapping of Zn atoms (the ratio of Zn atoms to all atoms is in the range of 6.69 to 24.99 [atomic%]).
  • 62A to 62C show the substrate temperature R.D. T.A. In a cross section of a sample manufactured at an oxygen gas flow rate ratio of 10%, a region in the same range is shown. Note that the EDX mapping shows the ratio of elements in light and dark so that the more measurement elements in the range, the brighter the brightness, and the darker the measurement elements. The magnification of EDX mapping shown in FIGS. 62A to 62C is 7.2 million times.
  • the range surrounded by the solid line includes many relatively dark regions, and the range surrounded by the broken line includes many relatively bright regions.
  • the range surrounded by a solid line includes many relatively bright areas, and the range surrounded by a broken line includes many relatively dark areas.
  • the range surrounded by the solid line is a region having a relatively large number of In atoms
  • the range surrounded by a broken line is a region having a relatively small number of In atoms.
  • the right side is a relatively bright region and the left side is a relatively dark region. Therefore, the range surrounded by the solid line is a region mainly composed of In X2 Zn Y2 O Z2 or InO X1 .
  • a range surrounded by a solid line is a region with relatively few Ga atoms
  • a range surrounded by a broken line is a region with relatively many Ga atoms.
  • the upper left region is a relatively bright region
  • the lower right region is a dark region. Therefore, the range surrounded by the broken line is a region whose main component is GaO X3 , Ga X4 Zn Y4 O Z4 , or the like.
  • the distribution of In atoms is relatively more uniform than that of Ga atoms.
  • In X2 Zn Y2 O Z2 is the main component. It seems to be connected to each other through the region.
  • the region mainly composed of In X2 Zn Y2 O Z2 or InO X1 is formed so as to spread in a cloud shape.
  • CAC-IGZO an In—Ga—Zn oxide having a structure in which a region containing GaO X3 as a main component and a region containing In X2 Zn Y2 O Z2 or InO X1 as a main component are unevenly distributed.
  • the crystal structure in CAC has an nc structure.
  • the nc structure possessed by CAC has several bright spots (spots) in addition to bright spots (spots) caused by IGZO including single crystal, polycrystal, or CAAC structure in an electron diffraction image.
  • a crystal structure is defined as a region having a high brightness in a ring shape.
  • regions GaO X3 is the main component
  • In X2 Zn Y2 O Z2 or the size of the area InO X1 is the main component is, 0.5 nm or more 10nm or less, or 1nm more 3nm or less Observed at.
  • the diameter of a region in which each metal element is a main component is 1 nm or more and 2 nm or less.
  • CAC-IGZO has a structure different from that of an IGZO compound in which metal elements are uniformly distributed, and has a property different from that of an IGZO compound. That, CAC-IGZO is a region such as GaO X3 is a region which is a main component, In X2 Zn Y2 O Z2 or InO X1 is phase-separated from each other region and, in the main component, is mainly composed of the elements Has a mosaic structure.
  • CAC-IGZO when CAC-IGZO is used for a semiconductor element, a high on-current can be obtained because the properties caused by GaO X3 and the like and the properties caused by In X2 Zn Y2 O Z2 or InO X1 act complementarily. (I on ) and high field effect mobility ( ⁇ ) can be realized.
  • CAC-IGZO is most suitable for various semiconductor devices including a display.

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Abstract

L'invention concerne un transistor à faible bruit. L'invention concerne également un dispositif d'imagerie qui comprend un transistor à faible bruit. Le transistor est caractérisé en ce qu'il comprend un premier oxyde semi-conducteur, un deuxième oxyde semi-conducteur, un troisième oxyde semi-conducteur, un film isolant de grille et une électrode de grille, et est en outre caractérisé en ce que : le deuxième oxyde semi-conducteur est disposé entre le premier oxyde semi-conducteur et le troisième oxyde semi-conducteur ; le premier oxyde semi-conducteur contient In, Zn et Ga dans ou autour d'un rapport de composition In:Ga:Zn = 1:3:4 (rapport atomique) ; le deuxième oxyde semi-conducteur contient In, Zn et Ga dans ou autour d'un rapport de composition In:Ga:Zn = 4:2:4,1 (rapport atomique) ; le troisième oxyde semi-conducteur contient In, Zn et Ga dans ou autour d'un rapport de composition In:Ga:Zn = 1:3:2 (rapport atomique) ; et le deuxième oxyde semi-conducteur possède une structure cristalline.
PCT/IB2016/052924 2016-01-22 2016-05-19 Transistor et dispositif d'imagerie WO2017125795A1 (fr)

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JP2014116594A (ja) * 2012-11-16 2014-06-26 Semiconductor Energy Lab Co Ltd 半導体装置
US20150243738A1 (en) * 2014-02-21 2015-08-27 Semiconductor Energy Laboratory Co., Ltd. Semiconductor film, transistor, semiconductor device, display device, and electronic appliance
JP2015195378A (ja) * 2014-03-28 2015-11-05 株式会社半導体エネルギー研究所 撮像装置
US20160013321A1 (en) * 2014-07-11 2016-01-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device

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Publication number Priority date Publication date Assignee Title
JP2014116594A (ja) * 2012-11-16 2014-06-26 Semiconductor Energy Lab Co Ltd 半導体装置
US20150243738A1 (en) * 2014-02-21 2015-08-27 Semiconductor Energy Laboratory Co., Ltd. Semiconductor film, transistor, semiconductor device, display device, and electronic appliance
JP2015195378A (ja) * 2014-03-28 2015-11-05 株式会社半導体エネルギー研究所 撮像装置
US20160013321A1 (en) * 2014-07-11 2016-01-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device

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