WO2017119177A1 - Solid-state image pickup element, method for driving solid-state image pickup element, and electronic apparatus - Google Patents

Solid-state image pickup element, method for driving solid-state image pickup element, and electronic apparatus Download PDF

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Publication number
WO2017119177A1
WO2017119177A1 PCT/JP2016/082015 JP2016082015W WO2017119177A1 WO 2017119177 A1 WO2017119177 A1 WO 2017119177A1 JP 2016082015 W JP2016082015 W JP 2016082015W WO 2017119177 A1 WO2017119177 A1 WO 2017119177A1
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semiconductor chip
unit
pixel
signal
solid
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PCT/JP2016/082015
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French (fr)
Japanese (ja)
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聡子 飯田
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ソニー株式会社
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B5/00Near-field transmission systems, e.g. inductive or capacitive transmission systems
    • H04B5/40Near-field transmission systems, e.g. inductive or capacitive transmission systems characterised by components specially adapted for near-field transmission
    • H04B5/48Transceivers
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70SSIS architectures; Circuits associated therewith
    • H04N25/76Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Definitions

  • the present disclosure relates to a solid-state imaging device, a driving method of the solid-state imaging device, and an electronic device.
  • Solid-state image sensors especially CMOS (Complementary Metal Oxide Semiconductor) image sensors, are used in electronic devices such as mobile phones, digital still cameras, single-lens reflex cameras, camcorders, and surveillance cameras, taking advantage of low power consumption and high speed. It is becoming widely installed. Recently, high-performance, high-quality image sensors that are on-chip together with the pixel array portion (pixel portion) are also appearing in functional circuit blocks such as image processing.
  • CMOS Complementary Metal Oxide Semiconductor
  • a micropad is formed corresponding to the position of both chips, and the microbumps are used to connect the two chips.
  • the microbumps are electrically connected (for example, see Patent Document 1).
  • a technique has been reported in which signals are transmitted (transmitted) between both chips by magnetic coupling in the peripheral region of the pixel array unit (see, for example, Non-Patent Document 1).
  • Non-Patent Document 1 a pixel signal read through a signal line is transmitted for each pixel column in the peripheral region of the pixel array unit. Therefore, an inductor (coil) for magnetic coupling is formed in a limited and narrow region around the pixel array portion, and the layout occupancy of the inductor cannot be secured sufficiently, resulting in poor transmission efficiency.
  • the present disclosure provides a solid-state imaging device capable of performing signal transmission with high transmission efficiency between stacked semiconductor chips while solving the problem of conductor connection, a driving method of the solid-state imaging device, and
  • An object is to provide an electronic apparatus having the solid-state imaging element.
  • a solid-state imaging device of the present disclosure includes the solid-state imaging device having the above configuration.
  • a method for driving a solid-state imaging device of the present disclosure includes A first semiconductor chip having a pixel array unit in which unit pixels for generating an electrical signal corresponding to incident light are arranged; A second semiconductor chip having a signal processing unit that performs predetermined signal processing on an electrical signal generated by each unit pixel of the pixel array unit; When driving a solid-state imaging device that is laminated, In the region of the pixel array portion, electrical signals are transmitted in a non-contact manner between the first semiconductor chip and the second semiconductor chip.
  • the present disclosure by transmitting signals between the stacked chips in the region of the pixel array unit, it is possible to sufficiently secure the layout occupancy of the elements constituting the signal transmission unit. Thus, signal transmission with high transmission efficiency can be performed between the stacked semiconductor chips.
  • FIG. 1 is a schematic configuration diagram illustrating an example of a basic configuration of a stacked solid-state imaging device.
  • FIG. 2 is a block diagram illustrating an overall configuration example of the solid-state imaging device according to the first embodiment.
  • FIG. 3 is a circuit diagram illustrating an example of a circuit configuration of a unit pixel and a voltage / current converter in the solid-state imaging device according to the first embodiment.
  • FIG. 4A is a circuit diagram illustrating an example of a circuit configuration of a signal detection unit in the solid-state imaging device according to the first embodiment
  • FIG. 4B is a block diagram illustrating an example of a circuit configuration of an AD converter.
  • FIG. 5 is a timing waveform diagram for explaining an operation example of the solid-state imaging device according to the first embodiment.
  • FIG. 6 is a diagram illustrating an example of the layout of the inductor on the first semiconductor chip side and the inductor on the second semiconductor chip side in the solid-state imaging device according to the first embodiment.
  • FIG. 7 is a diagram illustrating another example of the layout of the inductor on the first semiconductor chip side and the inductor on the second semiconductor chip side in the solid-state imaging device according to the first embodiment.
  • FIG. 8 is a block diagram illustrating an example of the overall configuration of the solid-state imaging device according to the second embodiment.
  • FIG. 9 is a circuit diagram illustrating an example of a circuit configuration of a unit pixel on the first semiconductor chip side and a signal detection unit on the second semiconductor chip side in the solid-state imaging device according to the second embodiment.
  • FIG. 10 is a timing waveform diagram for explaining an operation example of the solid-state imaging device according to the second embodiment.
  • FIG. 11 is a diagram illustrating an example of the layout of the inductor on the first semiconductor chip side and the inductor on the second semiconductor chip side in the solid-state imaging device according to the fourth embodiment.
  • FIG. 12 is a principle diagram of a transmission method using electrostatic coupling.
  • FIG. 13 is a block diagram illustrating a configuration of an imaging apparatus that is an example of the electronic apparatus of the present disclosure.
  • an electric signal is transmitted between the first semiconductor chip and the second semiconductor chip by magnetic (magnetic field) coupling between the first semiconductor chip and the second semiconductor chip. It can be configured to perform transmission.
  • the signal transmission unit is not limited to a transmission method using magnetic coupling, and may be another non-contact transmission method, for example, a transmission method using electrostatic coupling.
  • the unit pixel is preferably a back-illuminated pixel.
  • the “backside illuminated pixel” refers to a pixel structure that takes in incident light from the opposite side, that is, the back side when the side on which the wiring layer is disposed is the front side.
  • the unit pixel is not limited to the back-illuminated pixel, and may be a front-illuminated pixel.
  • the “front-illuminated pixel” refers to a pixel structure that captures incident light from the surface side where the wiring layer is disposed.
  • the electrical signal transmitted by the signal transmission unit may be an analog signal.
  • the electrical signal transmitted by the signal transmission unit may be a digital signal.
  • the unit pixel has a function of converting an electrical signal corresponding to incident light into a digital signal.
  • one or more inductors in the signal transmission unit are provided for one pixel column of the pixel array unit. It can be set as the structure currently provided. Alternatively, the inductor in the signal transmission unit may be formed along each pixel column of the pixel array unit.
  • one inductor for the signal transmission unit is provided for one unit pixel of the pixel array unit, or One pixel unit composed of a plurality of unit pixels can be provided.
  • the inductor in the signal transmission unit may be formed on the substrate surface opposite to the light-receiving side substrate surface of the back-illuminated pixel of the first semiconductor chip.
  • the stacked solid-state imaging device 10 includes a first semiconductor chip (semiconductor substrate) 11 and a second semiconductor chip 12.
  • the first semiconductor chip 11 is an upper chip and the second semiconductor chip 12 is a lower chip. It is a structure laminated as a chip (so-called laminated structure).
  • the upper first semiconductor chip 11 is formed by arranging unit pixels (hereinafter simply referred to as “pixels”) 20 including photoelectric conversion elements in a two-dimensional matrix (matrix).
  • pixels unit pixels
  • matrix matrix
  • the first semiconductor chip 11 is also equipped with a vertical scanning unit 14 that scans each pixel 20 of the pixel array unit 13 in the vertical direction (column direction). It has become.
  • the vertical scanning unit 14 may be mounted on the second semiconductor chip 12 side. It is arbitrary whether the vertical scanning unit 14 is mounted on the first semiconductor chip 11 side or the second semiconductor chip 12 side.
  • the lower second semiconductor chip 12 includes a signal processing unit 15 and a horizontal scanning unit 16 that perform various processes related to pixel signals read from each pixel 20 of the pixel array unit 13 formed on the first semiconductor chip 11.
  • the circuit chip is formed with a circuit portion.
  • the signal processing unit 15 performs predetermined signal processing including analog-digital conversion processing on the pixel signal read from each pixel 20 of the pixel array unit 13. Details of the signal processing unit 15 will be described later.
  • the horizontal scanning unit 16 scans the pixel signals in units of rows subjected to signal processing by the signal processing unit 15 in the horizontal direction (row direction), and performs processing of reading out in a predetermined order.
  • the above-described stacked-type (laminated structure) solid-state imaging device 10 needs only to be large enough to form the pixel array section 13 as the first semiconductor chip 11, the size of the first semiconductor chip 11, and thus, The overall size of the solid-state imaging device 10 can be reduced. Furthermore, since a process suitable for the creation of the pixel 20 can be applied to the first semiconductor chip 11 and a process suitable for the creation of a circuit can be applied to the second semiconductor chip 12, respectively, in manufacturing the stacked solid-state imaging device 10, There is also an advantage that the process can be optimized.
  • the solid-state imaging device according to the first embodiment is premised on a stacked solid-state imaging device formed by stacking the first semiconductor chip 11 and the second semiconductor chip 12 described above.
  • electrical signals are transmitted in a non-contact manner between the first semiconductor chip 11 and the second semiconductor chip 12, and
  • the signal to be transmitted is an analog signal.
  • non-contact transmission methods include a transmission method using magnetic (magnetic field) coupling and a transmission method using electrostatic coupling.
  • an electrical signal is transmitted between the first semiconductor chip 11 and the second semiconductor chip 12 by using a transmission method using magnetic coupling of inductors.
  • the transmission method is not limited to magnetic coupling.
  • FIG. 2 is a block diagram illustrating an example of the overall configuration of the solid-state imaging device (stacked solid-state imaging device) according to the first embodiment.
  • FIG. 2 mainly shows only functional units related to the technology of the present disclosure.
  • unit pixels 20 are arranged in a two-dimensional matrix (matrix) of m pixel rows and n pixel columns to form a pixel array unit 13.
  • matrix matrix
  • pixel drive lines 31 (31 1 to 31 m ) are wired along the row direction for each pixel row
  • signal lines 32 (32 1 to 32 n ) are provided for each pixel column.
  • the pixel drive line 31 is illustrated as one wiring, but is not limited to one.
  • a vertical scanning unit 14 On one side of the pixel array unit 13 in the row direction, a vertical scanning unit 14 is disposed.
  • the vertical scanning unit 14 outputs a drive signal for driving when reading a signal from the unit pixel 20 to the pixel drive lines 31 1 to 31 m .
  • one end of each of the pixel drive lines 31 _ 1 to 31 _m is connected to each output end corresponding to each row of the vertical scanning unit 14, and the drive signal output from these output ends is output for each pixel row.
  • the data is transmitted to the unit pixel 20.
  • the vertical scanning unit 14 includes a shift register, an address decoder, and the like, and drives each pixel 20 of the pixel array unit 13 at the same time or in units of rows.
  • the vertical scanning unit 14 is not shown in detail with respect to its specific configuration, the vertical scanning unit 14 generally has two scanning systems, a reading scanning system and a sweeping scanning system.
  • the readout scanning system selectively scans the unit pixels 20 in the pixel array unit 13 in order in units of rows in order to read out signals from the unit pixels 20.
  • a signal read from the unit pixel 20 is an analog signal.
  • the sweep-out scanning system performs sweep-out scanning with respect to the readout row on which readout scanning is performed by the readout scanning system, preceding the readout scanning by a time corresponding to the shutter speed.
  • a so-called electronic shutter operation is performed by sweeping (resetting) unnecessary charges by the sweep scanning system.
  • the electronic shutter operation refers to an operation in which the photoelectric charge of the photoelectric conversion element is discarded and a new exposure is started (photocharge accumulation is started).
  • the signal read out by the readout operation by the readout scanning system corresponds to the amount of light received after the immediately preceding readout operation or electronic shutter operation.
  • a period from the read timing by the immediately preceding read operation or the sweep timing by the electronic shutter operation to the read timing by the current read operation is the photo charge exposure period in the unit pixel 20.
  • a constant current source 33 is disposed on each one end side of the signal lines (column signal lines / vertical signal lines) 32 1 to 32 n .
  • the current source 33 has one end connected to one end of each of the signal lines 32 1 to 32 n and the other end connected to a fixed potential (for example, ground), and supplies current to the signal lines 32 1 to 32 n .
  • a voltage / current converter 41 and an inductor (coil) 42 are disposed at each other end of the signal lines 32 1 to 32 n . That is, the voltage / current converter 41 and the inductor 42 are provided for each pixel column of the pixel array unit 13.
  • Voltage-current conversion unit 41 is connected the input end to the other end of each of the signal lines 32 1 ⁇ 32 n, the signal lines 32 1 ⁇ 32 n voltage value of which varies according to the amount of incident light to the unit pixel 20 Is converted into a current value.
  • the inductor 42 has one end connected to the output end of the voltage / current converter 41 and the other end connected to a node of a fixed potential, and generates an electromotive force according to a change in the current value output from the voltage / current converter 41. appear.
  • the second semiconductor chip 12 is provided with an inductor 51 at a position corresponding to the inductor 42 provided for each pixel column in the first semiconductor chip 11. Then, by laminating the first semiconductor chip 11 and the second semiconductor chip 12, the inductor 42 and the inductor 51 are also laminated. As a result, the electromotive force generated in the inductor 42 on the first semiconductor chip 11 side is transmitted to the inductor 51 on the second semiconductor chip 12 side that is disposed in proximity by the mutual induction action. That is, the inductor 42 on the first semiconductor chip 11 side and the inductor 51 on the second semiconductor chip 12 side perform signal transmission between the first semiconductor chip 11 and the second semiconductor chip 12 in a contactless manner. Is configured.
  • the second semiconductor chip 12 further includes a signal detection unit 52, an analog-digital converter (hereinafter sometimes referred to as “AD converter”) 53, a memory 54, and a column selection corresponding to the inductor 51.
  • a switch 55 is provided. That is, the signal detection unit 52, the AD converter 53, the memory 54, and the column selection switch 55 are provided for each pixel column of the pixel array unit 13 on the first semiconductor chip 11 side together with the inductor 51.
  • the inductor 51, the signal detection unit 52, the AD converter 53, the memory 54, and the column selection switch 55 are used for pixel signals read from the pixels 20 of the pixel array unit 13 on the first semiconductor chip 11 side.
  • a signal processing unit 15 that performs predetermined signal processing including analog-digital conversion processing is configured.
  • the second semiconductor chip 12 is further provided with a horizontal scanning unit 16 that performs scanning in the horizontal direction on the pixel signals for each row processed by the signal processing unit 15 and reads them in a predetermined order.
  • the horizontal scanning unit 16 includes a shift register, an address decoder, and the like.
  • the inductor 51 on the second semiconductor chip 12 side generates a voltage equivalent to the electromotive force generated by the inductor 42 on the first semiconductor chip 11 side.
  • the signal detection unit 52 detects a voltage change of the inductor 51, converts it into an analog pixel signal, and supplies it to the AD converter 53.
  • the AD converter 53 converts the analog pixel signal into a digital pixel signal.
  • As the AD converter 53 a well-known AD converter can be used.
  • the AD converter 53 may include a gray code counter.
  • the AD converter 53 is not limited to these, and an AD converter such as a flash type, a half flash type, a sublens type, a pipeline type, a bit per stage type, a magnitude amplifier type, etc. Can also be mentioned.
  • the memory 54 stores the digital pixel signal that has been analog-digital converted by the AD converter 53.
  • the column selection switch 55 reads the digital pixel signal stored in the memory 54 to the signal output line 56 when turned on under scanning by the horizontal scanning unit 16.
  • the read digital pixel signal is subjected to final signal processing as necessary. Thereafter, the digital image data is output to the second semiconductor chip 12.
  • the unit pixel 20 includes, for example, a photodiode (PD) 21 as a photoelectric conversion element. As shown in FIG. 3, the unit pixel 20 includes a transfer transistor 22, a reset transistor 23, an amplification transistor 24, and a selection transistor 25 in addition to the photodiode 21.
  • PD photodiode
  • N-type MOSFETs are used as the four transistors of the transfer transistor 22, the reset transistor 23, the amplification transistor 24, and the selection transistor 25.
  • the combination of the conductivity types of the four transistors 22 to 25 illustrated here is merely an example, and is not limited to these combinations.
  • a plurality of drive lines 311, 312, and 313 are wired in common to the pixels in the same pixel row as the pixel drive lines 31 (31 1 to 31 m ) described above.
  • the plurality of drive lines 311, 312, 313 are connected to the output end corresponding to each pixel row of the vertical scanning unit 14 (see FIG. 2) in units of pixel rows.
  • the vertical scanning unit 14 appropriately outputs a transfer signal TRX, a reset signal RST, and a selection signal SEL to the plurality of drive lines 311, 312, 313.
  • the photodiode 21 has an anode electrode connected to a low-potential-side power source (for example, ground), and photoelectrically converts received light into photocharge (here, photoelectrons) having a charge amount corresponding to the amount of light. Accumulate charge.
  • the cathode electrode of the photodiode 21 is electrically connected to the gate electrode of the amplification transistor 24 through the transfer transistor 22.
  • a region electrically connected to the gate electrode of the amplification transistor 24 is a floating diffusion FD as a charge-voltage conversion unit (charge detection unit) that converts charges into voltage.
  • the transfer transistor 22 is connected between the cathode electrode of the photodiode 21 and the floating diffusion FD.
  • a transfer signal TRX that activates a high level (for example, V dd level) is applied to the gate electrode of the transfer transistor 22 from the vertical scanning unit 14 through the drive line 311.
  • V dd level for example, V dd level
  • the reset transistor 23 has a drain electrode connected to a node (power supply line) of the power supply potential Vdd , and a source electrode connected to the floating diffusion FD.
  • a reset signal RST that activates a high level is applied to the gate electrode of the reset transistor 23 from the vertical scanning unit 14 through the drive line 312.
  • Reset transistor 23 becomes conductive in response to a reset signal RST, which resets the floating diffusion FD by discarding the charge of the floating diffusion FD to a node of the power supply potential V dd.
  • the amplification transistor 24 has a gate electrode connected to the floating diffusion FD and a drain electrode connected to the node of the power supply potential Vdd .
  • the amplification transistor 24 serves as an input section of a source follower that is a readout circuit that reads a signal obtained by photoelectric conversion at the photodiode 21. That is, the amplifying transistor 24 forms a source follower with the current source 33 connected to the end of the signal line 32 by connecting the source electrode to the signal line 32 via the selection transistor 25.
  • the selection transistor 25 has, for example, a drain electrode connected to the source electrode of the amplification transistor 24 and a source electrode connected to the signal line 32.
  • a selection signal SEL that activates a high level is supplied from the vertical scanning unit 14 to the gate electrode of the selection transistor 25 through the drive line 313.
  • the selection transistor 25 becomes conductive in response to the selection signal SEL, and transmits the signal output from the amplification transistor 24 to the signal line 32 with the unit pixel 20 selected.
  • the selection transistor 25 may have a circuit configuration connected between the node of the power supply potential Vdd and the drain electrode of the amplification transistor 24.
  • a 4Tr configuration including the transfer transistor 22, the reset transistor 23, the amplification transistor 24, and the selection transistor 25, that is, four transistors (Tr) is given as an example.
  • the selection transistor 25 may be omitted, and a 3Tr configuration in which the amplification transistor 24 has the function of the selection transistor 25 may be used, or a configuration in which the number of transistors is increased as necessary.
  • the voltage / current converter 41 includes an operational amplifier 411, a MOS transistor 412, and a resistance element 413.
  • the operational amplifier 411 has a non-inverting (+) input terminal connected to the signal line 32.
  • the MOS transistor 412 has a gate electrode connected to the output terminal of the operational amplifier 411 and a source electrode connected to the inverting ( ⁇ ) input terminal of the operational amplifier 411.
  • One end of the resistance element 413 is connected to the source electrode of the MOS transistor 412, and the other end is connected to a low potential side power source (for example, ground).
  • the drain electrode of the MOS transistor 412 serves as the output terminal of the voltage-current converter 41.
  • the inductor 42 has one end connected to the output end of the voltage-current converter 41, that is, the drain electrode of the MOS transistor 412, and the other end connected to a node (power supply line) of a fixed potential, for example, the power supply potential Vdd . .
  • the operational amplifier 411 is configured so that the voltage I ⁇ R between both ends of the resistance element 413 and the non-inverting (+) input voltage of the operational amplifier 411 become equal due to an imaginary short in which the potential difference between the two input terminals becomes zero. Operate.
  • the current I flowing through the MOS transistor 412 changes so that the voltage of the signal line 32 that changes according to the amount of incident light of the unit pixel 20 becomes the voltage I ⁇ R across the resistor 413.
  • the current flowing through the inductor 42 is also I.
  • V ⁇ L ( ⁇ V / ⁇ I) (1)
  • L the inductance of the inductor 42
  • L ⁇ S / l ⁇ N 2
  • the magnetic permeability
  • S the cross-sectional area of the coil
  • l the length of the coil
  • N the number of turns of the coil.
  • FIG. 4A An example of the circuit configuration of the signal detector 52 is shown in FIG. 4A, and an example of the circuit configuration of the AD converter 53 is shown in FIG. 4B.
  • the signal detection unit 52 has a rectifier circuit configuration including a diode 521 and a capacitor 522.
  • the diode 521 has an anode electrode connected to one end of the inductor 51 and a cathode electrode connected to one electrode of the capacitor 522.
  • the other electrode of the capacitive element 522 is connected to the other end of the inductor 51.
  • a case where a single slope AD converter is used as the AD converter 53 is taken as an example.
  • a reference voltage V ref having a so-called ramp (RAMP) waveform (gradient waveform) in which the voltage value changes stepwise as time passes is used.
  • Reference voltage V ref of the ramp waveform is generated by the reference voltage generator 57.
  • the reference voltage generation unit 57 can be configured using, for example, a DAC (digital-analog conversion) circuit.
  • the AD converter 53 includes, for example, a comparator 531 and a counter 532.
  • an up / down counter (denoted as “U / DCNT” in the drawing) is used as the counter 532.
  • the comparator 531 uses the pixel signal read from each pixel 20 of the pixel array unit 13 as a comparison input, uses the reference voltage Vref of the ramp wave supplied from the reference voltage generation unit 57 as a reference input, and compares the two.
  • the comparator 531 for example, the reference voltage V ref is output when larger than the pixel signal is a first state (e.g., high level) and the output reference voltage V ref when: the pixel signal and the second (For example, low level). As a result, the output signal of the comparator 531 becomes a pulse signal having a pulse width corresponding to the level of the pixel signal.
  • the up / down counter 532 is supplied with the clock CK at the same timing as the supply start timing of the reference voltage V ref to the comparator 531. Then, the up / down counter 532 performs a down (DOWN) count or an up (UP) count in synchronization with the clock CK, so that the period of the pulse width of the output pulse of the comparator 531, that is, the start of the comparison operation. The comparison period from the end of the comparison operation to the end of the comparison operation is measured.
  • the count result (count value) of the up / down counter 532 becomes a digital value obtained by digitizing an analog pixel signal and is stored in the memory 54. Then, under scanning by the horizontal scanning unit 16 (see FIG. 2), a digital value obtained by AD converting an analog pixel signal from the memory 54 is appropriately read out.
  • CMOS image sensor In a solid-state imaging device (CMOS image sensor) in which the pixels 20 are arranged in a two-dimensional matrix, generally, correlated double sampling (CDS) is performed in order to remove noise during the reset operation of the pixels 20.
  • CDS correlated double sampling
  • the reset level V rst and the signal level V sig are read from the pixel 20 in this order.
  • the reset level V rst corresponds to the potential of the floating diffusion FD when the floating diffusion FD of the pixel 20 is reset.
  • the signal level V sig is equivalent to the potential of the floating diffusion FD when the transfer charge stored in the photodiode 21 to the floating diffusion FD.
  • the up / down counter 532 is, for example, the reset level V rst Down-counting, and up-counting is performed on the signal level V sig .
  • the difference between the signal level V sig and the reset level V rst can be obtained.
  • noise removal processing by correlated double sampling is performed during AD conversion by the AD converter 53.
  • the timing waveform diagram of FIG. 5 shows the timing relationship of the transfer signal TRX, the reset signal RST, and the selection signal SEL that drive the unit pixel 20.
  • the timing waveform diagram of FIG. 5 further shows changes in the potential of the signal line 32, the current flowing through the inductor 42 (coil current), the induced electromotive force generated in the inductor 42, and the output voltage of the signal detector 52. ing.
  • the reset signal RST transitions from a high level to a low level, so that the reset transistor 23 is turned off.
  • the reset of the floating diffusion FD that is, the gate electrode of the amplification transistor 24 is released, and the unit pixel 20 enters a non-reset state.
  • the gate electrode of the amplifying transistor 24 is fixed to a potential corresponding to darkness (dark).
  • the selection signal SEL already transitions from the low level to the high level at this time, and the selection transistor 25 is in the conductive state, so that the dark output of the unit pixel 20 appears on the signal line 32. .
  • the value of the current flowing through the inductor 42 is determined by the voltage of the signal line 32. Then, the peak value of the voltage change amount of the signal line 32 is clamped by the signal detection unit 52 on the second semiconductor chip 12 side through the inductor 42.
  • the transfer signal TRX is makes a transition from a low level to a high level, the transfer transistor 22 becomes conductive. Thereby, the photoelectric charge accumulated in the photodiode 21 is transferred to the floating diffusion FD.
  • the voltage appearing on the signal line 32 and the current flowing through the inductor 42 (coil current) differ depending on the amount of incident light, for example, in the dark (dark), intermediate light amount, and high light amount. Then, through the induced electromotive force generated in the inductor 42, the output voltage of the signal detection unit 52 changes as shown in FIG.
  • the correlated double sampling operation is realized by taking the difference between the reset level V rst obtained after time t 1 and the signal level V sig obtained after time t 2. Can do. As a result, since noise during the reset operation of the unit pixel 20 can be removed, a good captured image can be obtained.
  • Example of inductor layout Here, the layout of the inductor 42 on the first semiconductor chip 11 side and the inductor 51 on the second semiconductor chip 12 side in the solid-state imaging device 10 according to the first embodiment will be described. An example of the layout of the inductor 42 on the first semiconductor chip 11 side and the inductor 51 on the second semiconductor chip 12 side is shown in FIG.
  • the unit pixel 20 may be either a back-side illuminated pixel or a front-side illuminated pixel. However, it is preferable to use a back-illuminated pixel as the unit pixel 20 for the following reason.
  • the unit pixel 20 is composed of a back-illuminated pixel, and the inductor 42 is formed on the front surface side of the substrate, that is, on the substrate surface opposite to the light-receiving side substrate surface of the back-illuminated pixel. It will be. Thereby, the light incident on the photoelectric conversion element (photodiode 21) is not blocked by the inductor 42.
  • the inductor 42 is preferably formed along the pixel column of the pixel array unit 13 as shown in FIG. Further, the inductor 42 is appropriately formed in one or more layers in a rectangular (rectangular) spiral shape using a material such as aluminum, copper, or tungsten on the surface side of the substrate.
  • the rectangular shape is exemplified as the shape of the inductor 42, but the shape is not limited to this, and the shape is not limited as long as an electromotive force can be generated.
  • the inductance L of the inductor 42 increases according to the number of turns (the number of windings) and the area of the inductor 42 and is expressed as an induced electromotive force V as in the above-described equation (1). Therefore, in order to increase the signal transmission efficiency between the first semiconductor chip 11 and the second semiconductor chip 12, the number of turns and the area should be increased with as thin a wiring as possible. Further, by being close to the transmission destination inductor 51, transmission efficiency can be further improved without leakage.
  • the solid-state imaging device 10 in which the unit pixel 20 is a back-illuminated pixel is effective because the inductor 42 can be formed using the entire pixel area of one pixel column of the pixel array unit 13.
  • the inductor 42 on the first semiconductor chip 11 side and the inductor 51 on the second semiconductor chip 12 side are close to each other through an insulating film (not shown) having a thickness that does not cause dielectric breakdown.
  • Inductor 51 is formed. Similarly to the inductor 42, the inductor 51 is appropriately formed in one or more layers in a rectangular spiral shape using a material such as aluminum, copper, or tungsten. The inductor 51 receives a signal transmitted from the inductor 42.
  • This layout example illustrates a configuration in which the inductor 51 and the signal detection unit 52 are sequentially arranged in parallel, but is not limited to this configuration example. If the inductor 51 and the wiring layer constituting the signal detection unit 52 can be formed differently, the inductor 51 and the signal detection unit 52 are arranged so as to overlap in the direction perpendicular to the substrate surface of the second semiconductor chip 12. It is also possible to adopt a configuration.
  • FIG. 7 shows another example of the layout of the inductor 42 on the first semiconductor chip 11 side and the inductor 51 on the second semiconductor chip 12 side.
  • a plurality of signal lines 32 may be provided for one pixel column.
  • each pixel 20 of the pixel array unit 13 is divided into, for example, two vertically in the vertical direction (column direction), and the signal lines 32 corresponding to the upper and lower pixel lines with respect to one pixel column corresponding to this.
  • An example in which two wires are arranged for a pixel is shown.
  • the upper pixel wiring is referred to as a signal line 32a
  • the lower pixel wiring is referred to as a signal line 32b. That is, in the example of FIG. 7, two signal lines 32a and 32b divided vertically are arranged for one pixel column.
  • the number of signal lines 32 for each pixel column is not limited to two, and may be three or more.
  • a plurality of inductors 42 are formed for one pixel column according to the number of signal lines 32.
  • the inductor 42a is formed for the upper pixel, and the voltage-current converter 41a is formed correspondingly.
  • an inductor 42b is formed for the lower pixel, and a voltage / current converter 41b is formed correspondingly.
  • a plurality of inductors 51 are formed for one pixel column corresponding to the inductor 42 on the first semiconductor chip 11 side.
  • an inductor 51a is formed for the upper pixel, and a signal detection unit 52a and an AD converter 53a are formed correspondingly.
  • an inductor 51a is formed for the lower pixel, and a signal detector 52b and an AD converter 53b are formed correspondingly.
  • the first semiconductor chip 11 and the second semiconductor chip 12 are non-contacted by magnetic coupling in the region of the pixel array unit 13. Since signal transmission is performed, signal transmission with high transmission efficiency can be performed. Specifically, the layout occupancy of the elements (inductor 42 and inductor 51) constituting the signal transmission unit by magnetic coupling can be sufficiently secured as compared with the case where the layout is formed in a narrow region around the pixel array unit 13. Efficient signal transmission can be performed.
  • the inductor 42 can be formed on the substrate surface opposite to the light-receiving side substrate surface. Therefore, the degree of freedom in the layout of the inductor 42 is increased, and the layout of the inductor 42 is increased. The occupation ratio can be secured more sufficiently, and the laminated inductors 42 and 51 can be arranged close to each other. At this time, light incident on the photoelectric conversion element (photodiode 21) is not blocked by the inductor 42.
  • the signal transmission method is a magnetic coupling method
  • the problem of conductor connection by bumps can be solved.
  • the metal surface that becomes the electrode is not exposed, so there is no problem that the solid-state image sensor and the component of the signal processing unit are destroyed by electrostatic breakdown, and the yield is improved.
  • it is not necessary to form a protective element for countermeasures against electrostatic breakdown it is possible to reduce the size of the solid-state imaging device and speed up signal transmission.
  • the transmission target signal transmitted from the first semiconductor chip 11 side to the second semiconductor chip 12 side is an analog signal (analog pixel signal).
  • analog signal an analog signal
  • the potential of the signal line 32 after the stabilization is AD-converted, and then the pixel Transmission can be performed earlier than the method of reading and transmitting to the peripheral region of the array unit 13 (see, for example, Non-Patent Document 1).
  • the reading speed of the analog pixel signal can be increased.
  • the analog pixel signal is AD-converted and then read out to the peripheral area of the pixel array unit 13
  • the pixel signal after AD conversion is transmitted, so that it takes time to transmit to the second semiconductor chip 12 side. It will take.
  • the inductor 42 is formed along the pixel column of the pixel array unit 13 (see FIG. 6), the inductor 42 is connected to the signal line (column signal line). / Vertical signal line) 32 is laid out in parallel.
  • the capacitive coupling due to the parasitic capacitance between the signal line 32 and the inductor 42 allows the response of the electromotive force generated in the inductor 42 to follow the change in the potential of the signal line 32. Higher speed can be achieved.
  • the solid-state image sensor according to the second embodiment is also based on a stacked solid-state image sensor, and the first semiconductor chip 11 and the second semiconductor chip 11 Electric signals are transmitted to and from the semiconductor chip 12 in a non-contact manner.
  • the signal to be transmitted is an analog signal
  • the signal to be transmitted is a digital signal.
  • FIG. 8 is a block diagram illustrating an overall configuration example of a solid-state imaging device (stacked solid-state imaging device) according to the second embodiment.
  • the unit pixel on the first semiconductor chip side and the signal detection unit on the second semiconductor chip side An example of the circuit configuration is shown in the circuit diagram of FIG. FIG. 8 mainly illustrates only functional units related to the technology of the present disclosure.
  • the unit pixels 20 arranged in a two-dimensional matrix are configured to have an AD conversion function for converting an analog signal corresponding to incident light into a digital signal.
  • the unit pixel 20 includes a comparator 26 and a control transistor 27 in addition to the photodiode 21, the transfer transistor 22, and the reset transistor 23.
  • the comparator 26 corresponds to the comparator 531 in the AD converter (ADC) 53 shown in FIG. 4B.
  • the comparator 26 uses the potential of the floating diffusion FD as a comparison input and the reference voltage V ref of the ramp wave as a reference input, and compares the two.
  • the reference voltage V ref is generated by the reference voltage generator 57 (see FIG. 4B).
  • the comparator 26 compares the potential (signal level) of the floating diffusion FD when the signal charge is transferred from the photodiode 21 by the transfer transistor 22 with the reference voltage V ref of the ramp wave, thereby comparing the signal of the unit pixel 20. Digitize.
  • the comparison output of the comparator 26 becomes the gate input of the control transistor 27.
  • one inductor 42 on the first semiconductor chip 11 side is provided for one unit pixel 20 of the pixel array unit 13.
  • the present invention is not limited to this.
  • a pixel unit including a plurality of unit pixels 20 is used.
  • a configuration in which one inductor 42 is provided is also possible.
  • the inductor 42 is connected between the drain electrode of each control transistor 27 of the unit pixel 20 and the power source on the high potential (for example, power supply potential V dd ) side.
  • the source electrode of the control transistor 27 is connected to a low potential side power source (for example, ground) via the resistance element 28.
  • the control transistor 27 performs on / off control of the current flowing through the inductor 42 in accordance with the comparison output of the comparator 26.
  • the comparator 26 generates a high-level output at the timing when the potential of the floating diffusion FD matches the reference voltage Vref of the ramp wave.
  • the control transistor 27 becomes conductive, whereby a current flows from the power supply potential V dd to the ground through the inductor 42, the control transistor 27, and the resistance element 28.
  • an electromotive force corresponding to the flowing current is generated in the inductor 42 and is transmitted to the inductor 51 on the second semiconductor chip 12 side by a mutual induction effect.
  • the signal detection unit 52 includes a resistance element 523, a capacitance element 524, a counter 525, and a memory 526.
  • the resistive element 523 and the capacitive element 524 are connected to both ends of the inductor 51, and a signal is transmitted from the inductor 42 on the first semiconductor chip 11 side due to mutual induction, thereby generating an electromotive force generated in the inductor 51. Convert to square wave.
  • the pulse width of this rectangular wave corresponds to the level of the pixel signal of the unit pixel 20.
  • the counter 525 corresponds to the counter 532 in the AD converter 53 shown in FIG. 4B, and includes, for example, an up / down counter.
  • the counter 525 is supplied with the clock CK at the same timing as the supply start timing of the reference signal V ref to the comparator 26 of the unit pixel 20.
  • the counter 525 performs down-counting or up-counting in synchronization with the clock CK, so that the pulse width period of the rectangular wave converted by the resistor 523 and the capacitor 524, that is, the comparison operation of the comparator 26 is performed. The comparison period from the start to the end of the comparison operation is measured.
  • the measurement result of the counter 525 is stored in the memory 526.
  • the memory 526 corresponds to the memory 54 in the signal processing unit 15 illustrated in FIG.
  • the signal detection unit 52 is sequentially selected by the vertical scanning by the vertical scanning unit 14 and the horizontal scanning by the horizontal scanning unit 16, and a digital signal is transmitted from the memory 526 of the selected signal detection unit 52 through the column selection switch 55.
  • Read to output line 56 The read digital pixel signal is subjected to final signal processing as necessary. Thereafter, the digital image data is output to the second semiconductor chip 12.
  • the timing waveform diagram of FIG. 10 shows the timing relationship between the reset signal RST and the transfer signal TRX that drive the unit pixel 20.
  • the timing waveform diagram of FIG. 10 further shows changes in the comparison output of the comparator 26, the current flowing through the inductor 42 (coil current), the induced electromotive force generated in the inductor 42, and the output voltage of the signal detection unit 52. ing.
  • the reset signal RST transitions from a high level to a low level, so that the reset transistor 23 is turned off.
  • the reset of the floating diffusion FD that is, the input end of the comparator 26 is released, and the unit pixel 20 enters a non-reset state.
  • the input terminal of the comparator 26 is fixed at a potential corresponding to darkness.
  • the comparator 26 compares the potential of the floating diffusion FD with the reference voltage V ref of the ramp wave. Then, a determination potential of logic “0” / “1” is output from the comparator 26 according to the comparison result.
  • the determination potential of the comparator 26 is logic “1” (high level)
  • the control transistor 27 becomes conductive, and a current (coil current) flows through the inductor 42. Then, an induced electromotive force is generated in the inductor 42 at the change point of the coil current, and is transmitted to the inductor 51 on the second semiconductor chip 12 side by mutual induction.
  • the signal detector 52 generates a rectangular wave. Then, in the signal detection unit 52, the counter 525 counts the pulse width of the rectangular wave, and the measurement result is stored in the memory 526.
  • the transfer signal TRX is makes a transition from a low level to a high level, the transfer transistor 22 becomes conductive. Thereby, the photoelectric charge accumulated in the photodiode 21 is transferred to the floating diffusion FD.
  • the comparator 26 compares the potential of the floating diffusion FD and the reference voltage V ref of the ramp wave, and outputs a determination potential of logic “0” / “1” from the comparator 26 according to the comparison result. Is done.
  • an induced electromotive force is generated in the inductor 42 at a timing according to the amount of incident light, and is transmitted to the inductor 51 on the second semiconductor chip 12 side by mutual induction.
  • the signal detection unit 52 generates a rectangular wave and counts the pulse width of the rectangular wave, and stores the measurement result in the memory 526.
  • the unit pixel 20 may be either a back-illuminated pixel or a front-illuminated pixel. However, for the reason described in the first embodiment, it is preferable to use a back-illuminated pixel as the unit pixel 20.
  • one inductor 42 is preferably formed for each unit pixel 20, as shown in FIG. Further, the inductor 42 is appropriately formed in one or more layers in a rectangular (rectangular) spiral shape using a material such as aluminum, copper, or tungsten on the surface side of the substrate.
  • the rectangular shape is exemplified as the shape of the inductor 42, but the shape is not limited to this, and the shape is not limited as long as an electromotive force can be generated.
  • the second semiconductor chip 12 when the first semiconductor chip 11 and the second semiconductor chip 12 are stacked with respect to the inductor 42 that transmits a signal from the first semiconductor chip 11, the second semiconductor chip 12 is in a state of being close to the inductor 42.
  • one inductor 51 is formed for each signal detector 52.
  • the inductor 51 is appropriately formed in one or more layers in a rectangular spiral shape using a material such as aluminum, copper, or tungsten. The inductor 51 receives a signal transmitted from the inductor 42.
  • the transmission target signal is an analog signal
  • the transmission target signal is a digital signal.
  • the transmission method based on magnetic coupling using magnetism is exemplified as the transmission method based on the non-contact signal between the first semiconductor chip 11 and the second semiconductor chip 12. It is not limited to.
  • a transmission method using electrostatic coupling using an electric field can be exemplified.
  • FIG. 12 shows a principle diagram of a transmission method using electrostatic coupling.
  • two plate electrodes 61 and 62 are used. When a signal voltage is applied to one plate electrode 61, a signal voltage is induced on the other plate electrode 62 in proportion to the capacitance between the two plate electrodes 61 and 62. Signal transmission is performed by the electric field between the two plate electrodes 61 and 62.
  • one flat plate electrode 61 is formed on the first semiconductor chip 11 and the other flat plate electrode 62 is formed on the second semiconductor chip 12.
  • non-contact transmission of signals can be realized between the first semiconductor chip 11 and the second semiconductor chip 12.
  • the solid-state imaging device uses an imaging device such as a digital still camera and a video camera, a portable terminal device having an imaging function such as a mobile phone, and a solid-state imaging device for an image reading unit. It can be used as an imaging unit (image capturing unit) in electronic devices such as copying machines.
  • the above-described module form mounted on an electronic device, that is, a camera module is used as an imaging device.
  • FIG. 13 is a block diagram illustrating a configuration of an imaging apparatus that is an example of the electronic apparatus of the present disclosure.
  • an imaging apparatus 100 includes an optical system 101 including a lens group, an imaging unit 102, a DSP circuit 103 that is a camera signal processing unit, a frame memory 104, a display device 105, and a recording device 106. , An operation system 107, a power supply system 108, and the like.
  • the DSP circuit 103, the frame memory 104, the display device 105, the recording device 106, the operation system 107, and the power supply system 108 are connected to each other via a bus line 109.
  • the optical system 101 takes in incident light (image light) from a subject and forms an image on the imaging surface of the imaging unit 102.
  • the imaging unit 102 converts the amount of incident light imaged on the imaging surface by the optical system 101 into an electrical signal for each pixel and outputs the electrical signal as a pixel signal.
  • the DSP circuit 103 performs general camera signal processing, such as white balance processing, demosaic processing, and gamma correction processing.
  • the frame memory 104 is used for storing data as appropriate during the signal processing in the DSP circuit 103.
  • the display device 105 includes a panel type display device such as a liquid crystal display device or an organic EL (electroluminescence) display device, and displays a moving image or a still image captured by the imaging unit 102.
  • the recording device 106 records the moving image or still image captured by the imaging unit 102 on a recording medium such as a portable semiconductor memory, an optical disk, or an HDD (Hard Disk Disk Drive).
  • the operation system 107 issues operation commands for various functions of the imaging apparatus 100 under the operation of the user.
  • the power supply system 108 appropriately supplies various power supplies serving as operation power for the DSP circuit 103, the frame memory 104, the display device 105, the recording device 106, and the operation system 107 to these supply targets.
  • the solid-state imaging device according to the first and second embodiments described above can be used as the imaging unit 102.
  • this indication can also take the following structures.
  • a first semiconductor chip having a pixel array unit in which unit pixels for generating an electrical signal corresponding to incident light are arranged;
  • a second semiconductor chip having a signal processing unit that is stacked on the first semiconductor chip and that performs predetermined signal processing on an electrical signal generated by each unit pixel of the pixel array unit;
  • a signal transmission unit that transmits electrical signals in a non-contact manner between the first semiconductor chip and the second semiconductor chip;
  • a solid-state imaging device A solid-state imaging device.
  • the signal transmission unit transmits an electric signal between the first semiconductor chip and the second semiconductor chip by magnetic coupling of the inductor.
  • the unit pixel is a back-illuminated pixel.
  • the electrical signal transmitted by the signal transmission unit is an analog signal.
  • the electrical signal transmitted by the signal transmission unit is a digital signal.
  • the unit pixel has a function of converting an analog signal corresponding to incident light into a digital signal.
  • One or more inductors in the signal transmission unit are provided for one pixel column in the pixel array unit.
  • the solid-state imaging device according to any one of [2] to [6] above.
  • the inductor in the signal transmission unit is formed along each pixel column of the pixel array unit.
  • the solid-state imaging device according to [7] above.
  • One inductor in the signal transmission unit is provided for one unit pixel of the pixel array unit, or one for a pixel unit including a plurality of unit pixels.
  • the solid-state imaging device according to any one of [2] to [5] above.
  • the inductor in the signal transmission unit is formed on the substrate surface opposite to the light-receiving side substrate surface of the back-illuminated pixel of the first semiconductor chip.
  • the solid-state imaging device according to any one of [3] to [9] above.
  • a first semiconductor chip having a pixel array unit in which unit pixels for generating an electrical signal corresponding to incident light are arranged;
  • a second semiconductor chip having a signal processing unit that performs predetermined signal processing on an electrical signal generated by each unit pixel of the pixel array unit;
  • electrical signals are transmitted in a non-contact manner between the first semiconductor chip and the second semiconductor chip.
  • a method for driving a solid-state imaging device [12] An electric signal is transmitted between the first semiconductor chip and the second semiconductor chip by magnetic coupling of the inductor. The method for driving a solid-state imaging device according to [11] above.
  • the unit pixel is a back-illuminated pixel.
  • the method for driving a solid-state imaging device according to the above [11] or [12].
  • the electrical signal transmitted between the first semiconductor chip and the second semiconductor chip is an analog signal.
  • the method for driving a solid-state imaging device according to any one of [11] to [13].
  • the electrical signal transmitted between the first semiconductor chip and the second semiconductor chip is a digital signal.
  • the method for driving a solid-state imaging device according to any one of [11] to [13].
  • a first semiconductor chip having a pixel array unit in which unit pixels for generating an electrical signal corresponding to incident light are arranged;
  • a second semiconductor chip having a signal processing unit that is stacked on the first semiconductor chip and that performs predetermined signal processing on an electrical signal generated by each unit pixel of the pixel array unit;
  • a signal transmission unit that transmits electrical signals in a non-contact manner between the first semiconductor chip and the second semiconductor chip;
  • An electronic apparatus having a solid-state imaging device.
  • the signal transmission unit transmits an electric signal between the first semiconductor chip and the second semiconductor chip by magnetic coupling of the inductor.
  • the electronic device according to [16] above.
  • the unit pixel is a back-illuminated pixel.
  • the electronic device according to the above [16] or [17]. [19] The electrical signal transmitted by the signal transmission unit is an analog signal. The electronic device according to any one of [16] to [18]. [20] The electrical signal transmitted by the signal transmission unit is a digital signal. The electronic device according to any one of [16] to [18].
  • DESCRIPTION OF SYMBOLS 10 Stack type solid-state image sensor, 11 ... 1st semiconductor chip, 12 ... 2nd semiconductor chip, 13 ... Pixel array part (pixel part), 14, 17 ... Vertical scanning part, DESCRIPTION OF SYMBOLS 15 ... Signal processing part, 16 ... Horizontal scanning part, 20 ... Unit pixel, 21 ... Photodiode, 22 ... Transfer transistor, 23 ... Reset transistor, 24 ... Amplification transistor 25... Selection transistor, 26... Comparator, 27... Control transistor, 31 (31 1 to 31 m )... Pixel drive line, 32 (32 1 to 32 n ). 33 ... constant current source, 41 ... voltage-current converter, 42, 51 ... inductor (coil), 52 ... signal detector, 53 ... analog-digital converter (AD converter) 54 ... Memory 55 ... Column select switch, 56 ... signal output line, 57 ... reference voltage generating unit

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Abstract

Disclosed is a solid-state image pickup element that is provided with: a first semiconductor chip having a pixel array unit configured by disposing unit pixels that generate electric signals corresponding to incident light; a second semiconductor chip, which is laminated on the first semiconductor chip, and which has a signal processing unit that performs predetermined signal processing with respect to the electric signals generated by the unit pixels of the pixel array unit; and a signal transmission unit that performs, in a pixel array unit region, electric signal transmission between the first semiconductor chip and the second semiconductor chip in a non-contact manner.

Description

固体撮像素子、固体撮像素子の駆動方法、及び、電子機器Solid-state imaging device, driving method of solid-state imaging device, and electronic device
 本開示は、固体撮像素子、固体撮像素子の駆動方法、及び、電子機器に関する。 The present disclosure relates to a solid-state imaging device, a driving method of the solid-state imaging device, and an electronic device.
 固体撮像素子、特に、CMOS(Complementary Metal Oxide Semiconductor)イメージセンサは、低消費電力、高速性の優位性を活かし、携帯電話機、デジタルスチルカメラ、一眼レフカメラ、カムコーダ、監視用カメラ等の電子機器に広く搭載されるようになってきている。また、最近では、画像処理などの機能回路ブロックについても、画素アレイ部(画素部分)と一緒にオンチップ化した、高性能、高画質のイメージセンサも登場し始めている。 Solid-state image sensors, especially CMOS (Complementary Metal Oxide Semiconductor) image sensors, are used in electronic devices such as mobile phones, digital still cameras, single-lens reflex cameras, camcorders, and surveillance cameras, taking advantage of low power consumption and high speed. It is becoming widely installed. Recently, high-performance, high-quality image sensors that are on-chip together with the pixel array portion (pixel portion) are also appearing in functional circuit blocks such as image processing.
 近年、画素部分と回路部分とを別々の半導体チップ(半導体基板)上に形成し、これらの半導体チップを積層してなる積層型固体撮像素子の開発が、鋭意、進められている。この積層型固体撮像素子は、小型化、高画質化、高速化などを達成しつつ、多彩な機能を自由に組み込むことができる利点がある。 In recent years, the development of a stacked solid-state imaging device in which a pixel portion and a circuit portion are formed on separate semiconductor chips (semiconductor substrates) and these semiconductor chips are stacked has been earnestly advanced. This multilayer solid-state imaging device has an advantage that various functions can be freely incorporated while achieving miniaturization, high image quality, high speed, and the like.
 積層型固体撮像素子では、画素部側の半導体チップと回路部側の半導体チップとの間で信号を伝送するに当たって、両チップに位置を対応させてマイクロパッドを形成し、マイクロバンプによって両チップ間を電気的に接続するようにしている(例えば、特許文献1参照)。また、画素アレイ部の周辺領域において、磁気結合によって両チップ間で信号の伝送(伝達)を行うようにした技術も報告されている(例えば、非特許文献1参照)。 In a multilayer solid-state imaging device, when transmitting a signal between a semiconductor chip on the pixel unit side and a semiconductor chip on the circuit unit side, a micropad is formed corresponding to the position of both chips, and the microbumps are used to connect the two chips. Are electrically connected (for example, see Patent Document 1). In addition, a technique has been reported in which signals are transmitted (transmitted) between both chips by magnetic coupling in the peripheral region of the pixel array unit (see, for example, Non-Patent Document 1).
特開2006-49361号公報JP 2006-49361 A
 しかしながら、特許文献1に記載の従来技術のような、バンプによる導電体接続では、高度な加工技術が必要であるとともに、接続部分のばらつきや、ボイドの発生に起因する画質低下、歩留まり低下、製造コストの増加等の問題がある。また、TSV(Through Silicon Via)接続では、接合面も貫通させて半導体素子深部にまて形成する必要がある。また、形成可能なバンプのピッチに限度があるため、狭ピッチ化が困難である。 However, in the conductor connection by the bump as in the prior art described in Patent Document 1, a high level of processing technology is required, and the image quality, yield, and manufacturing due to variations in connection portions and the occurrence of voids are reduced. There are problems such as an increase in cost. In addition, in the TSV (Through Silicon Via) connection, it is necessary to penetrate the junction surface and form it deep in the semiconductor element. Moreover, since there is a limit to the pitch of bumps that can be formed, it is difficult to reduce the pitch.
 一方、非特許文献1に記載の従来技術では、画素アレイ部の周辺領域において、画素列毎に信号線を通して読み出される画素信号を伝送することになる。従って、磁気結合のためのインダクタ(コイル)を、画素アレイ部の周辺の限られた狭い領域に形成することになり、インダクタのレイアウト占有率を十分に確保できないために伝送効率が悪い。 On the other hand, in the conventional technique described in Non-Patent Document 1, a pixel signal read through a signal line is transmitted for each pixel column in the peripheral region of the pixel array unit. Therefore, an inductor (coil) for magnetic coupling is formed in a limited and narrow region around the pixel array portion, and the layout occupancy of the inductor cannot be secured sufficiently, resulting in poor transmission efficiency.
 そこで、本開示は、導電体接続での問題を解消しつつ、積層された半導体チップ間において、伝送効率の良い信号伝送を行うことが可能な固体撮像素子、固体撮像素子の駆動方法、及び、当該固体撮像素子を有する電子機器を提供することを目的とする。 Therefore, the present disclosure provides a solid-state imaging device capable of performing signal transmission with high transmission efficiency between stacked semiconductor chips while solving the problem of conductor connection, a driving method of the solid-state imaging device, and An object is to provide an electronic apparatus having the solid-state imaging element.
 上記の目的を達成するための本開示の固体撮像素子は、
 入射光に応じた電気信号を生成する単位画素が配置されて成る画素アレイ部を有する第1半導体チップと、
 第1半導体チップに対して積層され、画素アレイ部の各単位画素で生成された電気信号に対して所定の信号処理を施す信号処理部を有する第2半導体チップと、
 画素アレイ部の領域内において、第1半導体チップと第2半導体チップとの間で非接触にて電気信号の伝送を行う信号伝送部と、
 を備える。また、上記の目的を達成するための本開示の電子機器は、上記の構成の固体撮像素子を有する。
In order to achieve the above object, a solid-state imaging device of the present disclosure is provided.
A first semiconductor chip having a pixel array unit in which unit pixels for generating an electrical signal corresponding to incident light are arranged;
A second semiconductor chip having a signal processing unit that is stacked on the first semiconductor chip and that performs predetermined signal processing on an electrical signal generated by each unit pixel of the pixel array unit;
In the region of the pixel array unit, a signal transmission unit that transmits electrical signals in a non-contact manner between the first semiconductor chip and the second semiconductor chip;
Is provided. In addition, an electronic apparatus according to the present disclosure for achieving the above object includes the solid-state imaging device having the above configuration.
 上記の目的を達成するための本開示の固体撮像素子の駆動方法は、
 入射光に応じた電気信号を生成する単位画素が配置されて成る画素アレイ部を有する第1半導体チップと、
 画素アレイ部の各単位画素で生成された電気信号に対して所定の信号処理を施す信号処理部を有する第2半導体チップと、
 が積層されて成る固体撮像素子の駆動に当たって、
 画素アレイ部の領域内において、第1半導体チップと第2半導体チップとの間で非接触にて電気信号の伝送を行う。
In order to achieve the above object, a method for driving a solid-state imaging device of the present disclosure includes
A first semiconductor chip having a pixel array unit in which unit pixels for generating an electrical signal corresponding to incident light are arranged;
A second semiconductor chip having a signal processing unit that performs predetermined signal processing on an electrical signal generated by each unit pixel of the pixel array unit;
When driving a solid-state imaging device that is laminated,
In the region of the pixel array portion, electrical signals are transmitted in a non-contact manner between the first semiconductor chip and the second semiconductor chip.
 本開示によれば、画素アレイ部の領域内において、積層チップ間で信号の伝送を行うことで、信号伝送部を構成する素子のレイアウト占有率を十分に確保できるため、導電体接続での問題を解消しつつ、積層された半導体チップ間において、伝送効率の良い信号伝送を行うことができる。 According to the present disclosure, by transmitting signals between the stacked chips in the region of the pixel array unit, it is possible to sufficiently secure the layout occupancy of the elements constituting the signal transmission unit. Thus, signal transmission with high transmission efficiency can be performed between the stacked semiconductor chips.
 尚、ここに記載された効果に必ずしも限定されるものではなく、本明細書中に記載されたいずれかの効果であってもよい。また、本明細書に記載された効果はあくまで例示であって、これに限定されるものではなく、また付加的な効果があってもよい。 It should be noted that the effect described here is not necessarily limited, and may be any effect described in the present specification. Moreover, the effect described in this specification is an illustration to the last, Comprising: It is not limited to this, There may be an additional effect.
図1は、積層型固体撮像素子の基本的な構成の一例を示す概略構成図である。FIG. 1 is a schematic configuration diagram illustrating an example of a basic configuration of a stacked solid-state imaging device. 図2は、第1実施形態に係る固体撮像素子の全体の構成例を示すブロック図である。FIG. 2 is a block diagram illustrating an overall configuration example of the solid-state imaging device according to the first embodiment. 図3は、第1実施形態に係る固体撮像素子における単位画素及び電圧電流変換部の回路構成の一例を示す回路図である。FIG. 3 is a circuit diagram illustrating an example of a circuit configuration of a unit pixel and a voltage / current converter in the solid-state imaging device according to the first embodiment. 図4Aは、第1実施形態に係る固体撮像素子における信号検出部の回路構成の一例を示す回路図であり、図4Bは、AD変換器の回路構成の一例を示すブロック図である。FIG. 4A is a circuit diagram illustrating an example of a circuit configuration of a signal detection unit in the solid-state imaging device according to the first embodiment, and FIG. 4B is a block diagram illustrating an example of a circuit configuration of an AD converter. 図5は、第1実施形態に係る固体撮像素子の動作例の説明に供するタイミング波形図である。FIG. 5 is a timing waveform diagram for explaining an operation example of the solid-state imaging device according to the first embodiment. 図6は、第1実施形態に係る固体撮像素子における、第1半導体チップ側のインダクタ及び第2半導体チップ側のインダクタのレイアウトの一例を示す図である。FIG. 6 is a diagram illustrating an example of the layout of the inductor on the first semiconductor chip side and the inductor on the second semiconductor chip side in the solid-state imaging device according to the first embodiment. 図7は、第1実施形態に係る固体撮像素子における、第1半導体チップ側のインダクタ及び第2半導体チップ側のインダクタのレイアウトの他の例を示す図である。FIG. 7 is a diagram illustrating another example of the layout of the inductor on the first semiconductor chip side and the inductor on the second semiconductor chip side in the solid-state imaging device according to the first embodiment. 図8は、第2実施形態に係る固体撮像素子の全体の構成例を示すブロック図である。FIG. 8 is a block diagram illustrating an example of the overall configuration of the solid-state imaging device according to the second embodiment. 図9は、第2実施形態に係る固体撮像素子における第1半導体チップ側の単位画素及び第2半導体チップ側の信号検出部の回路構成の一例を示す回路図である。FIG. 9 is a circuit diagram illustrating an example of a circuit configuration of a unit pixel on the first semiconductor chip side and a signal detection unit on the second semiconductor chip side in the solid-state imaging device according to the second embodiment. 図10は、第2実施形態に係る固体撮像素子の動作例の説明に供するタイミング波形図である。FIG. 10 is a timing waveform diagram for explaining an operation example of the solid-state imaging device according to the second embodiment. 図11は、第4実施形態に係る固体撮像素子における、第1半導体チップ側のインダクタ及び第2半導体チップ側のインダクタのレイアウトの一例を示す図である。FIG. 11 is a diagram illustrating an example of the layout of the inductor on the first semiconductor chip side and the inductor on the second semiconductor chip side in the solid-state imaging device according to the fourth embodiment. 図12は、静電結合による伝送方式の原理図である。FIG. 12 is a principle diagram of a transmission method using electrostatic coupling. 図13は、本開示の電子機器の一例である撮像装置の構成を示すブロック図である。FIG. 13 is a block diagram illustrating a configuration of an imaging apparatus that is an example of the electronic apparatus of the present disclosure.
 以下、本開示の技術を実施するための形態(以下、「実施形態」と記述する)について図面を用いて詳細に説明する。本開示の技術は実施形態に限定されるものではなく、実施形態における種々の数値や材料などは例示である。以下の説明において、同一要素又は同一機能を有する要素には同一符号を用いることとし、重複する説明は省略する。尚、説明は以下の順序で行う。
1.本開示の固体撮像素子、その駆動方法、及び、電子機器、全般に関する説明
2.積層型固体撮像素子
3.第1実施形態(伝送対象の信号がアナログ信号の例)
4.第2実施形態(伝送対象の信号がデジタル信号の例)
5.変形例
6.本開示の電子機器(撮像装置の例)
Hereinafter, modes for carrying out the technology of the present disclosure (hereinafter referred to as “embodiments”) will be described in detail with reference to the drawings. The technology of the present disclosure is not limited to the embodiment, and various numerical values and materials in the embodiment are examples. In the following description, the same reference numerals are used for the same elements or elements having the same function, and redundant description is omitted. The description will be given in the following order.
1. 1. Description of the solid-state imaging device of the present disclosure, a driving method thereof, and an electronic device in general 2. Stacked solid-state imaging device First embodiment (an example where the signal to be transmitted is an analog signal)
4). Second Embodiment (Example in which a transmission target signal is a digital signal)
5). Modification 6 Electronic device of the present disclosure (example of imaging device)
<本開示の固体撮像素子、その駆動方法、及び、電子機器、全般に関する説明>
 本開示の固体撮像素子、その駆動方法、及び、電子機器にあっては、信号伝送部について、第1半導体チップと第2半導体チップとの間で、インダクタの磁気(磁界)結合によって電気信号の伝送を行う構成とすることができる。但し、信号伝送部としては、磁気結合による伝送方式に限られるものではなく、他の非接触による伝送方式、例えば、静電結合による伝送方式であってもよい。
<Description of Solid-State Imaging Device of the Present Disclosure, its Driving Method, and Electronic Device>
In the solid-state imaging device, the driving method thereof, and the electronic apparatus according to the present disclosure, an electric signal is transmitted between the first semiconductor chip and the second semiconductor chip by magnetic (magnetic field) coupling between the first semiconductor chip and the second semiconductor chip. It can be configured to perform transmission. However, the signal transmission unit is not limited to a transmission method using magnetic coupling, and may be another non-contact transmission method, for example, a transmission method using electrostatic coupling.
 上述した好ましい構成を含む本開示の固体撮像素子、その駆動方法、及び、電子機器にあっては、単位画素は、裏面照射型画素であることが好ましい。ここで、ここで、『裏面照射型画素』とは、配線層が配される側を表面側とするとき、その反対側、即ち裏面側から入射光を取り込む画素構造をいう。但し、単位画素は、裏面照射型画素に限られるものではなく、表面照射型画素であってもよい。ここで、『表面照射型画素』とは、配線層が配される表面側から入射光を取り込む画素構造をいう。 In the solid-state imaging device of the present disclosure including the preferable configuration described above, the driving method thereof, and the electronic device, the unit pixel is preferably a back-illuminated pixel. Here, the “backside illuminated pixel” refers to a pixel structure that takes in incident light from the opposite side, that is, the back side when the side on which the wiring layer is disposed is the front side. However, the unit pixel is not limited to the back-illuminated pixel, and may be a front-illuminated pixel. Here, the “front-illuminated pixel” refers to a pixel structure that captures incident light from the surface side where the wiring layer is disposed.
 更に、上述した好ましい構成を含む本開示の固体撮像素子、その駆動方法、及び、電子機器にあっては、信号伝送部が伝送する電気信号について、アナログ信号である構成とすることができる。 Furthermore, in the solid-state imaging device of the present disclosure including the preferable configuration described above, the driving method thereof, and the electronic device, the electrical signal transmitted by the signal transmission unit may be an analog signal.
 あるいは又、上述した好ましい構成を含む本開示の固体撮像素子、その駆動方法、及び、電子機器にあっては、信号伝送部が伝送する電気信号について、デジタル信号である構成とすることができる。このとき、単位画素は、入射光に応じた電気信号をデジタル信号に変換する機能を有する構成となる。 Alternatively, in the solid-state imaging device of the present disclosure including the preferable configuration described above, a driving method thereof, and an electronic device, the electrical signal transmitted by the signal transmission unit may be a digital signal. At this time, the unit pixel has a function of converting an electrical signal corresponding to incident light into a digital signal.
 更に、上述した好ましい構成を含む本開示の固体撮像素子、その駆動方法、及び、電子機器にあっては、信号伝送部におけるインダクタについて、画素アレイ部の一つの画素列に対して一つ以上設けられている構成とすることができる。あるいは又、信号伝送部におけるインダクタについて、画素アレイ部の各画素列に沿って形成されている構成とすることができる。 Further, in the solid-state imaging device of the present disclosure including the preferable configuration described above, a driving method thereof, and an electronic device, one or more inductors in the signal transmission unit are provided for one pixel column of the pixel array unit. It can be set as the structure currently provided. Alternatively, the inductor in the signal transmission unit may be formed along each pixel column of the pixel array unit.
 更に、上述した好ましい構成を含む本開示の固体撮像素子、その駆動方法、及び、電子機器にあっては、信号伝送部におけるインダクタについて、画素アレイ部の一つの単位画素に対して一つ、あるいは、複数の単位画素から成る画素ユニットに対して一つ設けられている構成とすることができる。あるいは又、信号伝送部におけるインダクタについて、第1半導体チップの裏面照射型画素の受光側基板面と反対側の基板面に形成されている構成とすることができる。 Further, in the solid-state imaging device of the present disclosure including the preferable configuration described above, a driving method thereof, and an electronic apparatus, one inductor for the signal transmission unit is provided for one unit pixel of the pixel array unit, or One pixel unit composed of a plurality of unit pixels can be provided. Alternatively, the inductor in the signal transmission unit may be formed on the substrate surface opposite to the light-receiving side substrate surface of the back-illuminated pixel of the first semiconductor chip.
<積層型固体撮像素子>
 先ず、本開示の技術が適用される積層型固体撮像素子について説明する。積層型固体撮像素子の基本的な構成の一例を図1に示す。積層型固体撮像素子10は、第1半導体チップ(半導体基板)11と第2半導体チップ12とを有し、例えば、第1半導体チップ11が上側のチップとし、第2半導体チップ12が下側のチップとして積層された構造(所謂、積層構造)となっている。
<Stacked solid-state image sensor>
First, a stacked solid-state imaging device to which the technology of the present disclosure is applied will be described. An example of a basic configuration of a stacked solid-state imaging device is shown in FIG. The stacked solid-state imaging device 10 includes a first semiconductor chip (semiconductor substrate) 11 and a second semiconductor chip 12. For example, the first semiconductor chip 11 is an upper chip and the second semiconductor chip 12 is a lower chip. It is a structure laminated as a chip (so-called laminated structure).
 この積層構造において、上側の第1半導体チップ11は、光電変換素子を含む単位画素(以下、単に『画素』と記述する場合がある)20が2次元マトリクス状(行列状)に配列されて成る画素アレイ部(画素部)13が形成された画素チップとなっている。本例に係る積層型固体撮像素子10にあっては、第1半導体チップ11には、画素アレイ部13の各画素20を垂直方向(列方向)において走査する垂直走査部14も搭載された構成となっている。尚、垂直走査部14については、第2半導体チップ12側に搭載する構成を採ることも可能である。垂直走査部14を第1半導体チップ11側及び第2半導体チップ12側のいずれに搭載するかは任意である。 In this stacked structure, the upper first semiconductor chip 11 is formed by arranging unit pixels (hereinafter simply referred to as “pixels”) 20 including photoelectric conversion elements in a two-dimensional matrix (matrix). This is a pixel chip in which a pixel array unit (pixel unit) 13 is formed. In the stacked solid-state imaging device 10 according to this example, the first semiconductor chip 11 is also equipped with a vertical scanning unit 14 that scans each pixel 20 of the pixel array unit 13 in the vertical direction (column direction). It has become. Note that the vertical scanning unit 14 may be mounted on the second semiconductor chip 12 side. It is arbitrary whether the vertical scanning unit 14 is mounted on the first semiconductor chip 11 side or the second semiconductor chip 12 side.
 下側の第2半導体チップ12は、第1半導体チップ11上に形成された画素アレイ部13の各画素20から読み出される画素信号に関する各種の処理を行う信号処理部15や水平走査部16などの回路部が形成された回路チップとなっている。信号処理部15は、画素アレイ部13の各画素20から読み出される画素信号に対して、アナログ-デジタル変換処理を含む所定の信号処理を施す。信号処理部15の詳細については後述する。水平走査部16は、信号処理部15で信号処理された行単位の画素信号を水平方向(行方向)において走査し、所定の順番で読み出す処理を行う。 The lower second semiconductor chip 12 includes a signal processing unit 15 and a horizontal scanning unit 16 that perform various processes related to pixel signals read from each pixel 20 of the pixel array unit 13 formed on the first semiconductor chip 11. The circuit chip is formed with a circuit portion. The signal processing unit 15 performs predetermined signal processing including analog-digital conversion processing on the pixel signal read from each pixel 20 of the pixel array unit 13. Details of the signal processing unit 15 will be described later. The horizontal scanning unit 16 scans the pixel signals in units of rows subjected to signal processing by the signal processing unit 15 in the horizontal direction (row direction), and performs processing of reading out in a predetermined order.
 上述した積層型(積層構造)の固体撮像素子10は、第1半導体チップ11として、画素アレイ部13を形成できる程度の大きさのもので済むために、第1半導体チップ11のサイズ、ひいては、固体撮像素子10全体のサイズを小さくできる。更に、第1半導体チップ11には画素20の作成に適したプロセスを、第2半導体チップ12には回路の作成に適したプロセスをそれぞれ適用できるために、積層型固体撮像素子10の製造に当たって、プロセスの最適化を図ることができるメリットもある。 Since the above-described stacked-type (laminated structure) solid-state imaging device 10 needs only to be large enough to form the pixel array section 13 as the first semiconductor chip 11, the size of the first semiconductor chip 11, and thus, The overall size of the solid-state imaging device 10 can be reduced. Furthermore, since a process suitable for the creation of the pixel 20 can be applied to the first semiconductor chip 11 and a process suitable for the creation of a circuit can be applied to the second semiconductor chip 12, respectively, in manufacturing the stacked solid-state imaging device 10, There is also an advantage that the process can be optimized.
<第1実施形態>
 第1実施形態に係る固体撮像素子は、上述した第1半導体チップ11と第2半導体チップ12とを積層して成る積層型固体撮像素子を前提としている。そして、第1実施形態に係る固体撮像素子10では、画素アレイ部13の領域内において、第1半導体チップ11と第2半導体チップ12との間で非接触にて電気信号の伝送を行うとともに、伝送対象の信号をアナログ信号としている。
<First Embodiment>
The solid-state imaging device according to the first embodiment is premised on a stacked solid-state imaging device formed by stacking the first semiconductor chip 11 and the second semiconductor chip 12 described above. In the solid-state imaging device 10 according to the first embodiment, in the region of the pixel array unit 13, electrical signals are transmitted in a non-contact manner between the first semiconductor chip 11 and the second semiconductor chip 12, and The signal to be transmitted is an analog signal.
 非接触による伝送方式として、磁気(磁界)結合による伝送方式や、静電結合による伝送方式などを例示することができる。本実施形態では、インダクタの磁気結合による伝送方式を用いて、第1半導体チップ11と第2半導体チップ12との間で電気信号の伝送を行うこととする。但し、磁気結合による伝送方式に限られるものではない。 Examples of non-contact transmission methods include a transmission method using magnetic (magnetic field) coupling and a transmission method using electrostatic coupling. In the present embodiment, an electrical signal is transmitted between the first semiconductor chip 11 and the second semiconductor chip 12 by using a transmission method using magnetic coupling of inductors. However, the transmission method is not limited to magnetic coupling.
 第1実施形態に係る固体撮像素子(積層型固体撮像素子)の全体の構成例を図2のブロック図に示す。図2には、主に、本開示の技術に関わる機能部のみを図示している。 FIG. 2 is a block diagram illustrating an example of the overall configuration of the solid-state imaging device (stacked solid-state imaging device) according to the first embodiment. FIG. 2 mainly shows only functional units related to the technology of the present disclosure.
(第1半導体チップ)
 第1半導体チップ11には、単位画素20がm行の画素行及びn列の画素列の2次元マトリクス状(行列状)に配列されて画素アレイ部13を構成している。この2次元マトリクス状の画素配列に対して、画素行毎に画素駆動線31(311~31m)が行方向に沿って配線され、画素列毎に信号線32(321~32n)が列方向に沿って配線されている。図2では、画素駆動線31について1本の配線として図示しているが、1本に限られるものではない。
(First semiconductor chip)
In the first semiconductor chip 11, unit pixels 20 are arranged in a two-dimensional matrix (matrix) of m pixel rows and n pixel columns to form a pixel array unit 13. For this two-dimensional matrix pixel arrangement, pixel drive lines 31 (31 1 to 31 m ) are wired along the row direction for each pixel row, and signal lines 32 (32 1 to 32 n ) are provided for each pixel column. Are wired along the column direction. In FIG. 2, the pixel drive line 31 is illustrated as one wiring, but is not limited to one.
 画素アレイ部13の行方向の一方側には、垂直走査部14が配置されている。垂直走査部14は、画素駆動線311~31mに対して、単位画素20から信号を読み出す際の駆動を行うための駆動信号を出力する。換言すれば、画素駆動線31_1~31_mは、各一端が垂直走査部14の各行に対応する各出力端に接続されており、これら出力端から出力される駆動信号を、画素行毎に単位画素20に伝送する。 On one side of the pixel array unit 13 in the row direction, a vertical scanning unit 14 is disposed. The vertical scanning unit 14 outputs a drive signal for driving when reading a signal from the unit pixel 20 to the pixel drive lines 31 1 to 31 m . In other words, one end of each of the pixel drive lines 31 _ 1 to 31 _m is connected to each output end corresponding to each row of the vertical scanning unit 14, and the drive signal output from these output ends is output for each pixel row. The data is transmitted to the unit pixel 20.
 垂直走査部14は、シフトレジスタやアドレスデコーダなどによって構成されており、画素アレイ部13の各画素20を全画素同時あるいは行単位等で駆動する。この垂直走査部14はその具体的な構成については図示を省略するが、一般的に、読出し走査系と掃出し走査系の2つの走査系を有する構成となっている。読出し走査系は、単位画素20から信号を読み出すために、画素アレイ部13の単位画素20を行単位で順に選択走査する。単位画素20から読み出される信号はアナログ信号である。掃出し走査系は、読出し走査系によって読出し走査が行われる読出し行に対して、その読出し走査よりもシャッタスピードの時間分だけ先行して掃出し走査を行う。 The vertical scanning unit 14 includes a shift register, an address decoder, and the like, and drives each pixel 20 of the pixel array unit 13 at the same time or in units of rows. Although the vertical scanning unit 14 is not shown in detail with respect to its specific configuration, the vertical scanning unit 14 generally has two scanning systems, a reading scanning system and a sweeping scanning system. The readout scanning system selectively scans the unit pixels 20 in the pixel array unit 13 in order in units of rows in order to read out signals from the unit pixels 20. A signal read from the unit pixel 20 is an analog signal. The sweep-out scanning system performs sweep-out scanning with respect to the readout row on which readout scanning is performed by the readout scanning system, preceding the readout scanning by a time corresponding to the shutter speed.
 この掃出し走査系による掃出し走査により、読出し行の単位画素20の光電変換素子から不要な電荷が掃き出されることによって当該光電変換素子がリセットされる。そして、この掃出し走査系によって不要電荷を掃き出す(リセットする)ことにより、所謂、電子シャッタ動作が行われる。ここで、電子シャッタ動作とは、光電変換素子の光電荷を捨てて、新たに露光を開始する(光電荷の蓄積を開始する)動作のことを言う。 By the sweep scanning by the sweep scanning system, unnecessary charges are swept out from the photoelectric conversion element of the unit pixel 20 in the readout row, thereby resetting the photoelectric conversion element. A so-called electronic shutter operation is performed by sweeping (resetting) unnecessary charges by the sweep scanning system. Here, the electronic shutter operation refers to an operation in which the photoelectric charge of the photoelectric conversion element is discarded and a new exposure is started (photocharge accumulation is started).
 読出し走査系による読出し動作によって読み出される信号は、その直前の読出し動作または電子シャッタ動作以降に受光した光量に対応するものである。そして、直前の読出し動作による読出しタイミングまたは電子シャッタ動作による掃出しタイミングから、今回の読出し動作による読出しタイミングまでの期間が、単位画素20における光電荷の露光期間となる。 The signal read out by the readout operation by the readout scanning system corresponds to the amount of light received after the immediately preceding readout operation or electronic shutter operation. A period from the read timing by the immediately preceding read operation or the sweep timing by the electronic shutter operation to the read timing by the current read operation is the photo charge exposure period in the unit pixel 20.
 画素アレイ部13の領域内において、信号線(列信号線/垂直信号線)321~32nの各一端側には、定電流源33が配置されている。電流源33は、一端が信号線321~32nの各一端に接続され、他端が固定電位(例えば、グランド)に接続されており、信号線321~32nに電流を供給する。信号線321~32nの各他端には、電圧電流変換部41及びインダクタ(コイル)42が配置されている。すなわち、電圧電流変換部41及びインダクタ42は、画素アレイ部13の画素列毎に設けられている。 In the region of the pixel array section 13, a constant current source 33 is disposed on each one end side of the signal lines (column signal lines / vertical signal lines) 32 1 to 32 n . The current source 33 has one end connected to one end of each of the signal lines 32 1 to 32 n and the other end connected to a fixed potential (for example, ground), and supplies current to the signal lines 32 1 to 32 n . A voltage / current converter 41 and an inductor (coil) 42 are disposed at each other end of the signal lines 32 1 to 32 n . That is, the voltage / current converter 41 and the inductor 42 are provided for each pixel column of the pixel array unit 13.
 電圧電流変換部41は、その入力端が信号線321~32nの各他端に接続されており、単位画素20への入射光量に応じて変化する信号線321~32nの電圧値を電流値に変換する。インダクタ42は、一端が電圧電流変換部41の出力端に接続され、他端が固定電位のノードに接続されており、電圧電流変換部41から出力される電流値の変化に応じた起電力を発生する。 Voltage-current conversion unit 41 is connected the input end to the other end of each of the signal lines 32 1 ~ 32 n, the signal lines 32 1 ~ 32 n voltage value of which varies according to the amount of incident light to the unit pixel 20 Is converted into a current value. The inductor 42 has one end connected to the output end of the voltage / current converter 41 and the other end connected to a node of a fixed potential, and generates an electromotive force according to a change in the current value output from the voltage / current converter 41. appear.
(第2半導体チップ)
 第2半導体チップ12には、第1半導体チップ11に画素列毎に設けられたインダクタ42に対応する位置にインダクタ51が設けられている。そして、第1半導体チップ11及び第2半導体チップ12が積層されることにより、インダクタ42及びインダクタ51も積層状態となる。これにより、第1半導体チップ11側のインダクタ42で生じた起電力は、相互誘導作用により、近接配置された第2半導体チップ12側のインダクタ51に伝達される。すなわち、第1半導体チップ11側のインダクタ42及び第2半導体チップ12側のインダクタ51は、第1半導体チップ11と第2半導体チップ12との間で非接触にて信号の伝送を行う信号伝送部を構成している。
(Second semiconductor chip)
The second semiconductor chip 12 is provided with an inductor 51 at a position corresponding to the inductor 42 provided for each pixel column in the first semiconductor chip 11. Then, by laminating the first semiconductor chip 11 and the second semiconductor chip 12, the inductor 42 and the inductor 51 are also laminated. As a result, the electromotive force generated in the inductor 42 on the first semiconductor chip 11 side is transmitted to the inductor 51 on the second semiconductor chip 12 side that is disposed in proximity by the mutual induction action. That is, the inductor 42 on the first semiconductor chip 11 side and the inductor 51 on the second semiconductor chip 12 side perform signal transmission between the first semiconductor chip 11 and the second semiconductor chip 12 in a contactless manner. Is configured.
 第2半導体チップ12には更に、インダクタ51に対応して、信号検出部52、アナログ-デジタル変換器(以下、『AD変換器』と記述する場合がある)53、メモリ54、及び、列選択スイッチ55が設けられている。すなわち、信号検出部52、AD変換器53、メモリ54、及び、列選択スイッチ55はインダクタ51と共に、第1半導体チップ11側の画素アレイ部13の画素列毎に設けられている。 The second semiconductor chip 12 further includes a signal detection unit 52, an analog-digital converter (hereinafter sometimes referred to as “AD converter”) 53, a memory 54, and a column selection corresponding to the inductor 51. A switch 55 is provided. That is, the signal detection unit 52, the AD converter 53, the memory 54, and the column selection switch 55 are provided for each pixel column of the pixel array unit 13 on the first semiconductor chip 11 side together with the inductor 51.
 そして、インダクタ51、信号検出部52、AD変換器53、メモリ54、及び、列選択スイッチ55は、第1半導体チップ11側の画素アレイ部13の各画素20から読み出される画素信号に対して、アナログ-デジタル変換処理を含む所定の信号処理を施す信号処理部15を構成している。第2半導体チップ12には更に、信号処理部15で信号処理された行単位の画素信号を水平方向において走査し、所定の順番で読み出す処理を行う水平走査部16が設けられている。水平走査部16は、シフトレジスタやアドレスデコーダなどによって構成される。 The inductor 51, the signal detection unit 52, the AD converter 53, the memory 54, and the column selection switch 55 are used for pixel signals read from the pixels 20 of the pixel array unit 13 on the first semiconductor chip 11 side. A signal processing unit 15 that performs predetermined signal processing including analog-digital conversion processing is configured. The second semiconductor chip 12 is further provided with a horizontal scanning unit 16 that performs scanning in the horizontal direction on the pixel signals for each row processed by the signal processing unit 15 and reads them in a predetermined order. The horizontal scanning unit 16 includes a shift register, an address decoder, and the like.
 第2半導体チップ12側のインダクタ51は、第1半導体チップ11側のインダクタ42で生じた起電力と同等の電圧を生じる。信号検出部52は、インダクタ51の電圧変化を検出し、アナログ画素信号に変換してAD変換器53に供給する。AD変換器53は、アナログ画素信号をデジタル画素信号に変換する。AD変換器53としては、周知のAD変換器を用いることができる。 The inductor 51 on the second semiconductor chip 12 side generates a voltage equivalent to the electromotive force generated by the inductor 42 on the first semiconductor chip 11 side. The signal detection unit 52 detects a voltage change of the inductor 51, converts it into an analog pixel signal, and supplies it to the AD converter 53. The AD converter 53 converts the analog pixel signal into a digital pixel signal. As the AD converter 53, a well-known AD converter can be used.
 周知のAD変換器として、シングルスロープ型AD変換器、逐次比較型AD変換器、又は、デルタ-シグマ変調型(ΔΣ変調型)AD変換器を例示することができる。また、AD変換器53は、グレイコードカウンタを備えていてもよい。但し、AD変換器53としては、これらに限定されるものではなく、フラッシュ型、ハーフ・フラッシュ型、サブレンシング型、パイプライン型、ビット・パー・ステージ型、マグニチュード・アンプ型等のAD変換器を挙げることもできる。 As a known AD converter, a single slope type AD converter, a successive approximation type AD converter, or a delta-sigma modulation type (ΔΣ modulation type) AD converter can be exemplified. Further, the AD converter 53 may include a gray code counter. However, the AD converter 53 is not limited to these, and an AD converter such as a flash type, a half flash type, a sublens type, a pipeline type, a bit per stage type, a magnitude amplifier type, etc. Can also be mentioned.
 メモリ54は、AD変換器53でアナログ-デジタル変換処理されたデジタル画素信号を格納する。列選択スイッチ55は、水平走査部16による走査の下に、オン状態となることによって、メモリ54に格納されたデジタル画素信号を信号出力線56へ読み出す。この読み出されたデジタル画素信号に対しては、必要に応じて、最終的な信号処理が行われる。その後、デジタル画像データとして第2半導体チップ12へ出力される。 The memory 54 stores the digital pixel signal that has been analog-digital converted by the AD converter 53. The column selection switch 55 reads the digital pixel signal stored in the memory 54 to the signal output line 56 when turned on under scanning by the horizontal scanning unit 16. The read digital pixel signal is subjected to final signal processing as necessary. Thereafter, the digital image data is output to the second semiconductor chip 12.
(単位画素及び電圧電流変換部)
 単位画素20及び電圧電流変換部41の回路構成の一例を図3に示す。本例に係る単位画素20は、光電変換素子として例えばフォトダイオード(PD)21を有している。図3に示すように、単位画素20は、フォトダイオード21に加えて、例えば、転送トランジスタ22、リセットトランジスタ23、増幅トランジスタ24、及び、選択トランジスタ25を有する構成となっている。
(Unit pixel and voltage-current converter)
An example of the circuit configuration of the unit pixel 20 and the voltage / current converter 41 is shown in FIG. The unit pixel 20 according to this example includes, for example, a photodiode (PD) 21 as a photoelectric conversion element. As shown in FIG. 3, the unit pixel 20 includes a transfer transistor 22, a reset transistor 23, an amplification transistor 24, and a selection transistor 25 in addition to the photodiode 21.
 尚、ここでは、転送トランジスタ22、リセットトランジスタ23、増幅トランジスタ24、及び、選択トランジスタ25の4つのトランジスタとして、例えばN型MOSFETを用いている。但し、ここで例示した4つのトランジスタ22~25の導電型の組み合わせは一例に過ぎず、これらの組み合わせに限られるものではない。 Here, for example, N-type MOSFETs are used as the four transistors of the transfer transistor 22, the reset transistor 23, the amplification transistor 24, and the selection transistor 25. However, the combination of the conductivity types of the four transistors 22 to 25 illustrated here is merely an example, and is not limited to these combinations.
 この単位画素20に対して、先述した画素駆動線31(311~31m)として、複数の駆動線311,312,313が同一画素行の各画素に対して共通に配線されている。複数の駆動線311,312,313は、垂直走査部14(図2参照)の各画素行に対応した出力端に画素行の単位で接続されている。垂直走査部14は、複数の駆動線311,312,313に対して転送信号TRX、リセット信号RST、及び、選択信号SELを適宜出力する。 For this unit pixel 20, a plurality of drive lines 311, 312, and 313 are wired in common to the pixels in the same pixel row as the pixel drive lines 31 (31 1 to 31 m ) described above. The plurality of drive lines 311, 312, 313 are connected to the output end corresponding to each pixel row of the vertical scanning unit 14 (see FIG. 2) in units of pixel rows. The vertical scanning unit 14 appropriately outputs a transfer signal TRX, a reset signal RST, and a selection signal SEL to the plurality of drive lines 311, 312, 313.
 フォトダイオード21は、アノード電極が低電位側電源(例えば、グランド)に接続されており、受光した光をその光量に応じた電荷量の光電荷(ここでは、光電子)に光電変換してその光電荷を蓄積する。フォトダイオード21のカソード電極は、転送トランジスタ22を介して増幅トランジスタ24のゲート電極と電気的に接続されている。増幅トランジスタ24のゲート電極と電気的に繋がった領域は、電荷を電圧に変換する電荷電圧変換部(電荷検出部)としてのフローティング・ディフュージョンFDである。 The photodiode 21 has an anode electrode connected to a low-potential-side power source (for example, ground), and photoelectrically converts received light into photocharge (here, photoelectrons) having a charge amount corresponding to the amount of light. Accumulate charge. The cathode electrode of the photodiode 21 is electrically connected to the gate electrode of the amplification transistor 24 through the transfer transistor 22. A region electrically connected to the gate electrode of the amplification transistor 24 is a floating diffusion FD as a charge-voltage conversion unit (charge detection unit) that converts charges into voltage.
 転送トランジスタ22は、フォトダイオード21のカソード電極とフローティング・ディフュージョンFDとの間に接続されている。転送トランジスタ22のゲート電極には、高レベル(例えば、Vddレベル)がアクティブ状態となる転送信号TRXが垂直走査部14から駆動線311を通して与えられる。転送トランジスタ22は、転送信号TRXに応答して導通状態となることで、フォトダイオード21で光電変換され、蓄積された光電荷をフローティング・ディフュージョンFDに転送する。 The transfer transistor 22 is connected between the cathode electrode of the photodiode 21 and the floating diffusion FD. A transfer signal TRX that activates a high level (for example, V dd level) is applied to the gate electrode of the transfer transistor 22 from the vertical scanning unit 14 through the drive line 311. When the transfer transistor 22 is turned on in response to the transfer signal TRX, it is photoelectrically converted by the photodiode 21 and transfers the accumulated photocharge to the floating diffusion FD.
 リセットトランジスタ23は、ドレイン電極が電源電位Vddのノード(電源線)に接続され、ソース電極がフローティング・ディフュージョンFDに接続されている。リセットトランジスタ23のゲート電極には、高レベルがアクティブ状態となるリセット信号RSTが垂直走査部14から駆動線312を通して与えられる。リセットトランジスタ23は、リセット信号RSTに応答して導通状態となり、フローティング・ディフュージョンFDの電荷を電源電位Vddのノードに捨てることによってフローティング・ディフュージョンFDをリセットする。 The reset transistor 23 has a drain electrode connected to a node (power supply line) of the power supply potential Vdd , and a source electrode connected to the floating diffusion FD. A reset signal RST that activates a high level is applied to the gate electrode of the reset transistor 23 from the vertical scanning unit 14 through the drive line 312. Reset transistor 23 becomes conductive in response to a reset signal RST, which resets the floating diffusion FD by discarding the charge of the floating diffusion FD to a node of the power supply potential V dd.
 増幅トランジスタ24は、ゲート電極がフローティング・ディフュージョンFDに接続され、ドレイン電極が電源電位Vddのノードに接続されている。この増幅トランジスタ24は、フォトダイオード21での光電変換によって得られる信号を読み出す読出し回路であるソースフォロワの入力部となる。すなわち、増幅トランジスタ24は、ソース電極が選択トランジスタ25を介して信号線32に接続されることで、当該信号線32の端部に接続された電流源33とソースフォロワを構成する。 The amplification transistor 24 has a gate electrode connected to the floating diffusion FD and a drain electrode connected to the node of the power supply potential Vdd . The amplification transistor 24 serves as an input section of a source follower that is a readout circuit that reads a signal obtained by photoelectric conversion at the photodiode 21. That is, the amplifying transistor 24 forms a source follower with the current source 33 connected to the end of the signal line 32 by connecting the source electrode to the signal line 32 via the selection transistor 25.
 選択トランジスタ25は、例えば、ドレイン電極が増幅トランジスタ24のソース電極に接続され、ソース電極が信号線32に接続されている。選択トランジスタ25のゲート電極には、高レベルがアクティブ状態となる選択信号SELが垂直走査部14から駆動線313を通して与えられる。選択トランジスタ25は、選択信号SELに応答して導通状態となることで、単位画素20を選択状態として増幅トランジスタ24から出力される信号を信号線32に伝達する。 The selection transistor 25 has, for example, a drain electrode connected to the source electrode of the amplification transistor 24 and a source electrode connected to the signal line 32. A selection signal SEL that activates a high level is supplied from the vertical scanning unit 14 to the gate electrode of the selection transistor 25 through the drive line 313. The selection transistor 25 becomes conductive in response to the selection signal SEL, and transmits the signal output from the amplification transistor 24 to the signal line 32 with the unit pixel 20 selected.
 尚、選択トランジスタ25については、電源電位Vddのノードと増幅トランジスタ24のドレイン電極との間に接続した回路構成を採ることも可能である。また、本例では、単位画素20の画素回路として、転送トランジスタ22、リセットトランジスタ23、増幅トランジスタ24、及び、選択トランジスタ25から成る、即ち4つのトランジスタ(Tr)から成る4Tr構成を例に挙げたが、これに限られるものではない。例えば、選択トランジスタ25を省略し、増幅トランジスタ24に選択トランジスタ25の機能を持たせた3Tr構成とすることもできるし、必要に応じて、トランジスタの数を増やした構成とすることもできる。 Note that the selection transistor 25 may have a circuit configuration connected between the node of the power supply potential Vdd and the drain electrode of the amplification transistor 24. In this example, as a pixel circuit of the unit pixel 20, a 4Tr configuration including the transfer transistor 22, the reset transistor 23, the amplification transistor 24, and the selection transistor 25, that is, four transistors (Tr) is given as an example. However, it is not limited to this. For example, the selection transistor 25 may be omitted, and a 3Tr configuration in which the amplification transistor 24 has the function of the selection transistor 25 may be used, or a configuration in which the number of transistors is increased as necessary.
 図3に示すように、電圧電流変換部41は、オペアンプ411、MOSトランジスタ412、及び、抵抗素子413を有する構成となっている。オペアンプ411は、その非反転(+)入力端子が信号線32に接続されている。MOSトランジスタ412は、ゲート電極がオペアンプ411の出力端子に接続され、ソース電極がオペアンプ411の反転(-)入力端子に接続されている。抵抗素子413は、一端がMOSトランジスタ412のソース電極に接続され、他端が低電位側電源(例えば、グランド)に接続されている。 As shown in FIG. 3, the voltage / current converter 41 includes an operational amplifier 411, a MOS transistor 412, and a resistance element 413. The operational amplifier 411 has a non-inverting (+) input terminal connected to the signal line 32. The MOS transistor 412 has a gate electrode connected to the output terminal of the operational amplifier 411 and a source electrode connected to the inverting (−) input terminal of the operational amplifier 411. One end of the resistance element 413 is connected to the source electrode of the MOS transistor 412, and the other end is connected to a low potential side power source (for example, ground).
 ここで、MOSトランジスタ412のドレイン電極が、電圧電流変換部41の出力端となる。そして、インダクタ42は、一端が電圧電流変換部41の出力端、即ちMOSトランジスタ412のドレイン電極に接続され、他端が固定電位、例えば電源電位Vddのノード(電源線)に接続されている。 Here, the drain electrode of the MOS transistor 412 serves as the output terminal of the voltage-current converter 41. The inductor 42 has one end connected to the output end of the voltage-current converter 41, that is, the drain electrode of the MOS transistor 412, and the other end connected to a node (power supply line) of a fixed potential, for example, the power supply potential Vdd . .
 上記の構成の電圧電流変換部41において、インダクタ42からMOSトランジスタ412に流れる電流Iは、抵抗素子413を通してグランドに流れるため、抵抗素子413の抵抗値をRとすると、抵抗素子413の両端間電圧はI×Rとなる。そして、オペアンプ411は、2つの入力端子間の電位差がゼロになるイマジナリ・ショートにより、抵抗素子413の両端間電圧I×Rと、オペアンプ411の非反転(+)入力電圧とが等しくなるように動作する。これにより、単位画素20の入射光量に応じで変化する信号線32の電圧が抵抗素子413の両端間電圧I×Rとなるように、MOSトランジスタ412に流れる電流Iが変化する。このとき、インダクタ42に流れる電流は同じくIである。 In the voltage-current converter 41 having the above configuration, the current I flowing from the inductor 42 to the MOS transistor 412 flows to the ground through the resistance element 413. Therefore, when the resistance value of the resistance element 413 is R, the voltage across the resistance element 413 is Becomes I × R. The operational amplifier 411 is configured so that the voltage I × R between both ends of the resistance element 413 and the non-inverting (+) input voltage of the operational amplifier 411 become equal due to an imaginary short in which the potential difference between the two input terminals becomes zero. Operate. As a result, the current I flowing through the MOS transistor 412 changes so that the voltage of the signal line 32 that changes according to the amount of incident light of the unit pixel 20 becomes the voltage I × R across the resistor 413. At this time, the current flowing through the inductor 42 is also I.
 信号線32の電圧が電流Iに変換されることにより、次式(1)のような、画素信号に応じた誘導起電力Vがインダクタ42に生じる。
   V=-L(ΔV/ΔI)  ・・・(1)
ここで、Lはインダクタ42のインダクタンスであり、L=μS/l×N2である。また、μは透磁率、Sはコイルの断面積、lはコイルの長さ、Nはコイルの巻き数である。
By converting the voltage of the signal line 32 into the current I, an induced electromotive force V corresponding to the pixel signal is generated in the inductor 42 as shown in the following equation (1).
V = −L (ΔV / ΔI) (1)
Here, L is the inductance of the inductor 42, and L = μS / l × N 2 . Further, μ is the magnetic permeability, S is the cross-sectional area of the coil, l is the length of the coil, and N is the number of turns of the coil.
(信号検出部及びAD変換器)
 信号検出部52の回路構成の一例を図4Aに示し、AD変換器53の回路構成の一例を図4Bに示す。図4Aに示すように、信号検出部52は、ダイオード521及び容量素子522から成る整流回路の構成となっている。ダイオード521は、アノード電極がインダクタ51の一端に接続され、カソード電極が容量素子522の一方の電極に接続されている。容量素子522は、他方の電極がインダクタ51の他端に接続されている。
(Signal detection unit and AD converter)
An example of the circuit configuration of the signal detector 52 is shown in FIG. 4A, and an example of the circuit configuration of the AD converter 53 is shown in FIG. 4B. As illustrated in FIG. 4A, the signal detection unit 52 has a rectifier circuit configuration including a diode 521 and a capacitor 522. The diode 521 has an anode electrode connected to one end of the inductor 51 and a cathode electrode connected to one electrode of the capacitor 522. The other electrode of the capacitive element 522 is connected to the other end of the inductor 51.
 本例では、AD変換器53として、例えば、シングルスロープ型AD変換器を用いる場合を例に挙げる。シングルスロープ型AD変換器では、時間が経過するにつれて電圧値が階段状に変化する、所謂、ランプ(RAMP)波形(傾斜状の波形)の参照電圧Vrefが用いられる。ランプ波形の参照電圧Vrefは、参照電圧生成部57で生成される。参照電圧生成部57については、例えば、DAC(デジタル-アナログ変換)回路を用いて構成することができる。 In this example, a case where a single slope AD converter is used as the AD converter 53 is taken as an example. In the single slope AD converter, a reference voltage V ref having a so-called ramp (RAMP) waveform (gradient waveform) in which the voltage value changes stepwise as time passes is used. Reference voltage V ref of the ramp waveform is generated by the reference voltage generator 57. The reference voltage generation unit 57 can be configured using, for example, a DAC (digital-analog conversion) circuit.
 AD変換器53は、例えば、コンパレータ531及びカウンタ532から成る。本例に係るAD変換器53では、カウンタ532として、アップ/ダウンカウンタ(図中、『U/DCNT』と記している)を用いている。コンパレータ531は、画素アレイ部13の各画素20から読み出される画素信号を比較入力とし、参照電圧生成部57から供給されるランプ波の参照電圧Vrefを基準入力とし、両者を比較する。そして、コンパレータ531は、例えば、参照電圧Vrefが画素信号よりも大きいときに出力が第1の状態(例えば、高レベル)になり、参照電圧Vrefが画素信号以下のときに出力が第2の状態(例えば、低レベル)になる。これにより、コンパレータ531の出力信号は、画素信号のレベルの大きさに対応したパルス幅を持つパルス信号となる。 The AD converter 53 includes, for example, a comparator 531 and a counter 532. In the AD converter 53 according to this example, an up / down counter (denoted as “U / DCNT” in the drawing) is used as the counter 532. The comparator 531 uses the pixel signal read from each pixel 20 of the pixel array unit 13 as a comparison input, uses the reference voltage Vref of the ramp wave supplied from the reference voltage generation unit 57 as a reference input, and compares the two. The comparator 531, for example, the reference voltage V ref is output when larger than the pixel signal is a first state (e.g., high level) and the output reference voltage V ref when: the pixel signal and the second (For example, low level). As a result, the output signal of the comparator 531 becomes a pulse signal having a pulse width corresponding to the level of the pixel signal.
 アップ/ダウンカウンタ532には、コンパレータ531に対する参照電圧Vrefの供給開始タイミングと同じタイミングでクロックCKが与えられる。そして、アップ/ダウンカウンタ532は、クロックCKに同期してダウン(DOWN)カウント、又は、アップ(UP)カウントを行うことにより、コンパレータ531の出力パルスのパルス幅の期間、即ち、比較動作の開始から比較動作の終了までの比較期間を計測する。このアップ/ダウンカウンタ532のカウント結果(カウント値)が、アナログの画素信号をデジタル化したデジタル値となり、メモリ54に格納される。そして、水平走査部16(図2参照)による走査の下に、メモリ54からアナログの画素信号をAD変換して得られるデジタル値が適宜読み出される。 The up / down counter 532 is supplied with the clock CK at the same timing as the supply start timing of the reference voltage V ref to the comparator 531. Then, the up / down counter 532 performs a down (DOWN) count or an up (UP) count in synchronization with the clock CK, so that the period of the pulse width of the output pulse of the comparator 531, that is, the start of the comparison operation. The comparison period from the end of the comparison operation to the end of the comparison operation is measured. The count result (count value) of the up / down counter 532 becomes a digital value obtained by digitizing an analog pixel signal and is stored in the memory 54. Then, under scanning by the horizontal scanning unit 16 (see FIG. 2), a digital value obtained by AD converting an analog pixel signal from the memory 54 is appropriately read out.
 画素20が2次元マトリクス状に配列されて成る固体撮像素子(CMOSイメージセンサ)では、一般的に、画素20のリセット動作時のノイズを除去するために、相関二重サンプリング(Correlated Double Sampling:CDS)によるノイズ除去処理が行わる。画素20からは、例えば、リセットレベルVrst及び信号レベルVsigの順に読み出される。リセットレベルVrstは、画素20のフローティング・ディフュージョンFDをリセットしたときのフローティング・ディフュージョンFDの電位に相当する。信号レベルVsigは、フォトダイオード21に蓄積された電荷をフローティング・ディフュージョンFDへ転送したときのフローティング・ディフュージョンFDの電位に相当する。 In a solid-state imaging device (CMOS image sensor) in which the pixels 20 are arranged in a two-dimensional matrix, generally, correlated double sampling (CDS) is performed in order to remove noise during the reset operation of the pixels 20. ) To remove noise. For example, the reset level V rst and the signal level V sig are read from the pixel 20 in this order. The reset level V rst corresponds to the potential of the floating diffusion FD when the floating diffusion FD of the pixel 20 is reset. The signal level V sig is equivalent to the potential of the floating diffusion FD when the transfer charge stored in the photodiode 21 to the floating diffusion FD.
 リセットレベルVrstを先に読み出す読み出し方式においては、リセットしたときに発生するランダムノイズはフローティング・ディフュージョンFDで保持されているため、信号電荷を加えて読み出された信号レベルVsigには、リセットレベルVrstと同じノイズ量が保持されている。このため、信号レベルVsigからリセットレベルVrstを減算する相関二重サンプリング動作を行うことにより、これらのノイズを除去した信号を得ることが可能となる。 In the reading method for reading the reset level V rst above, since the random noise generated when the reset is held in the floating diffusion FD, and the signal level V sig read added signal charges, reset The same amount of noise as level V rst is retained. For this reason, it is possible to obtain a signal from which these noises are removed by performing a correlated double sampling operation in which the reset level V rst is subtracted from the signal level V sig .
 上記の構成のシングルスロープ型AD変換器53では、AD変換の際に、相関二重サンプリング処理が実行される。具体的には、AD変換器53では、コンパレータ531での比較動作の開始から比較動作の終了までの比較期間の計測動作の際に、アップ/ダウンカウンタ532は、例えば、リセットレベルVrstに対してはダウンカウントを行い、信号レベルVsigに対してはアップカウントを行う。このダウンカウント/アップカウントの動作により、信号レベルVsigとリセットレベルVrstとの差分をとることができる。その結果、AD変換器53によるAD変換の際に、相関二重サンプリングによるノイズ除去処理が行われる。 In the single slope AD converter 53 having the above configuration, a correlated double sampling process is executed during AD conversion. Specifically, in the AD converter 53, during the measurement operation in the comparison period from the start of the comparison operation in the comparator 531 to the end of the comparison operation, the up / down counter 532 is, for example, the reset level V rst Down-counting, and up-counting is performed on the signal level V sig . By this down count / up count operation, the difference between the signal level V sig and the reset level V rst can be obtained. As a result, noise removal processing by correlated double sampling is performed during AD conversion by the AD converter 53.
(動作例)
 ここで、第1実施形態に係る固体撮像素子10の動作例について、図5のタイミング波形図を用いて説明する。図5のタイミング波形図には、単位画素20を駆動する転送信号TRX、リセット信号RST、及び、選択信号SELのタイミング関係を示している。図5のタイミング波形図には更に、信号線32の電位、インダクタ42に流れる電流(コイル電流)、インダクタ42に生じる誘導起電力、及び、信号検出部52の出力電圧の各変化を併せて示している。
(Operation example)
Here, an operation example of the solid-state imaging device 10 according to the first embodiment will be described with reference to a timing waveform diagram of FIG. The timing waveform diagram of FIG. 5 shows the timing relationship of the transfer signal TRX, the reset signal RST, and the selection signal SEL that drive the unit pixel 20. The timing waveform diagram of FIG. 5 further shows changes in the potential of the signal line 32, the current flowing through the inductor 42 (coil current), the induced electromotive force generated in the inductor 42, and the output voltage of the signal detector 52. ing.
 まず時刻t1にて、リセット信号RSTが高レベルから低レベルに遷移することで、リセットトランジスタ23が非導通状態になる。これにより、フローティング・ディフュージョンFD、即ち増幅トランジスタ24のゲート電極のリセットが解除され、単位画素20は非リセット状態になる。このとき、増幅トランジスタ24のゲート電極は暗時(ダーク)に対応する電位に固定される。 First, at time t 1 , the reset signal RST transitions from a high level to a low level, so that the reset transistor 23 is turned off. As a result, the reset of the floating diffusion FD, that is, the gate electrode of the amplification transistor 24 is released, and the unit pixel 20 enters a non-reset state. At this time, the gate electrode of the amplifying transistor 24 is fixed to a potential corresponding to darkness (dark).
 また、時刻t1では、このとき既に選択信号SELが低レベルから高レベルに遷移し、選択トランジスタ25が導通状態になっているため、単位画素20の暗時出力が信号線32に表れている。インダクタ42に流れる電流値は信号線32の電圧で決まる。そして、信号線32の電圧の変化量のピーク値が、インダクタ42を通じて第2半導体チップ12側の信号検出部52でクランプされることになる。 At time t 1 , the selection signal SEL already transitions from the low level to the high level at this time, and the selection transistor 25 is in the conductive state, so that the dark output of the unit pixel 20 appears on the signal line 32. . The value of the current flowing through the inductor 42 is determined by the voltage of the signal line 32. Then, the peak value of the voltage change amount of the signal line 32 is clamped by the signal detection unit 52 on the second semiconductor chip 12 side through the inductor 42.
 続いて、時刻t2にて、転送信号TRXが低レベルから高レベルに遷移することで、転送トランジスタ22が導通状態となる。これにより、フォトダイオード21に蓄積された光電荷がフローティング・ディフュージョンFDに転送される。このとき、入射光量に応じて、例えば暗時(ダーク)、中間光量、高光量で、信号線32に現れる電圧とインダクタ42に流れる電流(コイル電流)は異なる。そして、インダクタ42に生じる誘導起電力を通して、信号検出部52の出力電圧は図5に示すような変化を示す。 Subsequently, at time t 2, the transfer signal TRX is makes a transition from a low level to a high level, the transfer transistor 22 becomes conductive. Thereby, the photoelectric charge accumulated in the photodiode 21 is transferred to the floating diffusion FD. At this time, the voltage appearing on the signal line 32 and the current flowing through the inductor 42 (coil current) differ depending on the amount of incident light, for example, in the dark (dark), intermediate light amount, and high light amount. Then, through the induced electromotive force generated in the inductor 42, the output voltage of the signal detection unit 52 changes as shown in FIG.
 先述したように、AD変換器53において、時刻t1後に得られるリセットレベルVrstと、時刻t2後に得られる信号レベルVsigとの差分をとることにより、相関二重サンプリング動作を実現することができる。その結果、単位画素20のリセット動作時のノイズを除去することができるため、良好な撮像画像を得ることができる。 As described above, in the AD converter 53, the correlated double sampling operation is realized by taking the difference between the reset level V rst obtained after time t 1 and the signal level V sig obtained after time t 2. Can do. As a result, since noise during the reset operation of the unit pixel 20 can be removed, a good captured image can be obtained.
(インダクタのレイアウトの一例)
 ここで、第1実施形態に係る固体撮像素子10における、第1半導体チップ11側のインダクタ42及び第2半導体チップ12側のインダクタ51のレイアウトについて説明する。第1半導体チップ11側のインダクタ42及び第2半導体チップ12側のインダクタ51のレイアウトの一例を図6に示す。
(Example of inductor layout)
Here, the layout of the inductor 42 on the first semiconductor chip 11 side and the inductor 51 on the second semiconductor chip 12 side in the solid-state imaging device 10 according to the first embodiment will be described. An example of the layout of the inductor 42 on the first semiconductor chip 11 side and the inductor 51 on the second semiconductor chip 12 side is shown in FIG.
 第1実施形態に係る固体撮像素子10において、単位画素20は、裏面照射型画素及び表面照射型画素のいずれであってもよい。但し、以下の理由により、単位画素20として、裏面照射型画素を用いることが好ましい。 In the solid-state imaging device 10 according to the first embodiment, the unit pixel 20 may be either a back-side illuminated pixel or a front-side illuminated pixel. However, it is preferable to use a back-illuminated pixel as the unit pixel 20 for the following reason.
 第1半導体チップ11において、単位画素20は裏面照射型画素から成ることで、インダクタ42は、基板の表面側、即ち、裏面照射型画素の受光側基板面と反対側の基板面に形成されることになる。これにより、光電変換素子(フォトダイオード21)に入射する光が、インダクタ42によって妨げられることはない。 In the first semiconductor chip 11, the unit pixel 20 is composed of a back-illuminated pixel, and the inductor 42 is formed on the front surface side of the substrate, that is, on the substrate surface opposite to the light-receiving side substrate surface of the back-illuminated pixel. It will be. Thereby, the light incident on the photoelectric conversion element (photodiode 21) is not blocked by the inductor 42.
 インダクタ42は、図6に示すように、画素アレイ部13の画素列に沿って形成されることが好ましい。また、インダクタ42は、基板の表面側に、アルミニウムや銅やタングステンなどの材料を用いて矩形(長方形)の渦巻き状に、1層又は複数層で適宜形成される。ここでは、インダクタ42の形状として、長方形を例示したが、これに限られるものではなく、起電力を生じることができればその形状は問わない。 The inductor 42 is preferably formed along the pixel column of the pixel array unit 13 as shown in FIG. Further, the inductor 42 is appropriately formed in one or more layers in a rectangular (rectangular) spiral shape using a material such as aluminum, copper, or tungsten on the surface side of the substrate. Here, the rectangular shape is exemplified as the shape of the inductor 42, but the shape is not limited to this, and the shape is not limited as long as an electromotive force can be generated.
 インダクタ42のインダクタンスLは、先述した式(1)のように、インダクタ42の巻き数(巻線数)や面積に応じて大きくなり、誘導起電力Vとして表れる。従って、第1半導体チップ11と第2半導体チップ12との間における信号伝送効率を上げるには、なるべく細い配線で巻き数と面積を大きくすべきである。また、伝送先のインダクタ51と近接していることで、漏れなくより伝送効率を高めることができる。この点で、単位画素20が裏面照射型画素から成る固体撮像素子10では、画素アレイ部13の1画素列分の画素領域の全域を使ってインダクタ42を形成することができるため有効である。第1半導体チップ11側のインダクタ42と第2半導体チップ12側のインダクタ51とは、絶縁破壊しない程度の厚さの絶縁膜(図示せず)を介して近接することになる。 The inductance L of the inductor 42 increases according to the number of turns (the number of windings) and the area of the inductor 42 and is expressed as an induced electromotive force V as in the above-described equation (1). Therefore, in order to increase the signal transmission efficiency between the first semiconductor chip 11 and the second semiconductor chip 12, the number of turns and the area should be increased with as thin a wiring as possible. Further, by being close to the transmission destination inductor 51, transmission efficiency can be further improved without leakage. In this respect, the solid-state imaging device 10 in which the unit pixel 20 is a back-illuminated pixel is effective because the inductor 42 can be formed using the entire pixel area of one pixel column of the pixel array unit 13. The inductor 42 on the first semiconductor chip 11 side and the inductor 51 on the second semiconductor chip 12 side are close to each other through an insulating film (not shown) having a thickness that does not cause dielectric breakdown.
 第2半導体チップ12において、第1半導体チップ11からの信号を送信するインダクタ42に対し、第1半導体チップ11と第2半導体チップ12とを積層した際に、インダクタ42と近接した状態になるようにインダクタ51が形成される。インダクタ51は、インダクタ42と同様に、アルミニウムや銅やタングステンなどの材料を用いて矩形渦巻き状に、1層又は複数層で適宜形成される。そして、インダクタ51は、インダクタ42から送信される信号を受信する。 In the second semiconductor chip 12, when the first semiconductor chip 11 and the second semiconductor chip 12 are stacked with respect to the inductor 42 that transmits a signal from the first semiconductor chip 11, the second semiconductor chip 12 is in a state of being close to the inductor 42. Inductor 51 is formed. Similarly to the inductor 42, the inductor 51 is appropriately formed in one or more layers in a rectangular spiral shape using a material such as aluminum, copper, or tungsten. The inductor 51 receives a signal transmitted from the inductor 42.
 本レイアウト例では、インダクタ51と信号検出部52とが順次並列に配置された構成を例示しているが、この構成例に限られるものではない。インダクタ51と、信号検出部52を構成する配線層とが異なって形成可能であれば、第2半導体チップ12の基板面に垂直な方向において、インダクタ51と信号検出部52とが重ねて配置された構成とすることも可能である。 This layout example illustrates a configuration in which the inductor 51 and the signal detection unit 52 are sequentially arranged in parallel, but is not limited to this configuration example. If the inductor 51 and the wiring layer constituting the signal detection unit 52 can be formed differently, the inductor 51 and the signal detection unit 52 are arranged so as to overlap in the direction perpendicular to the substrate surface of the second semiconductor chip 12. It is also possible to adopt a configuration.
(インダクタのレイアウトの他の例)
 第1半導体チップ11側のインダクタ42及び第2半導体チップ12側のインダクタ51のレイアウトの他の例を図7に示す。
(Other examples of inductor layout)
FIG. 7 shows another example of the layout of the inductor 42 on the first semiconductor chip 11 side and the inductor 51 on the second semiconductor chip 12 side.
 画素アレイ部13において、1画素列に対して信号線32を複数配線する場合がある。図7は、画素アレイ部13の各画素20を垂直方向(列方向)において例えば上下に2分割し、これに対応して信号線32を1画素列に対して上側の画素用と下側の画素用に2本配線する例を示している。ここで、上側の画素用の配線を信号線32aとし、下側の画素用の配線を信号線32bとする。すなわち、図7の例では、1画素列に対して上下に分割された2本の信号線32a,32bが配線された構成となってい。但し、1画素列毎の信号線32の本数は2本に限られるものではなく、3本以上であってもよい。 In the pixel array unit 13, a plurality of signal lines 32 may be provided for one pixel column. In FIG. 7, each pixel 20 of the pixel array unit 13 is divided into, for example, two vertically in the vertical direction (column direction), and the signal lines 32 corresponding to the upper and lower pixel lines with respect to one pixel column corresponding to this. An example in which two wires are arranged for a pixel is shown. Here, the upper pixel wiring is referred to as a signal line 32a, and the lower pixel wiring is referred to as a signal line 32b. That is, in the example of FIG. 7, two signal lines 32a and 32b divided vertically are arranged for one pixel column. However, the number of signal lines 32 for each pixel column is not limited to two, and may be three or more.
 本レイアウト例では、図7に示すように、第1半導体チップ11において、信号線32の本数に応じて、1画素列に対して複数のインダクタ42が形成するようにする。具体的には、上側の画素用として、インダクタ42aを形成し、これに対応して電圧電流変換部41aを形成する。同様に、下側の画素用として、インダクタ42bを形成し、これに対応して電圧電流変換部41bを形成する。 In this layout example, as shown in FIG. 7, in the first semiconductor chip 11, a plurality of inductors 42 are formed for one pixel column according to the number of signal lines 32. Specifically, the inductor 42a is formed for the upper pixel, and the voltage-current converter 41a is formed correspondingly. Similarly, an inductor 42b is formed for the lower pixel, and a voltage / current converter 41b is formed correspondingly.
 第2半導体チップ12においても、第1半導体チップ11側のインダクタ42に対応して、1画素列に対して複数のインダクタ51を形成するようにする。具体的には、上側の画素用として、インダクタ51aを形成し、これに対応して信号検出部52a及びAD変換器53aを形成する。同様に、下側の画素用として、インダクタ51aを形成し、これに対応して信号検出部52b及びAD変換器53bを形成する。 Also in the second semiconductor chip 12, a plurality of inductors 51 are formed for one pixel column corresponding to the inductor 42 on the first semiconductor chip 11 side. Specifically, an inductor 51a is formed for the upper pixel, and a signal detection unit 52a and an AD converter 53a are formed correspondingly. Similarly, an inductor 51a is formed for the lower pixel, and a signal detector 52b and an AD converter 53b are formed correspondingly.
 以上説明したように、第1実施形態に係る固体撮像素子10では、画素アレイ部13の領域内において、第1半導体チップ11と第2半導体チップ12との間で、磁気結合による非接触にて信号伝送を行うようにしているため、伝送効率の良い信号伝送を行うことができる。具体的には、磁気結合による信号伝送部を構成する素子(インダクタ42、インダクタ51)のレイアウト占有率を、画素アレイ部13の周辺の狭い領域に形成する場合よりも十分に確保できるため、伝送効率の良い信号伝送を行うことができる。 As described above, in the solid-state imaging device 10 according to the first embodiment, the first semiconductor chip 11 and the second semiconductor chip 12 are non-contacted by magnetic coupling in the region of the pixel array unit 13. Since signal transmission is performed, signal transmission with high transmission efficiency can be performed. Specifically, the layout occupancy of the elements (inductor 42 and inductor 51) constituting the signal transmission unit by magnetic coupling can be sufficiently secured as compared with the case where the layout is formed in a narrow region around the pixel array unit 13. Efficient signal transmission can be performed.
 特に、単位画素20として裏面照射型画素を用いることで、受光側基板面と反対側の基板面にインダクタ42を形成することができるため、インダクタ42のレイアウトの自由度が上がり、インダクタ42のレイアウト占有率をより十分に確保できるとともに、積層されるインダクタ42,51を近接して配置できる。このとき、光電変換素子(フォトダイオード21)に入射する光が、インダクタ42によって妨げられることもない。 In particular, by using a back-illuminated pixel as the unit pixel 20, the inductor 42 can be formed on the substrate surface opposite to the light-receiving side substrate surface. Therefore, the degree of freedom in the layout of the inductor 42 is increased, and the layout of the inductor 42 is increased. The occupation ratio can be secured more sufficiently, and the laminated inductors 42 and 51 can be arranged close to each other. At this time, light incident on the photoelectric conversion element (photodiode 21) is not blocked by the inductor 42.
 また、信号の伝送方式が磁気結合による方式であることで、バンプによる導電体接続での問題も解消できる。すなわち、バンプ等により接続する場合とは異なり、電極となる金属面が露出していないため、静電破壊により固体撮像素子や信号処理部の構成素子が破壊されるといった問題はなく、歩留まりを向上させることができる。更に、静電破壊対策のための保護素子を形成する必要がないため、固体撮像素子の小型化及び信号伝達の高速化を図ることができる。 Also, since the signal transmission method is a magnetic coupling method, the problem of conductor connection by bumps can be solved. In other words, unlike the case of connecting with bumps and the like, the metal surface that becomes the electrode is not exposed, so there is no problem that the solid-state image sensor and the component of the signal processing unit are destroyed by electrostatic breakdown, and the yield is improved. Can be made. Furthermore, since it is not necessary to form a protective element for countermeasures against electrostatic breakdown, it is possible to reduce the size of the solid-state imaging device and speed up signal transmission.
 また、第1実施形態に係る固体撮像素子10では、第1半導体チップ11側から第2半導体チップ12側に伝送する伝送対象の信号をアナログ信号(アナログ画素信号)としている。この場合、信号線32の電位が静定する前の過渡状態を検出し、第2半導体チップ12側へ伝送することになるため、静定後の信号線32の電位をAD変換した後、画素アレイ部13の周辺領域へ読み出して伝送する方式(例えば、非特許文献1参照)よりも早期に伝送することが可能となる。これにより、アナログ画素信号の読出し速度の高速化が可能になる。因みに、アナログ画素信号をAD変換した後に、画素アレイ部13の周辺領域へ読み出すようにした場合、AD変換後の画素信号の伝送となるため、第2半導体チップ12側に伝送するまでに時間を要することになる。 Further, in the solid-state imaging device 10 according to the first embodiment, the transmission target signal transmitted from the first semiconductor chip 11 side to the second semiconductor chip 12 side is an analog signal (analog pixel signal). In this case, since the transient state before the potential of the signal line 32 is settled is detected and transmitted to the second semiconductor chip 12 side, the potential of the signal line 32 after the stabilization is AD-converted, and then the pixel Transmission can be performed earlier than the method of reading and transmitting to the peripheral region of the array unit 13 (see, for example, Non-Patent Document 1). As a result, the reading speed of the analog pixel signal can be increased. Incidentally, when the analog pixel signal is AD-converted and then read out to the peripheral area of the pixel array unit 13, the pixel signal after AD conversion is transmitted, so that it takes time to transmit to the second semiconductor chip 12 side. It will take.
 また、第1実施形態に係る固体撮像素子10では、インダクタ42を画素アレイ部13の画素列に沿って形成するようにしているために(図6参照)、インダクタ42を信号線(列信号線/垂直信号線)32と平行にレイアウトすることになる。これにより、信号線32とインダクタ42との間の寄生容量による容量結合によって、信号線32の電位の変化に対して、インダクタ42に生じる起電力の応答を追従させることができるため、信号伝送のより高速化を図ることができる。 Further, in the solid-state imaging device 10 according to the first embodiment, since the inductor 42 is formed along the pixel column of the pixel array unit 13 (see FIG. 6), the inductor 42 is connected to the signal line (column signal line). / Vertical signal line) 32 is laid out in parallel. As a result, the capacitive coupling due to the parasitic capacitance between the signal line 32 and the inductor 42 allows the response of the electromotive force generated in the inductor 42 to follow the change in the potential of the signal line 32. Higher speed can be achieved.
<第2実施形態>
 第2実施形態に係る固体撮像素子も、第1実施形態に係る固体撮像素子と同様に、積層型固体撮像素子を前提とし、画素アレイ部13の領域内において、第1半導体チップ11と第2半導体チップ12との間で非接触にて電気信号の伝送を行う。但し、第1実施形態に係る固体撮像素子では、伝送対象の信号をアナログ信号としているのに対して、第2実施形態に係る固体撮像素子では、伝送対象の信号をデジタル信号としている。
Second Embodiment
Similarly to the solid-state image sensor according to the first embodiment, the solid-state image sensor according to the second embodiment is also based on a stacked solid-state image sensor, and the first semiconductor chip 11 and the second semiconductor chip 11 Electric signals are transmitted to and from the semiconductor chip 12 in a non-contact manner. However, in the solid-state imaging device according to the first embodiment, the signal to be transmitted is an analog signal, whereas in the solid-state imaging device according to the second embodiment, the signal to be transmitted is a digital signal.
 第2実施形態に係る固体撮像素子(積層型固体撮像素子)の全体の構成例を図8のブロック図に示し、第1半導体チップ側の単位画素及び第2半導体チップ側の信号検出部のの回路構成の一例を図9の回路図に示す。図8には、主に、本開示の技術に関わる機能部のみを図示している。 FIG. 8 is a block diagram illustrating an overall configuration example of a solid-state imaging device (stacked solid-state imaging device) according to the second embodiment. The unit pixel on the first semiconductor chip side and the signal detection unit on the second semiconductor chip side An example of the circuit configuration is shown in the circuit diagram of FIG. FIG. 8 mainly illustrates only functional units related to the technology of the present disclosure.
(第1半導体チップ)
 第1半導体チップ11において、2次元マトリクス状に配列された単位画素20は、入射光に応じたアナログ信号をデジタル信号に変換するAD変換機能を備えた構成となっている。具体的には、単位画素20は、フォトダイオード21、転送トランジスタ22、及び、リセットトランジスタ23に加えて、コンパレータ26及び制御トランジスタ27を有する構成となっている。コンパレータ26は、図4Bに示すAD変換器(ADC)53におけるコンパレータ531に相当する。
(First semiconductor chip)
In the first semiconductor chip 11, the unit pixels 20 arranged in a two-dimensional matrix are configured to have an AD conversion function for converting an analog signal corresponding to incident light into a digital signal. Specifically, the unit pixel 20 includes a comparator 26 and a control transistor 27 in addition to the photodiode 21, the transfer transistor 22, and the reset transistor 23. The comparator 26 corresponds to the comparator 531 in the AD converter (ADC) 53 shown in FIG. 4B.
 コンパレータ26は、フローティング・ディフュージョンFDの電位を比較入力とし、ランプ波の参照電圧Vrefを基準入力とし、両者を比較する。参照電圧Vrefは、参照電圧生成部57(図4B参照))で生成される。コンパレータ26は、転送トランジスタ22によってフォトダイオード21から信号電荷が転送されたときのフローティング・ディフュージョンFDの電位(信号レベル)を、ランプ波の参照電圧Vrefと比較することで、単位画素20の信号をデジタル化する。コンパレータ26の比較出力は、制御トランジスタ27のゲート入力となる。 The comparator 26 uses the potential of the floating diffusion FD as a comparison input and the reference voltage V ref of the ramp wave as a reference input, and compares the two. The reference voltage V ref is generated by the reference voltage generator 57 (see FIG. 4B). The comparator 26 compares the potential (signal level) of the floating diffusion FD when the signal charge is transferred from the photodiode 21 by the transfer transistor 22 with the reference voltage V ref of the ramp wave, thereby comparing the signal of the unit pixel 20. Digitize. The comparison output of the comparator 26 becomes the gate input of the control transistor 27.
 第2実施形態に係る固体撮像素子10にあっては、第1半導体チップ11側のインダクタ42は、画素アレイ部13の一つの単位画素20に対して一つ設けられる。但し、これに限られるものではなく、例えば、隣接する複数の単位画素20をユニットとして画素アレイ部13の各画素20を分割する構成を採る場合、複数の単位画素20から成る画素ユニットに対してインダクタ42を一つ設ける構成とすることも可能である。 In the solid-state imaging device 10 according to the second embodiment, one inductor 42 on the first semiconductor chip 11 side is provided for one unit pixel 20 of the pixel array unit 13. However, the present invention is not limited to this. For example, when a configuration in which each pixel 20 of the pixel array unit 13 is divided using a plurality of adjacent unit pixels 20 as a unit, a pixel unit including a plurality of unit pixels 20 is used. A configuration in which one inductor 42 is provided is also possible.
 インダクタ42は、単位画素20の各々の制御トランジスタ27のドレイン電極と、高電位(例えば、電源電位Vdd)側電源との間に接続されている。制御トランジスタ27のソース電極は、抵抗素子28を介して低電位側電源(例えば、グランド)に接続されている。これにより、制御トランジスタ27は、コンパレータ26の比較出力に応じて、インダクタ42に流れる電流をオン/オフ制御する。 The inductor 42 is connected between the drain electrode of each control transistor 27 of the unit pixel 20 and the power source on the high potential (for example, power supply potential V dd ) side. The source electrode of the control transistor 27 is connected to a low potential side power source (for example, ground) via the resistance element 28. As a result, the control transistor 27 performs on / off control of the current flowing through the inductor 42 in accordance with the comparison output of the comparator 26.
 具体的には、コンパレータ26は、フローティング・ディフュージョンFDの電位がランプ波の参照電圧Vrefと一致したタイミングで高レベルの出力を発生する。これを受けて、制御トランジスタ27が導通状態になることにより、電源電位Vddから、インダクタ42、制御トランジスタ27、及び、抵抗素子28を通してグランドに電流が流れる。このとき、インダクタ42において、流れる電流に応じた起電力が発生し、相互誘導作用により、第2半導体チップ12側のインダクタ51へ伝送される。 Specifically, the comparator 26 generates a high-level output at the timing when the potential of the floating diffusion FD matches the reference voltage Vref of the ramp wave. In response to this, the control transistor 27 becomes conductive, whereby a current flows from the power supply potential V dd to the ground through the inductor 42, the control transistor 27, and the resistance element 28. At this time, an electromotive force corresponding to the flowing current is generated in the inductor 42 and is transmitted to the inductor 51 on the second semiconductor chip 12 side by a mutual induction effect.
(第2半導体チップ)
 第2半導体チップ12において、信号検出部52は、抵抗素子523、容量素子524、カウンタ525、及び、メモリ526を有する構成となっている。抵抗素子523及び容量素子524は、インダクタ51の両端に接続されており、相互誘導作用により、第1半導体チップ11側のインダクタ42から信号が伝送されることで、インダクタ51に発生する起電力を矩形波に変換する。この矩形波のパルス幅は、単位画素20の画素信号のレベルに対応する。
(Second semiconductor chip)
In the second semiconductor chip 12, the signal detection unit 52 includes a resistance element 523, a capacitance element 524, a counter 525, and a memory 526. The resistive element 523 and the capacitive element 524 are connected to both ends of the inductor 51, and a signal is transmitted from the inductor 42 on the first semiconductor chip 11 side due to mutual induction, thereby generating an electromotive force generated in the inductor 51. Convert to square wave. The pulse width of this rectangular wave corresponds to the level of the pixel signal of the unit pixel 20.
 カウンタ525は、図4Bに示すAD変換器53におけるカウンタ532に相当し、例えばアップ/ダウンカウンタから成る。カウンタ525には、単位画素20のコンパレータ26に対する参照信号Vrefの供給開始タイミングと同じタイミングでクロックCKが与えられる。そして、カウンタ525は、クロックCKに同期してダウンカウント、又は、アップカウントを行うことにより、抵抗素子523及び容量素子524によって変換された矩形波のパルス幅の期間、即ち、コンパレータ26の比較動作の開始から比較動作の終了までの比較期間を計測する。 The counter 525 corresponds to the counter 532 in the AD converter 53 shown in FIG. 4B, and includes, for example, an up / down counter. The counter 525 is supplied with the clock CK at the same timing as the supply start timing of the reference signal V ref to the comparator 26 of the unit pixel 20. The counter 525 performs down-counting or up-counting in synchronization with the clock CK, so that the pulse width period of the rectangular wave converted by the resistor 523 and the capacitor 524, that is, the comparison operation of the comparator 26 is performed. The comparison period from the start to the end of the comparison operation is measured.
 カウンタ525の計測結果は、メモリ526に格納される。メモリ526は、図2に示す信号処理部15におけるメモリ54に相当する。そして、垂直走査部14による垂直走査及び水平走査部16による水平走査により、信号検出部52が順次選択され、その選択された信号検出部52のメモリ526からデジタル信号が、列選択スイッチ55を通して信号出力線56へ読み出す。この読み出されたデジタル画素信号に対しては、必要に応じて、最終的な信号処理が行われる。その後、デジタル画像データとして第2半導体チップ12へ出力される。 The measurement result of the counter 525 is stored in the memory 526. The memory 526 corresponds to the memory 54 in the signal processing unit 15 illustrated in FIG. The signal detection unit 52 is sequentially selected by the vertical scanning by the vertical scanning unit 14 and the horizontal scanning by the horizontal scanning unit 16, and a digital signal is transmitted from the memory 526 of the selected signal detection unit 52 through the column selection switch 55. Read to output line 56. The read digital pixel signal is subjected to final signal processing as necessary. Thereafter, the digital image data is output to the second semiconductor chip 12.
 ここで、第2実施形態に係る固体撮像素子10の動作例について、図10のタイミング波形図を用いて説明する。図10のタイミング波形図には、単位画素20を駆動するリセット信号RST及び転送信号TRXのタイミング関係を示している。図10のタイミング波形図には更に、コンパレータ26の比較出力、インダクタ42に流れる電流(コイル電流)、インダクタ42に生じる誘導起電力、及び、信号検出部52の出力電圧の各変化を併せて示している。 Here, an operation example of the solid-state imaging device 10 according to the second embodiment will be described with reference to a timing waveform diagram of FIG. The timing waveform diagram of FIG. 10 shows the timing relationship between the reset signal RST and the transfer signal TRX that drive the unit pixel 20. The timing waveform diagram of FIG. 10 further shows changes in the comparison output of the comparator 26, the current flowing through the inductor 42 (coil current), the induced electromotive force generated in the inductor 42, and the output voltage of the signal detection unit 52. ing.
 まず時刻t1にて、リセット信号RSTが高レベルから低レベルに遷移することで、リセットトランジスタ23が非導通状態になる。これにより、フローティング・ディフュージョンFD、即ちコンパレータ26の入力端のリセットが解除され、単位画素20は非リセット状態になる。このとき、コンパレータ26の入力端は暗時(ダーク)に対応する電位に固定される。 First, at time t 1 , the reset signal RST transitions from a high level to a low level, so that the reset transistor 23 is turned off. As a result, the reset of the floating diffusion FD, that is, the input end of the comparator 26, is released, and the unit pixel 20 enters a non-reset state. At this time, the input terminal of the comparator 26 is fixed at a potential corresponding to darkness.
 その後、コンパレータ26において、フローティング・ディフュージョンFDの電位とランプ波の参照電圧Vrefとの比較が行われる。そして、その比較結果に応じて、コンパレータ26から論理“0”/“1”の判定電位が出力される。コンパレータ26の判定電位が論理“1”(高レベル)のとき、制御トランジスタ27が導通状態となり、インダクタ42に電流(コイル電流)が流れる。そして、コイル電流の変化点において、インダクタ42に誘導起電力が生じ、相互誘導作用により、第2半導体チップ12側のインダクタ51へ伝送される。この信号伝送により、信号検出部52で矩形波の生成が行われる。そして、信号検出部52において、矩形波のパルス幅の時間カウントがカウンタ525で行われ、その計測結果がメモリ526に格納される。 Thereafter, the comparator 26 compares the potential of the floating diffusion FD with the reference voltage V ref of the ramp wave. Then, a determination potential of logic “0” / “1” is output from the comparator 26 according to the comparison result. When the determination potential of the comparator 26 is logic “1” (high level), the control transistor 27 becomes conductive, and a current (coil current) flows through the inductor 42. Then, an induced electromotive force is generated in the inductor 42 at the change point of the coil current, and is transmitted to the inductor 51 on the second semiconductor chip 12 side by mutual induction. By this signal transmission, the signal detector 52 generates a rectangular wave. Then, in the signal detection unit 52, the counter 525 counts the pulse width of the rectangular wave, and the measurement result is stored in the memory 526.
 続いて、時刻t2にて、転送信号TRXが低レベルから高レベルに遷移することで、転送トランジスタ22が導通状態となる。これにより、フォトダイオード21に蓄積された光電荷がフローティング・ディフュージョンFDに転送される。そして、コンパレータ26において、フローティング・ディフュージョンFDの電位とランプ波の参照電圧Vrefとの比較が行われ、その比較結果に応じて、コンパレータ26から論理“0”/“1”の判定電位が出力される。このとき、入射光量に応じたタイミングで、インダクタ42において誘導起電力が生じ、相互誘導作用により、第2半導体チップ12側のインダクタ51へ伝送される。また、信号検出部52において、矩形波の生成、当該矩形波のパルス幅の時間カウントが行われ、その計測結果がメモリ526に格納される。 Subsequently, at time t 2, the transfer signal TRX is makes a transition from a low level to a high level, the transfer transistor 22 becomes conductive. Thereby, the photoelectric charge accumulated in the photodiode 21 is transferred to the floating diffusion FD. The comparator 26 compares the potential of the floating diffusion FD and the reference voltage V ref of the ramp wave, and outputs a determination potential of logic “0” / “1” from the comparator 26 according to the comparison result. Is done. At this time, an induced electromotive force is generated in the inductor 42 at a timing according to the amount of incident light, and is transmitted to the inductor 51 on the second semiconductor chip 12 side by mutual induction. In addition, the signal detection unit 52 generates a rectangular wave and counts the pulse width of the rectangular wave, and stores the measurement result in the memory 526.
 第2実施形態に係る固体撮像素子10においても、カウンタ525として、アップ/ダウンカウンタを用いることで、AD変換の際に、相関二重サンプリング動作を実現することができる。これにより、単位画素20のリセット動作時のノイズを除去することができるため、良好な撮像画像を得ることができる。 Also in the solid-state imaging device 10 according to the second embodiment, by using an up / down counter as the counter 525, a correlated double sampling operation can be realized during AD conversion. Thereby, noise during the reset operation of the unit pixel 20 can be removed, so that a good captured image can be obtained.
(インダクタのレイアウト)
 ここで、第2実施形態に係る固体撮像素子10における、第1半導体チップ11側のインダクタ42及び第2半導体チップ12側のインダクタ51のレイアウトについて説明する。第1半導体チップ11側のインダクタ42及び第2半導体チップ12側のインダクタ51のレイアウトの一例を図11に示す。
(Inductor layout)
Here, the layout of the inductor 42 on the first semiconductor chip 11 side and the inductor 51 on the second semiconductor chip 12 side in the solid-state imaging device 10 according to the second embodiment will be described. An example of the layout of the inductor 42 on the first semiconductor chip 11 side and the inductor 51 on the second semiconductor chip 12 side is shown in FIG.
 第2実施形態に係る固体撮像素子10において、単位画素20は、裏面照射型画素及び表面照射型画素のいずれであってもよい。但し、第1実施形態で述べた理由により、単位画素20として、裏面照射型画素を用いることが好ましい。 In the solid-state imaging device 10 according to the second embodiment, the unit pixel 20 may be either a back-illuminated pixel or a front-illuminated pixel. However, for the reason described in the first embodiment, it is preferable to use a back-illuminated pixel as the unit pixel 20.
 第1半導体チップ11において、インダクタ42は、図11に示すように、単位画素20毎に一つ形成されることが好ましい。また、インダクタ42は、基板の表面側に、アルミニウムや銅やタングステンなどの材料を用いて矩形(長方形)の渦巻き状に、1層又は複数層で適宜形成される。ここでは、インダクタ42の形状として、長方形を例示したが、これに限られるものではなく、起電力を生じることができればその形状は問わない。 In the first semiconductor chip 11, one inductor 42 is preferably formed for each unit pixel 20, as shown in FIG. Further, the inductor 42 is appropriately formed in one or more layers in a rectangular (rectangular) spiral shape using a material such as aluminum, copper, or tungsten on the surface side of the substrate. Here, the rectangular shape is exemplified as the shape of the inductor 42, but the shape is not limited to this, and the shape is not limited as long as an electromotive force can be generated.
 第2半導体チップ12において、第1半導体チップ11からの信号を送信するインダクタ42に対し、第1半導体チップ11と第2半導体チップ12とを積層した際に、インダクタ42と近接した状態になるように、信号検出部52毎にインダクタ51が一つ形成される。インダクタ51は、インダクタ42と同様に、アルミニウムや銅やタングステンなどの材料を用いて矩形渦巻き状に、1層又は複数層で適宜形成される。そして、インダクタ51は、インダクタ42から送信される信号を受信する。 In the second semiconductor chip 12, when the first semiconductor chip 11 and the second semiconductor chip 12 are stacked with respect to the inductor 42 that transmits a signal from the first semiconductor chip 11, the second semiconductor chip 12 is in a state of being close to the inductor 42. In addition, one inductor 51 is formed for each signal detector 52. Similarly to the inductor 42, the inductor 51 is appropriately formed in one or more layers in a rectangular spiral shape using a material such as aluminum, copper, or tungsten. The inductor 51 receives a signal transmitted from the inductor 42.
 以上説明したように、第2実施形態に係る固体撮像素子10でも、画素アレイ部13の領域内において、第1半導体チップ11と第2半導体チップ12との間で、磁気結合による非接触にて信号伝送を行うようにしているため、伝送効率の良い信号伝送を行うことができる。また、第1実施形態に係る固体撮像素子10では、伝送対象の信号がアナログ信号であるのに対して、本実施形態に係る固体撮像素子10では、伝送対象の信号がデジタル信号である。このように、単位画素20毎にAD変換したデジタル画素信号を伝送する構成を採ることで、物理接続を必要としたバンプの狭ピッチ化が解消され、微細画素の積層を可能にすることができる。 As described above, even in the solid-state imaging device 10 according to the second embodiment, the first semiconductor chip 11 and the second semiconductor chip 12 are contacted by magnetic coupling in the region of the pixel array unit 13. Since signal transmission is performed, signal transmission with high transmission efficiency can be performed. In the solid-state imaging device 10 according to the first embodiment, the transmission target signal is an analog signal, whereas in the solid-state imaging device 10 according to the present embodiment, the transmission target signal is a digital signal. In this way, by adopting a configuration for transmitting a digital pixel signal that is AD-converted for each unit pixel 20, the narrow pitch of bumps that require physical connection is eliminated, and it is possible to stack fine pixels. .
<変形例>
 以上、本開示を好ましい実施形態に基づき説明したが、本開示はこれらの実施形態に限定されるものではない。上記の各実施形態において説明した固体撮像素子の構成、構造、固体撮像素子の駆動方法の構成は例示であり、適宜、変更することができる。
<Modification>
Although the present disclosure has been described based on the preferred embodiments, the present disclosure is not limited to these embodiments. The configuration and structure of the solid-state imaging device described in the above embodiments and the configuration of the driving method of the solid-state imaging device are examples, and can be changed as appropriate.
 例えば、上記の各実施形態では、第1半導体チップ11と第2半導体チップ12との間における信号の非接触による伝送方式として、磁気(磁界)を用いる磁気結合による伝送方式を例示したが、これに限られるものではない。非接触による他の伝送方式として、例えば、電界を用いる静電結合による伝送方式を例示することができる。静電結合による伝送方式の原理図を図12に示す。静電結合による伝送方式では、二つの平板電極61,62を用いる。そして、一方の平板電極61に信号電圧を印加すると、二つの平板電極61,62間の静電容量に比例して、他方の平板電極62に信号電圧が誘起される。信号の伝送は、二つの平板電極61,62間の電界が担うことになる。 For example, in each of the above-described embodiments, the transmission method based on magnetic coupling using magnetism (magnetic field) is exemplified as the transmission method based on the non-contact signal between the first semiconductor chip 11 and the second semiconductor chip 12. It is not limited to. As another non-contact transmission method, for example, a transmission method using electrostatic coupling using an electric field can be exemplified. FIG. 12 shows a principle diagram of a transmission method using electrostatic coupling. In the transmission method using electrostatic coupling, two plate electrodes 61 and 62 are used. When a signal voltage is applied to one plate electrode 61, a signal voltage is induced on the other plate electrode 62 in proportion to the capacitance between the two plate electrodes 61 and 62. Signal transmission is performed by the electric field between the two plate electrodes 61 and 62.
 従って、非接触による伝送方式として、静電結合による伝送方式を用いる場合は、一方の平板電極61を第1半導体チップ11に形成し、他方の平板電極62を第2半導体チップ12に形成することで、第1半導体チップ11と第2半導体チップ12との間で信号の非接触による伝送を実現できることになる。 Therefore, when using a transmission method based on electrostatic coupling as a non-contact transmission method, one flat plate electrode 61 is formed on the first semiconductor chip 11 and the other flat plate electrode 62 is formed on the second semiconductor chip 12. Thus, non-contact transmission of signals can be realized between the first semiconductor chip 11 and the second semiconductor chip 12.
<本開示の電子機器>
 上述した第1、第2実施形態に係る固体撮像素子は、デジタルスチルカメラやビデオカメラ等の撮像装置や、携帯電話機などの撮像機能を有する携帯端末装置や、画像読取部に固体撮像素子を用いる複写機などの電子機器全般において、その撮像部(画像取込部)として用いることができる。尚、電子機器に搭載される上記モジュール状の形態、即ち、カメラモジュールを撮像装置とする場合もある。
<Electronic device of the present disclosure>
The solid-state imaging device according to the first and second embodiments described above uses an imaging device such as a digital still camera and a video camera, a portable terminal device having an imaging function such as a mobile phone, and a solid-state imaging device for an image reading unit. It can be used as an imaging unit (image capturing unit) in electronic devices such as copying machines. In some cases, the above-described module form mounted on an electronic device, that is, a camera module is used as an imaging device.
[撮像装置]
 図13は、本開示の電子機器の一例である撮像装置の構成を示すブロック図である。図13に示すように、本例に係る撮像装置100は、レンズ群等を含む光学系101、撮像部102、カメラ信号処理部であるDSP回路103、フレームメモリ104、表示装置105、記録装置106、操作系107、及び、電源系108等を有している。そして、DSP回路103、フレームメモリ104、表示装置105、記録装置106、操作系107、及び、電源系108がバスライン109を介して相互に接続された構成となっている。
[Imaging device]
FIG. 13 is a block diagram illustrating a configuration of an imaging apparatus that is an example of the electronic apparatus of the present disclosure. As shown in FIG. 13, an imaging apparatus 100 according to this example includes an optical system 101 including a lens group, an imaging unit 102, a DSP circuit 103 that is a camera signal processing unit, a frame memory 104, a display device 105, and a recording device 106. , An operation system 107, a power supply system 108, and the like. The DSP circuit 103, the frame memory 104, the display device 105, the recording device 106, the operation system 107, and the power supply system 108 are connected to each other via a bus line 109.
 光学系101は、被写体からの入射光(像光)を取り込んで撮像部102の撮像面上に結像する。撮像部102は、光学系101によって撮像面上に結像された入射光の光量を画素単位で電気信号に変換して画素信号として出力する。DSP回路103は、一般的なカメラ信号処理、例えば、ホワイトバランス処理、デモザイク処理、ガンマ補正処理などを行う。 The optical system 101 takes in incident light (image light) from a subject and forms an image on the imaging surface of the imaging unit 102. The imaging unit 102 converts the amount of incident light imaged on the imaging surface by the optical system 101 into an electrical signal for each pixel and outputs the electrical signal as a pixel signal. The DSP circuit 103 performs general camera signal processing, such as white balance processing, demosaic processing, and gamma correction processing.
 フレームメモリ104は、DSP回路103での信号処理の過程で適宜データの格納に用いられる。表示装置105は、液晶表示装置や有機EL(electro luminescence)表示装置等のパネル型表示装置から成り、撮像部102で撮像された動画または静止画を表示する。記録装置106は、撮像部102で撮像された動画または静止画を、可搬型の半導体メモリや、光ディスク、HDD(Hard Disk Drive)等の記録媒体に記録する。 The frame memory 104 is used for storing data as appropriate during the signal processing in the DSP circuit 103. The display device 105 includes a panel type display device such as a liquid crystal display device or an organic EL (electroluminescence) display device, and displays a moving image or a still image captured by the imaging unit 102. The recording device 106 records the moving image or still image captured by the imaging unit 102 on a recording medium such as a portable semiconductor memory, an optical disk, or an HDD (Hard Disk Disk Drive).
 操作系107は、ユーザによる操作の下に、本撮像装置100が持つ様々な機能について操作指令を発する。電源系108は、DSP回路103、フレームメモリ104、表示装置105、記録装置106、及び、操作系107の動作電源となる各種の電源を、これら供給対象に対して適宜供給する。 The operation system 107 issues operation commands for various functions of the imaging apparatus 100 under the operation of the user. The power supply system 108 appropriately supplies various power supplies serving as operation power for the DSP circuit 103, the frame memory 104, the display device 105, the recording device 106, and the operation system 107 to these supply targets.
 上記の構成の撮像装置100において、撮像部102として、先述した第1、第2実施形態に係る固体撮像素子を用いることができる。 In the imaging apparatus 100 having the above-described configuration, the solid-state imaging device according to the first and second embodiments described above can be used as the imaging unit 102.
 尚、本開示は、以下のような構成をとることもできる。
[1]入射光に応じた電気信号を生成する単位画素が配置されて成る画素アレイ部を有する第1半導体チップと、
 第1半導体チップに対して積層され、画素アレイ部の各単位画素で生成された電気信号に対して所定の信号処理を施す信号処理部を有する第2半導体チップと、
 画素アレイ部の領域内において、第1半導体チップと第2半導体チップとの間で非接触にて電気信号の伝送を行う信号伝送部と、
 を備える固体撮像素子。
[2]信号伝送部は、第1半導体チップと第2半導体チップとの間で、インダクタの磁気結合によって電気信号の伝送を行う、
 上記[1]に記載の固体撮像素子。
[3]単位画素は、裏面照射型画素である、
 上記[1]又は[2]に記載の固体撮像素子。
[4]信号伝送部が伝送する電気信号は、アナログ信号である、
 上記[1]~[3]のいずれかに記載の固体撮像素子。
[5]信号伝送部が伝送する電気信号は、デジタル信号である、
 上記[1]~[3]のいずれかに記載の固体撮像素子。
[6]単位画素は、入射光に応じたアナログ信号をデジタル信号に変換する機能を有する、
 上記[5]に記載の固体撮像素子。
[7]信号伝送部におけるインダクタは、画素アレイ部の一つの画素列に対して一つ以上設けられている、
 上記[2]~[6]のいずれかに記載の固体撮像素子。
[8]信号伝送部におけるインダクタは、画素アレイ部の各画素列に沿って形成されている、
 上記[7]に記載の固体撮像素子。
[9]信号伝送部におけるインダクタは、画素アレイ部の一つの単位画素に対して一つ、あるいは、複数の単位画素から成る画素ユニットに対して一つ設けられている、
 上記[2]~[5]のいずれかに記載の固体撮像素子。
[10]信号伝送部におけるインダクタは、第1半導体チップの裏面照射型画素の受光側基板面と反対側の基板面に形成されている、
 上記[3]~[9]のいずれかに記載の固体撮像素子。
[11]入射光に応じた電気信号を生成する単位画素が配置されて成る画素アレイ部を有する第1半導体チップと、
 画素アレイ部の各単位画素で生成された電気信号に対して所定の信号処理を施す信号処理部を有する第2半導体チップと、
 が積層されて成る固体撮像素子の駆動に当たって、
 画素アレイ部の領域内において、第1半導体チップと第2半導体チップとの間で非接触にて電気信号の伝送を行う、
 固体撮像素子の駆動方法。
[12]第1半導体チップと第2半導体チップとの間で、インダクタの磁気結合によって電気信号の伝送を行う、
 上記[11]に記載の固体撮像素子の駆動方法。
[13]単位画素は、裏面照射型画素である、
 上記[11]又は[12]に記載の固体撮像素子の駆動方法。
[14]第1半導体チップと第2半導体チップとの間で伝送する電気信号は、アナログ信号である、
 上記[11]~[13]のいずれかに記載の固体撮像素子の駆動方法。
[15]第1半導体チップと第2半導体チップとの間で伝送する電気信号は、デジタル信号である、
 上記[11]~[13]のいずれかに記載の固体撮像素子の駆動方法。
[16]入射光に応じた電気信号を生成する単位画素が配置されて成る画素アレイ部を有する第1半導体チップと、
 第1半導体チップに対して積層され、画素アレイ部の各単位画素で生成された電気信号に対して所定の信号処理を施す信号処理部を有する第2半導体チップと、
 画素アレイ部の領域内において、第1半導体チップと第2半導体チップとの間で非接触にて電気信号の伝送を行う信号伝送部と、
 を備える固体撮像素子を有する電子機器。
[17]信号伝送部は、第1半導体チップと第2半導体チップとの間で、インダクタの磁気結合によって電気信号の伝送を行う、
 上記[16]に記載の電子機器。
[18]単位画素は、裏面照射型画素である、
 上記[16]又は[17]に記載の電子機器。
[19]信号伝送部が伝送する電気信号は、アナログ信号である、
 上記[16]~[18]のいずれかに記載の電子機器。
[20]信号伝送部が伝送する電気信号は、デジタル信号である、
 上記[16]~[18]のいずれかに記載の電子機器。
In addition, this indication can also take the following structures.
[1] a first semiconductor chip having a pixel array unit in which unit pixels for generating an electrical signal corresponding to incident light are arranged;
A second semiconductor chip having a signal processing unit that is stacked on the first semiconductor chip and that performs predetermined signal processing on an electrical signal generated by each unit pixel of the pixel array unit;
In the region of the pixel array unit, a signal transmission unit that transmits electrical signals in a non-contact manner between the first semiconductor chip and the second semiconductor chip;
A solid-state imaging device.
[2] The signal transmission unit transmits an electric signal between the first semiconductor chip and the second semiconductor chip by magnetic coupling of the inductor.
The solid-state imaging device according to [1] above.
[3] The unit pixel is a back-illuminated pixel.
The solid-state imaging device according to the above [1] or [2].
[4] The electrical signal transmitted by the signal transmission unit is an analog signal.
The solid-state imaging device according to any one of [1] to [3] above.
[5] The electrical signal transmitted by the signal transmission unit is a digital signal.
The solid-state imaging device according to any one of [1] to [3] above.
[6] The unit pixel has a function of converting an analog signal corresponding to incident light into a digital signal.
The solid-state imaging device according to [5] above.
[7] One or more inductors in the signal transmission unit are provided for one pixel column in the pixel array unit.
The solid-state imaging device according to any one of [2] to [6] above.
[8] The inductor in the signal transmission unit is formed along each pixel column of the pixel array unit.
The solid-state imaging device according to [7] above.
[9] One inductor in the signal transmission unit is provided for one unit pixel of the pixel array unit, or one for a pixel unit including a plurality of unit pixels.
The solid-state imaging device according to any one of [2] to [5] above.
[10] The inductor in the signal transmission unit is formed on the substrate surface opposite to the light-receiving side substrate surface of the back-illuminated pixel of the first semiconductor chip.
The solid-state imaging device according to any one of [3] to [9] above.
[11] a first semiconductor chip having a pixel array unit in which unit pixels for generating an electrical signal corresponding to incident light are arranged;
A second semiconductor chip having a signal processing unit that performs predetermined signal processing on an electrical signal generated by each unit pixel of the pixel array unit;
When driving a solid-state imaging device that is laminated,
In the region of the pixel array portion, electrical signals are transmitted in a non-contact manner between the first semiconductor chip and the second semiconductor chip.
A method for driving a solid-state imaging device.
[12] An electric signal is transmitted between the first semiconductor chip and the second semiconductor chip by magnetic coupling of the inductor.
The method for driving a solid-state imaging device according to [11] above.
[13] The unit pixel is a back-illuminated pixel.
The method for driving a solid-state imaging device according to the above [11] or [12].
[14] The electrical signal transmitted between the first semiconductor chip and the second semiconductor chip is an analog signal.
The method for driving a solid-state imaging device according to any one of [11] to [13].
[15] The electrical signal transmitted between the first semiconductor chip and the second semiconductor chip is a digital signal.
The method for driving a solid-state imaging device according to any one of [11] to [13].
[16] a first semiconductor chip having a pixel array unit in which unit pixels for generating an electrical signal corresponding to incident light are arranged;
A second semiconductor chip having a signal processing unit that is stacked on the first semiconductor chip and that performs predetermined signal processing on an electrical signal generated by each unit pixel of the pixel array unit;
In the region of the pixel array unit, a signal transmission unit that transmits electrical signals in a non-contact manner between the first semiconductor chip and the second semiconductor chip;
An electronic apparatus having a solid-state imaging device.
[17] The signal transmission unit transmits an electric signal between the first semiconductor chip and the second semiconductor chip by magnetic coupling of the inductor.
The electronic device according to [16] above.
[18] The unit pixel is a back-illuminated pixel.
The electronic device according to the above [16] or [17].
[19] The electrical signal transmitted by the signal transmission unit is an analog signal.
The electronic device according to any one of [16] to [18].
[20] The electrical signal transmitted by the signal transmission unit is a digital signal.
The electronic device according to any one of [16] to [18].
 10・・・積層型固体撮像素子、11・・・第1半導体チップ、12・・・第2半導体チップ、13・・・画素アレイ部(画素部)、14,17・・・垂直走査部、15・・・信号処理部、16・・・水平走査部、20・・・単位画素、21・・・フォトダイオード、22・・・転送トランジスタ、23・・・リセットトランジスタ、24・・・増幅トランジスタ、25・・・選択トランジスタ、26・・・コンパレータ、27・・・制御トランジスタ、31(311~31m)・・・画素駆動線、32(321~32n)・・・信号線、33・・・定電流源、41・・・電圧電流変換部、42,51・・・インダクタ(コイル)、52・・・信号検出部、53・・・アナログ-デジタル変換器(AD変換器)、54・・・メモリ、55・・・列選択スイッチ、56・・・信号出力線、57・・・参照電圧生成部 DESCRIPTION OF SYMBOLS 10 ... Stack type solid-state image sensor, 11 ... 1st semiconductor chip, 12 ... 2nd semiconductor chip, 13 ... Pixel array part (pixel part), 14, 17 ... Vertical scanning part, DESCRIPTION OF SYMBOLS 15 ... Signal processing part, 16 ... Horizontal scanning part, 20 ... Unit pixel, 21 ... Photodiode, 22 ... Transfer transistor, 23 ... Reset transistor, 24 ... Amplification transistor 25... Selection transistor, 26... Comparator, 27... Control transistor, 31 (31 1 to 31 m )... Pixel drive line, 32 (32 1 to 32 n ). 33 ... constant current source, 41 ... voltage-current converter, 42, 51 ... inductor (coil), 52 ... signal detector, 53 ... analog-digital converter (AD converter) 54 ... Memory 55 ... Column select switch, 56 ... signal output line, 57 ... reference voltage generating unit

Claims (20)

  1.  入射光に応じた電気信号を生成する単位画素が配置されて成る画素アレイ部を有する第1半導体チップと、
     第1半導体チップに対して積層され、画素アレイ部の各単位画素で生成された電気信号に対して所定の信号処理を施す信号処理部を有する第2半導体チップと、
     画素アレイ部の領域内において、第1半導体チップと第2半導体チップとの間で非接触にて電気信号の伝送を行う信号伝送部と、
     を備える固体撮像素子。
    A first semiconductor chip having a pixel array unit in which unit pixels for generating an electrical signal corresponding to incident light are arranged;
    A second semiconductor chip having a signal processing unit that is stacked on the first semiconductor chip and that performs predetermined signal processing on an electrical signal generated by each unit pixel of the pixel array unit;
    In the region of the pixel array unit, a signal transmission unit that transmits electrical signals in a non-contact manner between the first semiconductor chip and the second semiconductor chip;
    A solid-state imaging device.
  2.  信号伝送部は、第1半導体チップと第2半導体チップとの間で、インダクタの磁気結合によって電気信号の伝送を行う、
     請求項1に記載の固体撮像素子。
    The signal transmission unit transmits an electrical signal by magnetic coupling of the inductor between the first semiconductor chip and the second semiconductor chip.
    The solid-state imaging device according to claim 1.
  3.  単位画素は、裏面照射型画素である、
     請求項1に記載の固体撮像素子。
    The unit pixel is a back-illuminated pixel.
    The solid-state imaging device according to claim 1.
  4.  信号伝送部が伝送する電気信号は、アナログ信号である、
     請求項1に記載の固体撮像素子。
    The electrical signal transmitted by the signal transmission unit is an analog signal.
    The solid-state imaging device according to claim 1.
  5.  信号伝送部が伝送する電気信号は、デジタル信号である、
     請求項1に記載の固体撮像素子。
    The electrical signal transmitted by the signal transmission unit is a digital signal.
    The solid-state imaging device according to claim 1.
  6.  単位画素は、入射光に応じたアナログ信号をデジタル信号に変換する機能を有する、
     請求項5に記載の固体撮像素子。
    The unit pixel has a function of converting an analog signal corresponding to incident light into a digital signal.
    The solid-state imaging device according to claim 5.
  7.  信号伝送部におけるインダクタは、画素アレイ部の一つの画素列に対して一つ以上設けられている、
     請求項2に記載の固体撮像素子。
    One or more inductors in the signal transmission unit are provided for one pixel column of the pixel array unit,
    The solid-state imaging device according to claim 2.
  8.  信号伝送部におけるインダクタは、画素アレイ部の各画素列に沿って形成されている、
     請求項7に記載の固体撮像素子。
    The inductor in the signal transmission unit is formed along each pixel column of the pixel array unit,
    The solid-state imaging device according to claim 7.
  9.  信号伝送部におけるインダクタは、画素アレイ部の一つの単位画素に対して一つ、あるいは、複数の単位画素から成る画素ユニットに対して一つ設けられている、
     請求項2に記載の固体撮像素子。
    One inductor for the signal transmission unit is provided for one unit pixel of the pixel array unit, or one for a pixel unit composed of a plurality of unit pixels.
    The solid-state imaging device according to claim 2.
  10.  信号伝送部におけるインダクタは、第1半導体チップの裏面照射型画素の受光側基板面と反対側の基板面に形成されている、
     請求項3に記載の固体撮像素子。
    The inductor in the signal transmission unit is formed on the substrate surface opposite to the light receiving side substrate surface of the back-illuminated pixel of the first semiconductor chip.
    The solid-state imaging device according to claim 3.
  11.  入射光に応じた電気信号を生成する単位画素が配置されて成る画素アレイ部を有する第1半導体チップと、
     画素アレイ部の各単位画素で生成された電気信号に対して所定の信号処理を施す信号処理部を有する第2半導体チップと、
     が積層されて成る固体撮像素子の駆動に当たって、
     画素アレイ部の領域内において、第1半導体チップと第2半導体チップとの間で非接触にて電気信号の伝送を行う、
     固体撮像素子の駆動方法。
    A first semiconductor chip having a pixel array unit in which unit pixels for generating an electrical signal corresponding to incident light are arranged;
    A second semiconductor chip having a signal processing unit that performs predetermined signal processing on an electrical signal generated by each unit pixel of the pixel array unit;
    When driving a solid-state imaging device that is laminated,
    In the region of the pixel array portion, electrical signals are transmitted in a non-contact manner between the first semiconductor chip and the second semiconductor chip.
    A method for driving a solid-state imaging device.
  12.  第1半導体チップと第2半導体チップとの間で、インダクタの磁気結合によって電気信号の伝送を行う、
     請求項11に記載の固体撮像素子の駆動方法。
    An electrical signal is transmitted between the first semiconductor chip and the second semiconductor chip by magnetic coupling of the inductor.
    The method for driving a solid-state imaging device according to claim 11.
  13.  単位画素は、裏面照射型画素である、
     請求項11に記載の固体撮像素子の駆動方法。
    The unit pixel is a back-illuminated pixel.
    The method for driving a solid-state imaging device according to claim 11.
  14.  第1半導体チップと第2半導体チップとの間で伝送する電気信号は、アナログ信号である、
     請求項11に記載の固体撮像素子の駆動方法。
    The electrical signal transmitted between the first semiconductor chip and the second semiconductor chip is an analog signal.
    The method for driving a solid-state imaging device according to claim 11.
  15.  第1半導体チップと第2半導体チップとの間で伝送する電気信号は、デジタル信号である、
     請求項11に記載の固体撮像素子の駆動方法。
    The electrical signal transmitted between the first semiconductor chip and the second semiconductor chip is a digital signal.
    The method for driving a solid-state imaging device according to claim 11.
  16.  入射光に応じた電気信号を生成する単位画素が配置されて成る画素アレイ部を有する第1半導体チップと、
     第1半導体チップに対して積層され、画素アレイ部の各単位画素で生成された電気信号に対して所定の信号処理を施す信号処理部を有する第2半導体チップと、
     画素アレイ部の領域内において、第1半導体チップと第2半導体チップとの間で非接触にて電気信号の伝送を行う信号伝送部と、
     を備える固体撮像素子を有する電子機器。
    A first semiconductor chip having a pixel array unit in which unit pixels for generating an electrical signal corresponding to incident light are arranged;
    A second semiconductor chip having a signal processing unit that is stacked on the first semiconductor chip and that performs predetermined signal processing on an electrical signal generated by each unit pixel of the pixel array unit;
    In the region of the pixel array unit, a signal transmission unit that transmits electrical signals in a non-contact manner between the first semiconductor chip and the second semiconductor chip;
    An electronic apparatus having a solid-state imaging device.
  17.  信号伝送部は、第1半導体チップと第2半導体チップとの間で、インダクタの磁気結合によって電気信号の伝送を行う、
     請求項16に記載の電子機器。
    The signal transmission unit transmits an electrical signal by magnetic coupling of the inductor between the first semiconductor chip and the second semiconductor chip.
    The electronic device according to claim 16.
  18.  単位画素は、裏面照射型画素である、
     請求項16に記載の電子機器。
    The unit pixel is a back-illuminated pixel.
    The electronic device according to claim 16.
  19.  信号伝送部が伝送する電気信号は、アナログ信号である、
     請求項16に記載の電子機器。
    The electrical signal transmitted by the signal transmission unit is an analog signal.
    The electronic device according to claim 16.
  20.  信号伝送部が伝送する電気信号は、デジタル信号である、
     請求項16に記載の電子機器。
    The electrical signal transmitted by the signal transmission unit is a digital signal.
    The electronic device according to claim 16.
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