Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/30181—Instruction operation extension or modification
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F11/00—Error detection; Error correction; Monitoring
  • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
  • G06F11/14—Error detection or correction of the data by redundancy in operation
  • G06F11/1402—Saving, restoring, recovering or retrying
  • G06F11/1405—Saving, restoring, recovering or retrying at machine instruction level
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F11/00—Error detection; Error correction; Monitoring
  • G06F11/36—Prevention of errors by analysis, debugging or testing of software
  • G06F11/362—Debugging of software
  • G06F11/3648—Debugging of software using additional hardware
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/30003—Arrangements for executing specific machine instructions
  • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
  • G06F9/30043—LOAD or STORE instructions; Clear instruction
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F9/3824—Operand accessing
  • G06F9/383—Operand prefetching
  • G06F9/3832—Value prediction for operands; operand history buffers
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
  • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
  • G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers

Definitions

• the technology of the disclosure relates generally to execution of instructions in a processor-based system, and more particularly to processor-based systems employing a block-atomic execution model in which instructions are grouped into instruction blocks in which either all instructions in the instruction block are committed or none of the instructions are committed.
• a conventional microprocessor application includes a central processing unit (CPU) that includes or more processors, also known as "processor cores," that execute software instructions.
• the software instructions instruct a CPU to perform operations based on data. Examples of such data include immediate values encoded in instruction fetch data, data stored in a register, data from a location in memory, and data from external devices, such as input/output (I/O) devices.
• the CPU performs an operation according to the instructions to generate a result. The result may then be stored in a register or memory, or provided as output to an I O device.
• FIG. 1 illustrates an exemplary instruction block 100 comprised of a plurality of instructions 102(1)-102(N) to be executed by a processor employing a block-atomic execution model.
• a processor operating according to a block-atomic execution model logically fetches, executes, and commits the instruction block 100 as a single entity.
• a block-atomic execution model has an advantage of reducing the complexity of an out-of-order processor (OoP).
• OoP out-of-order processor
• an OoP that employs a block-atomic execution model does not have to report back the precise state of the processor after execution of each instruction.
• intermediate produced results 104(1), 104(2), 104(4), 104( -2)-104(N) from execution of the instructions 102(1), 102(2), 102(4), 102(N-2)- 102(N) that would otherwise be stored in global registers do not need to be saved to registers.
• instruction 102(1) as an example, its intermediate produced result 104(1) can be provided to a consumer instruction 102(2) in the instruction block 100 in a peer-to-peer manner without having to save the intermediate produced result 104(1). This enables fewer register read and write operations.
• a processor employing a block-atomic execution model has the advantage of reduced complexity
• a processor employing a block-atomic execution model has a disadvantage of having to execute all instructions in an instruction block before external results are committed. As an example, this can make debugging more difficult in the presence of a multi-threaded CPU, because it is generally not possible to reproduce whatever behavior led to an exception or breakpoint that occurred during execution of an instruction block.
• the intermediate produced results of the instruction block which may have been read from a previous write operation in another thread, are not stored.
• This also presents difficulties with side-effect operations, such as I/O device side-effects, where an I/O operation has already been executed prior to an exception occurring.
• the intermediate data read from the I/O operation in instruction 102(4) may no longer be available during re-execution of the instruction block 100.
• the intermediate data read during the first execution of instruction 102(4) may not be reproducibly stored in a register r2.
• a partial replay controller is provided in a processor(s) of a central processing unit (CPU) that employs a block-atomic execution model.
• a block-atomic execution model instructions are grouped in instruction blocks that are fully executed in a processor (e.g., an out-of-order processor (OoP)) before external produced results are committed.
• OoP out-of-order processor
• the partial replay controller is configured to record/replay results of load/store instructions during re-execution of the instruction block.
• the instruction block is re-executed.
• the partial replay controller is configured to record the produced results from the load/store instructions.
• a partial replay controller for controlling execution replay of an instruction block executed in a processor.
• the partial replay controller comprises a detection circuit configured to set a record/replay state to an active state for an instruction block, in response to detection of an instruction associated with a potential architectural state modification, or an occurrence of an exception in the processor.
• the partial replay controller also comprises a record/replay circuit.
• the record/replay circuit is configured to inspect an entry state in a record/replay log file corresponding to a next load/store instruction to be executed in the instruction block to determine if previously produced data is recorded for the next load/store instruction.
• the partial replay controller comprises a means for setting a means for storing a record/replay state to an active state for an instruction block, in response to detection of an instruction associated with a potential architectural state modification, or an occurrence of an exception in the processor.
• the partial replay controller also comprises a means for inspecting an entry state in a means for storing a record/replay log file corresponding to a next load/store instruction to be executed in the instruction block to determine if previously produced data is recorded for the next load/store instruction, in response to the means for storing the record/replay state to an active state for the instruction block.
• FIG. 2 is a block diagram of an exemplary multiple processor (“multiprocessor") CPU, wherein each processor is configured to execute software instructions to perform functions, including accesses to external memory and I/O devices;
• Figure 3 is a block diagram illustrating exemplary detail of a processor that can be included in the multi-processor CPU in Figure 2, wherein the processor includes a partial replay controller configured to record and/or replay results of load/store instructions during re-execution of an instruction block, in response to detecting an instruction in the instruction block associated with a potential architectural state modification, and/or in response to an occurrence of an exception, during execution of instructions in the instruction block;
• a partial replay controller configured to record and/or replay results of load/store instructions during re-execution of an instruction block, in response to detecting an instruction in the instruction block associated with a potential architectural state modification, and/or in response to an occurrence of an exception, during execution of instructions in the instruction block;
• the partial replay controller 206 may also be configured to record and/or replay results of the load/store instructions 302L during re-execution of the instruction block 308, in response to the occurrence of an actual exception in the processor 204.
• exceptions may include a static block exception, such as an instruction page fault, an invalid block header, and an invalid instruction encoding.
• the partial replay controller 206 may be configured to record and/or replay results of the load/store instructions 302L during re-execution of the instruction block 308.
• the record/replay state 330 remains in the active state ("ACTIVE") until all the instructions 302 in the instruction block 308 have been executed. Thereafter, the external produced results from the executed instructions 302 in the instruction block 308 are committed (or in the case of a partial commit functionality, produced results from instructions 302 that were not previously committed are committed) (712 in Figure 7).
• ACTIVE active state
• the external produced results from the executed instructions 302 in the instruction block 308 are committed (or in the case of a partial commit functionality, produced results from instructions 302 that were not previously committed are committed) (712 in Figure 7).
• ACTIVE active state
• the partial replay controller 206 sets the record/replay state 330 back to the idle state ("IDLE") to execute a next instruction block 308. If an exception occurs when the record/replay state 330 is in the idle state (“IDLE”), the operating system in the CPU 202 saves the current architectural state and switches the locked state "LOCKED” to resolve the exception such that no further instructions 302 are executed in the instruction block 308 (714 in Figure 7). Once the exception is resolved in the locked state "LOCKED", the operating system restores the architectural state that existed before the exception occurred and switches the record/replay state 330 back to the idle state (“IDLE”) (716 in Figure 7).
• a summary of exemplary exception categories wherein an architectural state of an instruction block 308 can be preserved by employing the partial replay controller 206 is shown below. However, if the current instruction block 308 is executing with the PBR model enabled by the partial replay controller 206, an interrupt may be taken with a precise partial block state as well. As discussed previously and as shown in the table below, if an instruction block encounters side-effects or has stored produced data before an exception occurs, a partial replay controller could be configured to discard produced results from instructions that were executed in the instruction block before the exception occurred. After the processor recovers from the exception, the partial replay controller would then be configured to start execution back from the beginning instruction of the instruction block to record and/or replay results of the load/store instructions.
• the partial replay controller for controlling execution replay of an instruction block executed in a processor could be provided that includes a means for setting a means for storing a record/replay state to an active state for an instruction block, in response to detection of an instruction associated with a potential architectural state modification, or an occurrence of an exception in the processor.
• the partial replay controller 206, the detection circuit 332 or the record/replay circuit 334 in Figure 3 are examples of such a means for setting, where the partial replay controller 206 is configured to set the record/replay state 330 to the active state in response to detection of an instruction associated with a potential architectural state modification, or an occurrence of an exception in the processor 204.
• the partial replay controller 206 could also include a means for inspecting an entry state in a means for storing a record/replay log file corresponding to a next load/store instruction to be executed in the instruction block to determine if previously produced data is recorded for the next load/store instruction, in response to the means for storing the record/replay state to an active state for the instruction block.
• this means for inspecting an entry state could be provided by the partial replay controller 206 or the record/replay circuit 334 in Figure 3, by accessing the record/replay log file 338.
• the partial replay controller 206 could also include a means for recording produced data of the executed next load/store instruction in the means for storing the record/replay log file, in response to the previously produced data not being recorded in the means for storing the record/replay log file for the next load/store instruction.
• the means for storing the record/replay log file could be provided by the partial replay controller 206 or the record/replay circuit 334 in Figure 3 to store previously produced data not being recorded in the record/replay log file 338 for the next load/store instruction.
• a processor that includes a partial replay controller configured to record and/or replay results of load/store instructions during re-execution of an instruction block, in response to detecting an instruction in the instruction block associated with a potential architectural state modification, and/or in response to an occurrence of an exception, during execution of instructions in the instruction block, such as the partial replay controller 206 in the processor 204 in Figure 3 for example, and according to any of the examples disclosed herein, may be provided in or integrated into any processor- based device.
• PDA personal digital assistant
• Figure 8 illustrates an example of a processor-based system 800 that includes a CPU 802 that includes one or more processors 804.
• the processor(s) 804 can each include a partial replay controller 806 that is configured to record and/or replay results of load/store instructions during re-execution of an instruction block, in response to detecting a potential side-effect during execution of instructions in the instruction block.
• the partial replay controller 806 can be the partial replay controller 206 in Figure 3 as an example.
• the CPU 802 may have a cache memory 808 coupled to the processor(s) 804 for rapid access to temporarily stored data.
• the CPU 802 is coupled to a system bus 810 and can intercouple peripheral devices included in the processor-based system 800.
• the processor(s) 804 in the CPU 802 can communicate with these other devices by exchanging address, control, and data information over the system bus 810.
• multiple system buses 810 could be provided, wherein each system bus 810 constitutes a different fabric.
• the CPU 802 can communicate bus transaction requests to a memory controller 812 in a memory system 814 as an example of a slave device.
• the memory controller 812 is configured to provide memory access operations to a memory array 816 in the memory system 814.
• Other devices can be connected to the system bus 810.
• these devices can include the memory system 814, one or more input devices 818, one or more output devices 820, one or more network interface devices 822, and one or more display controllers 824, as examples.
• the input device(s) 818 can include any type of input device, including but not limited to input keys, switches, voice processors, etc.
• the output device(s) 820 can include any type of output device, including but not limited to audio, video, other visual indicators, etc.
• the network interface device(s) 822 can be any devices configured to allow exchange of data to and from a network 826.
• a partial replay controller configured to record and/or replay results of load/store instructions during re-execution of an instruction block, in response to detecting a potential side-effect during execution of instructions in the instruction block, can also be provided in a software-based system.
• the partial replay controller does not have to be implemented in a hardware-only circuit that provides the functions of the partial replay controller without software instructions.
• the partial replay controller such as the partial replay controller 206 in Figure 3, could be provided in a non- transitory computer-readable medium having stored thereon computer executable instructions which, when executed by a processor, such a processor 204(1)-204(P) like in Figure 2, cause the processor to set a record/replay state to an active state for an instruction block, in response to detection of an instruction associated with a potential architectural state modification, or an occurrence of an exception in the processor.
• the computer executable instructions which, when executed by a processor, cuase the processor to inspect an entry state in a record/replay log file corresponding to a next load/store instruction to be executed in the instruction block to determine if previously produced data is recorded for the next load/store instruction, record produced data of the executed next load/store instruction in the record/replay log file, in response to the previously produced data not being recorded in the record/replay log file for the next load/store instruction, and execute the next load/store instruction using the previously produced data recorded for the next load/store instruction in the record/replay log file, in response to the previously produced data being recorded in the record/replay log file for the next load/store instruction.
• the "computer-readable medium” should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that store the one or more sets of instructions.
• the term "computer- readable medium” shall also be taken to include any medium that is capable of storing, encoding, or carrying a set of instructions for execution by a processor and that cause the processor to perform any one or more of the methodologies of the aspects disclosed herein.
• the term “computer-readable medium” shall accordingly be taken to include, but not be limited to, solid-state memories, optical medium, and magnetic medium.
• DSP Digital Signal Processor
• ASIC Application Specific Integrated Circuit
• FPGA Field Programmable Gate Array
• a processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine.
• a processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
• RAM Random Access Memory
• ROM Read Only Memory
• EPROM Electrically Programmable ROM
• EEPROM Electrically Erasable Programmable ROM
• registers a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art.
• An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium.
• the storage medium may be integral to the processor.
• the processor and the storage medium may reside in an ASIC.
• the ASIC may reside in a remote station.
• the processor and the storage medium may reside as discrete components in a remote station, base station, or server.

Landscapes

• Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Software Systems (AREA)
• Physics & Mathematics (AREA)
• General Engineering & Computer Science (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Quality & Reliability (AREA)
• Debugging And Monitoring (AREA)
• Advance Control (AREA)
• Executing Machine-Instructions (AREA)
• Retry When Errors Occur (AREA)

Priority Applications (7)

Applications Claiming Priority (4)

Publications (1)

Family

ID=59086553

Family Applications (1)

Country Status (8)

Cited By (1)

Families Citing this family (3)

Citations (1)

Family Cites Families (19)

• 2016
  • 2016-08-31 US US15/252,323 patent/US11188336B2/en active Active
  • 2016-12-09 JP JP2018531614A patent/JP6963552B2/ja active Active
  • 2016-12-09 WO PCT/US2016/065740 patent/WO2017116652A1/en not_active Ceased
  • 2016-12-09 AU AU2016380796A patent/AU2016380796B2/en active Active
  • 2016-12-09 KR KR1020187017864A patent/KR102706938B1/ko active Active
  • 2016-12-09 ES ES16820447T patent/ES2824474T3/es active Active
  • 2016-12-09 EP EP16820447.7A patent/EP3398060B1/en active Active
  • 2016-12-09 CN CN201680072709.XA patent/CN108369519B/zh active Active

Patent Citations (1)

Non-Patent Citations (4)

Also Published As

Similar Documents

Legal Events