WO2017114134A1 - 电机保护电路和控制电机保护电路的方法 - Google Patents

电机保护电路和控制电机保护电路的方法 Download PDF

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Publication number
WO2017114134A1
WO2017114134A1 PCT/CN2016/109138 CN2016109138W WO2017114134A1 WO 2017114134 A1 WO2017114134 A1 WO 2017114134A1 CN 2016109138 W CN2016109138 W CN 2016109138W WO 2017114134 A1 WO2017114134 A1 WO 2017114134A1
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Prior art keywords
control chip
resistor
voltage value
value
voltage
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PCT/CN2016/109138
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English (en)
French (fr)
Inventor
刘若鹏
邱胜林
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深圳光启合众科技有限公司
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Publication of WO2017114134A1 publication Critical patent/WO2017114134A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
    • H02H7/08—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for dynamo-electric motors
    • H02H7/09—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for dynamo-electric motors against over-voltage; against reduction of voltage; against phase interruption

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  • the present invention relates to the field of power management technologies, and in particular, to a motor protection circuit and a method of controlling a motor protection circuit.
  • the power protection circuit relies on a bulky inductor, capacitor, fuse or transient voltage suppressor to prevent damage to the device and the control circuit caused by sudden changes in the power supply voltage and current, an effective solution has not been proposed yet.
  • Embodiments of the present invention provide a motor protection circuit and a method of controlling a motor protection circuit to at least solve the prior art power protection circuit relying on a bulky inductor, capacitor, fuse or transient voltage suppressor to prevent a sudden change in power supply voltage and current Technical problems with damage to equipment and control circuits.
  • a motor protection circuit includes: a voltage dividing resistor and a sampling resistor; a control chip, one end of the voltage dividing resistor is connected to the control chip, and both ends of the sampling resistor are connected to the control chip.
  • the method is configured to stabilize the power supply voltage to a preset voltage value when detecting that the voltage value across the voltage dividing resistor is greater than the preset voltage value, and/or when detecting that the current value flowing through the sampling resistor is greater than the preset current value
  • a turn-off signal is issued; the field effect transistor, the gate is connected to the control chip, and the source is connected to one end of the sampling resistor for turning off according to the turn-off signal generated by the control chip.
  • a method for controlling a motor protection circuit includes: controlling a chip to detect a voltage value across a voltage dividing resistor of the access control chip, and determining whether the voltage value is greater than a preset voltage value And/or detecting a current value of a sampling resistor that is connected to the control chip through both ends, and determining whether the current value is greater than a preset current value; wherein, in the case where the voltage value is greater than the preset voltage value, the control chip sets the voltage The value is stabilized to a preset voltage value and then output to the load; wherein, when the current value is greater than the preset current value, the chip control is controlled.
  • the field effect transistor connected between the power supply and the load is turned off to disconnect the power supply from the load.
  • the voltage value across the voltage dividing resistor is detected by the control chip to determine the voltage outputted by the power output terminal, and the voltage value is determined when the voltage value outputted by the power output terminal is greater than the preset voltage value.
  • the control chip detects the current value flowing through the sampling resistor, determines the current outputted from the power output terminal, and controls the connection to the power source and the load when it is determined that the current value is greater than the maximum current value.
  • the field effect transistor is turned off, so that when the voltage suddenly increases, the output voltage can be stabilized to the set clamp voltage by its own output clamp circuit, providing a safe and stable working voltage for the motor and the rear stage circuit.
  • the output current can be cut off by turning off the external MOS to achieve the purpose of protecting the latter circuit and the motor, further solving the prior art that the power protection circuit relies on a bulky inductor, Capacitors, fuses or transient voltage suppressors to prevent sudden changes in supply voltage and current to devices and control circuits Technical problems damage.
  • the detection and control process is simple and quick, and the whole motor protection circuit has low cost, high integration and strong practicability.
  • FIG. 1 is a schematic diagram of a motor protection circuit in accordance with an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of an optional motor protection circuit in accordance with an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of another alternative motor protection circuit in accordance with an embodiment of the present invention.
  • FIG. 4 is a flow chart of a method of controlling a motor protection circuit in accordance with an embodiment of the present invention.
  • FIG. 1 is a schematic diagram of a motor protection circuit according to an embodiment of the present invention. As shown in FIG. 1, the motor protection circuit: a voltage dividing resistor 11, sampling The resistor 13, the control chip 15 and the field effect transistor 17.
  • the control chip 15 and one end of the voltage dividing resistor 11 are connected to the control chip 15. Both ends of the sampling resistor 13 are connected to the control chip 15 for detecting that the voltage value across the voltage dividing resistor is greater than the preset voltage value. Next, the power supply voltage is stabilized to a preset voltage value, and/or a turn-off signal is issued if it is detected that the current value flowing through the sampling resistor is greater than the preset current value.
  • the preset voltage value may be a clamp voltage output by the motor protection circuit
  • the preset current value may be a maximum current value allowed to pass through the power line
  • the load may be a circuit and a motor of a subsequent stage.
  • the field effect transistor 17 is connected to the control chip 15, and the source is connected to one end of the sampling resistor 13 for turning off according to the turn-off signal generated by the control chip.
  • the above field effect transistor may be an NMOS transistor, model number FDB33N25.
  • the first pin of the control chip may be an FB pin, and the second pin may be an OUT pin.
  • the three pins can be SNS pins, the fourth pin can be GATE pins, the output of the power supply is connected to the input terminal VIN of the motor protection circuit, the output of the motor protection circuit VOUT is connected to the load, and the OUT pin and output of the control chip are controlled.
  • the VOUT is connected, one end of the sampling resistor is connected to the source of the NMOS transistor Q1, and is connected to the SNS pin of the control chip, the other end is connected to the output terminal VOUT, and is connected to the OUT pin of the control chip, and one end of the voltage dividing resistor is connected to the control.
  • the FB pin of the chip is connected to the output terminal VOUT, the drain of the NMOS transistor Q1 is connected to the input terminal VIN of the motor protection circuit, and the gate is connected to the GATE pin of the control chip.
  • the control chip can determine the voltage value across the voltage dividing resistor by detecting the potential of the FB pin, thereby determining the voltage value of the power output to the motor protection circuit, and performing the voltage value and the clamping voltage. Comparing, if the voltage value of the power output is less than or equal to the clamp voltage, it means that the voltage value of the power output does not exceed the safe voltage of the load, and the voltage value can be directly output to the circuit and motor of the latter stage; if the voltage value of the power output is greater than The clamp voltage indicates that the voltage value exceeds the safe voltage of the load, and overvoltage protection is required. The output voltage is stabilized to the clamp voltage by the clamp function of the control chip, and outputted through the OUT pin of the control chip. Level circuit and motor.
  • control chip can determine the voltage value on the sampling resistor by detecting the potential difference between the SNS pin and the OUT pin, and obtain the current value flowing through the sampling resistor according to Ohm's law, thereby obtaining The current value of the power output is compared with the maximum current value. If the current value of the power output is greater than the maximum current value, the current exceeds the safe current of the load, and overcurrent protection is required, and the GATE tube is controlled by the control chip. The foot control NMOS transistor Q1 is turned off, and the electrical connection between the power supply and the circuit of the subsequent stage and the motor is cut off, thereby cutting off the output current.
  • the voltage value across the voltage dividing resistor is detected by the control chip to determine the voltage outputted by the power output terminal, and the voltage value is determined when the voltage value outputted by the power output terminal is greater than the preset voltage value.
  • the control chip After being stabilized as the clamp voltage, it is output to the load, and the control chip detects the current value flowing through the sampling resistor, determines the current outputted from the power output terminal, and controls the connection to the power source and the load when it is determined that the current value is greater than the maximum current value.
  • the field effect transistor is turned off, so that when the voltage suddenly increases, the output voltage can be stabilized to the set clamp voltage by its own output clamp circuit, providing a safe and stable working voltage for the motor and the rear stage circuit.
  • the output current can be cut off by turning off the external MOS to achieve the purpose of protecting the latter circuit and the motor, further solving the prior art that the power protection circuit relies on a bulky inductor, Capacitors, fuses or transient voltage suppressors to prevent sudden changes in supply voltage and current to equipment and control Technical problems damage.
  • the detection and control process is simple and quick, and the whole motor protection circuit has low cost, high integration and strong practicability.
  • the type of the above control chip is LT4363-2.
  • the voltage dividing resistor includes: a first sub-dividing resistor and a second sub-divider resistor, wherein one end of the first sub-divider resistor is connected between the sampling resistor and the load, and the first sub-dividing The other end of the resistor and one end of the second sub-divider resistor are connected to the first node Z1 and are connected to the first pin of the control chip, and the other end of the second sub-divider resistor is grounded.
  • the first pin of the control chip may be an FB pin, and the second pin may be an OUT pin.
  • the third pin can be an SNS pin
  • the fourth pin can be a GATE pin
  • the fifth pin can be a VCC pin
  • the sixth pin can be a SHDN pin
  • the seventh pin can be an OV pin.
  • the eighth pin can be a UV pin and the twelfth pin can be a TMR pin.
  • the first sub-divider resistor may be a resistor R4, the second sub-divider resistor may be a resistor R5, R4 and R5 are connected in series, and the other end of the R4 is connected to the OUT pin of the control chip. The other end of R5 is grounded, and the connection point Z1 of R4 and R5 is connected to the FB pin of the control chip.
  • the first end of the sampling resistor is connected to the power supply via the field effect transistor, and the second end is connected to the load, wherein the second pin of the control chip is connected between the second end of the sampling resistor and the load.
  • the third pin of the control chip is coupled to node Z3 between the first terminal of the sampling resistor and the source of the field effect transistor.
  • the second pin of the control chip may be an OUT pin
  • the third pin may be an SNS pin
  • the sampling resistor may be a resistor R1
  • the sampling resistor R1 is one end. It is connected to the source of the NMOS transistor Q1, and is connected to the SNS pin of the control chip, and the other end is connected to the output terminal VOUT, and is connected to the OUT pin of the control chip.
  • control chip is further configured to determine a preset voltage value according to the resistance value of the voltage dividing resistor; and the control chip is further configured to determine the preset current value according to the resistance value of the sampling resistor.
  • the preset voltage value and the preset current value are determined according to the following formula:
  • U REG is a preset voltage value
  • R 4 and R 5 are resistance values of R4 and R5, respectively
  • I max is a preset current value
  • R 1 is a resistance value of R1.
  • the clamp voltage of the output can be set by changing the resistance values of the two sub-resistors, when the resistance value of the sub-resistor R4 is 49.9 K ⁇ , and the resistance value of the sub-resistor R5 is 4.7 K ⁇ , according to the above
  • the calculation formula can be used to obtain a clamp voltage of 14.8V.
  • the maximum current value allowed on the power supply line can be set by changing the resistance value of the sampling resistor R1. When the resistance value of the sampling resistor R1 is 12.5 m ⁇ , the maximum current value can be obtained according to the above formula.
  • the motor protection circuit further includes:
  • the protection resistor has one end connected to the power supply and the other end connected to the control chip.
  • the protection resistor includes: a first sub-protection resistor, a second sub-protection resistor and a third sub-protection resistor, wherein one end of the first sub-protection resistor is connected between the drain of the field effect transistor and the power source
  • the other end of the first sub-protective resistor and one end of the second sub-protective resistor are connected to the second node Z4, and are connected to the eighth pin of the control chip, the other end of the second sub-protective resistor and the third sub-protective resistor
  • One end is connected to the third node Z5, and is connected to the seventh pin of the control chip, and the other end of the third sub-protection resistor is grounded.
  • the seventh pin of the control chip may be an OV pin
  • the eighth pin may be a UV pin, a first sub-protective resistor, and a second sub-protective resistor.
  • the third sub-protection resistor can be resistor R6, resistor R7 and resistor R8, R6, R7 and R8 are connected in series, the other end of R6 is connected to the input terminal VIN, the other end of R8 is grounded, and the connection point Z4 of R6 and R7 is connected.
  • R6 and R7 Contact Z5 is connected to the OV pin of the control chip.
  • control chip is further configured to determine an overvoltage voltage value and an undervoltage voltage value according to the resistance value of the protection resistor; the control chip is further configured to detect that the voltage value across the protection resistor is greater than the overvoltage voltage value, Or, if it is less than the undervoltage voltage value, a shutdown signal is issued.
  • overvoltage voltage value and the undervoltage voltage value can be determined according to the following formula:
  • U OV is the overvoltage voltage value
  • U UV is the undervoltage voltage value
  • R 6 , R 7 and R 8 are the resistance values of R6, R7 and R8, respectively.
  • the overvoltage voltage value and the undervoltage voltage value can be set by changing the resistance values of the three sub-resistors.
  • the resistance value of the sub-resistor R6 is 100K ⁇
  • the resistance value of the sub-resistor R7 is 11.1K ⁇ .
  • the resistance value of the sub-resistor R8 is 10 k ⁇
  • the overvoltage voltage value is 15.4 V
  • the undervoltage voltage value is 7.3 V according to the above calculation formula.
  • the control chip can further determine whether the voltage value is greater than 15.4V or less than 7.3V after detecting the voltage value outputted by the power output terminal.
  • the NMOS transistor Q1 is turned off by the GATE pin, and the circuit between the power supply and the circuit of the subsequent stage and the motor is cut off, thereby cutting off the output voltage.
  • the motor protection circuit further includes:
  • the capacitor is connected to the twelfth pin of the control chip at one end and grounded at the other end for charging according to the charging signal sent by the control chip.
  • the twelfth pin of the control chip may be a TMR pin, and one end of the capacitor C2 is connected to the TMR pin of the control chip, and the other end is grounded.
  • the control chip can further detect that the voltage value of the power output is greater than the overvoltage voltage value, or is less than the undervoltage voltage value, the control capacitor C2 is charged, and the voltage value of the capacitor C2 is detected in real time during the charging process.
  • the control chip is further configured to issue a shutdown signal when it is detected that the voltage value of the capacitor is greater than or equal to the first preset value.
  • the first preset value may be 1.375V.
  • control chip can detect when the voltage value of the capacitor C2 reaches 1.375V.
  • the NMOS transistor Q1 that controls the GATE pin is turned off, thereby cutting off the connection between the power output terminal and the circuit of the rear stage and the motor input terminal, and protecting the circuit and the motor of the subsequent stage.
  • control chip is further configured to control the capacitor to continue charging.
  • the control capacitor discharges, and when the discharge process is detected.
  • the voltage value of the capacitor is less than or equal to the third preset value, and the voltage value across the protection resistor is detected and/or the current value flowing through the sampling resistor satisfies the conduction condition, an on signal is issued.
  • the field effect transistor is also used to conduct based on the received on signal.
  • the second preset value may be 4.3V
  • the third preset value may be 0.5V
  • the control chip can continue to control the capacitor C2 for charging after controlling the NMOS transistor Q1 to be turned off, and detect the voltage value of the capacitor C2 in real time during charging, when the voltage value of the capacitor C2 is detected.
  • the control capacitor C2 discharges, and the voltage of the capacitor C2 is detected in real time during the discharge process.
  • the control chip detects whether the voltage value of the power supply output satisfies the conduction condition. Whether the current value of the power supply output satisfies the conduction condition, and if the conduction condition is satisfied, the NMOS transistor Q1 is controlled to be turned on.
  • control chip is further configured to start timing after the field effect transistor is turned off, and when the timing time reaches the preset time, and detecting the voltage value across the protection resistor and/or the current value flowing through the sampling resistor When the on condition is satisfied, a turn-on signal is issued; the field effect transistor is also used to conduct according to the received turn-on signal.
  • the delay time may be a cooling time of the control chip, and may be calculated according to the following formula:
  • the cooling time can be calculated according to the above formula to be 336 ms, and the control chip can start timing after the NMOS transistor Q1 is turned off, when the timing time reaches 336 ms.
  • the control chip detects whether the voltage value of the power supply output satisfies the conduction condition, or whether the current value of the power supply output satisfies the conduction condition, if the conduction condition is satisfied, the NMOS transistor Q1 is controlled to be turned on.
  • control chip controls the field effect transistor to be turned on according to the voltage value of the capacitor and the control chip controls the field effect transistor to be turned on according to the timing time.
  • the implementation effects of the two schemes are all controlled by the control chip in controlling the NMOS transistor Q1. After the break, wait for a cooling time to control the NMOS transistor Q1 to conduct.
  • control chip is further configured to detect, when the voltage value across the protection resistor is greater than or equal to the undervoltage voltage value, and less than or equal to the overvoltage voltage value, and/or detect the flow through the sampling resistor. When the current value is less than or equal to the preset current value, an on signal is issued.
  • the control chip when the control chip determines that the voltage value of the power supply output is greater than the overvoltage voltage of 15.4V, or is less than 7.3V and the NMOS transistor Q1 is turned off, the control chip can drop the voltage value of the capacitor C2. When it reaches 0.5V, or the timing time reaches 336ms, it is judged whether the voltage value of the power supply output is greater than or equal to 7.3V and less than or equal to 15.4V, and when the voltage value is greater than or equal to 7.3V and less than or equal to 15.4V, the NMOS transistor Q1 is controlled. If the voltage value is less than 7.3V, or greater than 15.4V, it is necessary to wait for the voltage value of the power supply output to return to the range of 7.3V to 15.4V and then control the NMOS transistor Q1 to conduct.
  • the control chip can reduce the voltage value of the capacitor C2 to 0.5V, or When the timing reaches 336ms, it is judged whether the current value of the power output is less than or equal to 4A, and when the current value is less than or equal to 4A, the NMOS transistor Q1 is controlled to be turned on; if the current value is greater than 4A, the current value of the power output is required to be lower than the set value. When the maximum current is 4A, the NMOS transistor Q1 is controlled to be turned on.
  • the output end of the power supply is disconnected from the input end of the load by cutting off the external NMOS transistor Q1, so that the protection circuit itself is not damaged, and
  • the output end of the power supply and the input end of the load will be turned back on, so that the entire motor protection circuit works normally, thereby realizing the overcurrent fault of the motor protection circuit, and having the function of reconnecting. purpose.
  • the above circuit further includes:
  • the first protection resistor has one end connected to the fifth pin and the sixth pin of the control chip, and the other end connected between the drain of the field effect transistor and the power source.
  • the second protection resistor has one end connected to the fourth pin of the control chip and the other end connected to the gate of the field effect transistor.
  • the protection capacitor has one end connected between the sampling resistor and the load and the other end grounded.
  • the fifth pin of the control chip may be a VCC pin
  • the sixth pin may be a SHDN pin
  • the first protection resistor may be a resistor R2
  • a second The protection resistor can be R3, the protection capacitor can be C1, one end of the resistor R2 is connected to the input terminal VIN and the drain of the NMOS transistor Q1, the other end is connected to the VCC pin and the SHDN pin of the control chip, and the resistor R3 is connected to the NMOS transistor.
  • the gate of Q1 is connected to the GATE pin of the control chip, the C1 end is connected to the output terminal VOUT, the other end is grounded, the resistor R2 and the resistor R3 are used for current limiting, and the capacitor C1 is used for filtering the current spike.
  • the selection of the resistor R2, the resistor R3 and the capacitor C1, and the connection manner of the control chip VCC pin and the SHDN pin can be referred to the linear LT4363 data sheet, which is not used in this application.
  • the FLT pin is deasserted to indicate that the power system has an abnormal function. Therefore, the ENOUT pin and the FLT pin of the control chip are not connected, and can be connected as needed during actual use.
  • an embodiment of a method of controlling a motor protection circuit is provided, it being noted that the steps illustrated in the flowchart of the figures may be performed in a computer system such as a set of computer executable instructions, and Although the logical order is shown in the flowcharts, in some cases the steps shown or described may be performed in a different order than the ones described herein.
  • FIG. 4 is a flow chart of a method for controlling a motor protection circuit according to an embodiment of the present invention. As shown in FIG. 4, as shown in FIG. 4, the method includes the following steps:
  • Step S102 the control chip detects the voltage value across the voltage dividing resistor of the access control chip, and determines whether the voltage value is greater than a preset voltage value, and/or detects a current value of a sampling resistor that is connected to the control chip through both ends. And determine whether the current value is greater than the preset current value.
  • control chip may be an LT4363-2 chip
  • the preset voltage value may be a clamp voltage output by the motor protection circuit
  • the preset current value may be a maximum current value allowed to pass through the power line.
  • the first pin of the control chip may be an FB pin
  • the second pin may be an OUT pin
  • the third pin may be an SNS pin
  • the fourth pin may be a GATE pin, a power supply.
  • the output end is connected to the input terminal VIN of the motor protection circuit
  • the output end of the motor protection circuit VOUT is connected to the load
  • the VCC pin of the control chip is connected with the input terminal VIN
  • the OUT pin is connected with the output terminal VOUT
  • the sampling resistor end is connected with the NMOS transistor Q1.
  • the source is connected and connected to the SNS pin of the control chip, and the other end is connected to the output terminal VOUT, and is connected to the OUT pin of the control chip.
  • One end of the voltage dividing resistor is connected to the FB pin of the control chip, and the other end and the output end are connected.
  • VOUT is connected, the drain of the NMOS transistor Q1 is connected to the input terminal VIN of the motor protection circuit, and the gate is connected to the GATE pin of the control chip.
  • control chip can determine the voltage value across the voltage dividing resistor by detecting the potential of the FB pin, thereby determining the voltage value output from the power output terminal to the motor protection circuit, and clamping the voltage value with the clamp voltage.
  • the voltage is compared, if the voltage output from the power output is greater than the clamp voltage, the voltage exceeds the safe voltage of the load and overvoltage protection is required.
  • control chip can determine the voltage value on the sampling resistor by detecting the potential difference between the SNS pin and the OUT pin, and obtain the current value flowing through the sampling resistor according to Ohm's law, thereby obtaining The current value of the power output is compared with the maximum current value. If the current value of the power supply output is greater than the maximum current value, the current exceeds the safe current of the load, and overcurrent protection is required.
  • Step S104 in the case that the voltage value is greater than the preset voltage value, the control chip outputs the voltage value to the preset voltage value and then outputs the load to the load.
  • the above load may be a circuit and a motor of a subsequent stage.
  • control chip can stabilize the output voltage to the clamp voltage by detecting the clamping function of the chip when the voltage value of the power output is greater than the preset voltage value, that is, when an overvoltage phenomenon occurs, and Output to the circuit and motor of the subsequent stage through the OUT pin of the control chip.
  • Step S106 in the case that the current value is greater than the preset current value, the control chip controls the field effect transistor connected between the power source and the load to be turned off to disconnect the power source from the load.
  • the above field effect transistor may be an NMOS transistor.
  • control chip can detect that the current value of the power output is greater than the maximum current value, that is, when an overcurrent phenomenon occurs, the NMOS transistor Q1 is turned off by the control chip GATE pin, and the power supply and the subsequent stage are cut off. An electrical connection between the circuit and the motor to cut off the output current.
  • the voltage value across the voltage dividing resistor is detected by the control chip to determine the voltage outputted by the power output terminal, and the voltage value is determined when the voltage value outputted by the power output terminal is greater than the preset voltage value.
  • the control chip After being stabilized as the clamp voltage, it is output to the load, and the control chip detects the current value flowing through the sampling resistor, determines the current outputted from the power output terminal, and controls the connection to the power source and the load when it is determined that the current value is greater than the maximum current value.
  • the field effect transistor is turned off, so that when the voltage suddenly increases, the output voltage can be stabilized to the set clamp voltage by its own output clamp circuit, providing a safe and stable working voltage for the motor and the rear stage circuit.
  • the output current can be cut off by turning off the external MOS to achieve the purpose of protecting the latter circuit and the motor, further solving the prior art that the power protection circuit relies on a bulky inductor, Capacitors, fuses or transient voltage suppressors to prevent sudden changes in supply voltage and current to equipment and control Technical problems damage.
  • the detection and control process is simple and quick, and the whole motor protection circuit has low cost, high integration and strong practicability.
  • step S102 the control chip detects the voltage value across the voltage dividing resistor of the access control chip, and determines whether the voltage value is greater than a preset voltage value, and/or detects that both ends are connected to the control.
  • the method further includes the following steps: before the current value of the sampling resistor of the chip is determined, and the current value is greater than the preset current value.
  • Step S112 the control chip determines the preset voltage value according to the resistance value of the voltage dividing resistor according to the following formula:
  • U REG is a preset voltage value
  • R 4 and R 5 are respectively a resistance value of the first sub-divider resistor and the second sub-divider resistor in the voltage dividing resistor, and one end of the first sub-divider resistor is connected to the sampling Between the resistor and the load, the other end of the first sub-divider resistor and one end of the second sub-divider resistor are connected to the first node Z1, and are connected to the first pin of the control chip, and the second sub-divider resistor is further One end is grounded.
  • the first pin of the control chip may be an FB pin
  • the first sub-divider resistor may be R4
  • the second sub-divider resistor may be R5, R4.
  • R5 Connected to R5 in series, the other end of R4 is connected to the OUT pin of the control chip, the other end of R5 is grounded, and the connection point Z1 of R4 and R5 is connected to the FB pin of the control chip.
  • the clamp voltage of the output can be set by changing the resistance value of the two sub-resistors.
  • the resistance value of the sub-resistor R4 is 49.9K ⁇ and the resistance value of the sub-resistor R5 is 4.7K ⁇
  • the clamp voltage can be obtained according to the above formula. V.
  • Step S114 the control chip determines the preset current value according to the resistance value of the sampling resistor according to the following formula:
  • I max is a preset current value
  • R 1 is a resistance value of the sampling resistor
  • the second pin of the control chip is connected to the node Z2 between the second end of the sampling resistor and the load, and the third pin of the control chip is connected.
  • a node Z3 between the first end of the sampling resistor and the source of the field effect transistor.
  • the second pin of the control chip may be an OUT pin
  • the third pin may be an SNS pin
  • the sampling resistor may be a resistor R1
  • the sampling resistor R1 is one end. It is connected to the source of the NMOS transistor Q1, and is connected to the SNS pin of the control chip, and the other end is connected to the output terminal VOUT, and is connected to the OUT pin of the control chip.
  • the maximum current value allowed on the power supply line can be set by changing the resistance value of the sampling resistor R1. When the resistance value of the sampling resistor R1 is 12.5 m ⁇ , the maximum current value can be obtained according to the above formula.
  • control chip may first determine the preset current value according to the resistance value of the sampling resistor, and then determine the preset voltage value according to the resistance value of the voltage dividing resistor.
  • the method further includes the following steps:
  • step S122 the control chip determines whether the voltage value across the protection resistor of the access control chip is greater than the overvoltage voltage value or less than the undervoltage voltage value.
  • the above-mentioned overvoltage voltage value and undervoltage voltage value may be set according to the requirement of the protection voltage.
  • step S124 the control chip controls the field effect transistor to turn off when the voltage value across the protection resistor is greater than the overvoltage voltage value or less than the undervoltage voltage value.
  • the control chip after detecting the voltage value across the protection resistor, the control chip further determines whether the voltage value is greater than the overvoltage voltage value or less than the undervoltage voltage value, and if the voltage value is greater than the overvoltage voltage When the value is used, or when it is judged that the voltage value is smaller than the undervoltage voltage value, the NMOS transistor Q1 is turned off by the GATE pin, and the circuit between the power supply and the circuit of the subsequent stage and the motor is cut off, thereby cutting off the output voltage.
  • step S122 the control chip determines whether the voltage value across the protection resistor of the access control chip is greater than the overvoltage voltage value or less than the undervoltage voltage value, and the method further includes the following steps:
  • step S1232 the control chip determines the overvoltage voltage value and the undervoltage voltage value according to the resistance value of the protection resistor according to the following formula:
  • one end of the protection resistor is connected to the output end of the power source, the other end is connected to the control chip, U OV is an overvoltage voltage value, U UV is an undervoltage voltage value, and R 6 , R 7 and R 8 are respectively in the protection resistor a resistance value of the first sub-resistor, the second sub-resistor and the third sub-resistor, one end of the first sub-protection resistor is connected between the drain of the field effect transistor and the power source, and the other end of the first sub-protection resistor and the second sub- One end of the protection resistor is connected to the second node Z4, and is connected to the eighth pin of the control chip. The other end of the second sub-protection resistor and one end of the third sub-protection resistor are connected to the third node Z5, and are connected to the control chip. The seventh pin, the other end of the third sub-protective resistor is grounded.
  • the seventh pin of the control chip may be an OV pin
  • the eighth pin may be a UV pin, a first sub-protective resistor, and a second sub-protective resistor.
  • the third sub-protection resistor can be resistor R6, resistor R7 and resistor R8, R6, R7 and R8 are connected in series, the other end of R6 is connected to the input terminal VIN, the other end of R8 is grounded, and the connection point Z4 of R6 and R7 is connected.
  • the connection point Z5 of R6 and R7 is connected to the OV pin of the control chip.
  • the overvoltage voltage value and the undervoltage voltage value can be set by changing the resistance values of the three sub-resistors.
  • the resistance value of the sub-resistor R6 is 100K ⁇
  • the resistance value of the sub-resistor R7 is 11.1K ⁇
  • the resistance value of the sub-resistor R8 is 10K ⁇ .
  • the overvoltage voltage value is 15.4V
  • the undervoltage voltage value is 7.3V.
  • step S106 the control chip controls the turn-off of the field effect transistor to include the following steps:
  • step S1062 the control chip controls the capacitance of the twelfth pin of the access control chip to perform charging, and detects the voltage value of the capacitor.
  • the twelfth pin of the control chip may be a TMR pin, and the capacitor may be C2.
  • One end of the capacitor C2 is connected to the TMR end of the control chip, and the other end is grounded.
  • the control chip can further detect that the voltage value of the power output is greater than the overvoltage voltage value, or is less than the undervoltage voltage value, the control capacitor C2 is charged, and the voltage value of the capacitor C2 is detected in real time during the charging process.
  • step S1064 when the voltage value of the capacitor is greater than or equal to the first preset value, the control chip controls the field effect transistor to turn off.
  • the first preset value may be 1.375V.
  • control chip can control the NMOS transistor Q1 of the GATE pin to be turned off when the voltage value of the capacitor C2 reaches 1.375V, thereby cutting off the circuit of the power output to the circuit of the motor and the input of the motor. Connect and protect the circuit and motor of the rear stage.
  • the method further includes the following steps:
  • Step S132 the control chip controls the capacitor to continue charging, and detects the voltage value of the capacitor during the charging process in real time.
  • control chip can continue to control the capacitor C2 for charging after controlling the NMOS transistor Q1 to be turned off, and detect the voltage value of the capacitor C2 in real time during the charging process.
  • Step S134 in the charging process, when the voltage value of the capacitor is greater than or equal to the second preset value, the control chip controls the capacitor to discharge, and continues to detect the voltage value of the capacitor during the discharging process.
  • the second preset value may be 4.3V.
  • control chip can control the capacitor C2 to discharge when the voltage value of the capacitor C2 reaches 4.3V, and detect the voltage of the capacitor C2 in real time during the discharging process.
  • Step S136 in the discharging process, when the voltage value of the capacitor is less than or equal to the third preset value, and the voltage value across the protection resistor and/or the current value flowing through the sampling resistor is detected to satisfy the conduction condition, the control chip control field is controlled. The effect transistor is turned on.
  • the third preset value may be 0.5V.
  • control chip when the control chip detects that the voltage value of the capacitor C2 drops to 0.5V, the control chip detects whether the voltage value of the power supply output satisfies the conduction condition, or whether the current value of the power supply output satisfies the conduction. Condition, if the on condition is satisfied, the NMOS transistor Q1 is controlled to be turned on.
  • the method further includes the following steps:
  • Step S142 the control chip starts timing, and when the timing time reaches the preset time, and the voltage value across the protection resistor is detected and/or the current value flowing through the sampling resistor satisfies the conduction condition, the control field effect transistor is turned on, wherein
  • the preset time can be determined according to the following formula:
  • C 2 is the capacitance value of the capacitor, one end of the capacitor is connected to the twelfth pin of the control chip, and the other end is grounded.
  • the delay time may be a cooling time of the control chip.
  • the cooling time can be calculated according to the above formula to be 336 ms, and the control chip can start timing after the NMOS transistor Q1 is turned off, when the timing time reaches 336 ms.
  • the control chip detects whether the voltage value of the power supply output satisfies the conduction condition, or whether the current value of the power supply output satisfies the conduction condition, if the conduction condition is satisfied, the NMOS transistor Q1 is controlled to be turned on.
  • step S142 the control chip needs to wait for a period of time to control the conduction of the NMOS transistor Q1 after the control NMOS transistor Q1 is turned off. Therefore, any of the two schemes can be selected according to the needs of the actual circuit.
  • control chip controlling the field effect transistor to turn on includes the following steps:
  • Step S152 the control chip determines whether the voltage value across the protection resistor of the access control chip is greater than or equal to the undervoltage voltage value, and is less than or equal to the overvoltage voltage value, wherein the voltage value across the protection resistor of the access control chip is greater than or equal to When the voltage value is pressed and is less than or equal to the overvoltage voltage value, the field effect transistor is controlled to be turned on.
  • the control chip when the control chip determines that the voltage value of the power supply output is greater than the overvoltage voltage of 15.4V, or is less than 7.3V and the NMOS transistor Q1 is turned off, the control chip can drop the voltage value of the capacitor C2. When it reaches 0.5V, or the timing time reaches 336ms, it is judged whether the voltage value of the power supply output is greater than or equal to 7.3V and less than or equal to 15.4V, and when the voltage value is greater than or equal to 7.3V and less than or equal to 15.4V, the NMOS transistor Q1 is controlled. If the voltage value is less than 7.3V, or greater than 15.4V, it is necessary to wait for the voltage value of the power supply output to return to the range of 7.3V to 15.4V and then control the NMOS transistor Q1 to conduct.
  • Step S154 the control chip determines whether the current value flowing through the sampling resistor is less than or equal to a preset current value, wherein the control field effect transistor is turned on if the current value flowing through the sampling resistor is less than or equal to the preset current value.
  • the control chip can reduce the voltage value of the capacitor C2 to 0.5V, or time.
  • the time reaches 336ms, it is judged whether the current value of the power output is less than or equal to 4A, and when the current value is less than or equal to 4A, the NMOS transistor Q1 is controlled to be turned on; if the current value is greater than 4A, the current value of the power output is required to be lower than the setting.
  • the NMOS transistor Q1 is controlled to be turned on.
  • the output end of the power supply is disconnected from the input end of the load by cutting off the external NMOS transistor Q1, so that the protection circuit itself is not damaged, and
  • the output end of the power supply and the input end of the load will be turned back on, so that the entire motor protection circuit works normally, thereby realizing the overcurrent fault of the motor protection circuit, and having the function of reconnecting. purpose.
  • the disclosed technical contents may be implemented in other manners.
  • the device embodiments described above are only schematic.
  • the division of the unit may be a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or may be Integrate into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, unit or module, and may be electrical or otherwise.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.
  • the integrated unit if implemented in the form of a software functional unit and sold or used as a standalone product, may be stored in a computer readable storage medium.
  • the technical solution of the present invention may contribute to the prior art or all or part of the technical solution may be in the form of a software product.
  • the computer software product is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, server or network device, etc.) to perform all or part of the methods of the various embodiments of the present invention. step.
  • the foregoing storage medium includes: a U disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic disk, or an optical disk, and the like. .

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Abstract

一种电机保护电路和控制所述电路的方法。该电机保护电路包括：分压电阻(R4、R5)和采样电阻(R1)；控制芯片，分压电阻(R4、R5)的一端接入控制芯片，采样电阻(R1)的两端都接入控制芯片，用于在检测到分压电阻(R4、R5)两端的电压值大于预设电压值的情况下，将电源电压稳定为预设电压值，和/或在检测到流经采样电阻(R1)的电流值大于预设电流值的情况下，发出关断信号；场效应晶体管(Q1)，栅极接入控制芯片，源极接入采样电阻(R1)一端，用于根据控制芯片产生的关断信号进行关断。所述保护电路及控制方法解决了现有技术中电源保护电路依靠笨重的电感器、电容器、保险丝或瞬态电压抑制器来防止电源电压电流突变损害设备及控制电路的技术问题。

Description

电机保护电路和控制电机保护电路的方法 技术领域
本发明涉及电源管理技术领域，具体而言，涉及一种电机保护电路和控制电机保护电路的方法。
背景技术
在运动控制领域，电源开关的闭合或断开都会产生较大的浪涌及尖峰，从而产生较大的瞬态电流和瞬态电压，对电机及控制电路容易造成损坏或者使电机工作异常。因此，有必要设计一种过流过压保护电路来防止电流或电压突然增大时对控制电路及电机造成损坏。
针对现有技术中电源保护电路依靠笨重的电感器、电容器、保险丝或瞬态电压抑制器来防止电源电压电流突变对设备及控制电路的损害的技术问题，目前尚未提出有效的解决方案。
发明内容
本发明实施例提供了一种电机保护电路和控制电机保护电路的方法，以至少解决现有技术中电源保护电路依靠笨重的电感器、电容器、保险丝或瞬态电压抑制器来防止电源电压电流突变对设备及控制电路的损害的技术问题。
根据本发明实施例的一个方面，提供了一种电机保护电路，包括：分压电阻和采样电阻；控制芯片，分压电阻的一端接入控制芯片，采样电阻的两端都接入控制芯片，用于在检测到分压电阻两端的电压值大于预设电压值的情况下，将电源电压稳定为预设电压值，和/或在检测到流经采样电阻的电流值大于预设电流值的情况下，发出关断信号；场效应晶体管，栅极接入控制芯片，源极接入采样电阻的一端，用于根据控制芯片产生的关断信号进行关断。
根据本发明实施例的另一方面，还提供了一种控制电机保护电路的方法，包括：控制芯片检测接入控制芯片的分压电阻两端的电压值，并判断电压值是否大于预设电压值，和/或检测流经两端都接入控制芯片的采样电阻的电流值，并判断电流值是否大于预设电流值；其中，在电压值大于预设电压值的情况下，控制芯片将电压值稳定为预设电压值之后输出至负载；其中，在电流值大于预设电流值的情况下，控制芯片控 制连接于电源和负载之间的场效应晶体管关断，以断开电源与负载的电连接。
在本发明实施例中，通过控制芯片检测分压电阻两端的电压值，确定电源输出端输出的电压，并在判断出电源输出端输出的电压值大于预设电压值的情况下，将电压值稳定为钳位电压之后输出至负载，通过控制芯片检测流经采样电阻的电流值，确定电源输出端输出的电流，并在判断出电流值大于最大电流值的情况下，控制连接于电源和负载之间的场效应晶体管关断，从而实现在电压突然增大时，可通过自身的输出钳位电路，将输出电压稳定为设置的钳位电压，为电机及后级电路提供安全稳定的工作电压；在电流超出设置的最大阈值电流时，可通过关断外部的MOS关来切断输出电流，以达到保护后级电路和电机的目的，进一步解决现有技术中电源保护电路依靠笨重的电感器、电容器、保险丝或瞬态电压抑制器来防止电源电压电流突变对设备及控制电路的损害的技术问题。通过本申请提供实施例，检测和控制过程简便快捷，整个电机保护电路成本低，集成度高，实用性强。
附图说明
此处所说明的附图用来提供对本发明的进一步理解，构成本申请的一部分，本发明的示意性实施例及其说明用于解释本发明，并不构成对本发明的不当限定。在附图中：
图1是根据本发明实施例的一种电机保护电路的示意图；
图2是根据本发明实施例的一种可选的电机保护电路的示意图；
图3是根据本发明实施例的另一种可选的电机保护电路的示意图；以及
图4是根据本发明实施例的一种控制电机保护电路的方法的流程图。
具体实施方式
为了使本技术领域的人员更好地理解本发明方案，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分的实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都应当属于本发明保护的范围。
需要说明的是，本发明的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本发明的实施例能够以除了在这里图示或描述的那些以外的顺序实施。此外，术语“包括”和“具有”以及他们的 任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
实施例1
根据本发明实施例，提供了一种电机保护电路实施例，图1是根据本发明实施例的一种电机保护电路的示意图，如图1所示，该电机保护电路：分压电阻11，采样电阻13，控制芯片15和场效应晶体管17。
其中，控制芯片15，分压电阻11的一端接入控制芯片15，采样电阻13的两端都接入控制芯片15，用于在检测到分压电阻两端的电压值大于预设电压值的情况下，将电源电压稳定为预设电压值，和/或在检测到流经采样电阻的电流值大于预设电流值的情况下，发出关断信号。
具体地，上述预设电压值可以是电机保护电路输出的钳位电压，上述预设电流值可以是电源线上允许通过的最大电流值，上述负载可以是后级的电路和电机。
场效应晶体管17，栅极接入控制芯片15，源极接入采样电阻13的一端，用于根据控制芯片产生的关断信号进行关断。
具体地，上述场效应晶体管可以是NMOS管，型号为FDB33N25。
图2是根据本发明实施例的一种可选的电机保护电路的示意图，如图2所示，控制芯片的第一管脚可以是FB管脚，第二管脚可以是OUT管脚，第三管脚可以是SNS管脚，第四管脚可以是GATE管脚，电源的输出端连接电机保护电路的输入端VIN，电机保护电路的输出端VOUT连接负载，控制芯片的OUT管脚与输出端VOUT连接，采样电阻一端与NMOS管Q1的源极连接，并连接控制芯片的SNS管脚，另一端与输出端VOUT连接，并连接控制芯片的OUT管脚，分压电阻的一端接入控制芯片的FB管脚，另一端与输出端VOUT连接，NMOS管Q1的漏极与电机保护电路的输入端VIN连接，栅极与控制芯片的GATE管脚连接。
在一种可选的方案中，控制芯片可以通过检测FB管脚的电势，确定分压电阻两端的电压值，从而确定电源输出至电机保护电路的电压值，将该电压值与钳位电压进行比较，如果电源输出的电压值小于等于钳位电压，则说明电源输出的电压值未超过负载的安全电压，可以直接将该电压值输出至后级的电路和电机；如果电源输出的电压值大于钳位电压，则说明该电压值超过负载的安全电压，需要进行过压保护，并通过控制芯片的钳位功能，将输出电压稳定为钳位电压，并通过控制芯片的OUT管脚输出至后级的电路和电机。
在另一种可选的方案中，控制芯片可以通过检测SNS管脚和OUT管脚之间的电势差，确定采样电阻上的电压值，并根据欧姆定律得到流经采样电阻的电流值，从而得到电源输出的电流值，将该电流值与最大电流值进行比较，如果电源输出的电流值大于最大电流值，则说明该电流超出负载的安全电流，需要进行过流保护，并通过控制芯片GATE管脚控制NMOS管Q1关断，切断电源与后级的电路和电机之间的电连接，从而切断输出电流。
本申请上述实施例中，通过控制芯片检测分压电阻两端的电压值，确定电源输出端输出的电压，并在判断出电源输出端输出的电压值大于预设电压值的情况下，将电压值稳定为钳位电压之后输出至负载，通过控制芯片检测流经采样电阻的电流值，确定电源输出端输出的电流，并在判断出电流值大于最大电流值的情况下，控制连接于电源和负载之间的场效应晶体管关断，从而实现在电压突然增大时，可通过自身的输出钳位电路，将输出电压稳定为设置的钳位电压，为电机及后级电路提供安全稳定的工作电压；在电流超出设置的最大阈值电流时，可通过关断外部的MOS关来切断输出电流，以达到保护后级电路和电机的目的，进一步解决现有技术中电源保护电路依靠笨重的电感器、电容器、保险丝或瞬态电压抑制器来防止电源电压电流突变对设备及控制电路的损害的技术问题。通过本申请提供实施例，检测和控制过程简便快捷，整个电机保护电路成本低，集成度高，实用性强。
根据本申请上述实施例，上述控制芯片的类型为LT4363-2。
根据本申请上述实施例，分压电阻包括：第一子分压电阻和第二子分压电阻，其中，第一子分压电阻的一端连接于采样电阻和负载之间，第一子分压电阻的另一端与第二子分压电阻的一端连接于第一节点Z1，并接入控制芯片的第一管脚，第二子分压电阻的另一端接地。
图3是根据本发明实施例的另一种可选的电机保护电路的示意图，如图3所示，控制芯片的第一管脚可以是FB管脚，第二管脚可以是OUT管脚，第三管脚可以是SNS管脚，第四管脚可以是GATE管脚，第五管脚可以是VCC管脚，第六管脚可以是SHDN管脚，第七管脚可以是OV管脚，第八管脚可以是UV管脚，第十二管脚可以是TMR管脚。在一种可选的方案中，上述第一子分压电阻可以是电阻R4，第二子分压电阻可以是电阻R5，R4和R5串联连接，R4的另一端连接控制芯片的OUT管脚，R5的另一端接地，R4和R5的连接点Z1接入控制芯片的FB管脚。
根据本申请上述实施例，采样电阻的第一端经由场效应晶体管接入电源，第二端接入负载，其中，控制芯片的第二管脚接入采样电阻的第二端与负载之间的节点Z2，控制芯片的第三管脚接入采样电阻的第一端和场效应晶体管的源极之间的节点Z3。
在一种可选的方案中，如图3所示，上述控制芯片的第二管脚可以是OUT管脚，第三管脚可以是SNS管脚，采样电阻可以是电阻R1，采样电阻R1一端与NMOS管Q1的源极连接，并接入控制芯片的SNS管脚，另一端与输出端VOUT连接，并接入控制芯片的OUT管脚。
根据本申请上述实施例，控制芯片还用于根据分压电阻的电阻值，确定预设电压值；控制芯片还用于根据采样电阻的电阻值，确定预设电流值。
具体地，根据如下公式确定预设电压值和预设电流值：
Figure PCTCN2016109138-appb-000001
Figure PCTCN2016109138-appb-000002
其中，UREG为预设电压值，R4和R5分别为R4和R5的电阻值，Imax为预设电流值，R1为R1的电阻值。
在一种可选的方案中，可以通过改变两个子电阻的电阻值，设置输出的钳位电压，当子电阻R4的电阻值为49.9KΩ，子电阻R5的电阻值为4.7KΩ时，根据上述计算公式可以得到钳位电压为14.8V。可以通过改变采样电阻R1的电阻值，设置电源线上允许通过的最大电流值，当采样电阻R1的电阻值为12.5mΩ时，根据上述计算公式可以得到最大电流值为4A。
根据本申请上述实施例，上述电机保护电路还包括：
保护电阻，一端与电源连接，另一端与控制芯片连接。
根据本申请上述实施例，保护电阻包括：第一子保护电阻，第二子保护电阻和第三子保护电阻，其中，第一子保护电阻的一端连接于场效应晶体管的漏极和电源之间，第一子保护电阻的另一端与第二子保护电阻的一端连接于第二节点Z4，并接入控制芯片的第八管脚，第二子保护电阻的另一端与第三子保护电阻的一端连接于第三节点Z5，并接入控制芯片的第七管脚，第三子保护电阻的另一端接地。
在一种可选的方案中，如图3所示，上述控制芯片的第七管脚可以是OV管脚，第八管脚可以是UV管脚，第一子保护电阻，第二子保护电阻和第三子保护电阻可以分别是电阻R6，电阻R7和电阻R8，R6、R7和R8串联连接，R6的另一端与输入端VIN连接，R8的另一端接地，R6和R7的连接点Z4接入控制芯片的UV管脚，R6和R7的连 接点Z5接入控制芯片的OV管脚。
根据本申请上述实施例，控制芯片还用于根据保护电阻的电阻值，确定过压电压值和欠压电压值；控制芯片还用于在检测到保护电阻两端的电压值大于过压电压值，或者小于欠压电压值的情况下，发出关断信号。
具体地，可以根据如下公式确定过压电压值和欠压电压值：
Figure PCTCN2016109138-appb-000003
Figure PCTCN2016109138-appb-000004
其中，UOV为过压电压值，UUV为欠压电压值，R6，R7和R8分别为R6，R7和R8的电阻值。
在一种可选的方案中，可以通过改变三个子电阻的电阻值，设置过压电压值和欠压电压值，当子电阻R6的电阻值为100KΩ，子电阻R7的电阻值为11.1KΩ，子电阻R8的电阻值为10KΩ时，根据上述计算公式可以得到过压电压值为15.4V，欠压电压值为7.3V。控制芯片可以在检测到电源输出端输出的电压值之后，进一步判断该电压值是否大于15.4V或者小于7.3V，如果判断出电压值大于15.4V时，或者判断出电压值小于7.3V时，则通过GATE管脚控制NMOS管Q1关断，切断电源与后级的电路和电机之间的电路，从而切断输出电压。
根据本申请上述实施例，上述电机保护电路还包括：
电容，一端接入控制芯片的第十二管脚，另一端接地，用于根据控制芯片发出的充电信号进行充电。
在一种可选的方案中，如图3所示，上述控制芯片的第十二管脚可以是TMR管脚，电容C2的一端接控制芯片的TMR管脚，另一端接地。控制芯片可以再检测到电源输出的电压值大于过压电压值，或者小于欠压电压值时，控制电容C2进行充电，并在充电的过程中，实时检测电容C2的电压值。
控制芯片还用于在检测到电容的电压值大于等于第一预设值的情况下，发出关断信号。
具体地，上述第一预设值可以是1.375V。
在一种可选的方案中，控制芯片可以在检测到电容C2的电压值到达1.375V时， 控制GATE管脚的NMOS管Q1关断，从而切断电源输出端至后级的电路和电机输入端的连接，保护后级的电路和电机。
根据本申请上述实施例，控制芯片还用于控制电容继续进行充电，在充电过程中当检测到电容的电压值大于等于第二预设值时，控制电容进行放电，在放电过程中当检测到电容的电压值小于等于第三预设值，且检测到保护电阻两端的电压值和/或流经采样电阻的电流值满足导通条件时，发出导通信号。
场效应晶体管还用于根据接收到的导通信号进行导通。
具体地，上述第二预设值可以是4.3V，上述第三预设值可以是0.5V。
在一种可选的方案中，控制芯片可以在控制NMOS管Q1关断之后，继续控制电容C2进行充电，并在充电的过程中实时检测电容C2的电压值，当检测到电容C2的电压值达到4.3V时，控制电容C2进行放电，并在放电过程中实时检测电容C2的电压，当检测到电容C2的电压值降至0.5V时，控制芯片检测电源输出的电压值是否满足导通条件，或者电源输出的电流值是否满足导通条件，如果满足导通条件，则控制NMOS管Q1导通。
根据本申请上述实施例，控制芯片还用于在场效应晶体管关断之后，开始计时，并当计时时间到达预设时间，且检测到保护电阻两端的电压值和/或流经采样电阻的电流值满足导通条件时，发出导通信号；场效应晶体管还用于根据接收到的导通信号进行导通。
具体地，上述延时时间可以是控制芯片的冷却时间，可以根据如下公式计算得到：
Figure PCTCN2016109138-appb-000005
其中，t为预设时间，C2为C2的电容值。
在一种可选的方案中，当电容C2的电容值为0.1μF时，根据上述公式可以计算得到冷却时间为336ms，控制芯片可以在NMOS管Q1关断之后，开始计时，当计时时间到达336ms时，控制芯片检测电源输出的电压值是否满足导通条件，或者电源输出的电流值是否满足导通条件，如果满足导通条件，则控制NMOS管Q1导通。
此处需要说明的是，上述控制芯片根据电容的电压值控制场效应晶体管导通和控制芯片根据计时时间控制场效应晶体管导通，两种方案的实现效果均为控制芯片在控制NMOS管Q1关断之后，等待一段冷却时间在控制NMOS管Q1导通。
根据本申请上述实施例，控制芯片还用于在检测到保护电阻两端的电压值大于等于欠压电压值，且小于等于过压电压值的情况下，和/或在检测到流经采样电阻的电流值小于等于预设电流值的情况下，发出导通信号。
在一种可选的方案中，当控制芯片因为判断出电源输出的电压值大于过压电压15.4V，或者小于7.3V而控制NMOS管Q1关断之后，控制芯片可以在电容C2的电压值降至0.5V，或者计时时间到达336ms时，判断电源输出的电压值是否大于等于7.3V，且小于等于15.4V，并在电压值大于等于7.3V，且小于等于15.4V时，控制NMOS管Q1导通；如果电压值小于7.3V，或者大于15.4V，则需等待电源输出的电压值恢复至7.3V～15.4V范围内再控制NMOS管Q1导通。
在另一种可选的方案中，当控制芯片因为判断出电源输出的电流值大于最大电流值4A而控制NMOS管Q1关断之后，控制芯片可以在电容C2的电压值降至0.5V，或者计时时间到达336ms时，判断电源输出的电流值是否小于等于4A，并在电流值小于等于4A时，控制NMOS管Q1导通；如果电流值大于4A，则需等待电源输出的电流值低于设定的最大电流4A时再控制NMOS管Q1导通。
本申请上述实施例中，在持续过压欠压和过流的情况下，通过切断外接的NMOS管Q1，使电源的输出端与负载的输入端断开，从而不会损坏保护电路本身，并且当电压电流恢复正常值时，电源的输出端和负载的输入端会重新导通，使整个电机保护电路工作正常，从而实现电机保护电路的发生过流过压故障时，具有重新接通功能的目的。
根据本申请上述实施例，上述电路还包括：
第一保护电阻，一端接入控制芯片的第五管脚和第六管脚，另一端连接于场效应晶体管的漏极和电源之间。
第二保护电阻，一端接入控制芯片的第四管脚，另一端与场效应晶体管的栅极连接。
保护电容，一端连接于采样电阻和负载之间，另一端接地。
在一种可选的方案中，如图3所示，上述控制芯片的第五管脚可以是VCC管脚，第六管脚可以是SHDN管脚，第一保护电阻可以是电阻R2，第二保护电阻可以是R3，保护电容可以是C1，电阻R2的一端与输入端VIN和NMOS管Q1的漏极连接，另一端接入控制芯片的VCC管脚和SHDN管脚，电阻R3的连接NMOS管Q1的栅极，另一端接入控制芯片的GATE管脚，C1一端连接输出端VOUT，另一端接地，电阻R2和电阻R3用于进行限流，电容C1用于对电流尖峰进行滤波。
需要说明的是，如图3所示，电阻R2，电阻R3和电容C1的选择，以及控制芯片VCC管脚和SHDN管脚的连接方式可以参考linear公司的LT4363数据手册，由于本申请中没有使用FLT管脚被置低以提示电源系统有异常的功能，因此控制芯片ENOUT管脚和FLT管脚没有进行连接，实际使用过程中可以根据需要进行连接。
实施例2
根据本发明实施例，提供了一种控制电机保护电路的方法实施例，需要说明的是，在附图的流程图示出的步骤可以在诸如一组计算机可执行指令的计算机系统中执行，并且，虽然在流程图中示出了逻辑顺序，但是在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤。
图4是根据本发明实施例的一种控制电机保护电路的方法的流程图，如图4所示，结合图4可知，该方法包括如下步骤：
步骤S102，控制芯片检测接入控制芯片的分压电阻两端的电压值，并判断电压值是否大于预设电压值，和/或检测流经两端都接入控制芯片的采样电阻的电流值，并判断电流值是否大于预设电流值。
具体地，上述控制芯片可以是LT4363-2芯片，上述预设电压值可以是电机保护电路输出的钳位电压，上述预设电流值可以是电源线上允许通过的最大电流值。
如图3所示，控制芯片的第一管脚可以是FB管脚，第二管脚可以是OUT管脚，第三管脚可以是SNS管脚，第四管脚可以是GATE管脚，电源的输出端连接电机保护电路的输入端VIN，电机保护电路的输出端VOUT连接负载，控制芯片的VCC管脚与输入端VIN连接，OUT管脚与输出端VOUT连接，采样电阻一端与NMOS管Q1的源极连接，并连接控制芯片的SNS管脚，另一端与输出端VOUT连接，并连接控制芯片的OUT管脚，分压电阻的一端接入控制芯片的FB管脚，另一端与输出端VOUT连接，NMOS管Q1的漏极与电机保护电路的输入端VIN连接，栅极与控制芯片的GATE管脚连接。
在一种可选的方案中，控制芯片可以通过检测FB管脚的电势，确定分压电阻两端的电压值，从而确定电源输出端输出至电机保护电路的电压值，将该电压值与钳位电压进行比较，如果电源输出端输出的电压值大于钳位电压，则说明该电压值超过负载的安全电压，需要进行过压保护。
在另一种可选的方案中，控制芯片可以通过检测SNS管脚和OUT管脚之间的电势差，确定采样电阻上的电压值，并根据欧姆定律得到流经采样电阻的电流值，从而得到电源输出的电流值，将该电流值与最大电流值进行比较，如果电源输出的电流值大于最大电流值，则说明该电流超出负载的安全电流，需要进行过流保护。
步骤S104，在电压值大于预设电压值的情况下，控制芯片将电压值稳定为预设电压值之后输出至负载。
具体地，上述负载可以是后级的电路和电机。
在一种可选的方案中，控制芯片可以在检测电源输出的电压值大于预设电压值，即出现过压现象时，通过控制芯片的钳位功能，将输出电压稳定为钳位电压，并通过控制芯片的OUT管脚输出至后级的电路和电机。
步骤S106，在电流值大于预设电流值的情况下，控制芯片控制连接于电源和负载之间的场效应晶体管关断，以断开电源与负载的电连接。
具体地，上述场效应晶体管可以是NMOS管。
在一种可选的方案中，控制芯片可以在检测电源输出的电流值大于最大电流值，即出现过流现象时，通过控制芯片GATE管脚控制NMOS管Q1关断，切断电源与后级的电路和电机之间的电连接，从而切断输出电流。
本申请上述实施例中，通过控制芯片检测分压电阻两端的电压值，确定电源输出端输出的电压，并在判断出电源输出端输出的电压值大于预设电压值的情况下，将电压值稳定为钳位电压之后输出至负载，通过控制芯片检测流经采样电阻的电流值，确定电源输出端输出的电流，并在判断出电流值大于最大电流值的情况下，控制连接于电源和负载之间的场效应晶体管关断，从而实现在电压突然增大时，可通过自身的输出钳位电路，将输出电压稳定为设置的钳位电压，为电机及后级电路提供安全稳定的工作电压；在电流超出设置的最大阈值电流时，可通过关断外部的MOS关来切断输出电流，以达到保护后级电路和电机的目的，进一步解决现有技术中电源保护电路依靠笨重的电感器、电容器、保险丝或瞬态电压抑制器来防止电源电压电流突变对设备及控制电路的损害的技术问题。通过本申请提供实施例，检测和控制过程简便快捷，整个电机保护电路成本低，集成度高，实用性强。
根据本申请上述实施例，在步骤S102，控制芯片检测接入控制芯片的分压电阻两端的电压值，并判断电压值是否大于预设电压值，和/或检测流经两端都接入控制芯片的采样电阻的电流值，并判断电流值是否大于预设电流值之前，上述方法还包括如下步骤：
步骤S112，控制芯片根据分压电阻的电阻值，根据如下公式确定预设电压值：
Figure PCTCN2016109138-appb-000006
其中，UREG为预设电压值，R4和R5分别为分压电阻中的第一子分压电阻和第二子分压电阻的电阻值，第一子分压电阻的一端连接于采样电阻和负载之间，第一子分压电阻的另一端与第二子分压电阻的一端连接于第一节点Z1，并接入控制芯片的第一管脚，第二子分压电阻的另一端接地。
在一种可选的方案中，如图3所示，上述控制芯片的第一管脚可以是FB管脚，第一子分压电阻可以是R4，第二子分压电阻可以是R5，R4和R5串联连接，R4的另一端连接控制芯片的OUT管脚，R5的另一端接地，R4和R5的连接点Z1接入控制芯片的FB管脚。可以通过改变两个子电阻的电阻值，设置输出的钳位电压，当子电阻R4的电阻值为49.9KΩ，子电阻R5的电阻值为4.7KΩ时，根据上述计算公式可以得到钳位电压为14.8V。
步骤S114，控制芯片根据采样电阻的电阻值，根据如下公式确定预设电流值：
Figure PCTCN2016109138-appb-000007
其中，Imax为预设电流值，R1为采样电阻的电阻值，控制芯片的第二管脚接入采样电阻的第二端与负载之间的节点Z2，控制芯片的第三管脚接入采样电阻的第一端和场效应晶体管的源极之间的节点Z3。
在一种可选的方案中，如图3所示，上述控制芯片的第二管脚可以是OUT管脚，第三管脚可以是SNS管脚，采样电阻可以是电阻R1，采样电阻R1一端与NMOS管Q1的源极连接，并接入控制芯片的SNS管脚，另一端与输出端VOUT连接，并接入控制芯片的OUT管脚。可以通过改变采样电阻R1的电阻值，设置电源线上允许通过的最大电流值，当采样电阻R1的电阻值为12.5mΩ时，根据上述计算公式可以得到最大电流值为4A。
此处需要说明的是，上述步骤S112和步骤S114的执行顺序可以互换，本发明对此不作具体限定。可选地，控制芯片可以先根据采样电阻的电阻值确定预设电流值，然后在根据分压电阻的电阻值确定预设电压值。
根据本申请上述实施例，在步骤S102，控制芯片检测接入控制芯片的分压电阻两端的电压值之后，上述方法还包括如下步骤：
步骤S122，控制芯片判断接入控制芯片的保护电阻两端的电压值是否大于过压电压值，或者小于欠压电压值。
具体地，上述过压电压值和欠压电压值可以根据保护电压的需求进行设置。
步骤S124，在保护电阻两端的电压值大于过压电压值，或者小于欠压电压值的情况下，控制芯片控制场效应晶体管关断。
在一种可选的方案中，控制芯片可以在检测到保护电阻两端的电压值之后，进一步判断该电压值是否大于过压电压值或者小于欠压电压值，如果判断出电压值大于过压电压值时，或者判断出电压值小于欠压电压值时，则通过GATE管脚控制NMOS管Q1关断，切断电源与后级的电路和电机之间的电路，从而切断输出电压。
根据本申请上述实施例，在步骤S122，控制芯片判断接入控制芯片的保护电阻两端的电压值是否大于过压电压值，或者小于欠压电压值之前，上述方法还包括如下步骤：
步骤S1232，控制芯片根据保护电阻的电阻值，根据如下公式确定过压电压值和欠压电压值：
Figure PCTCN2016109138-appb-000008
Figure PCTCN2016109138-appb-000009
其中，保护电阻的一端与电源的输出端连接，另一端与控制芯片连接，UOV为过压电压值，UUV为欠压电压值，R6，R7和R8分别为保护电阻中的第一子电阻，第二子电阻和第三子电阻的电阻值，第一子保护电阻的一端连接于场效应晶体管的漏极和电源之间，第一子保护电阻的另一端与第二子保护电阻的一端连接于第二节点Z4，并接入控制芯片的第八管脚，第二子保护电阻的另一端与第三子保护电阻的一端连接于第三节点Z5，并接入控制芯片的第七管脚，第三子保护电阻的另一端接地。
在一种可选的方案中，如图3所示，上述控制芯片的第七管脚可以是OV管脚，第八管脚可以是UV管脚，第一子保护电阻，第二子保护电阻和第三子保护电阻可以分别是电阻R6，电阻R7和电阻R8，R6、R7和R8串联连接，R6的另一端与输入端VIN连接，R8的另一端接地，R6和R7的连接点Z4接入控制芯片的UV管脚，R6和R7的连接点Z5接入控制芯片的OV管脚。可以通过改变三个子电阻的电阻值，设置过压电压值和欠压电压值，当子电阻R6的电阻值为100KΩ，子电阻R7的电阻值为11.1KΩ，子电阻R8的电阻值为10KΩ时，根据上述计算公式可以得到过压电压值为15.4V，欠压电压值为7.3V。
根据本申请上述实施例，步骤S106，控制芯片控制场效应晶体管关断包括如下步骤：
步骤S1062，控制芯片控制接入控制芯片的第十二管脚的电容进行充电，并检测电容的电压值。
在一种可选的方案中，如图3所示，上述控制芯片的第十二管脚可以是TMR管脚，电容可以是C2，电容C2的一端接控制芯片的TMR端，另一端接地。控制芯片可以再检测到电源输出的电压值大于过压电压值，或者小于欠压电压值时，控制电容C2进行充电，并在充电的过程中，实时检测电容C2的电压值。
步骤S1064，在电容的电压值大于等于第一预设值的情况下，控制芯片控制场效应晶体管关断。
具体地，上述第一预设值可以是1.375V。
在一种可选的方案中，控制芯片可以在检测到电容C2的电压值到达1.375V时，控制GATE管脚的NMOS管Q1关断，从而切断电源输出端至后级的电路和电机输入端的连接，保护后级的电路和电机。
根据本申请上述实施例，在步骤S106，控制芯片控制场效应晶体管关断之后，上述方法还包括如下步骤：
步骤S132，控制芯片控制电容继续进行充电，并实时检测电容在充电过程中的电压值。
在一种可选的方案中，控制芯片可以在控制NMOS管Q1关断之后，继续控制电容C2进行充电，并在充电的过程中实时检测电容C2的电压值。
步骤S134，在充电过程中，当电容的电压值大于等于第二预设值时，控制芯片控制电容进行放电，并继续检测电容在放电过程中的电压值。
具体地，上述第二预设值可以是4.3V。
在一种可选的方案中，控制芯片可以当检测到电容C2的电压值达到4.3V时，控制电容C2进行放电，并在放电过程中实时检测电容C2的电压。
步骤S136，在放电过程中，当电容的电压值小于等于第三预设值，且检测到保护电阻两端的电压值和/或流经采样电阻的电流值满足导通条件时，控制芯片控制场效应晶体管导通。
具体地，上述第三预设值可以是0.5V。
在一种可选的方案中，控制芯片可以当检测到电容C2的电压值降至0.5V时，控制芯片检测电源输出的电压值是否满足导通条件，或者电源输出的电流值是否满足导通条件，如果满足导通条件，则控制NMOS管Q1导通。
根据本申请上述实施例，在步骤S106，控制芯片控制场效应晶体管关断之后，上述方法还包括如下步骤：
步骤S142，控制芯片开始计时，当计时时间到达预设时间，且检测到保护电阻两端的电压值和/或流经采样电阻的电流值满足导通条件时，控制场效应晶体管导通，其中，预设时间可以根据如下公式确定：
Figure PCTCN2016109138-appb-000010
其中，t为预设时间，C2为电容的电容值，电容的一端接入控制芯片的第十二管脚，另一端接地。
具体地，上述延时时间可以是控制芯片的冷却时间。
在一种可选的方案中，当电容C2的电容值为0.1μF时，根据上述公式可以计算得到冷却时间为336ms，控制芯片可以在NMOS管Q1关断之后，开始计时，当计时时间到达336ms时，控制芯片检测电源输出的电压值是否满足导通条件，或者电源输出的电流值是否满足导通条件，如果满足导通条件，则控制NMOS管Q1导通。
此处需要说明的是，上述步骤S132至S136和步骤S142两种方案的实现方式不同，但是本质都是控制芯片在控制NMOS管Q1关断之后，需要等待一段时间在控制NMOS管Q1导通，因此可以根据实际电路的需要选择两种方案中的任意一种。
根据本申请上述实施例，控制芯片控制场效应晶体管导通包括如下步骤：
步骤S152，控制芯片判断接入控制芯片的保护电阻两端的电压值是否大于等于欠压电压值，且小于等于过压电压值，其中，在接入控制芯片的保护电阻两端的电压值大于等于欠压电压值，且小于等于过压电压值的情况下，控制场效应晶体管导通。
在一种可选的方案中，当控制芯片因为判断出电源输出的电压值大于过压电压15.4V，或者小于7.3V而控制NMOS管Q1关断之后，控制芯片可以在电容C2的电压值降至0.5V，或者计时时间到达336ms时，判断电源输出的电压值是否大于等于7.3V，且小于等于15.4V，并在电压值大于等于7.3V，且小于等于15.4V时，控制NMOS管Q1导通；如果电压值小于7.3V，或者大于15.4V，则需等待电源输出的电压值恢复至7.3V～15.4V范围内再控制NMOS管Q1导通。
步骤S154，控制芯片判断流经采样电阻的电流值是否小于等于预设电流值，其中，在流经采样电阻的电流值小于等于预设电流值的情况下，控制场效应晶体管导通。
在一种可选的方案中，当控制芯片因为判断出电源输出的电流值大于最大电流值4A而控制NMOS管Q1关断之后，控制芯片可以在电容C2的电压值降至0.5V，或者计时时间到达336ms时，判断电源输出的电流值是否小于等于4A，并在电流值小于等于4A时，控制NMOS管Q1导通；如果电流值大于4A，则需等待电源输出的电流值低于设定的最大电流4A时再控制NMOS管Q1导通。
本申请上述实施例中，在持续过压欠压和过流的情况下，通过切断外接的NMOS管Q1，使电源的输出端与负载的输入端断开，从而不会损坏保护电路本身，并且当电压电流恢复正常值时，电源的输出端和负载的输入端会重新导通，使整个电机保护电路工作正常，从而实现电机保护电路的发生过流过压故障时，具有重新接通功能的目的。
上述本发明实施例序号仅仅为了描述，不代表实施例的优劣。
在本发明的上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
在本申请所提供的几个实施例中，应该理解到，所揭露的技术内容，可通过其它的方式实现。其中，以上所描述的装置实施例仅仅是示意性的，例如所述单元的划分，可以为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，单元或模块的间接耦合或通信连接，可以是电性或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的 形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可为个人计算机、服务器或者网络设备等)执行本发明各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、移动硬盘、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (23)

  1. 一种电机保护电路，其特征在于，包括：
    分压电阻和采样电阻；
    控制芯片，所述分压电阻的一端接入所述控制芯片，所述采样电阻的两端都接入所述控制芯片，用于在检测到所述分压电阻两端的电压值大于预设电压值的情况下，将电源电压稳定为所述预设电压值，和/或在检测到流经所述采样电阻的电流值大于预设电流值的情况下，发出关断信号；
    场效应晶体管，栅极接入所述控制芯片，源极接入所述采样电阻的一端，用于根据所述控制芯片产生的所述关断信号进行关断。
  2. 根据权利要求1所述的电路，其特征在于，所述控制芯片的类型为LT4363-2。
  3. 根据权利要求1所述的电路，其特征在于，所述分压电阻包括：第一子分压电阻和第二子分压电阻，其中，所述第一子分压电阻的一端连接于所述采样电阻和负载之间，所述第一子分压电阻的另一端与所述第二子分压电阻的一端连接于第一节点，并接入所述控制芯片的第一管脚，所述第二子分压电阻的另一端接地。
  4. 根据权利要求1所述的电路，其特征在于，所述采样电阻的第一端经由所述场效应晶体管接入电源，第二端接入负载，其中，所述控制芯片的第二管脚接入所述采样电阻的第二端与负载之间的节点，所述控制芯片的第三管脚接入所述采样电阻的第一端和所述场效应晶体管的源极之间的节点。
  5. 根据权利要求2所述的电路，其特征在于，
    所述控制芯片还用于根据所述分压电阻的电阻值，确定所述预设电压值；
    所述控制芯片还用于根据所述采样电阻的电阻值，确定所述预设电流值。
  6. 根据权利要求2所述的电路，其特征在于，所述电路还包括：
    保护电阻，一端与所述电源连接，另一端与所述控制芯片连接。
  7. 根据权利要求6所述的电路，其特征在于，所述保护电阻包括：第一子保护电阻，第二子保护电阻和第三子保护电阻，其中，所述第一子保护电阻的一端连接于所述场效应晶体管的漏极和所述电源之间，所述第一子保护电阻的另一端与所述第二子保护电阻的一端连接于第二节点，并接入所述控制芯片的第八管脚，所述第二子保护电阻的另一端与所述第三子保护电阻的一端连接于第三节点，并接入所 述控制芯片的第七管脚，所述第三子保护电阻的另一端接地。
  8. 根据权利要求6所述的电路，其特征在于，
    所述控制芯片还用于根据所述保护电阻的电阻值，确定过压电压值和欠压电压值；
    所述控制芯片还用于根据在检测到所述保护电阻两端的电压值大于所述过压电压值，或者小于所述欠压电压值的情况下，发出所述关断信号。
  9. 根据权利要求2所述的电路，其特征在于，所述电路还包括：
    电容，一端接入所述控制芯片的第十二管脚，另一端接地，用于根据所述控制芯片发出的充电信号进行充电；
    所述控制芯片还用于在检测到所述电容的电压值大于等于预设值的情况下，发出所述关断信号。
  10. 根据权利要求1至9中任意一项所述的电路，其特征在于，
    所述控制芯片还用于在所述场效应晶体管关断之后，控制电容继续进行充电；
    所述控制芯片还用于当检测到所述电容的电压值大于等于第二预设值时，控制所述电容进行放电；
    所述场效应晶体管还用于根据所述控制芯片产生的导通信号进行导通。
  11. 根据权利要求10所述的电路，其特征在于，所述控制芯片还用于当检测到所述电容两端的电压值小于等于第三预设值时，在检测到保护电阻两端的电压值大于等于欠压电压值，且小于等于过压电压值的情况下，和/或在检测到流经所述采样电阻的电流值小于等于所述预设电流值的情况下，发出所述导通信号。
  12. 根据权利要求1至9中任意一项所述的电路，其特征在于，
    所述控制芯片还用于在所述场效应晶体管关断之后，开始计时；
    所述场效应晶体管还用于根据所述控制芯片产生的导通信号进行导通。
  13. 根据权利要求12所述的电路，其特征在于，所述控制芯片还用于当计时时间到达预设时间时，在检测到保护电阻两端的电压值大于等于欠压电压值，且小于等于过压电压值的情况下，和/或在检测到流经所述采样电阻的电流值小于等于所述预设电流值的情况下，发出所述导通信号。
  14. 根据权利要求2所述的电路，其特征在于，所述电路还包括：
    第一保护电阻，一端接入所述控制芯片的第五管脚和第六管脚，另一端连接于所述场效应晶体管的漏极和电源之间；
    第二保护电阻，一端接入所述控制芯片的第四管脚，另一端与所述场效应晶体管的栅极连接；
    保护电容，一端连接于所述采样电阻和负载之间，另一端接地。
  15. 一种控制电机保护电路的方法，其特征在于，包括：
    控制芯片检测接入所述控制芯片的分压电阻两端的电压值，并判断所述电压值是否大于预设电压值，和/或检测流经两端都接入所述控制芯片的采样电阻的电流值，并判断所述电流值是否大于预设电流值；
    其中，在所述电压值大于所述预设电压值的情况下，所述控制芯片将电源电压稳定为所述预设电压值之后输出至负载；
    其中，在所述电流值大于所述预设电流值的情况下，所述控制芯片控制连接于所述电源和所述负载之间的场效应晶体管关断，以断开所述电源与所述负载的电连接。
  16. 根据权利要求15所述的方法，其特征在于，在控制芯片检测接入所述控制芯片的分压电阻两端的电压值，并判断所述电压值是否大于预设电压值，和/或检测流经两端都接入所述控制芯片的采样电阻的电流值，并判断所述电流值是否大于预设电流值之前，所述方法还包括：
    所述控制芯片根据所述分压电阻的电阻值，根据如下公式确定所述预设电压值：
    Figure PCTCN2016109138-appb-100001
    其中，所述UREG为所述预设电压值，所述R4和所述R5分别为所述分压电阻中的第一子分压电阻和第二子分压电阻的电阻值，所述第一子分压电阻的一端连接于所述采样电阻和负载之间，所述第一子分压电阻的另一端与所述第二子分压电阻的一端连接于第一节点，并接入所述控制芯片的第一管脚，所述第二子分压电阻的另一端接地；
    所述控制芯片根据所述采样电阻的电阻值，根据如下公式确定所述预设电流值：
    Figure PCTCN2016109138-appb-100002
    其中，所述Imax为所述预设电流值，所述R1为所述采样电阻的电阻值，所述控制芯片的第二管脚接入所述采样电阻的第二端与负载之间的节点，所述控制芯片的第三管脚接入所述采样电阻的第一端和所述场效应晶体管的源极之间的节点。
  17. 根据权利要求15所述的方法，其特征在于，在控制芯片检测接入所述控制芯片的分压电阻两端的电压值之后，所述方法还包括：
    所述控制芯片判断接入所述控制芯片的保护电阻两端的电压值是否大于过压电压值，或者小于欠压电压值；
    在所述保护电阻两端的电压值大于所述过压电压值，或者小于所述欠压电压值的情况下，所述控制芯片控制所述场效应晶体管关断。
  18. 根据权利要求17所述的方法，其特征在于，在所述控制芯片判断所述保护电阻两端的电压值是否大于过压电压值，或者小于欠压电压值之前，所述方法还包括：
    所述控制芯片根据所述保护电阻的电阻值，根据如下公式确定所述过压电压值和所述欠压电压值：
    Figure PCTCN2016109138-appb-100003
    Figure PCTCN2016109138-appb-100004
    其中，所述UOV为所述过压电压值，所述UUV为所述欠压电压值，所述R6，所述R7和所述R8分别为所述保护电阻中的第一子保护电阻，第二子保护电阻和第三子保护电阻的电阻值，所述第一子保护电阻的一端连接于所述场效应晶体管的漏极和所述电源之间，所述第一子保护电阻的另一端与所述第二子保护电阻的一端连接于第二节点，并接入所述控制芯片的第八管脚，所述第二子保护电阻的另一端与所述第三子保护电阻的一端连接于第三节点，并接入所述控制芯片的第七管脚，所述第三子保护电阻的另一端接地。
  19. 根据权利要求17所述的方法，其特征在于，所述控制芯片控制所述场效应晶体管关断包括：
    所述控制芯片控制接入所述控制芯片的第十二管脚的电容进行充电，并检测所述电容的电压值；
    在所述电容的电压值大于等于预设值的情况下，所述控制芯片控制所述场效应晶体管关断。
  20. 根据权利要求15至19中任意一项所述的方法，其特征在于，在所述控制芯片控制所述场效应晶体管关断之后，所述方法还包括：
    所述控制芯片控制电容继续进行充电，并实时检测所述电容在充电过程中的电压值；
    在所述充电过程中，当所述电容的电压值大于等于第二预设值时，所述控制芯片控制所述电容进行放电，并继续检测所述电容在放电过程中的电压值；
    在所述放电过程中，当所述电容的电压值小于等于第三预设值，且检测到保护电阻两端的电压值和/或流经所述采样电阻的电流值满足导通条件时，所述控制芯片控制所述场效应晶体管导通。
  21. 根据权利要求20所述的方法，其特征在于，所述控制芯片控制所述场效应晶体管导通包括：
    所述控制芯片判断所述保护电阻两端的电压值是否大于等于欠压电压值，且小于等于过压电压值，其中，在所述保护电阻两端的电压值大于等于所述欠压电压值，且小于等于所述过压电压值的情况下，控制所述场效应晶体管导通；和/或
    所述控制芯片判断流经所述采样电阻的电流值是否小于等于所述预设电流值，其中，在流经所述采样电阻的电流值小于等于所述预设电流值的情况下，控制所述场效应晶体管导通。
  22. 根据权利要求15至19中任意一项所述的方法，其特征在于，在所述控制芯片控制所述场效应晶体管关断之后，所述方法还包括：
    所述控制芯片开始计时，当计时时间到达预设时间，且检测到接入所述控制芯片的保护电阻两端的电压值和/或流经所述采样电阻的电流值满足导通条件时，控制所述场效应晶体管导通，其中，所述预设时间可以根据如下公式确定：
    Figure PCTCN2016109138-appb-100005
    其中，所述t为所述预设时间，所述C2为电容的电容值，所述电容的一端接入所述控制芯片的第十二管脚，另一端接地。
  23. 根据权利要求22所述的方法，其特征在于，所述控制芯片控制所述场效应晶体管导通包括：
    所述控制芯片判断保护电阻两端的电压值是否大于等于欠压电压值，且小于等于过压电压值，其中，在接入所述控制芯片的保护电阻两端的电压值大于等于所述欠压电压值，且小于等于所述过压电压值的情况下，控制所述场效应晶体管导通；和/或
    所述控制芯片判断流经所述采样电阻的电流值是否小于等于所述预设电流值，其中，在流经所述采样电阻的电流值小于等于所述预设电流值的情况下，控制所述场效应晶体管导通。
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