WO2017114061A1 - Système de multitraitement asymétrique, et procédé pour gérer une ressource matérielle de ce dernier - Google Patents

Système de multitraitement asymétrique, et procédé pour gérer une ressource matérielle de ce dernier Download PDF

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Publication number
WO2017114061A1
WO2017114061A1 PCT/CN2016/107744 CN2016107744W WO2017114061A1 WO 2017114061 A1 WO2017114061 A1 WO 2017114061A1 CN 2016107744 W CN2016107744 W CN 2016107744W WO 2017114061 A1 WO2017114061 A1 WO 2017114061A1
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core
hardware resource
standard
hardware resources
common hardware
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PCT/CN2016/107744
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Chinese (zh)
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廖通
廖俊锋
钟小武
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中兴通讯股份有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5061—Partitioning or combining of resources
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/177—Initialisation or configuration control

Definitions

  • This paper refers to, but is not limited to, the field of wireless communication technology, and relates to a multi-core heterogeneous system and a method for managing its hardware resources.
  • multi-core processing systems mainly have two structures: one is SMP (Symmetric Multi-Processing), and the other is AMP (Asymmetric Multi-Processing).
  • SMP Symmetric Multi-Processing
  • AMP Asymmetric Multi-Processing
  • baseband chips need to process baseband signals.
  • the processing of baseband signals includes L1 (physical layer), L2 (MAC (Medium Access Control), and RLC. (Radio Link Control, Radio Link Layer Control Protocol), PDCP (Packet Data Convergence Protocol) and other protocol layer, such as RRC (Radio Resource Control)
  • L1 physical layer
  • L2 Medium Access Control
  • RLC Radio Link Control, Radio Link Layer Control Protocol
  • PDCP Packet Data Convergence Protocol
  • RRC Radio Resource Control
  • the baseband chip should use a special processor or accelerator, and also have a universal core for the management of the base station and the functions of the L2 and L3 of the wireless communication protocol. Therefore, the baseband chip can adopt the AMP architecture chip, and some cores complete the L1 (physical The function of the layer), part of the core completes the management of the base station and the L2 and L3 functions of the wireless communication protocol.
  • a wireless base station As a common communication device in the field of wireless communication, a wireless base station includes a single-system base station and a multi-standard base station (the common system of the base station includes GSM, UMTS, CDMA, LTE-FDD, LTE_TDD, etc.) base stations.
  • the wireless base station In order to expand its capacity, baseband chips use heterogeneous multi-core processing systems, and the baseband chips of related wireless base stations have fixed hardware resources for each system (hardware resources include but are not limited to network port queues, counters, and shares. Memory, inter-core interrupts, etc.), hardware resources can not be shared, thus causing a waste of hardware resources.
  • the embodiment of the invention provides a hardware resource management method for a multi-core heterogeneous system, which can dynamically allocate resources required by each system according to the requirements of the standard resource configuration, and reduce waste of hardware resources.
  • the embodiment of the invention provides a method for managing hardware resources of a multi-core heterogeneous system, including:
  • the main core registers the common hardware resources required for the operation of each standard
  • the main core performs read management on common hardware resources
  • the primary core After receiving the hardware resource requirement information sent by the core corresponding to any standard, the primary core allocates the common hardware resources required for the operation of the system to the slave core corresponding to the standard according to the registration information corresponding to the standard.
  • the multi-core heterogeneous system is a multi-core heterogeneous system of a base station.
  • the method further includes: the primary core receives the hardware resource requirement information sent by the core from any system, and allocates the common hardware resources required for the operation of the system according to the registration information corresponding to the standard After the step of the slave core corresponding to the standard, the operating state of each system is monitored;
  • the master core performs read management on the common hardware resources, including:
  • the primary core reserves a common hardware resource required for transferring data between the primary core and the secondary core;
  • the common hardware resources of the common hardware resources except the reserved common hardware resources are arranged through a mapping relationship table, where the mapping relationship table includes location information of the common hardware resources.
  • the common hardware resource required for the operation of the standard is allocated to the standard corresponding
  • the slave core includes:
  • the primary core After receiving the hardware resource requirement information sent by the core from any core, the primary core queries the location information corresponding to the common hardware resource required for the operation according to the mapping relationship table;
  • the location information corresponding to the common hardware resource required for the operation of the system is sent to the slave core corresponding to the standard.
  • the embodiment of the present invention further provides a multi-core heterogeneous system, including a primary core, a secondary core, and a common hardware resource, where the primary core includes:
  • a hardware resource registration module configured to register a common hardware resource required for the operation of each standard
  • a hardware resource management module configured to read and manage common hardware resources
  • the hardware resource allocation module is configured to: after receiving the hardware resource requirement information sent by the core of any standard, and according to the registration information corresponding to the standard, allocate the common hardware resources required for the operation of the standard to the corresponding system From the nuclear.
  • the multi-core heterogeneous system is a multi-core heterogeneous system of a base station.
  • the primary core further includes:
  • the system operation monitoring module is set to monitor the operating status of each system
  • the hardware resource recovery module is configured to recover all common hardware resources of the system if an abnormality is detected in any of the systems.
  • the hardware resource management module includes:
  • a hardware resource reservation unit configured to reserve a common hardware resource required for transferring data between the primary core and the secondary core
  • a hardware resource list unit configured to: arrange, by the mapping relationship table, the remaining common hardware resources except the reserved common hardware resource in the common hardware resource, where the mapping relationship table includes a location of the common hardware resource. information.
  • the hardware resource allocation module includes:
  • the hardware resource query unit is configured to: after receiving the hardware resource requirement information sent by the core of any standard, query the location information corresponding to the common hardware resource required for the operation according to the mapping relationship table;
  • the hardware resource delivery unit is configured to send the location information corresponding to the common hardware resource required for the standard operation to the slave core corresponding to the standard.
  • the embodiment of the invention further provides a computer readable storage medium, wherein the computer readable storage medium stores computer executable instructions, and when the computer executable instructions are executed, a method for managing hardware resources of a multi-core heterogeneous system is implemented.
  • Embodiments of the present invention provide a multi-core heterogeneous system and a hardware resource management method thereof.
  • the management method of the hardware resources of the nuclear heterogeneous system includes: the main core registers the common hardware resources required for the operation of each system; reads and manages the common hardware resources; and receives the hardware resources sent by the core from any standard.
  • the hardware resource management method of the multi-core heterogeneous system can dynamically allocate the common hardware resources required by each system according to the requirements of the standard resource configuration, so as to ensure that the common hardware resources of the multi-core heterogeneous system can be more flexibly utilized. Avoid wasting hardware resources.
  • FIG. 1 is a schematic flowchart of a method for managing hardware resources of a multi-core heterogeneous system according to Embodiment 1 of the present invention
  • step S12 in FIG. 1 is a schematic flow chart of step S12 in FIG. 1;
  • step S14 in FIG. 1 is a schematic flow chart of step S14 in FIG. 1;
  • FIG. 4 is another schematic flowchart of a method for managing hardware resources of a multi-core heterogeneous system according to Embodiment 1 of the present invention.
  • FIG. 5 is a schematic structural diagram of a main core of a multi-core heterogeneous system according to Embodiment 2 of the present invention.
  • FIG. 6 is a schematic structural diagram of a hardware resource management module of the primary core in FIG. 5;
  • FIG. 7 is a schematic structural diagram of a hardware resource allocation module of the primary core in FIG. 5;
  • FIG. 8 is another schematic structural diagram of a main core of a multi-core heterogeneous system according to Embodiment 2 of the present invention.
  • FIG. 9 is a schematic structural diagram of applying a multi-core heterogeneous system to a base station system according to Embodiment 2 of the present invention.
  • FIG. 10 is a schematic structural view of the multi-core heterogeneous system of FIG. 9 further refined.
  • FIG. 1 is a schematic flowchart of a method for managing hardware resources of a multi-core heterogeneous system according to an embodiment of the present invention.
  • the management methods of the hardware resources of the system include:
  • Step S10 The main core registers the public hardware resources required for the operation of each standard
  • Multi-core heterogeneous systems include a primary core and at least one secondary core.
  • the number of cores is not limited. The specific quantity depends on the requirements of the system, and usually the primary core and the operating system from the core are different.
  • the main core runs an operating system that supports multi-process scheduling, which facilitates the registration and registration of hardware resource requirements for each standard. It runs a lightweight operating system from the core or does not run the operating system, which is convenient for high performance and low performance of each system. Delay requirement.
  • the main core is created with the main process, and the corresponding slave processes are respectively created according to the system configuration system.
  • the system standard is single-system or multi-standard. Accordingly, the number of slave processes of the master core is also one or more, from the process.
  • the function is to perform protocol processing between the core and the main core corresponding to each standard, and to register and register the hardware resources required for each system.
  • Step S12 Perform reading management on common hardware resources
  • the main process reads and manages the common hardware resources according to certain rules.
  • the main process retains a part of the hardware resources for the normal data (including request messages and response messages) between the primary core and the secondary core to maintain the primary core.
  • Step S14 Receive hardware resource requirement information sent by the core according to any standard, and allocate hardware resources required for the operation of the system to the corresponding slave core according to the registration information corresponding to the standard.
  • the main process waits for the hardware resource requirement message sent by the core of each system, and the hardware resource requirement information sent by the core from any system to the main core, and the main core receives the hardware sent by the core of the system.
  • the main core passes the slave process of the standard in the main core, and the hardware resource
  • the source demand information is processed by the protocol, and the processed hardware resource requirement information is sent to the main process, and the main process obtains the hardware resource of the standard requirement according to the corresponding registration information in the slave process of the standard, and runs the system.
  • the required hardware resources are allocated to the corresponding slave cores.
  • the multi-core heterogeneous system may be a multi-core heterogeneous system of the base station, for example, a multi-core heterogeneous baseband chip of the wireless base station, or a multi-core heterogeneous radio frequency chip of the wireless base station, etc., of course,
  • the multi-core heterogeneous system is not limited thereto, and may be a multi-core heterogeneous chip of other communication devices.
  • FIG. 2 is a schematic flowchart of step S12 in FIG. 1.
  • Step S12 includes:
  • Step S120 The main core reserves a common hardware resource required for transferring data between the primary core and the secondary core;
  • Step S122 The remaining common hardware resources are arranged in the form of a mapping relationship table, where the mapping relationship table includes location information of the common hardware resources.
  • Common hardware resources include, but are not limited to, network port queues, counters, shared memory, and inter-core interrupts.
  • the primary core reserves the need for fixed hardware resources to be transmitted between the primary core and the secondary core. Data (including request information, response information, etc.) to maintain the normal communication between the primary core and the secondary core. In view of this, it is necessary to reserve the common hardware resources needed to transfer data between the primary core and the secondary core.
  • the public hardware resources except the reserved main core and the common hardware resources required to transfer data between the cores are arranged through the mapping relationship table, as the common hardware resources of the slave core corresponding to each system. , that is, the resource pool, the mapping relationship table should include the location of the hardware resources (including the index or address), and may also include the type and size of the hardware resources.
  • FIG. 3 is a schematic flowchart of step S14 in FIG. 1.
  • Step S14 includes:
  • Step S140 Receive hardware resource requirement information sent by the core from any standard, and query location information corresponding to hardware resources required for the operation according to the mapping relationship table;
  • Step S142 sending location information corresponding to the hardware resources required for the operation of the system to the standard Corresponding from the core.
  • the slave core sends hardware resource requirement information to the master core, and the master core passes the corresponding slave process in the master core to perform protocol processing on the hardware resource requirement information, and the processed hardware is processed.
  • the resource requirement information is sent to the main process, and the main process obtains the hardware resources required by the standard according to the registration information corresponding to the standard in the corresponding process of the corresponding system, and further, the corresponding hardware resource can be found through the mapping relationship table.
  • Location information (including an index or an address), and then the location information is processed by the protocol of the process and sent to the corresponding slave core, and the slave core can call the common hardware resource according to the location information.
  • FIG. 4 is still another schematic flowchart of a method for managing hardware resources of a multi-core heterogeneous system according to an embodiment of the present invention. Referring to FIG. 4, after step S14, the method further includes:
  • Step S16 monitoring the operating status of each system
  • Each system has a corresponding slave process in the slave core of the master core and the system.
  • the slave process established in the master core is the protocol processing corresponding to the standard (for example, the L3 part of the corresponding baseband chip).
  • the slave process in the slave core mainly lies in the specific operation of the system (for example, the L1 and L2 parts of the corresponding baseband chip). For this reason, monitoring the operating state of each system requires monitoring the corresponding slave processes in the master core and correspondingly. From the nuclear process.
  • Step S18 If an abnormality occurs in the operation of any of the standards, all common hardware resources of the system are recovered.
  • the embodiment of the present invention further provides a multi-core heterogeneous system, including a primary core 100, a secondary core (not shown), and a common hardware resource (not shown, including but not limited to a network port queue, a counter, a shared memory, and an inter-core interrupt.
  • FIG. 5 is a structural diagram of a main core of a multi-core heterogeneous system according to an embodiment of the present invention.
  • the main core 100 includes a hardware resource registration module 10, a hardware resource management module 12, and a hardware resource allocation module 14.
  • the hardware resource registration module 10 is configured to register a common hardware resource required for the operation of each standard
  • Multi-core heterogeneous systems include a primary core and at least one secondary core.
  • the number of cores is not limited. The specific quantity depends on the requirements of the system, and usually the primary core and the operating system from the core are different.
  • the main core runs an operating system that supports multi-process scheduling, which facilitates registration and registration of hardware resource requirements of various standards. It runs a lightweight operating system from the core or does not run an operating system, which is convenient for high performance and low operation of each system. Delay requirement.
  • the main core is created with the main process, and the corresponding slave processes are respectively created according to the system configuration system.
  • the system standard is single-system or multi-standard. Accordingly, the number of slave processes of the master core is also one or more, from the process.
  • the function is to perform protocol processing between the core and the main core corresponding to each standard, and to register and register the hardware resources required for each system.
  • the hardware resource management module 12 is configured to perform read management on common hardware resources
  • the main process reads and manages the common hardware resources according to certain rules.
  • the main process retains a part of the hardware resources for the normal data (including request messages and response messages) between the primary core and the secondary core to maintain the primary core.
  • the hardware resource allocation module 14 is configured to allocate the common hardware resources required for the operation of the system to the corresponding slave core according to the registration information corresponding to the standard after receiving the hardware resource requirement information sent by the core of any standard. .
  • the main process waits for the hardware resource requirement message sent by the core in each mode, and the hardware resource requirement information sent by the core from any system to the main core, and the main core passes the corresponding standard slave process in the main core, and the hardware resource requirement
  • the information is processed by the protocol, and the processed hardware resource requirement information is sent to the main process, and the main process obtains the hardware resources required by the standard according to the registration information corresponding to the standard in the process according to the corresponding standard, and the The hardware resources required for the operation of the system are allocated to the corresponding slave cores.
  • FIG. 6 is a structure of a hardware resource management module of the primary core in FIG.
  • the hardware resource management module 12 includes a hardware resource reservation unit 120 and a hardware resource list unit 122:
  • the hardware resource reservation unit 120 is configured to reserve a common hardware resource required for transferring data between the primary core and the secondary core;
  • the hardware resource list unit 122 is configured to arrange the common hardware resources except the reserved common hardware resources in the common hardware resource by using a mapping relationship table, where the mapping relationship table includes location information of the common hardware resources. .
  • Common hardware resources include, but are not limited to, network port queues, counters, shared memory, and inter-core interrupts. Each system has different requirements for hardware resource usage.
  • the primary core reserves the need for fixed hardware resources to be transmitted between the primary core and the secondary core. Data (including request information, response information, etc.) to maintain the normal communication between the primary core and the secondary core. In view of this, it is necessary to reserve the common hardware resources needed to transfer data between the primary core and the secondary core.
  • the remaining common hardware resources are arranged in the form of a mapping relationship table, which is a common hardware resource corresponding to the core operation time, that is, a resource pool corresponding to each system, and the mapping relationship table should include the location of the hardware resource (including an index or an address), and It can include the type and size of hardware resources.
  • a mapping relationship table which is a common hardware resource corresponding to the core operation time, that is, a resource pool corresponding to each system, and the mapping relationship table should include the location of the hardware resource (including an index or an address), and It can include the type and size of hardware resources.
  • FIG. 7 is a schematic structural diagram of a hardware resource allocation module of the primary core in FIG. 5, where the hardware resource allocation module includes a hardware resource query unit 140 and a hardware resource delivery unit 142:
  • the hardware resource query unit 140 is configured to: after receiving the hardware resource requirement information sent by the core of any standard, query the location information corresponding to the hardware resource required for the operation according to the mapping relationship table;
  • the hardware resource delivery unit 142 is configured to send the location information corresponding to the hardware resources required for the standard operation to the slave core corresponding to the standard.
  • the slave core sends hardware resource requirement information to the master core, and the master core passes the corresponding slave process in the master core to perform protocol processing on the hardware resource requirement information, and the processed hardware is processed.
  • the resource requirement information is sent to the main process, and the main process obtains the hardware resource of the system operation requirement according to the corresponding registration information in the slave process of the system, and further, through the above mapping
  • the relationship table can find the location information (including the index or address) of the corresponding public hardware resource, and then the location information is sent to the slave core through the protocol of the process, and the slave core can use the location information to the common hardware.
  • the resource is called.
  • FIG. 8 is another schematic structural diagram of a main core of a multi-core heterogeneous system according to an embodiment of the present invention.
  • the main core further includes a standard operation monitoring module 16 and hardware resource recovery.
  • Module 18 :
  • the system operation monitoring module 16 is configured to monitor the operating status of each system
  • each system corresponds to a master process
  • a slave process corresponding to the master core has a corresponding slave process.
  • the slave process established in the master core is a protocol process corresponding to the standard (for example, a corresponding baseband).
  • the L3 portion of the chip), the slave process in the slave core is primarily used for the specific operation of the system (eg, the L1 and L2 portions of the corresponding baseband chip). To this end, to monitor the operating status of each system, it is necessary to simultaneously monitor the corresponding slave processes in the master core and the slave processes corresponding to the slave cores.
  • the hardware resource recovery module 18 is configured to recover all hardware resources of the system if an abnormality occurs in any of the systems monitored.
  • the multi-core heterogeneous system may be a multi-core heterogeneous system of the base station, for example, a multi-core heterogeneous baseband chip of the wireless base station, or a multi-core heterogeneous radio frequency chip of the wireless base station, etc., of course,
  • the multi-core heterogeneous system is not limited thereto, and may also be a multi-core heterogeneous chip of other communication devices.
  • FIG. 9 is a schematic structural diagram of a multi-core heterogeneous system applied to a base station system according to an embodiment of the present invention
  • FIG. 10 is a schematic structural diagram of further refinement of the multi-core heterogeneous system of FIG. 9.
  • the multi-core The heterogeneous system uses the main core of the multi-core heterogeneous system in the embodiment of Figure 8:
  • AMP-based SoC System-on-a-Chip
  • baseband chip with strong processing capability, each with N cores, including UMTS (Universal Mobile Telecommunications System), GSM (Global System for In the multi-standard site of Mobile communication (Global System for Mobile Communications), in some scenarios, a new generation of baseband chips can support two UMTS and GSM standards at the same time. In order to fully utilize the hardware capabilities, plan each piece. The baseband chip runs UMTS and GSM simultaneously.
  • the main core runs on the Linux multi-process operating system and creates three processes, one main process, one slave process corresponding to the UMTS system (mainly responsible for UMTS standard protocol processing), and one GSM standard corresponding slave.
  • Process 2 (mainly responsible for GSM standard protocol processing); running a lightweight LWOS operating system from the core, running a lightweight task from the core, and deploying UMTS services from core 1 to core M according to resource requirements,
  • the cores M+1 to N are used to deploy GSM services, where M and N are positive integers greater than 1, and M is less than N.
  • the main core main process is split into a hardware resource allocation module (abbreviated as an allocation module in FIG. 10) and a standard operation monitoring module (referred to as a monitoring module in FIG. 10), and the main core is removed from the process 1.
  • the hardware resource registration module (referred to as registration in FIG. 10) divided into UMTS base station service (L3) and UMTS standard requirements, and is divided into GSM base station service (L3) and hardware resource registration module required by UMTS system from process 2 (in In FIG.
  • L1 ⁇ L2 UMTS base station service
  • L1 ⁇ L2 UMTS base station service
  • the embodiment of the invention further provides a computer readable storage medium, wherein the computer readable storage medium stores computer executable instructions, and when the computer executable instructions are executed, a method for managing hardware resources of a multi-core heterogeneous system is implemented.
  • the above technical solution can dynamically allocate the common hardware resources required by each system, and ensure that the common hardware resources of the multi-core heterogeneous system can be more flexibly utilized to avoid waste of hardware resources.

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Abstract

L'invention concerne un système de multitraitement asymétrique et un procédé pour gérer une ressource matérielle de ce dernier. Le procédé pour gérer une ressource matérielle du système de multitraitement asymétrique comprend les étapes suivantes : enregistrer, par un cœur maître, une ressource matérielle commune requise pour une opération de chaque mode (S10) ; lire et gérer la ressource matérielle commune (S12) ; et recevoir, en provenance d'un cœur esclave correspondant à un mode, des informations associées à une ressource matérielle requise pour une opération du mode, et attribuer, selon des informations d'enregistrement correspondant au mode, au cœur esclave, une ressource matérielle commune requise pour l'opération du mode (S14). Le procédé pour gérer une ressource matérielle du système de multitraitement asymétrique peut attribuer de manière dynamique des ressources matérielles communes requises par des modes respectifs selon des exigences d'attribution de ressource des modes respectifs, en permettant ainsi de garantir une utilisation souple des ressources matérielles communes du système de multitraitement asymétrique, et d'empêcher le gaspillage des ressources matérielles communes.
PCT/CN2016/107744 2015-12-28 2016-11-29 Système de multitraitement asymétrique, et procédé pour gérer une ressource matérielle de ce dernier WO2017114061A1 (fr)

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CN112068955A (zh) * 2020-08-21 2020-12-11 北京科技大学 一种异构多核平台处理器内的通信优化方法及电子设备

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