WO2017111826A1 - Recuit sous deutérium pour transistor à effet de champ iii-v non planar - Google Patents

Recuit sous deutérium pour transistor à effet de champ iii-v non planar Download PDF

Info

Publication number
WO2017111826A1
WO2017111826A1 PCT/US2015/000384 US2015000384W WO2017111826A1 WO 2017111826 A1 WO2017111826 A1 WO 2017111826A1 US 2015000384 W US2015000384 W US 2015000384W WO 2017111826 A1 WO2017111826 A1 WO 2017111826A1
Authority
WO
WIPO (PCT)
Prior art keywords
iii
layer
deuterium
channel
barrier layer
Prior art date
Application number
PCT/US2015/000384
Other languages
English (en)
Inventor
Srinivasa Aravind KILLAMPALLI
Jay Prakash GUPTA
Willy Rachmady
Joshua M. HOWARD
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to PCT/US2015/000384 priority Critical patent/WO2017111826A1/fr
Publication of WO2017111826A1 publication Critical patent/WO2017111826A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/3003—Hydrogenation or deuterisation, e.g. using atomic hydrogen from a plasma
    • H01L21/3006—Hydrogenation or deuterisation, e.g. using atomic hydrogen from a plasma of AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66522—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with an active layer made of a group 13/15 material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Definitions

  • New transistor architectures such as non-planar field effect transistors (FETs)
  • new transistor materials such as group III-V materials
  • FETs field effect transistors
  • group III-V materials group III-V materials
  • current manufacturing processes are failing to adequately passivate interfaces (such as III-V semiconductor channel/gate interfaces) and defects in gate dielectric materials in non-planar group III-V FETs, particularly for highly scaled non-planar group ⁇ -V transistor architectures.
  • FIG. 2A illustrates a schematic cross-sectional view of the integrated circuit device of FIG. 1 A along line B-B during a high pressure, deuterium anneal process according to various aspects of the present disclosure
  • FIG. 2B illustrate a schematic cross-sectional view of the integrated circuit device of FIG. 1A along line B-B after a high pressure, deuterium anneal process according to various aspects of the present disclosure
  • FIG. 3 is a capacitance-voltage graph for a capacitor with III-V semiconductor channel material after a super-atmospheric (high pressure), deuterium anneal and a sub- atmospheric, hydrogen anneal according to various aspects of the present disclosure
  • FIG. 4A is a capacitance-voltage graph for a capacitor with ⁇ -V semiconductor channel material both pre- and post- a high pressure, deuterium anneal according to various aspects of the present disclosure
  • FIG. 4B is a capacitance-voltage graph for a capacitor with ⁇ -V semiconductor channel material both pre- and post- a low pressure, deuterium anneal according to various aspects of the present disclosure
  • Described herein are integrated circuit devices, such as non-planar group ⁇ -V field effect transistors (FETs), having deuterium-passivated interfaces, surfaces, and/or films along with methods for passivation in integrated circuit devices.
  • FETs field effect transistors
  • a high pressure, deuterium anneal is disclosed for passivating interfaces (for example, III-V semiconductor channel/gate interfaces), surfaces, and/or films in non-planar group III-V FETs.
  • deuterium-passivated interfaces, surfaces, and/or films described herein are included in non-planar group ⁇ -V FETs, it should be appreciated that the embodiments described herein may be readily adapted to other capacitively-coupled device designs which employ a material layer (such as a dielectric layer) interfacing with a III-V semiconductor surface (for example, planar group III-V transistors (including metal-oxide-semiconductor FETs (MOSFETs)), MOS capacitors, etc.).
  • a material layer such as a dielectric layer
  • III-V semiconductor surface for example, planar group III-V transistors (including metal-oxide-semiconductor FETs (MOSFETs)), MOS capacitors, etc.
  • the present disclosure contemplates using the deuterium anneal disclosed herein for passivating interfaces (for example, group IV semiconductor channel/gate interfaces), surfaces, and/or films in non-planar group IV FETs and/or planar group IV FETs.
  • FIG. 1A illustrates a schematic view of an integrated circuit device 100 according to various aspects of the present disclosure
  • FIG. IB illustrates a schematic cross- sectional view of integrated circuit device 100 of FIG. 1A along line B-B according to various aspects of the present disclosure
  • integrated circuit device 100 includes a non-planar group III-V field effect transistor (FET) 102A and a non-planar group m-V FET 102B fabricated on a substrate 104.
  • FET field effect transistor
  • integrated circuit device 100 includes one or more planar ⁇ -V FETs.
  • substrate 104 includes various doped regions, including p-type doped regions (for example, areas doped with p-type dopants, such as boron) and/or n-type doped regions (for example, areas doped with n-type dopants, such as phosphorus).
  • Isolation regions 106 such as shallow trench isolations (STIs) or deep trench isolations (DTIs), formed over and/or in substrate 104 isolate electronic components of integrated circuit device 100, such as non-planar group ⁇ -V FET 102A and non-planar group III-V FET 102B.
  • Isolation regions 106 include any suitable isolation material, such as a dielectric material.
  • Non-planar group III-V FET 102A and non-planar group III-V FET 102B may be configured as double-gate transistors, tri-gate transistors, wrap-around gate transistors, or all- around gate transistors (such as nanowire and nanoribbon-based transistors).
  • non-planar group ⁇ -V FET 102A and non-planar group III-V FET 102B are fin- like FETs (FinFETs) that include a fin 1 10 protruding from substrate 104.
  • Fin 1 10 is configured as a heterostructure that includes a stack of material layers, such as a barrier layer 1 12, a channel layer 1 14, and a barrier layer 1 16.
  • barrier layer 1 12, channel layer 1 14, and/or barrier layer 116 are composed of binary compounds (for example, InP, InAs, InSb, GaAs, or other suitable binary compound), ternary compounds (for example, InAsSb, InGaAs, InAlAs, AlGaAs, or other suitable ternary compound), or quaternary compounds (for example, InGaAsSb, InAlAsSb, InAlGaAs, or other suitable quaternary compound).
  • binary compounds for example, InP, InAs, InSb, GaAs, or other suitable binary compound
  • ternary compounds for example, InAsSb, InGaAs, InAlAs, AlGaAs, or other suitable ternary compound
  • quaternary compounds for example, InGaAsSb, InAlAsSb, InAlGaAs, or other suitable quaternary compound.
  • barrier layer 1 12 is an InAlAs layer or an InAlSb layer
  • channel layer 114 is an InAs layer or an InSb layer
  • barrier layer 116 is an InGaAs layer.
  • Barrier layer 1 12, channel layer 114, and/or barrier layer 1 16 can include different materials or same materials with varying constituent ratios to achieve desired band gaps and/or lattice spacing.
  • barrier layer 1 12 and/or barrier layer 1 16 include a material having a band gap that is wider than a bandgap of a material of channel layer 114.
  • Non-planar group ⁇ -V FET 102A and non-planar group III-V FET 102B each include a source region 120, a drain region 122, and a channel region 124 disposed between source region 120 and drain region 122.
  • source region 120, drain region 122, and channel region 124 are portions of (and/or defined in) at least one material layer (such as group III, group V, and/or group ⁇ -V material layers) included in the heterostructure of fin 1 10.
  • source region 120 and drain region 122 include barrier layer 1 16, and channel region 124 is a portion of channel layer 1 14 disposed between source region 120 and drain region 122.
  • fin 110 may be etched to form recesses at desired locations for source/drain regions, and then an epitaxial deposition process may be performed to fill the recesses with a suitable material for source region 120 and drain region 122.
  • source region 120 and drain region 122 are formed by epitaxially growing a semiconductor material, such as a group III, a group V, or a group III-V material.
  • the epitaxially grown (deposited) semiconductor material may be doped in situ with any suitable dopants (such as boron, arsenic, or phosphorous).
  • source region 120 and drain region 122 can be formed from a silicon alloy, such as silicon germanium or silicon carbide.
  • one or more layers of metal and/or metal alloys may be used to form source/drain regions.
  • a gate stack 130 is disposed over channel region 124 of fin 1 10.
  • gate stack 130 wraps around channel layer 1 14 to define channel region 124 of fin 1 10.
  • Gate stack 130 includes at least two material layers, such as a gate dielectric layer 132 and a gate electrode layer 134.
  • Gate dielectric layer 132 is disposed on channel layer 1 14, and gate electrode layer 134 is disposed on gate dielectric layer 132.
  • Gate dielectric layer 132 includes a dielectric material, such as silicon oxide, silicon dioxide (S1O2), a high-k dielectric material, or a combination thereof.
  • Exemplary high-k dielectric materials include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, other high-k dielectric material, or a combination thereof.
  • gate dielectric layer 132 includes more than one gate dielectric layer, such as an interface layer (for example, a S1O2 layer) formed on channel layer 1 14 and a high-k dielectric layer formed on the interface layer.
  • gate electrode layer 134 includes an n- type work function metal, such as hafnium, zirconium, titanium, tantalum, aluminum, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, metal alloys thereof, other n-type work function metal, or a combination thereof.
  • the NMOS transistor includes a NMOS gate electrode having a work function between about 3.9 eV and about 4.2 eV.
  • gate electrode layer 134 includes at least two metal layers, for example, a work function metal layer and a metal fill layer. Gate electrode layer 134 can include other metal layers, such as barrier layers.
  • gate stack 130 includes additional layers, such as interface layers, barrier layers, gate silicide layers, and/or other suitable layers.
  • a gate silicide layer includes any metal capable of reacting with silicon (such as titanium, tantalum, tungsten, cobalt, nickel, platinum, palladium, other suitable metal, metal alloys thereof, or a combination thereof) to form a metal silicide, which can enhance electrical contact to gate stack 130.
  • gate spacers 136 are disposed on sidewalls of gate stack 130. Gate spacers 136 include any suitable material, such as silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, or a combination thereof.
  • gate spacers 136 include silicon nitride doped with carbon. Gate spacers 136 can include any number of gate spacer pairs, for example, two pairs, three pairs, or four pairs of sidewall spacers formed on opposing sides of gate stack 130.
  • Various deposition, patterning, and/or etching processes are performed to form isolation regions 106, fin 110 (including barrier layer 112, channel layer 1 14, and barrier layer 116), source region 120, drain region 122, channel region 124, gate stack 130 (including gate dielectric layer 132 and gate electrode layer 134), and gate spacers 136.
  • Deposition processes can include physical vapor deposition processes, chemical vapor deposition processes, atomic layer deposition processes, electrodeposition processes (such as electroplating and/or electroless plating), epitaxial processes, thermal oxidation processes, other suitable deposition processes, or a combination thereof.
  • Patterning processes include any process used to pattern a material layer.
  • Various patterning processes can include forming a photoresist (resist) layer and/or hard mask layer over substrate 104 (for example, by a spin coating process) and performing a lithography process to pattern the photoresist layer and or hard mask layer.
  • the lithography process can include optical photolithography, immersion photolithography, deep ultraviolet (UV) lithography, extreme UV lithography, other suitable lithography process, or a combination thereof.
  • Etching processes can include dry etching processes, wet etching processes, other suitable etching processes, or a combination thereof. Forming the various features of integrated circuit device 100 can further include performing annealing processes and/or any other suitable process.
  • Non-planar FETs based on III-V semiconductor materials are promising for improving performance of highly scaled transistor architectures.
  • III-V semiconductor channel regions (such as channel region 124) exhibit higher channel mobility and lower effective mass than conventional silicon channel regions, leading to higher carrier (injection) velocity for non- planar group III-V FETs.
  • non-planar group ⁇ -V FETs currently lack transistor architectures that can fully benefit from the high channel mobility and/or low effective mass in the ⁇ -V semiconductor channel regions.
  • high density of interface states existing at an III-V semiconductor channel/gate interface, such as an interface 138 between channel layer 1 14 (particularly, III-V semiconductor channel region 124) and overlying gate stack 130 (particularly, gate dielectric layer 132), can diminish gains in transistor performance achieved by higher channel mobility and/or lower effective mass.
  • surface states at or near a surface of channel layer 1 14 can trap electrons and or holes, causing a high density of interface states at or near interface 138.
  • surface states of gate dielectric layer 132 at or near interface 138 can also trap electrons and/or holes, contributing to the high density of interface states at or near interface 138.
  • a high pressure, deuterium anneal for passivating a non-planar group III-V FET's channel/gate interface (such as interface 138 of non-planar group III-V FET 102A and non-planar group ⁇ -V FET 102B).
  • the high pressure, deuterium anneal process described herein can provide a number of significant benefits that over conventional passivation processes, including current hydrogen annealing processes.
  • FIG. 2A illustrates a schematic cross-sectional view of integrated circuit device 100 of FIG. 1A along line B-B during a high pressure, deuterium anneal process according to various aspects of the present disclosure
  • FIG. 2B illustrates a schematic cross-sectional view of integrated circuit device 100 of FIG. 1A along line B-B after the high pressure, deuterium anneal process according to various aspects of the present disclosure
  • an interlayer dielectric (ILD) layer 140 is formed over integrated circuit device 100 (for example, over non-planar group III-V FET 102 A and non-planar group III-V FET 102B).
  • ILD layer 140 includes any suitable dielectric material, such as a low-k dielectric material.
  • Exemplary low-k dielectric materials include silicon dioxide, carbon doped oxide, silicon nitride, organic polymers (such as perfluorocyclobutane or polytetrafluoroethylene), fluorosilicate glass (FSG), organosilicates (such as silsesquioxane, siloxane, or organosilicate glass), other low-k dielectric material, or combinations thereof.
  • ILD layer 140 can include pores or air gaps to reduce its dielectric constant.
  • the conductive interconnect layer includes any suitable conductive material for forming interconnects in an interconnect structure, including copper, aluminum, tungsten, cobalt, ruthenium, nickel, iron, molybdenum, other suitable conductive material, metal alloys thereof, or a combination thereof.
  • integrated circuit device 100 (particularly, non-planar group ⁇ -V FET 102 A and/or non-planar group III-V FET 102B) is subjected to an annealing process 150, which is a high pressure, deuterium anneal.
  • annealing process 150 anneals integrated circuit device 100 at a pressure ranging from about 10 atmospheres to about 20 atmospheres.
  • deuterium can diffuse into gate dielectric layer 132 and/or isolation region 106 proximal to a surface of barrier layer 1 12 and/or channel layer 1 14. In yet other embodiments, deuterium can diffuse into other layers of integrated circuit 100 proximal to an interface that needs passivated.
  • annealing process 150 is performed for any suitable time. In some embodiments, annealing process 150 anneals integrated circuit device 100 for a time ranging from about 30 minutes to about two hours. In alternate embodiments, annealing process 150 anneals integrated circuit device 100 for a time less than 30 minutes or greater than two hours.
  • annealing process 150 is performed at a temperature less than about 450°C. In some embodiments, annealing process 150 anneals integrated circuit device 100 at a temperature of about 350°C. Annealing process 150 can implement different pressures, times, and temperatures in various embodiments to enhance diffusion of deuterium into fin 1 10 and passivate interface 138 (the ⁇ -V semiconductor channel/gate interface), other interface, and/or any defects present in dielectric layers of in integrated circuit device 100.
  • deuterium (D) penetrates integrated circuit device 100, diffusing into fin 1 10 and passivating ⁇ -V semiconductor interfaces, such as the III-V semiconductor channel/gate dielectric interface (channel region 124), along with any defects present in dielectric layers (such as gate dielectric layer 132) of non-planar group III-V FET 102A and non-planar group ⁇ -V FET 102B.
  • High pressure implemented by annealing process 150 allows more deuterium species to diffuse into fin 1 10, other interface, and/or any defects present in dielectric layers of (such as gate dielectric layer 132) at lower temperatures required for annealing III-V semiconductor materials.
  • deuterium passivates surface states (electrons and/or holes) at or near the surface of channel layer 1 14 and/or barrier layer 1 12. For example, in some embodiments, deuterium attaches to dangling ⁇ -V semiconductor bonds at or near the surface of channel layer 1 14 and/or barrier layer 1 12. In some embodiments, deuterium passivates surface states (electrons and/or holes) at or near a surface of gate dielectric layer 132 that is proximal interface 138. For example, in some embodiments, deuterium attaches to dangling silicon bonds at or near the surface of gate dielectric layer 132 that is proximal interface 138. Turning to FIG.
  • deuterium passivates source-drain junctions, such as an interface between channel layer 1 14 and source region 120 and/or drain region 122. Passivating isolation interfaces and/or source-drain junctions can minimize off-state leakage exhibited by non-planar group III-V FET 102A and/or non-planar group III-V FET 102B, for example, by saturating dangling III- V semiconductor bonds and or dangling silicon bonds at these interfaces.
  • annealing process 150 is performed near an end of fabricating integrated circuit device 100, for example, after forming the interconnect structure. In various embodiments, no other thermal processes are performed on integrated circuit device 100 after annealing process 150.
  • Deuterium-passivated III-V semiconductor surfaces exhibit less surface states than conventional hydrogen-passivated III-V semiconductor surfaces, allowing non-planar group III-V FET 102A and/or non-planar group ⁇ -V FET 102B to benefit from higher channel mobility and/or lower effective mass provided by their ⁇ -V semiconductor channel regions (such as III-V semiconductor channel region 124).
  • FIG. 1 Deuterium-passivated III-V semiconductor surfaces, such as deuterium-passivated surface 160, exhibit less surface states than conventional hydrogen-passivated III-V semiconductor surfaces, allowing non-planar group III-V FET 102A and/or non-planar group ⁇ -V FET 102B to benefit from higher channel mobility and/or lower effective mass provided by their ⁇ -V semiconductor channel regions (such as III-V semiconductor channel region 124).
  • the super-atmospheric pressure, deuterium anneal involved annealing the III-V semiconductor channel material in 100% deuterium ambient greater than or equal to about 10 atmospheres
  • the sub-atmospheric pressure, hydrogen anneal involved annealing the ⁇ -V semiconductor channel material in 100% hydrogen ambient less than or equal to about one atmosphere.
  • post-hydrogen anneal C-V curves 190 reveal that sub-atmospheric, hydrogen anneal process minimally reduces frequency dispersion, which corresponds with hydrogen failing to adequately passivate surface states at the surface of the III-V semiconductor channel material. Accordingly, super-atmospheric, deuterium anneal can significantly improve passivation of interfaces (such as ⁇ -V channel/gate interfaces), surfaces (such as III-V semiconductor channel layer surfaces), and/or any defects in dielectric materials (such as gate dielectric layers) in non-planar group III-V FETs, leading to non- planar group III-V FETs exhibiting improved performance and reliability.
  • interfaces such as ⁇ -V channel/gate interfaces
  • surfaces such as III-V semiconductor channel layer surfaces
  • any defects in dielectric materials such as gate dielectric layers
  • High pressure, deuterium-passivated ⁇ -V semiconductor surfaces exhibit less surface states than low pressure, deuterium- passivated III-V semiconductor surfaces, allowing non-planar group ⁇ -V FET 102A and/or non-planar group III-V FET 102B to benefit from the higher channel mobility and/or lower effective mass provided by their III-V semiconductor channel regions (such as III-V semiconductor channel region 124).
  • III-V semiconductor channel regions such as III-V semiconductor channel region 124
  • C-V capacitance-voltage graph 200 that illustrates capacitance per unit area (C/A) (in F/cm 2 ) as a function of a gate voltage (in V) for a capacitor with ⁇ -V semiconductor channel material both pre- and post- a high pressure, deuterium anneal (such as anneal process 150) according to various aspects of the present disclosure.
  • the III-V semiconductor channel material was annealed in 100% deuterium ambient greater than or equal to about 10 atmospheres.
  • C-V graph 220 includes a pre-anneal C-V curve 222A and a corresponding post-anneal C-V curve 222B, a pre-anneal C-V curve 224A and a corresponding post-anneal C-V curve 224B, a pre-anneal C-V curve 226A and a corresponding post-anneal C-V curve 226B, a pre-anneal C-V curve 228A and a corresponding post-anneal C-V curve 228B, and a pre-anneal C-V curve 23 OA and a corresponding post-anneal C-V curve 230B.
  • a high pressure, deuterium anneal can significantly improve passivation of interfaces (such as III-V channel/gate interfaces), surfaces (such as III-V semiconductor channel layer surfaces), and or any defects in dielectric materials (such as gate dielectric layers) in non-planar group ⁇ -V FETs, leading to non- planar group III-V FETs exhibiting improved performance and reliability.
  • interfaces such as III-V channel/gate interfaces
  • surfaces such as III-V semiconductor channel layer surfaces
  • dielectric materials such as gate dielectric layers
  • FIG. 5 illustrates a flow chart of an exemplary method 300 for passivating interfaces of an integrated circuit device, such as integrated circuit device 100, according to various aspects of the present disclosure.
  • Method 300 begins at block 310, where a non- planar FET (such as non-planar group III-V FET 102 A) is formed that includes a III-V semiconductor channel region (such as channel region 124) and a gate stack (such as gate stack 130) disposed over the III-V semiconductor channel region.
  • a non- planar FET such as non-planar group III-V FET 102 A
  • III-V semiconductor channel region such as channel region 12
  • gate stack such as gate stack 130
  • an interface between the III-V semiconductor channel region and the gate stack (such as interface 138) is passivated by annealing the non-planar FET in a deuterium-containing ambient at a pressure greater than one atmosphere (such as by subjecting non-planar group III-V FET 102 A to annealing process 150). Subsequent processing may be performed to complete fabrication of the integrated circuit device 100.
  • the various embodiments described herein are with respect to benefits for non-planar FETs, such benefits may also be achieved for planar devices, such as planar transistors (for example, MOSFETs). Furthermore, embodiments described herein may be effective for source-drain junction isolation.
  • FIG. 6 illustrates a schematic cross-sectional view of an exemplary interposer 400 according to various aspects of the present disclosure.
  • Interposer 400 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, a polymer material (such as polyimide), or any other suitable material.
  • interposer 400 is formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, group ⁇ -V materials, group rv materials, or combinations thereof.
  • Interposer 400 is an intervening substrate used to bridge a first substrate 402 to a second substrate 404.
  • first substrate 402 is an integrated circuit die (for example, an integrated circuit die that includes integrated circuit device 100 described above, which includes non-planar group III-V FET 102A and/or non-planar group ⁇ -V FET 102B having passivated III-V semiconductor channel/gate interfaces and/or passivated dielectric layers), and second substrate 404 is another integrated circuit die, a memory module, or a computer motherboard.
  • interposer 400 serves as an electrical interface routing between first substrate 402 and second substrate 404. For example, interposer 400 can spread a connection to a wider pitch or reroute a connection to a different connection.
  • interposer 400 couples first substrate 402 (for example, an integrated circuit die) to a ball grid array (BGA) 406, which is coupled to second substrate 404.
  • first substrate 402 and second substrate 404 are attached to opposing sides of interposer 400.
  • first substrate 402 and second substrate 404 are attached to the same side of interposer 400.
  • three or more substrates may be interconnected by way of interposer 400.
  • Interposer 400 can include an interconnect structure 408 that includes metal interconnects, including but not limited to, trenches 410, vias 412, and through-silicon vias (TSVs) 414.
  • TSVs through-silicon vias
  • Interposer 400 can also include embedded devices 416, including both passive devices and active devices.
  • Exemplary embedded devices include capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, other suitable embedded devices, or combinations thereof.
  • ESD electrostatic discharge
  • RF devices, power amplifiers, power management devices, antennas, arrays, sensors, microelectromechanical systems (MEMS) devices, other devices, or combinations thereof can be formed on and/or attached to interposer 400.
  • MEMS microelectromechanical systems
  • computing device 500 includes an integrated circuit die 502 (which can include a processor 504 and a memory 506 (such as an on-chip memory)) and a communications chip 508.
  • integrated circuit die 502 physically and electrically couples to a motherboard.
  • communications chip 508 also physically and electrically couples to the motherboard.
  • communications chip 508 is part of integrated circuit die 502 and/or processor 504.
  • the term "processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • Memory 506, often used as cache memory can be provided by any suitable memory technology, such as embedded DRAM (eDRAM) or spin- transfer torque memory (STTM).
  • eDRAM embedded DRAM
  • STTM spin- transfer torque memory
  • Communications chip 508 (also referred to as a communications logic unit) enables wireless communications for data transfer to and from computing device 500.
  • the term "wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • computing device 500 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a tablet, a personal digital assistant (PDA), an ultra- mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.
  • computing device 500 may be any other electronic device that processes data.
  • an exemplary non-planar field effect transistor includes a source region, a drain region, and a III-V semiconductor channel region disposed between the source region and the drain region.
  • the non-planar FET further includes a gate stack disposed over the III-V semiconductor channel region, where the ⁇ -V semiconductor channel region includes deuterium proximal an interface between the gate stack and the III-V semiconductor channel region.
  • the gate stack includes a gate dielectric layer disposed on the ⁇ -V semiconductor channel region, and a gate electrode layer disposed on the gate dielectric layer.
  • the gate dielectric layer is a high-k dielectric layer.
  • the III-V channel region includes GaAs, InAs, InP, InSb, InGaAs, InAlAs, InAsSb, AlGaAs, InAlAsSb, In GaAsSb, InAlGaAs, InAlAsP, or InGaAsP.
  • the source region, the drain region, and the III-V semiconductor channel region are portions of a heterostructure disposed over a substrate.
  • the heterostructure includes a first barrier layer disposed over the substrate, a III-V channel layer disposed over the first barrier layer, wherein the gate stack is disposed over the ⁇ -V channel layer, and a second barrier layer disposed over the III-V channel layer.
  • the III-V channel layer includes deuterium proximal an interface between the gate stack and the ⁇ -V channel layer.
  • the first barrier layer includes deuterium proximal an interface between an isolation region and the first barrier layer.
  • the first barrier layer and the second barrier layer include a group III material, a group V material, or a group III-V material.
  • the III-V channel layer includes GaAs, InAs, InP, InSb, InGaAs, InAlAs, InAsSb, AlGaAs, InAlAsSb, In GaAsSb, InAlGaAs, InAlAsP, or InGaAsP.
  • an exemplary the gate dielectric layer is a high-k dielectric layer.
  • the fin further includes a first barrier layer disposed between the substrate and the ⁇ -V channel layer, and a second barrier layer disposed over the III-V channel layer.
  • the first barrier layer includes a first barrier layer surface, wherein deuterium is proximal the first barrier layer surface.
  • the deuterium is in the first barrier layer and/or other material layer adjacent the first barrier layer (such as in an isolation feature formed adjacent the first barrier layer).
  • the first barrier layer and the second barrier layer include a group III material, a group V material, or a group ⁇ -V material.
  • forming the gate stack includes forming a gate dielectric layer on the III-V channel layer, and forming a gate electrode layer on the gate dielectric layer.
  • forming the fin includes forming a first barrier layer between the substrate and the III-V channel layer and a second barrier layer over the ⁇ -V channel layer.
  • annealing the non-planar FET further includes diffusing deuterium proximal to a surface of the first barrier layer.
  • the deuterium is diffused into the first barrier layer, the ⁇ -V channel layer, and/or other material layer adjacent the first barrier layer (such as in an isolation feature) proximal to the surface of first barrier layer.
  • an exemplary transistor includes a ⁇ -V semiconductor channel layer disposed over a substrate, wherein deuterium is proximal to an interface associated with the III-V semiconductor channel layer, and a gate stack disposed over the III- V semiconductor channel layer.
  • the interface is between the gate stack and the III-V semiconductor channel layer.
  • the III-V semiconductor channel layer includes the deuterium proximal to the interface.
  • the gate stack includes a gate dielectric layer disposed on the III-V semiconductor channel layer, wherein the gate dielectric layer includes the deuterium proximal to the interface, and a gate electrode layer disposed on the gate dielectric layer.
  • the gate dielectric layer is a high-k gate dielectric layer.
  • a first barrier layer disposed between the substrate and the III-V semiconductor channel layer, and a second barrier layer disposed over the III-V semiconductor channel layer.
  • the first barrier layer includes deuterium proximal an interface between an isolation region and the first barrier layer.
  • the interface is between the III-V semiconductor channel layer and the second barrier layer, and the III-V semiconductor channel layer includes the deuterium proximal to the interface.
  • the ⁇ -V channel layer includes GaAs, InAs, InP, InSb, InGaAs, InAlAs, InAsSb, AlGaAs, InAlAsSb, In GaAsSb, InAlGaAs, InAlAsP, or InGaAsP.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

L'invention concerne un recuit sous deutérium à pression élevée, destiné à passiver des interfaces dans des transistors à effet de champ des groupes III-V non planar. Un exemple de transistor à effet de champ (TEC) non planar comprend une zone de source, une zone de drain, et une zone de canal semi-conducteur III-V disposée entre la zone de source et la zone de drain. Le TEC non planar comprend en outre un empilement de grille disposé au-dessus de la zone de canal semi-conducteur III-V, la zone de canal semi-conducteur III-V comprenant du deutérium à proximité d'une interface entre l'empilement de grille et la zone de canal semi-conducteur III-V.
PCT/US2015/000384 2015-12-26 2015-12-26 Recuit sous deutérium pour transistor à effet de champ iii-v non planar WO2017111826A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/US2015/000384 WO2017111826A1 (fr) 2015-12-26 2015-12-26 Recuit sous deutérium pour transistor à effet de champ iii-v non planar

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2015/000384 WO2017111826A1 (fr) 2015-12-26 2015-12-26 Recuit sous deutérium pour transistor à effet de champ iii-v non planar

Publications (1)

Publication Number Publication Date
WO2017111826A1 true WO2017111826A1 (fr) 2017-06-29

Family

ID=59089669

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2015/000384 WO2017111826A1 (fr) 2015-12-26 2015-12-26 Recuit sous deutérium pour transistor à effet de champ iii-v non planar

Country Status (1)

Country Link
WO (1) WO2017111826A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10374154B1 (en) 2018-01-18 2019-08-06 Globalfoundries Inc. Methods of shielding an embedded MRAM array on an integrated circuit product comprising CMOS based transistors
US10439129B2 (en) 2018-01-18 2019-10-08 Globalfoundries Inc. Shielded MRAM cell

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030219950A1 (en) * 1996-01-16 2003-11-27 Lyding Joseph W. Deuterium treatment of semiconductor device
US20090104741A1 (en) * 2007-10-18 2009-04-23 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor devices using a plasma process with non-silane gas including deuterium
US20120273894A1 (en) * 2011-04-27 2012-11-01 International Business Machines Corporation High pressure deuterium treatment for semiconductor/high-k insulator interface
CN103515213A (zh) * 2012-06-25 2014-01-15 中芯国际集成电路制造(上海)有限公司 形成FinFET栅介质层的方法和形成FinFET的方法
WO2015026371A1 (fr) * 2013-08-23 2015-02-26 Intel Corporation Couche à haute résistance pour canal iii-v déposé sur des substrats du groupe iv pour transistors mos

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030219950A1 (en) * 1996-01-16 2003-11-27 Lyding Joseph W. Deuterium treatment of semiconductor device
US20090104741A1 (en) * 2007-10-18 2009-04-23 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor devices using a plasma process with non-silane gas including deuterium
US20120273894A1 (en) * 2011-04-27 2012-11-01 International Business Machines Corporation High pressure deuterium treatment for semiconductor/high-k insulator interface
CN103515213A (zh) * 2012-06-25 2014-01-15 中芯国际集成电路制造(上海)有限公司 形成FinFET栅介质层的方法和形成FinFET的方法
WO2015026371A1 (fr) * 2013-08-23 2015-02-26 Intel Corporation Couche à haute résistance pour canal iii-v déposé sur des substrats du groupe iv pour transistors mos

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10374154B1 (en) 2018-01-18 2019-08-06 Globalfoundries Inc. Methods of shielding an embedded MRAM array on an integrated circuit product comprising CMOS based transistors
US10439129B2 (en) 2018-01-18 2019-10-08 Globalfoundries Inc. Shielded MRAM cell

Similar Documents

Publication Publication Date Title
US10580882B2 (en) Low band gap semiconductor devices having reduced gate induced drain leakage (GIDL)
US10497785B2 (en) Gallium nitride voltage regulator
US20220336634A1 (en) Source electrode and drain electrode protection for nanowire transistors
US20180013000A1 (en) Apparatus and methods of forming fin structures with asymmetric profile
US11695081B2 (en) Channel layer formation for III-V metal-oxide-semiconductor field effect transistors (MOSFETs)
US11264453B2 (en) Methods of doping fin structures of non-planar transistor devices
WO2017111826A1 (fr) Recuit sous deutérium pour transistor à effet de champ iii-v non planar
EP4109523A1 (fr) Rail d'alimentation enterré avec une couche de siliciure pour la polarisation des puits
US20200194577A1 (en) Gan based hemt device relaxed buffer structure on silicon
US10529808B2 (en) Dopant diffusion barrier for source/drain to curb dopant atom diffusion
US10636907B2 (en) Deep EPI enabled by backside reveal for stress enhancement and contact
US11342232B2 (en) Fabrication of Schottky barrier diode using lateral epitaxial overgrowth
US11508824B2 (en) Gallium nitride transistors with multiple threshold voltages and their methods of fabrication
US11335796B2 (en) Source to channel junction for III-V metal-oxide-semiconductor field effect transistors (MOSFETs)
US20200203484A1 (en) Superlattice finfet with tunable drive current capability
US10665688B2 (en) Low Schottky barrier contact structure for Ge NMOS
US20240113116A1 (en) Epitaxial structure and gate metal structures with a planar top surface
US20240113109A1 (en) Plug between two gates of a semiconductor device
US20230111323A1 (en) Oxide layer doping on a sub channel of a transistor structure
US20220415796A1 (en) Power rail between fins of a transistor structure
US20230097898A1 (en) Transistor structure with a monolayer edge contact
US20240224504A1 (en) Dynamic random-access memory using wide band gap materials
US20240222438A1 (en) Transistor including wide band gap materials
US20240222440A1 (en) Transistor with a body and back gate structure in different material layers
US20230197867A1 (en) Planar germanium photodetector

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15911525

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15911525

Country of ref document: EP

Kind code of ref document: A1