WO2017111815A1

WO2017111815A1 - Transmitter with improved substrate thicknesses and interfaces

Info

Publication number: WO2017111815A1
Application number: PCT/US2015/000372
Authority: WO
Inventors: Benjamin Vincent; Avi Feshali
Original assignee: Intel Corporation
Priority date: 2015-12-26
Filing date: 2015-12-26
Publication date: 2017-06-29

Abstract

An embodiment includes a transmitter comprising: an oxide layer between a substrate and an epitaxial silicon layer; a modulator included within the silicon layer and a hybrid laser on the silicon layer; wherein (a) the silicon layer is thinner directly adjacent the modulator than directly adjacent the laser; and (b) the silicon layer comprises gratings directly under the laser and directly contacting the oxide layer. Other embodiments are described herein.

Description

TRANSMITTER WITH IMPROVED

SUBSTRATE THICKNESSES AND INTERFACES

Technical Field

[0001] Embodiments of the invention are in the field of waveguides. Background

[0002] An optical waveguide is a structure that conveys an optical light signal from an optic source (e.g., laser diode). Conventionally, an optical waveguide may include a substrate and a core encased within an upper and lower cladding. The bulk of the light signal typically travels within the core along the axis of the waveguide structure. Optical waveguides may be used in optical modulators, such as phase modulators, absorption modulators, and Mach-Zehnder Modulators (MZM). An optical modulator may be optically coupled to an external optical device, such as an optical fiber or photodetector. An optical modulator is a device which is used to modulate a beam of light. Depending on the parameter of a light beam which is manipulated, modulators may be categorized into amplitude modulators, phase modulators, polarization modulators, and the like.

Brief Description of the Drawings

[0003] Features and advantages of embodiments of the present invention will become apparent from the appended claims, the following detailed description of one or more example embodiments, and the corresponding figures. Where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements.

Figure 1 includes a process in an embodiment.

Figures 2A-2F depict a transmitter portion after various stages of its manufacture.

Figure 3 includes an embodiment comprising a waveguide, modulator, and laser.

Figures 4 and 5 include systems that may include an embodiment. Detailed Description

[0004] Reference will now be made to the drawings wherein like structures may be provided with like suffix reference designations. In order to show the structures of various embodiments more clearly, the drawings included herein are diagrammatic representations of semiconductor/circuit structures. Thus, the actual appearance of the fabricated integrated circuit structures, for example in a photomicrograph, may appear different while still incorporating the claimed structures of the illustrated embodiments. Moreover, the drawings may only show the structures useful to understand the illustrated embodiments. Additional structures known in the art may not have been included to maintain the clarity of the drawings. For example, not every layer of a semiconductor device is necessarily shown. "An embodiment", "various embodiments" and the like indicate embodiment(s) so described may include particular features, structures, or characteristics, but not every embodiment necessarily includes the particular features, structures, or characteristics. Some embodiments may have some, all, or none of the features described for other embodiments. "First", "second", "third" and the like describe a common object arid indicate different instances of like objects are being referred to. Such adjectives do not imply objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner. "Connected" may indicate elements are in direct physical or electrical contact with each other and "coupled" may indicate elements co-operate or interact with each other, but they may or may not be in direct physical or electrical contact.

[0005] Embodiments include a transmitter system (which may be a component of a transceiver) having various components, including a waveguide, laser, and modulator. The laser component of the transmitter may be a "hybrid" laser that is formed, for example, by bonding a lll-V material Multi Quantum Well (MQW) stack on top of a silicon on insulator (SOI) RIB waveguide. The gain region of the laser is in the lll-V MQW, whereas the resonant cavity of the laser is obtained by gratings etched into the silicon RIB waveguide. The laser may be a Distributed Feedback (DFB) laser. Such a laser enables good control of single mode lasing. [0006] Embodiments include a transmitter system (which may be a component of a transceiver) having various components, including a waveguide, laser, and modulator. The laser component of the transmitter may be a hybrid laser that is formed, for example, by bonding a lll-V QW or Single QW stack on top of a SOI RIB waveguide. The bonding may be performed by a method of molecular bonding or adhesive bonding using DVS-BCB material. The gain region of the laser is in the QW, whereas the resonant cavity of the laser is obtained by gratings etched into the silicon RIB waveguide. The laser may be a DFB laser. Such a laser enables good control of single mode lasing.

[0007] In an embodiment the gratings are located below the lll-V gain area and etched on or into the silicon waveguide. In an embodiment, this grating of the waveguide is done prior to bonding the lll-V die onto the silicon. Conventionally, these gratings are located at the silicon/lll-V interface. However, Applicant determined the presence of these gratings at this particular interface reduces the contact area between the lll-V MWQ and the silicon surface. Applicant further determined this reduction in contact area also reduces coupling efficiency (albeit at the benefit of Kappa optimization). Thus, Applicant determined the laser's Kappa and coupling efficiency cannot be optimized independently because of the grating's presence at the silicon/lll-V interface. However, embodiments described further below resolve this issue by repositioning the gratings in relation to the gain portion of the laser.

[0008] An embodiment has increased reliability because the gratings are on the Si- buried oxide (BOX) interface and not at a lll-V SOI epi interface (the location of the highest intensity within the laser cavity). In an embodiment, the wavelength selecting element and the gain of the device are decoupled. A user may maximize the confinement factor, which is correlated to the mode overlapping the gain section, but not cause reliability failures such as catastrophically optical damage (COD). This is possible with embodiments described herein.

[0009] Before addressing repositioning the gratings, attention is now turned to another problem Applicant has identified. Specifically, another key component of a transmitter chip is a Mach-Zehnder interferometer (MZI) base MZM (which is located in the silicon slab). The modulator and the hybrid laser are built on the same silicon slab waveguide. In an embodiment, the SOI part of the laser and the modulator (included in the SOI) are processed simultaneously. However, Applicant determined the optimal top SOI thickness is not necessarily the same for the laser and the modulator. For example, an embodiment includes a top SOI thickness of 0.4 um for the laser (which produces desirable mode evanescence from the lll-V area to the SOI waveguide). Yet, a thinner top SOI (less than 0.4 um) is desired as it may yield a faster silicon based modulator. Applicant identified these conflicting goals (thicker silicon slab at the silicon portion the laser vs. thinner silicon slab where the

modulator is formed) and how conventional systems cannot optimize both the modulator and the laser as a result because they share a common SOI substrate. However, embodiments described further below resolve this issue by providing a slab that is thicker near the laser and thinner near the modulator.

[0010] An embodiment provides an engineered SOI substrate having various thicknesses. The thicknesses may be measured from (a) a bottom of the silicon (which includes the modulator and the laser or at least a portion of the laser) to the top of the silicon, or (b) from a bottom of the oxide of the SOI (e.g., BOX) to the top of the silicon (which includes the modulator and the laser or at least a portion of the laser). Such an engineered substrate allows for the independent optimization of the different parameters and components of the transmitter chip. The various

thicknesses include different thicknesses for the silicon modulator and the laser (e.g., hybrid laser) areas. Another embodiment includes grating at the silicon/BOX interface instead of conventionally locating the grating at the lll-V/silicon bonding interface. Another embodiment includes both varying substrate thickness and gratings at the silicon/BOX interface.

[001 1] Such embodiments allow for a DFB design with silicon grating relatively far away from the lll-V/silicon bonding interface. This allows more freedom for a hybrid laser device such as, for example, having grating design not limited by minimum III- V/Si bonding. Further, by tapering the silicon as described herein an advantage is gained over previous attempts to provide varying silicon thicknesses. For example, a transition from thicker silicon to laser to thinner silicon for the modulator may also be achieved by tapering the top of the SOI layer. However, Applicant determined this architecture leads to a non-planar top surface, which requires different implants/etch processes for the laser and modulator areas (e.g., standard processes, such as implant or etch, prefer to be handled on a flat surface). However, embodiments described herein provide a SOI with a planar top surface which allows for the laser and modulator to be processed simultaneously with the same process conditions (thereby saving costs and adding manufacturing efficiency).

[0012] As described more fully with regard to Figures 2A-2H, an embodiment may employ ion implantation followed by controlled exfoliation to determine the thickness of the uppermost silicon layer. An embodiment includes pre-processing the silicon donor wafer to: (a) introduce gratings at the silicon/BOX interface, and (b) taper the BOX/silicon thickness. A SiGe layer interlayer (or any other material that can be further used as a Si etch stop layer) is introduced due to the topography present on the wafer prior to H implant since H implantation depth depends on the material thickness/density the H goes through. With the difference in Si EPI/BOX thicknesses across the wafers the H implantation depth might not be uniform. A hydrogen implant is then provided and will be deeper (lower) than the location of the SiGe layer. The SiGe layer is removed after the silicon wafer is split and allows for a smooth top silicon surface, to which the MQW may be bonded.

[0013] Figure 1 includes a process in an embodiment. Figures 2A-2F depict a transmitter portion after various stages of its manufacture. These figures are now discussed.

[0014] Block 105 includes forming an interlayer (e.g., SiGe) 2 on a substrate 1 (bulk silicon slab) and an epitaxial monocrystalline silicon layer 3 on the interlayer. (Figure 2A) Block 1 10 includes forming gratings 7 in the silicon layer 3 and tapering (e.g., by grayscale etching) the silicon layer (so the silicon layer is relatively thinner directly adjacent to where the modulator will eventually be located and relatively thicker directly adjacent where the laser will eventually be located). (Figure 2B) In various embodiments, the gratings 7 may be formed before, after, or simultaneously with the taper 9. [0015] Block 115 includes forming a first oxide layer 4 on the gratings 7. (Figure 2C) Block 120 includes implanting hydrogen 19 below the interlayer 2 and within the substrate 1 (thereby forming substrate portions 1 ' and 1"). (Figure 2D) Block 125 includes coupling the first oxide layer 4 to a second oxide layer 5 (that couples to an additional silicon layer 6). (Figures 2E and 2F). Bock 130 includes separating a first portion 1 ' of the substrate from a second portion 1" of the substrate where the hydrogen 19 was implanted and allowing the second portion 1 " to remain. (Figure 2G). Block 135 includes removing the second portion 1" (etching) and then the interlayer 2. Due to removing the first portion V, no grinding process is needed (which may waste an entire Si substrate). Block 140 includes forming a modulator 8 within the silicon layer 3 and Block 145 includes forming a laser portion 18 (e.g., Ill-V gain portion of the laser) on the silicon layer (which includes another portion of the laser).

[0016] Thus, the embodiment of Figure 2H includes an apparatus (e.g., transmitter) comprising: a substrate 6 and an oxide layer. In an embodiment the oxide layer is a composite of layers 4, 5. The silicon layer 3 is epitaxially grown (and primarily having a monocrystalline structure having been grown on SiGe interlayer 2). In another embodiment layer 3 can come from a thin SOI wafer if, for example, SiOx is used in place of SiGe 2. Layer 3 forms a waveguide coupling laser 18 to modulator 8 (and includes the bottom surface 16 of the silicon layer 3 that slopes 9). Modulator 8 is included within the silicon layer 3. Hybrid laser 18 is on the silicon layer 3 (and portions thereof may be considered to be within layer 3). A first vertical axis 10 intersects the modulator 8, the silicon layer 3, the oxide layer (4, 5), and the substrate 6. A second vertical axis 1 1 intersects the laser 18, the silicon layer 3, the oxide layer (4, 5), and the substrate 6. The silicon layer has a first height 20, collinear with the first vertical axis 10 and extending from a bottom surface 16 of the silicon layer to a top surface 15 of the silicon layer. The silicon layer has a second height 21 , collinear with the second vertical axis 11 and extending from the bottom surface 16 of the silicon layer to the top surface 15 of the silicon layer. The second height is greater than the first height. [0017] The silicon layer 3 comprises gratings 7, one of which intersects the second vertical axis 1 1. The gratings 7 directly contact the oxide layer (4, 5). The gratings 7 do not directly contact the lll-V gain region 18 of the laser.

[0018] In an embodiment laser 18 is a DFB laser (which includes a lll-V MQW); the modulator 8 is a MZI modulator; the substrate 6, oxide layer (4, 5), and silicon layer 3 collectively form a Sol substrate; and the gratings 7 include a series of trenches, which are parallel to each other, formed in the bottom surface of the silicon layer 3.

[0019] In an embodiment the bottom surface 16 of the silicon layer slopes 9 non- orthogonally from a first level 14 where the first vertical axis 10 intersects the bottom surface 16 of the silicon layer 3 to a second level 13 where the second vertical axis 11 intersects the bottom surface 16 of the silicon layer 3. The bottom surface 16 of the silicon layer that slopes 9 is located between the first and second vertical axes 10, 11. The substrate 6, the oxide layer (4, 5), and the silicon layer 3 each include a monolithic portion that intersects both the first and second axes 10, 11. For example, the portion 4 of the oxide layer is monolithic between the first and second axes 10, 11.

[0020] In an embodiment, a horizontal axis 12 intersects the silicon layer 3, the oxide layer (portion 4), the gratings 7, and the second vertical axis 11.

[0021] In an embodiment the top surface 15 of the silicon layer 3 includes a monolithic portion that is horizontally planar (e.g., parallel to axis 12) and contacts the first and second vertical axes 10, 11.

[0022] In an embodiment the laser 18 directly contacts the silicon layer 3. In an embodiment the silicon layer 3 directly contacts the oxide layer (portion 4) and the oxide layer (portion 5) directly contacts the substrate 6.

[0023] Substrate 6 may be a bulk semiconductive material this is part of a wafer. In an embodiment, the semiconductive substrate is a bulk semiconductive material as part of a chip that has been singulated from a wafer. In an embodiment, the SOI structure includes semiconductive material 3 that is formed above an insulator (4, 5) such as a SOI substrate. [0024] Figure 3 includes multiple rib waveguides formed in silicon portions 3, 3', 3", 3"', which are above buried oxide 17 (which may or may not include multiple layers, such as layers 4, 5), and substrate 6. Area 18' is where a laser will be formed and area 8' is where a modulator will be formed. Portions 3, 3"' may be monolithic with each other (formed by etching).

[0025] Various embodiments have described rib waveguides. A rib waveguide (such as the waveguide of Figure 3) has a structure similar to that of a strip or ridge waveguide, but the strip has the same index as the high index planar layer beneath it and is part of the waveguiding core. However, other embodiments are not so limited and may include nonplanar channel waveguides, which include buried channel waveguides, strip-loaded waveguides, ridge waveguides, and diffused waveguides. In a nonplanar waveguide of two-dimensional transverse optical confinement, the core is surrounded by cladding in all transverse directions, and n(x, y) is a function of both x and y coordinates.

[0026] A buried channel waveguide is formed with a high-index waveguiding core buried in a low-index surrounding medium. The waveguiding core can have any cross-sectional geometry though it is often a rectangular shape. In an embodiment the waveguiding core may still be tapered and/or include gratings on the bottom surface of the core.

[0027] A strip-loaded waveguide is formed by loading a planar waveguide, which already provides optical confinement in the x direction, with a dielectric strip of index n3<ni or a metal strip to facilitate optical confinement in the y direction. The waveguiding core of a strip waveguide is the n1 region under the loading strip, with its thickness d determined by the thickness of the n1 layer and its width w defined by the width of the loading strip. In an embodiment the waveguiding core (n1 layer) may still be tapered and/or include gratings on the bottom surface of the core.

[0028] A ridge waveguide has a structure that looks like a strip waveguide, but the strip, or the ridge, on top of its planar structure has a high index and is actually the waveguiding core. A ridge waveguide has strong optical confinement because it is surrounded on three sides by low-index air (or cladding material). In an embodiment the waveguiding core may still be tapered and/or include gratings on the bottom surface of the core.

[0029] These four types of waveguides (buried channel, strip-loaded, ridge, and rib) are usually termed rectangular waveguides with a thickness d in the x direction and a width w in the y direction, though their shapes are normally not exactly rectangular.

[0030] A diffused waveguide is formed by creating a high-index region in a substrate through diffusion of dopants, such as LiNb03 waveguide with a core formed by Ti diffusion. Because of the diffusion process, the core boundaries in the substrate are not sharply defined. A diffused waveguide also has a thickness d defined by the diffusion depth of the dopant in the x direction and a width w defined by the distribution of the dopant in the y direction. In an embodiment the waveguiding core (the diffused high index region) may still be tapered and/or include gratings on the bottom surface of the core.

[0031] In some embodiments, SiGe interlayer 2 may instead include oxide. Also, EPI layer 3 does not necessarily have be silicon and my instead include other materials such as SiGe and the like.

[0032] While various embodiments described herein have concerned transmitters, other embodiments are not so limited and may include the optical waveguides that are the basic elements for confinement and transmission of light over various distances, ranging from tens or hundreds of pm in integrated photonics. Such optical waveguides form key structures in semiconductor lasers, and act as passive and active devices such as waveguide couplers and modulators. Thus, some

embodiments may include only portions or elements of other embodiments such as the embodiment of Figure 2H. For example, some embodiments only include waveguides having varying thicknesses, and some include laser systems with gratings located along BOX/silicon interface. Such laser systems or waveguides do not necessarily have to be in transmitters and can instead be stand-alone

components.

[0033] Referring now to Figure 4, shown is a block diagram of an example system with which embodiments can be used. As seen, system 900 may be a smartphone or other wireless communicator or any other loT device. A baseband processor 905 is configured to perform various signal processing with regard to communication signals to be transmitted from or received by the system. In turn, baseband processor 905 is coupled to an application processor 910, which may be a main CPU of the system to execute an OS and other system software, in addition to user applications such as many well-known social media and multimedia apps.

Application processor 910 may further be configured to perform a variety of other computing operations for the device.

[0034] In turn, application processor 910 can couple to a user interface/display 920 (e.g., touch screen display). In addition, application processor 910 may couple to a memory system including a non-volatile memory, namely a flash memory 930 and a system memory, namely a DRAM 935. In some embodiments, flash memory 930 may include a secure portion 932 in which secrets and other sensitive information may be stored. As further seen, application processor 910 also couples to a capture device 945 such as one or more image capture devices that can record video and/or still images.

[0035] A universal integrated circuit card (UICC) 940 comprises a subscriber identity module, which in some embodiments includes a secure storage 942 to store secure user information. System 900 may further include a security processor 950 (e.g., Trusted Platform Module (TPM)) that may couple to application processor 910. A plurality of sensors 925, including one or more multi-axis accelerometers may couple to application processor 910 to enable input of a variety of sensed information such as motion and other environmental information. In addition, one or more authentication devices 995 may be used to receive, for example, user biometric input for use in authentication operations.

[0036] As further illustrated, a near field communication (NFC) contactless interface 960 is provided that communicates in a NFC near field via an NFC antenna 965. While separate antennae are shown, understand that in some implementations one antenna or a different set of antennae may be provided to enable various wireless functionalities. [0037] A power management integrated circuit (PMIC) 915 couples to application processor 910 to perform platform level power management. To this end, PMIC 915 may issue power management requests to application processor 910 to enter certain low power states as desired. Furthermore, based on platform constraints, PMIC 915 may also control the power level of other components of system 900.

[0038] To enable communications to be transmitted and received such as in one or more loT networks, various circuitries may be coupled between baseband processor 905 and an antenna 990. Specifically, a radio frequency (RF) transceiver 970 and a wireless local area network (WLAN) transceiver 975 may be present. In general, RF transceiver 970 may be used to receive and transmit wireless data and calls according to a given wireless communication protocol such as 3G or 4G wireless communication protocol such as in accordance with a code division multiple access (CDMA), global system for mobile communication (GSM), long term evolution (LTE) or other protocol.

[0039] In an embodiment, transceivers 970 and/or 975 (if implemented as optical transceivers) may include embodiments described herein, such as transmitters including varying substrate thickness and/or gratings at the silicon/BOX interface.

[0040] In addition a GPS sensor 980 may be present, with location information being provided to security processor 950 for use as described herein when context information is to be used in a pairing process. Other wireless communications such as receipt or transmission of radio signals (e.g., AM/FM) and other signals may also be provided. In addition, via WLAN transceiver 975, local wireless communications, such as according to a Bluetooth™ or IEEE 802.11 standard can also be realized.

[0041] In an embodiment, sensors 925 may include portions of embodiments described herein. For example, chemical sensors using wave guides (e.g., U.S. Patent Application Publication 2010/0330553, filed June 30, 2009, and assigned to Intel Corp.) may include portions the embodiment of Figure 2H.

[0042] Referring now to Figure 5, shown is a block diagram of a system in accordance with another embodiment of the present invention. Multiprocessor system 1000 is a point-to-point interconnect system such as a server system, and includes a first processor 1070 and a second processor 1080 coupled via a point-to- point interconnect 1050. Each of processors 1070 and 1080 may be multicore processors such as SoCs, including first and second processor cores (i.e., processor cores 1074a and 1074b and processor cores 1084a and 1084b), although potentially many more cores may be present in the processors. In addition, processors 1070 and 1080 each may include a secure engine 1075 and 1085 to perform security operations such as attestations, loT network onboarding or so forth.

[0043] First processor 1070 further includes a memory controller hub (MCH) 1072 and point-to-point (P-P) interfaces 1076 and 1078. Similarly, second processor 1080 includes a MCH 1082 and P-P interfaces 1086 and 1088. MCH's 1072 and 1082 couple the processors to respective memories, namely a memory 1032 and a memory 1034, which may be portions of main memory (e.g., a DRAM) locally attached to the respective processors. First processor 070 and second processor 1080 may be coupled to a chipset 1090 via P-P interconnects 1052 and 1054, respectively. Chipset 1090 includes P-P interfaces 1094 and 1098.

[0044] Furthermore, chipset 1090 includes an interface 1092 to couple chipset 1090 with a high performance graphics engine 1038, by a P-P interconnect 1039. In turn, chipset 1090 may be coupled to a first bus 1016 via an interface 1096. Various input/output (I/O) devices 1014 may be coupled to first bus 1016, along with a bus bridge 1018 which couples first bus 1016 to a second bus 1020. Various devices may be coupled to second bus 1020 including, for example, a keyboard/mouse 1022, communication devices 1026 and a data storage unit 1028 such as a nonvolatile storage or other mass storage device. As seen, data storage unit 1028 may include code 1030, in one embodiment. As further seen, data storage unit 1028 also includes a trusted storage 1029 to store sensitive information to be protected.

Further, an audio I/O 1024 may be coupled to second bus 1020.

[0045] Audio I/O 1024 may instead be a more generalized I/O including, for example, the waveguide and optical source of Figure 2H.

[0046] The following examples pertain to further embodiments. [0047] Example 1 includes An apparatus comprising: a substrate; an oxide layer on the substrate; an epitaxial monocrystalline silicon layer, on the oxide layer, including a waveguide; a modulator included within the silicon layer; and a hybrid laser on the silicon layer; wherein (a) a first vertical axis intersects the modulator, the silicon layer, the oxide layer, and the substrate; (b) a second vertical axis intersects the laser, the silicon layer, the oxide layer, and the substrate; (c) the silicon layer has a first height, collinear with the first vertical axis and extending from a bottom surface of the silicon layer to a top surface of the silicon layer; (d) the silicon layer has a second height, collinear with the second vertical axis and extending from the bottom surface of the silicon layer to the top surface of the silicon layer; and (e) the second height is greater than the first height.

[0048] In example 2 the subject matter of the Example 1 can optionally include wherein the silicon layer comprises gratings, one of which intersects the second vertical axis.

[0049] In example 3 the subject matter of the Examples 1-2 can optionally include wherein the gratings directly contact the oxide layer.

[0050] In example 4 the subject matter of the Examples 1-3 can optionally include a transmitter, wherein: the laser is a distributed feedback (DFB) laser; the modulator is a Mach-Zehnder interferometer (MZI) modulator; the substrate, oxide layer, and silicon layer collectively form a silicon-on-insulator (Sol) substrate; and the gratings include a series of trenches, which are parallel to each other, formed in the bottom surface of the silicon layer.

[0051] In example 5 the subject matter of the Examples 1-4 can optionally include wherein the DFB laser includes a lll-V gain region.

[0052] In example 6 the subject matter of the Examples 1 -5 can optionally include wherein the gratings do not directly contact the lll-V gain region.

[0053] In an embodiment, the gratings are considered part of the laser.

[0054] In example 7 the subject matter of the Examples 1-6 can optionally include wherein the bottom surface of the silicon layer slopes non-orthogonally from a first level where the first vertical axis intersects the bottom surface of the silicon layer to a second level where the second vertical axis intersects the bottom surface of the silicon layer.

[0055] In example 8 the subject matter of the Examples 1-7 can optionally include wherein the substrate, the oxide layer, and the silicon layer each include a monolithic portion that intersects both the first and second axes.

[0056] In example 9 the subject matter of the Examples 1-8 can optionally include wherein the bottom surface of the silicon layer that slopes is located between the first and second vertical axes.

[0057] In example 10 the subject matter of the Examples 1-9 can optionally include wherein a horizontal axis intersects the silicon layer, the oxide layer, the gratings, and the second vertical axis.

[0058] In example 1 1 the subject matter of the Examples 1-10 can optionally include wherein the top surface of the silicon layer includes a monolithic portion that is horizontally planar and contacts the first and second vertical axes.

[0059] In example 12 the subject matter of the Examples 1-1 1 can optionally include a waveguide that couples the laser to the modulator; wherein the waveguide includes the bottom surface of the silicon layer that slopes.

[0060] In example 13 the subject matter of the Examples 1-12 can optionally include wherein the laser directly contacts the monolithic portion of the silicon layer.

[0061] In example 14 the subject matter of the Examples 1-13 can optionally include wherein the silicon layer directly contacts the oxide layer and the oxide layer directly contacts the substrate.

[0062] Example 15 includes a method comprising: providing a substrate; forming an interlayer on the substrate; forming an epitaxial monocrystalline silicon layer on the interlayer; forming gratings in the silicon layer; forming a first oxide layer on the gratings; coupling the first oxide layer to a second oxide layer that couples to an additional silicon layer; removing the substrate and the interlayer; forming a modulator within the silicon layer; and forming a laser portion on the silicon layer; wherein the silicon layer is thinner directly adjacent to the modulator than directly adjacent the laser portion.

[0063] In example 16 the subject matter of the Example 15 can optionally include thinning the silicon layer, before forming the first oxide layer on the gratings, so the silicon layer is thinner directly adjacent to the modulator than directly adjacent the laser portion.

[0064] In example 17 the subject matter of the Example 15-16 can optionally include implanting hydrogen below the interlayer and within the substrate.

[0065] In example 18 the subject matter of the Examples 15-17 can optionally include wherein: (a) removing the substrate comprises separating a first portion of the substrate from a second portion of the substrate where the hydrogen was implanted; (b) removing the first portion but allowing the second portion to remain coupled to the first and second oxide layers.

[0066] In example 19 the subject matter of the Examples 15-18 can optionally include etching away the second portion of the substrate after removing the first portion of the substrate but before removing the interlayer.

[0067] Example 20 includes a transmitter comprising: an oxide layer between a substrate and an epitaxial silicon layer; a modulator included within the silicon layer and a hybrid laser on the silicon layer; wherein (a) the silicon layer is thinner directly adjacent the modulator than directly adjacent the laser; and (b) the silicon layer comprises gratings directly under the laser and directly contacting the oxide layer.

[0068] In example 21 the subject matter of the Example 20 can optionally include wherein the gratings do not direct contact the laser.

[0069] In example 22 the subject matter of the Examples 20-21 can optionally include wherein an outer edge of the silicon layer slopes non-orthogonally between the modulator and the laser.

[0070] In example 23 the subject matter of the Examples 20-22 can optionally be included within a system on a chip. [0071] Example 24 includes an apparatus comprising: a substrate; an oxide layer on the substrate; an epitaxial monocrystalline silicon layer, on the oxide layer, including a waveguide; wherein (a) a first vertical axis intersects the silicon layer, the oxide layer, and the substrate; (b) a second vertical axis intersects the silicon layer, the oxide layer, and the substrate; (c) the silicon layer has a first height, collinear with the first vertical axis and extending from a bottom surface of the silicon layer to a top surface of the silicon layer; (d) the silicon layer has a second height, collinear with the second vertical axis and extending from the bottom surface of the silicon layer to the top surface of the silicon layer; (e) the silicon layer comprises gratings, one of which intersects the second vertical axis, and (f) the gratings directly contact the oxide layer.

[0072] In example 25 the subject matter of the Example 24 can optionally include wherein the second height is greater than the first height and the substrate is a silicon on insulator (SOI) substrate.

[0073] Another example includes an apparatus comprising: a substrate; an oxide layer on the substrate; an epitaxial monocrystalline silicon layer, on the oxide layer, including a waveguide; a modulator included within the silicon layer; and a hybrid laser on the silicon layer; wherein (a) a first vertical axis intersects the modulator, the silicon layer, the oxide layer, and the substrate; (b) a second vertical axis intersects the laser, the silicon layer, the oxide layer, and the substrate; (c) the silicon layer has a first height, collinear with the first vertical axis and extending from a bottom surface of the silicon layer to a top surface of the silicon layer; (d) the silicon layer has a second height, collinear with the second vertical axis and extending from the bottom surface of the silicon layer to the top surface of the silicon layer; (e) the silicon layer comprises gratings, one of which intersects the second vertical axis, and (f) the gratings directly contact the oxide layer.

[0074] An additional example includes the subject matter of the above "another example" and optionally includes wherein the second height is greater than the first height. [0075] The foregoing description of the embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. This description and the claims following include terms, such as left, right, top, bottom, over, under, upper, lower, first, second, etc. that are used for descriptive purposes only and are not to be construed as limiting. For example, terms designating relative vertical position refer to a situation where a device side (or active surface) of a substrate or integrated circuit is the "top" surface of that substrate; the substrate may actually be in any orientation so that a "top" side of a substrate may be lower than the "bottom" side in a standard terrestrial frame of reference and still fall within the meaning of the term "top." The term "on" as used herein (including in the claims) does not indicate that a first layer "on" a second layer is directly on and in immediate contact with the second layer unless such is specifically stated; there may be a third layer or other structure between the first layer and the second layer on the first layer. The embodiments of a device or article described herein can be manufactured, used, or shipped in a number of positions and orientations. Persons skilled in the relevant art can appreciate that many modifications and variations are possible in light of the above teaching. Persons skilled in the art will recognize various equivalent combinations and substitutions for various components shown in the Figures. It is therefore intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.

Claims

What is claimed is:

1. An apparatus comprising:

a substrate;

an oxide layer on the substrate;

an epitaxial monocrystalline silicon layer, on the oxide layer, including a waveguide;

a modulator included within the silicon layer; and

a hybrid laser on the silicon layer;

wherein (a) a first vertical axis intersects the modulator, the silicon layer, the oxide layer, and the substrate; (b) a second vertical axis intersects the laser, the silicon layer, the oxide layer, and the substrate; (c) the silicon layer has a first height, collinear with the first vertical axis and extending from a bottom surface of the silicon layer to a top surface of the silicon layer; (d) the silicon layer has a second height, collinear with the second vertical axis and extending from the bottom surface of the silicon layer to the top surface of the silicon layer; and (e) the second height is greater than the first height.

2. The apparatus of claim 1 , wherein the silicon layer comprises gratings, one of which intersects the second vertical axis.

3. The apparatus of claim 2, wherein the gratings directly contact the oxide layer.

4. The apparatus of claim 3 comprising a transmitter, wherein:

the laser is a distributed feedback (DFB) laser;

the modulator is a Mach-Zehnder interferometer (MZI) modulator;

the substrate, oxide layer, and silicon layer collectively form a silicon-on- insulator (Sol) substrate; and

the gratings include a series of trenches, which are parallel to each other, formed in the bottom surface of the silicon layer.

5. The apparatus of claim 4, wherein the DFB laser includes a lll-V gain region.

6. The apparatus of claim 5, wherein the gratings do not directly contact the lll-V gain region.

7. The apparatus of claim 3, wherein the bottom surface of the silicon layer slopes non-orthogonally from a first level where the first vertical axis intersects the bottom surface of the silicon layer to a second level where the second vertical axis intersects the bottom surface of the silicon layer.

8. The apparatus of claim 7, wherein the substrate, the oxide layer, and the silicon layer each include a monolithic portion that intersects both the first and second axes.

9. The apparatus of claim 7, wherein the bottom surface of the silicon layer that slopes is located between the first and second vertical axes.

10. The apparatus of claim 7, wherein a horizontal axis intersects the silicon layer, the oxide layer, the gratings, and the second vertical axis.

11. The apparatus of claim 7, wherein the top surface of the silicon layer includes a monolithic portion that is horizontally planar and contacts the first and second vertical axes.

12. The apparatus of claim 3 comprising a waveguide that couples the laser to the modulator; wherein the waveguide includes the bottom surface of the silicon layer that slopes.

13. The apparatus of claim 3, wherein the laser directly contacts the monolithic portion of the silicon layer.

14. The apparatus of claim 1 , wherein the silicon layer directly contacts the oxide layer and the oxide layer directly contacts the substrate.

15. A method comprising:

providing a substrate;

forming an interlayer on the substrate;

forming an epitaxial monocrystalline silicon layer on the interlayer;

forming gratings in the silicon layer;

forming a first oxide layer on the gratings;

coupling the first oxide layer to a second oxide layer that couples to an additional silicon layer;

removing the substrate and the interlayer;

forming a modulator within the silicon layer; and

forming a laser portion on the silicon layer;

wherein the silicon layer is thinner directly adjacent to the modulator than directly adjacent the laser portion.

16. The method of claim 15 comprising thinning the silicon layer, before forming the first oxide layer on the gratings, so the silicon layer is thinner directly adjacent to the modulator than directly adjacent the laser portion.

17. The method of claim 15 comprising implanting hydrogen below the interlayer and within the substrate.

18. The method of claim 17, wherein: (a) removing the substrate comprises separating a first portion of the substrate from a second portion of the substrate where the hydrogen was implanted; (b) removing the first portion but allowing the second portion to remain coupled to the first and second oxide layers.

19. The method of claim 18 comprising etching away the second portion of the substrate after removing the first portion of the substrate but before removing the interlayer.

20. A transmitter comprising:

an oxide layer between a substrate and an epitaxial silicon layer;

a modulator included within the silicon layer and a hybrid laser on the silicon layer;

wherein (a) the silicon layer is thinner directly adjacent the modulator than directly adjacent the laser; and (b) the silicon layer comprises gratings directly under the laser and directly contacting the oxide layer.

21. The transmitter of claim 20, wherein the gratings do not direct contact the laser.

22. The transmitter of claim 20, wherein an outer edge of the silicon layer slopes non-orthogonally between the modulator and the laser.

23. The transmitter of claim 20 included within a system on a chip.

24. An apparatus comprising:

a substrate;

an oxide layer on the substrate;

wherein (a) a first vertical axis intersects the silicon layer, the oxide layer, and the substrate; (b) a second vertical axis intersects the silicon layer, the oxide layer, and the substrate; (c) the silicon layer has a first height, collinear with the first vertical axis and extending from a bottom surface of the silicon layer to a top surface of the silicon layer; (d) the silicon layer has a second height, collinear with the second vertical axis and extending from the bottom surface of the silicon layer to the top surface of the silicon layer; (e) the silicon layer comprises gratings, one of which intersects the second vertical axis, and (f) the gratings directly contact the oxide layer.

25. The transmitter of claim 24, wherein the second height is greater than the first height and the substrate is a silicon on insulator (SOI) substrate.