WO2017107528A1 - 一种支持多安全引导的芯片及其启动方法、存储介质 - Google Patents

一种支持多安全引导的芯片及其启动方法、存储介质 Download PDF

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Publication number
WO2017107528A1
WO2017107528A1 PCT/CN2016/096743 CN2016096743W WO2017107528A1 WO 2017107528 A1 WO2017107528 A1 WO 2017107528A1 CN 2016096743 W CN2016096743 W CN 2016096743W WO 2017107528 A1 WO2017107528 A1 WO 2017107528A1
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Prior art keywords
boot
data
check
security
read
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PCT/CN2016/096743
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English (en)
French (fr)
Inventor
唐剑
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深圳市中兴微电子技术有限公司
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Publication of WO2017107528A1 publication Critical patent/WO2017107528A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/57—Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/57—Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
    • G06F21/575—Secure boot
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/60—Software deployment
    • G06F8/65—Updates
    • G06F8/66—Updates of program code stored in read-only memory [ROM]

Definitions

  • the present invention relates to a boot technology in the field of embedded chips, and more particularly to a chip supporting a multi-safe boot, a booting method thereof, and a storage medium.
  • the baseband chip adopts an embedded architecture, and is responsible for initialization of the system hardware and bootloading of the secondary boot program by boot code (boot code, read code in read only memory). At the same time, the bootrom is cured in the memory (ROM) of the chip.
  • boot code boot code, read code in read only memory
  • the bootrom is cured in the memory (ROM) of the chip.
  • ROM memory
  • product areas for chip applications such as smart phones and data cards. Each product form may use different boot startup methods. In this case, the security of the system is paid more and more attention.
  • the bootrom implementation that supports multiple secure boot modes is critical for product baseband chips in product applications.
  • baseband chips were mainly used in data card products.
  • the boot boot mode used was relatively simple, including hardware boot controller (bootctrl, boot controller) and software flash boot (nandflash boot).
  • hardware boot controller boot controller
  • software flash boot flash boot
  • an embodiment of the present invention provides a chip supporting a multi-security boot, a booting method thereof, and a storage medium.
  • the register value is read from the register
  • the corresponding boot operation is started to read data, and the data is performed. safety certificate.
  • the boot operation corresponding to the register value is determined, and the configuration field information is checked; after the check is passed, the corresponding boot operation is started to read data, and the data is secured.
  • Certification including:
  • the Nandflash boot operation is performed, and the data read by the Nandflash boot operation is checked for security;
  • the read data is normally executed, and the boot operation is performed; when the security check fails, the universal serial bus device boot (usb device boot) operation is performed.
  • the boot operation corresponding to the register value is determined, and the configuration field information is checked; after the check is passed, the corresponding boot operation is started to read data, and the data is secured.
  • Certification including:
  • the read data is normally executed and the operation is started.
  • the security check fails, the Nandflash boot operation is performed.
  • the boot operation corresponding to the register value is determined, and the configuration field information is checked; after the check is passed, the corresponding boot operation is started to read data, and the data is secured.
  • Certification including:
  • the read data is normally executed, and the operation is started; when the security check fails, the reset operation is performed.
  • the boot operation corresponding to the register value is determined, and the configuration field information is checked; after the check is passed, the corresponding boot operation is started to read data, and the data is secured.
  • Certification including:
  • the read data is normally executed, and the operation is started; when the security check fails, the reset operation is performed.
  • the boot operation corresponding to the register value is determined, and the configuration field information is checked; after the check is passed, the corresponding boot operation is started to read data, and the data is secured.
  • Certification including:
  • the boot operation is started based on the embedded multimedia card boot (emmc boot, embedded multi media card boot), and the configuration field information is read;
  • the emmc boot operation is performed, and the data read by the emmc boot operation is checked for security;
  • the read data is normally executed and the operation is started.
  • the usb device boot operation is performed.
  • the boot operation corresponding to the register value is determined, and the configuration field information is checked; after the check is passed, the corresponding boot operation is started to read data, and the data is secured.
  • Certification including:
  • the read data is normally executed, and the operation is started; when the security check fails, the emmc boot operation is performed.
  • the boot operation corresponding to the register value is determined, and the configuration field information is checked; after the check is passed, the corresponding boot operation is started to read data, and the data is secured.
  • Certification including:
  • Reading configuration field information from a serial peripheral interface nandflash (spinandflash, serial peripheral interface nandflash);
  • the spinandflash boot operation is performed, and the data read by the spinandflash boot operation is checked for security;
  • the read data is normally executed and the boot operation is performed; when the security check is passed, the usb device boot operation is performed.
  • the boot operation corresponding to the register value is determined, and the configuration field information is checked; after the check is passed, the corresponding boot operation is started to read data, and the data is secured.
  • Certification including:
  • the read data is normally executed and the operation is started; when the security check fails, the spinandflash boot process is executed.
  • the boot operation corresponding to the register value is determined, and the configuration field information is checked; after the check is passed, the corresponding boot operation is started to read data, and the data is secured.
  • Certification including:
  • a first reading unit configured to read a register value from a register after the system is initialized
  • the authentication unit is configured to determine a boot operation corresponding to the register, and check the configuration field information
  • a second reading unit configured to: after the check is passed, start the corresponding boot operation to read data
  • An execution unit configured to securely authenticate the data.
  • the executing unit includes:
  • the first execution sub-unit is configured to start a boot operation based on the Nandflash boot, read configuration field information, perform field information check based on the configuration field information, perform a Nandflash boot operation, and operate the Nandflash boot after the check is passed
  • the read data is checked for security; when the security check is passed, the read data is normally executed and the operation is started; when the security check fails, the usb device boot operation is performed.
  • the execution unit includes:
  • the second execution subunit is configured to read configuration field information from the Nandflash, obtain a usb timeout value, perform a usb device boot operation, and perform security check on the data read by the usb device boot operation; Normally execute the read data and start the operation; when the security check fails, the Nandflash boot operation is executed.
  • the execution unit includes:
  • the third execution subunit is configured to perform a usb hsic boot operation, and perform security check on the data read by the usb hsic boot operation; when the security check is passed, the read data is normally executed, and the operation is started; when the security check is not After the pass, a reset operation is performed.
  • the execution unit includes:
  • a fourth execution subunit configured to perform a sdio slave boot operation and to the sdio slave
  • the data read by the boot operation is checked for security; when the security check is passed, the read data is normally executed, and the operation is started; when the security check fails, the reset operation is performed.
  • the execution unit includes:
  • the fifth execution sub-unit is configured to start a boot operation based on the emmc boot, read configuration field information, perform field information check based on the configuration field information, perform an emmc boot operation, and perform the emmc boot operation after the check is passed
  • the read data is checked for security; when the security check is passed, the read data is normally executed and the operation is started; when the security check fails, the usb device boot operation is performed.
  • the execution unit includes:
  • the sixth execution subunit is configured to read configuration field information from emmc, obtain a usb timeout value, perform a usb device boot operation, and perform security check on the data read by the usb device boot operation; when the security check is passed Normally execute the read data and start the operation; when the security check fails, execute the emmc boot operation.
  • the execution unit includes:
  • a seventh execution subunit configured to read configuration field information from the spinandflash; perform field information check based on the configuration field information; perform a spinandflash boot operation after the check is passed, and read the data read by the spinandflash boot operation Perform security check; after the security check is passed, the read data is normally executed and the operation is started; when the security check is passed, the usb device boot operation is performed.
  • the execution unit includes:
  • the eighth execution subunit is configured to read configuration field information from the spinandflash, obtain a usb timeout value, perform a usb device boot operation, and perform security check on the data read by the usb device boot operation; when the security check is passed The read data is normally executed, and the boot operation is performed; when the security check fails, the spinandflash boot process is executed.
  • the execution unit includes:
  • the ninth execution subunit is configured to initiate a boot operation based on the uart boot.
  • the invention provides a storage medium, wherein the storage medium stores a computer program, and the computer program is configured to execute the chip startup method supporting the multi-safe boot boot.
  • the register value is read from the register; the boot operation corresponding to the register value is determined, and the configuration field information is checked; after the check is passed, the corresponding The boot operation reads the data and securely authenticates the data.
  • the bootrom of the chip supports multi-secure boot startup mode, and supports the usb boot mode for version download function, which achieves the corresponding multi-product application and software version burning effect, saves product hardware cost and software version burning cost, and improves different products. The utilization rate and software version production/maintenance efficiency, and the safety of the entire system are improved.
  • FIG. 1 is a schematic flowchart of a method for starting a chip supporting multiple secure boot according to an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of a chip supporting a multi-security boot according to an embodiment of the present invention
  • FIG. 3 is a flowchart of a nandflash boot startup according to an embodiment of the present invention.
  • FIG. 4 is a flowchart of booting a usb device boot according to an embodiment of the present invention.
  • FIG. 5 is a flowchart of an emmc boot startup according to an embodiment of the present invention.
  • FIG. 6 is a flowchart of starting a sdio slave boot according to an embodiment of the present invention.
  • FIG. 7 is a flowchart of a spinandflash boot startup according to an embodiment of the present invention.
  • FIG. 8 is a flowchart of a boot of a usb hsic boot according to an embodiment of the present invention.
  • FIG. 9 is a flowchart of security check of a bootrom according to an embodiment of the present invention.
  • the present invention provides a chip supporting multiple security boot and a startup method thereof.
  • the communication interface mode such as usb hsic boot, sdio slave boot, and uart boot is required to be connected to the application processor (AP, Application Processer) chip; in the data card and uFi products, nandflash boot, emmc boot, The external storage mode such as spinandflash is started, and the security process check is used, and the license information can be run.
  • AP Application Processer
  • the chip in the debugging production, testing and market applications will involve software version burning or updating problems, generally using the burner to burn or use the emulator to burn, for the burner burning mode, generally need a specific Hardware device and software support, suitable for storage device (nandflash, emmc, etc.) factory programming, for emulator burning, suitable for laboratory debugging phase.
  • the usb device boot mode is implemented in the bootrom, and the USB port is connected to the PC through the USB port to implement the version burning and version update function.
  • FIG. 1 is a schematic flowchart of a method for starting a chip supporting multiple security boots according to an embodiment of the present invention. As shown in FIG. 1 , the method for starting a chip supporting multiple security boots includes the following steps:
  • Step 101 After the system is initialized, the register value is read from the register.
  • the central processing unit (CPU, Center Processing Unit) in the chip starts to execute the bootrom program from the memory (ROM), performs the shutdown interrupt, initializes the stack, sets the data segment, initializes the timer, and Uart.
  • the bootrom program consists of a number of column bootrom instructions.
  • the purpose of reading the register value from the register is to obtain a boot operation corresponding to the register value.
  • Step 102 Determine a boot operation corresponding to the register value, and check configuration field information.
  • Step 103 After the check is passed, start the corresponding boot operation to read data, and The data is verified for security.
  • the configuration relationship between the register value and the boot operation is not limited.
  • the register value is 0000: the boot operation is started based on the Nandflash boot, and the configuration field information is read; the field information check is performed based on the configuration field information; when the check is passed, the Nandflash boot operation is performed, and the Nandflash boot operation is read.
  • the data is checked for security; when the security check is passed, the read data is normally executed, and the operation is started; when the security check fails, the universal serial bus device is executed to boot the usb device boot operation. .
  • the chip system starts directly from the Nandflash boot, reads the configuration field information, and judges the configuration field information. If the configuration field information is consistent, the Nandflash boot process is performed to perform security check, otherwise the process jumps to the usb device boot process.
  • the chip usb interface is connected to the PC for software version download and burning.
  • the register value is 0001: the configuration field information is read from the flash Nandflash, and the usb timeout value is obtained; the usb device boot operation is performed, and the data read by the usb device boot operation is checked; when the security check is passed, the normal check is performed. Execute the read data and start the operation; when the security check fails, perform the Nandflash boot operation.
  • the chip system reads the configuration field information from the Nandflash, obtains the usb timeout value, enters the usb device boot process, and the chip usb interface is connected to the PC for downloading the software version. If the usb times out, the nandflash boot process is returned. .
  • the register value is 0010: the usb hsic boot operation is performed, and the data read by the usb hsic boot operation is checked for security; when the security check is passed, the read data is normally executed, and the operation is started; when the security check fails, Perform a reset operation.
  • the chip When doing a smart modem (Modem), the chip supports no external boot, downloading the version from the AP chip side to the internal random access memory of the chip through usb hsic (IRAM, Inner Random Access) Executed in Memory).
  • IRAM Inner Random Access
  • the value of the register is 0011: the sdio slave boot operation is performed, and the data read by the sdio slave boot operation is checked for security; when the security check is passed, the read data is normally executed, and the operation is started; when the security check fails, Perform a reset operation.
  • the chip When doing the smart machine Modem, the chip supports no external boot, and downloads the version from the AP chip side to the IRAM in the chip through the sdio slave.
  • the register value is 0100: the boot operation is started based on the emmc boot, and the configuration field information is read; the field information check is performed based on the configuration field information; when the check is passed, the emmc boot operation is performed, and the emmc boot operation is read.
  • the data is checked for security; when the security check is passed, the read data is normally executed, and the operation is started; when the security check fails, the usb device boot operation is performed.
  • the chip system starts directly from the emmc boot, and reads the configuration field information for judgment. If the configuration field information is consistent, the emmc boot process is entered, and the security check is performed, otherwise the process jumps to the usb device boot process.
  • the chip usb interface is connected to the PC for software version download and burning.
  • the value of the register is 0101: the configuration field information is read from the emmc, and the usb timeout value is obtained.
  • the usb device boot operation is performed, and the data read by the usb device boot operation is checked for security; when the security check is passed, the normal execution is performed. Read data, start operation; when the security check fails, execute the emmc boot operation.
  • the chip system reads the configuration field information from emmc, obtains the usb timeout value, and enters the usb device boot process.
  • the chip usb interface is connected to the PC for software version download burning. If the usb times out, it returns the emmc boot process.
  • the register value is 1000: the configuration field information is read from the spinandflash; the field information check is performed based on the configuration field information; when the check is passed, the spinandflash boot operation is performed, And performing security check on the data read by the spinandflash boot operation; after the security check is passed, the read data is normally executed, and the operation is started; when the security check is passed, the usb device boot operation is performed.
  • the chip system directly reads the configuration field information from the spinandflash to determine, if the configuration field information is consistent, enters the spinandflash boot process, and performs a security check, otherwise, the device jumps to the usb device boot process, and the chip usb interface is connected with the PC. Download the burn in the software version.
  • the register value is 1001: the configuration field information is read from the spinandflash, and the usb timeout value is obtained; the usb device boot operation is performed, and the data read by the usb device boot operation is checked for security; when the security check is passed, the normal execution is performed. Read data, start operation; when the security check fails, execute the spinandflash boot process.
  • the chip system reads the configuration field information from the spinandflash, obtains the usb timeout value, enters the usb device boot process, and the chip usb interface is connected to the PC for downloading the software version. If the usb times out, the spinandflash boot process is returned. .
  • the register value is other: Start the boot operation based on the uart boot.
  • the uart boot mode is adopted, and the 1K modem protocol is used to interact with the PC console program through uart, which facilitates debugging and downloading, and also supports an external AP chip through the uart interface, and downloads the version from the AP chip side to the IRAM of the chip through uart. .
  • the USB boot when the storage peripheral is used as the boot mode, the USB boot is supported as the combined boot mode, and the storage peripheral is used for booting the software version of the usb device boot when there is no software version or wrong software version.
  • FIG. 2 is a schematic structural diagram of a chip supporting a multi-security boot according to an embodiment of the present invention. As shown in FIG. 2, the chip supporting the multi-security boot includes:
  • the first reading unit 21 is configured to read the register value from the register after the system is initialized
  • the authentication unit 22 is configured to determine a boot operation corresponding to the register and to configure a configuration word Segment information is checked;
  • the second reading unit 23 is configured to: after the check passes, start the corresponding boot operation to read data;
  • the executing unit 24 is configured to perform security authentication on the data.
  • the executing unit 24 includes:
  • the first execution sub-unit 241 is configured to start a boot operation based on the Nandflash boot, read configuration field information, perform field information check based on the configuration field information, perform a Nandflash boot operation, and perform the Nandflash boot operation after the check is passed.
  • the data read by the operation is checked for security; when the security check is passed, the read data is normally executed, and the operation is started; when the security check fails, the usb device boot operation is performed.
  • the execution unit 24 includes:
  • the second execution sub-unit 242 is configured to read configuration field information from the Nandflash, obtain a usb timeout value, perform a usb device boot operation, and perform security check on the data read by the usb device boot operation; After that, the read data is normally executed, and the operation is started; when the security check fails, the Nandflash boot operation is performed.
  • the execution unit 24 includes:
  • the third execution sub-unit 243 is configured to perform a usb hsic boot operation, and perform security check on the data read by the usb hsic boot operation; when the security check is passed, the read data is normally executed, and the operation is started; when the security check is performed; After failing, perform a reset operation.
  • the execution unit 24 includes:
  • the fourth execution sub-unit 244 is configured to perform a sdio slave boot operation, and perform security check on the data read by the sdio slave boot operation; when the security check is passed, the read data is normally executed, and the operation is started; when the security check is performed; After failing, perform a reset operation.
  • the execution unit 24 includes:
  • the fifth execution sub-unit 245 is configured to start a boot operation based on the emmc boot, and read the configuration. Setting field information; performing field information check based on the configuration field information; performing an emmc boot operation after the check is passed, and performing security check on the data read by the emmc boot operation; when the security check is passed, the normal read is performed. Take the data, start the operation; after the security check fails, execute the usb device boot operation.
  • the execution unit 24 includes:
  • the sixth execution sub-unit 246 is configured to read the configuration field information from the emmc, obtain the usb timeout value, perform the usb device boot operation, and perform security check on the data read by the usb device boot operation; After that, the read data is normally executed, and the operation is started; when the security check fails, the emmc boot operation is performed.
  • the execution unit 24 includes:
  • the seventh execution sub-unit 247 is configured to read configuration field information from the spinandflash; perform field information check based on the configuration field information; perform a spinandflash boot operation after the check is passed, and read the spinandflash boot operation The data is checked for security; when the security check is passed, the read data is normally executed, and the operation is started; when the security check is passed, the usb device boot operation is performed.
  • the execution unit 24 includes:
  • the eighth execution sub-unit 248 is configured to read configuration field information from the spinandflash, obtain a usb timeout value, perform a usb device boot operation, and perform security check on the data read by the usb device boot operation; After that, the read data is normally executed, and the boot operation is performed; when the security check fails, the spinandflash boot process is executed.
  • the execution unit 24 includes:
  • the ninth execution subunit 249 is configured to initiate a boot operation based on the uart boot.
  • FIG. 3 is a flowchart of a nandflash boot startup according to an embodiment of the present invention, including:
  • Step 301 Configure a system clock and the like required by the nandflash.
  • Step 302 Configure the nandflash controller and enable nandflash.
  • Step 303 The bootrom module determines the nandflash bit width and page size and the number of page address periods according to the pin.
  • Step 304 Configure the nandflash control with the parsed data bit width and page size.
  • Step 306 Read the code data of the nandflash to the IRAM.
  • Step 307 Jump to IRAM for execution.
  • FIG. 4 is a flowchart of booting a usb device boot according to an embodiment of the present invention, including:
  • Step 401 Configure a phase locked loop (PLL, Phase Lock Loop) and a frequency dividing register required by usb.
  • PLL Phase locked Loop
  • Step 402 Configure the usb module to be enabled.
  • Step 403 Detect whether there is a reset command of the usb connection during the usb insertion time. Received instructions have a usb connection, timeout is considered no usb connection (if no connection jumps to emmc boot).
  • Step 404 Start the usb enumeration process (the synchronization process of the usb host and the device according to the protocol).
  • Step 405 The enumeration succeeds in the usb enumeration time (if timeout (the device does not have a device driver on the host side), jump to the emmc boot).
  • Step 406 Wait for the synchronization character in the usb synchronization time, time out the usb device boot, and start the emmc boot.
  • Step 407 Receive the synchronization character, wait for the configuration register flag character, followed by the configuration data.
  • Step 408 The first data is a register address.
  • Step 409 The second data is configuration data.
  • Step 410 Exit the register configuration when the received register address is 0.
  • Step 411 Waiting for the download data flag character, followed by downloading the data.
  • Step 412 The first one is a download address.
  • Step 413 The second data is the download data length.
  • Step 414 Receive the download data until the data length is reached.
  • Step 415 The downloading process of 9-12 steps can be performed by continuously downloading data multiple times.
  • Step 416 If the execution sync character is received, the following is the execution address.
  • Step 417 Assign the received execution address to Image_addr and jump to Image_addr for execution.
  • FIG. 5 is a flowchart of an emmc boot startup according to an embodiment of the present invention, including:
  • Step 501 Configure a system clock and other configurations required by emmc.
  • Step 502 Configure the emmc controller to initialize the emmc driver.
  • Step 503 Read the emmc device register parameter, so that the emmc controller parameter and the emmc device parameter match each other.
  • Step 504 Configure the size of the data to be loaded from the emmc according to the Loaded_size (Loaded_size has different values according to different scenarios, and the loaded_size value needs to be calculated according to the scenario in advance).
  • Step 505 Send a multi-block read command to load the Loaded_size data from the main area to the specified address.
  • Step 506 Assign the specified address value to Image_addr and jump to Image_addr for execution.
  • FIG. 6 is a flowchart of a startup of a sdio slave boot according to an embodiment of the present invention, including:
  • Step 601 Configure the PLL and the frequency division register required by the sdio slave.
  • Step 602 Configure the sdio slave module and enable the sdio slave.
  • Step 603 Detect whether there is a sdio slave connection. If there is no connection, continue to wait.
  • Step 604 If there is a connection, start the sdio slave initialization process, and initialize the configuration according to the configuration of the sdio host connected to the sdio slave.
  • Step 605 If the initialization fails, re-enter the check sdio connection process.
  • Step 606 The sdio slave receives the code data to the IRAM_RM_BASE address.
  • Step 607 Assign IRAM_RM_BASE to Image_addr and jump to Image_addr for execution.
  • FIG. 7 is a flowchart of a spinandflash boot startup according to an embodiment of the present invention, including:
  • Step 701 Configure a system clock and the like required by the spifc.
  • Step 702 Configure the spifc controller.
  • Step 703 Determine the page size of the spinandflash according to the external pin.
  • Step 704 Configure the controller according to the page size.
  • Step 705 Read the spinandflash data into the IRAM through the spifc interface.
  • Step 706 Jump to IRAM for execution.
  • FIG. 8 is a flowchart of a boot of a usb hsic boot according to an embodiment of the present invention, including:
  • Step 801 Configure the PLL and the frequency division register required by usb hsic.
  • Step 802 Configure the usb hsic module and enable usb hsic.
  • Step 803 Detect whether there is a reset command of the usb hsic connection. After receiving the description, there is a usb connection. If it times out, it will continue to wait if there is no usb hsic connection.
  • Step 804 Start the usb hsic enumeration process (the synchronization process of the usb host and the device according to the protocol).
  • Step 805 If the enumeration fails, the process waits for the reset command to wait for the connection again.
  • Step 806 Wait for the sync character if successful, and continue waiting if the sync word is not received.
  • Step 807 Receive the synchronization character, wait for the configuration register flag character, followed by the configuration data.
  • Step 808 The first data is a register address.
  • Step 809 The second data is configuration data.
  • Step 810 Exit the register configuration when the received register address is 0.
  • Step 811 Waiting for the download data flag character, followed by downloading the data.
  • Step 812 The first data is a download address.
  • Step 813 The second data is the download data length.
  • Step 814 Receive the download data until the number of data bytes is reached.
  • Step 815 The downloading process of steps 809-812 may be performed by continuously downloading data multiple times.
  • Step 816 If the execution sync character is received, the following is the execution address.
  • Step 817 Pay the received execution address to Image_addr and jump to Image_addr to execute.
  • FIG. 9 is a flowchart of security check of a bootrom according to an embodiment of the present invention, including:
  • Step 901 Read the value corresponding to the pin of the efuse_bypass. If it is 0, the security boot function is enabled. Otherwise, the security function is not enabled, and the security check is directly considered.
  • Step 902 Read the secure boot enable value.
  • Step 903 Determine whether it is a secure boot according to the security boot enable value. If the security boot enable value is not equal to 0xff, the secure boot is not enabled.
  • Step 904 The security boot enable value is equal to 0xff, and the PUK HASH value of the secure boot is read.
  • Step 905 Determine whether the HASH value of the secure boot PUK is greater than 0. If greater than 0, enable the secure boot, otherwise the secure boot is not enabled.
  • Step 906 If the security boot is not turned on, the process directly jumps to the security check process.
  • Step 907 If it is a secure boot, the HASH module is called to calculate the HASH value of the PUK, and compared with the HASH value of the secure boot PUK, if not equal, it indicates that the PUK is not valid.
  • Step 908 If they are equal, the HASH module is called to calculate the HASH value HASH_X of the primary boot. Otherwise, the security check fails and the USB boot process is re-entered.
  • Step 909 Read the encrypted HASH data of the primary boot.
  • Step 910 The rsa module is called to decrypt to obtain HASH_Y.
  • Step 911 Compare whether HASH_X is equal to HASH_Y.
  • Step 912 If equal, the security check passes.
  • Step 913 If not equal, the security check fails.
  • the secondary boot code After reading the secondary boot code from the Nandflash device, the secondary boot code is verified by the security check process described in FIG. 10, and the secondary boot code is executed after the verification is passed.
  • the configuration field information is read and judged. If the information is consistent, the secondary boot code is verified and decrypted by the security check process described in FIG. Boot code; if the information does not match, after downloading the secondary boot code through the usb slave device interface, use the security check process described in Figure 9 to encrypt and decrypt the secondary boot code, and execute the downloaded secondary boot code after verification.
  • the secondary boot code After downloading the secondary boot code through the usb slave device interface, the secondary boot code is verified and decrypted by the security check process described in FIG. 9, and the secondary boot code is executed after the verification is passed.
  • the secondary boot code After reading the secondary boot code from the emmc device, the secondary boot code is verified by the security check process described in FIG. 9, and the secondary boot code is executed after the verification is passed.
  • the secondary boot code After downloading the secondary boot code through the sdio interface, the secondary boot code is verified and decrypted by the security check process described in FIG. 9, and the secondary boot code is executed after the verification is passed.
  • the secondary boot code After reading the secondary boot code from the spinandflash device, the secondary boot code is verified by the security check process described in FIG. 9, and the secondary boot code is executed after the verification is passed.
  • the secondary boot code After downloading the secondary boot code through the usb hsic device interface, the secondary boot code is verified and decrypted by the security check process described in FIG. 9, and the secondary boot code is executed after the verification is passed.
  • the embodiment of the invention further describes a storage medium in which a computer program is stored, the computer program being configured to execute the chip startup method supporting the multiple secure boot boot of the foregoing embodiments.
  • the disclosed method and smart device may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner such as: multiple units or components may be combined, or Can be integrated into another system, or some features can be ignored or not executed.
  • the coupling, or direct coupling, or communication connection of the components shown or discussed may be indirect coupling or communication connection through some interfaces, devices or units, and may be electrical, mechanical or other forms. of.
  • the units described above as separate components may or may not be physically separated, and the components displayed as the unit may or may not be physical units, that is, may be located in one place or distributed to multiple network units; Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one second processing unit, or each unit may be separately used as one unit, or two or more units may be integrated into one unit;
  • the above integrated unit can be implemented in the form of hardware or in the form of hardware plus software functional units.
  • the bootrom of the chip of the invention supports multiple security boot startup modes, and supports the usb boot mode for version downloading function, which achieves corresponding multi-product application and software version burning effect, saves product hardware cost and software version burning cost, and improves Different product usage rates and software version production/repair efficiency, and improved overall system security.

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Abstract

一种支持多安全boot的芯片及其启动方法、存储介质，所述方法包括：系统初始化后，从寄存器中读取寄存器值(101)；确定出与所述寄存器值对应的boot操作，并对配置字段信息进行检查(102)；检查通过后，启动所述对应的boot操作读取数据，并对所述数据进行安全认证(103)。

Description

一种支持多安全引导的芯片及其启动方法、存储介质 技术领域
本发明涉及嵌入式芯片领域中的引导(boot)技术，尤其涉及一种支持多安全boot的芯片及其启动方法、存储介质。
背景技术
基带芯片采用嵌入式架构，通过引导代码(bootrom，boot code in read only memory)来负责系统硬件的初始化及二级boot程序的引导加载。同时，bootrom是固化在芯片的内存(ROM)中。而芯片应用的产品领域比较多，如智能机，数据卡等，每一种产品形态都可能使用不同的boot启动方式，在这种情况下，系统的安全性受到越来越多的重视，因此，支持多种安全boot方式的bootrom实现对于手机基带芯片在产品应用方面至关重要。
以往基带芯片主要应用在数据卡产品中，使用的boot启动方式比较单一，包括硬件引导控制器(bootctrl，boot controller)和软件闪存引导(nandflash boot)方式。随着基带芯片的产品应用形态增加，单一的boot方式已无法满足产品要求。
发明内容
为解决上述技术问题，本发明实施例提供了一种支持多安全boot的芯片及其启动方法、存储介质。
本发明实施例提供的支持多安全boot的芯片启动方法，包括：
系统初始化后，从寄存器中读取寄存器值；
确定出与所述寄存器值对应的boot操作，并对配置字段信息进行检查；
检查通过后，启动所述对应的boot操作读取数据，并对所述数据进行 安全认证。
本发明实施例中，所述确定出与所述寄存器值对应的boot操作，并对配置字段信息进行检查；检查通过后，启动所述对应的boot操作读取数据，并对所述数据进行安全认证，包括：
基于Nandflash boot启动boot操作，读取配置字段信息；
基于所述配置字段信息，执行字段信息检查；
当检查通过后，执行Nandflash boot操作，并对所述Nandflash boot操作读取的数据进行安全检查；
当安全检查通过后，正常执行读取的数据、启动操作；当安全检查未通过后，执行通用串行总线设备引导(usb device boot)操作。
本发明实施例中，所述确定出与所述寄存器值对应的boot操作，并对配置字段信息进行检查；检查通过后，启动所述对应的boot操作读取数据，并对所述数据进行安全认证，包括：
从闪存(Nandflash)中读取配置字段信息，获取通用串行总线(usb，universal serial bus)超时时间值；
执行usb device boot操作，并对所述usb device boot操作读取的数据进行安全检查；
当安全检查通过后，正常执行读取的数据、启动操作；当安全检查未通过后，执行Nandflash boot操作。
本发明实施例中，所述确定出与所述寄存器值对应的boot操作，并对配置字段信息进行检查；检查通过后，启动所述对应的boot操作读取数据，并对所述数据进行安全认证，包括：
执行通用串行总线高速集成电路引导(usb hsic boot，universal serial bus high speed intergrated circuit boot)操作并对所述usb hsic boot操作读取的数据进行安全检查；
当安全检查通过后，正常执行读取的数据、启动操作；当安全检查未通过后，执行复位操作。
本发明实施例中，所述确定出与所述寄存器值对应的boot操作，并对配置字段信息进行检查；检查通过后，启动所述对应的boot操作读取数据，并对所述数据进行安全认证，包括：
执行同步动态输入输出引导(sdio slave boot，synchronous dynamic input output slave boot)操作，并对所述sdio slave boot操作读取的数据进行安全检查；
当安全检查通过后，正常执行读取的数据、启动操作；当安全检查未通过后，执行复位操作。
本发明实施例中，所述确定出与所述寄存器值对应的boot操作，并对配置字段信息进行检查；检查通过后，启动所述对应的boot操作读取数据，并对所述数据进行安全认证，包括：
基于嵌入式多媒体卡引导(emmc boot，embedded multi media card boot)启动boot操作，读取配置字段信息；
基于所述配置字段信息，执行字段信息检查；
当检查通过后，执行emmc boot操作，并对所述emmc boot操作读取的数据进行安全检查；
当安全检查通过后，正常执行读取的数据、启动操作；当安全检查未通过后，执行usb device boot操作。
本发明实施例中，所述确定出与所述寄存器值对应的boot操作，并对配置字段信息进行检查；检查通过后，启动所述对应的boot操作读取数据，并对所述数据进行安全认证，包括：
从emmc中读取配置字段信息，获取usb超时时间值；
执行usb device boot操作，并对所述usb device boot操作读取的数据进 行安全检查；
当安全检查通过后，正常执行读取的数据、启动操作；当安全检查未通过后，执行emmc boot操作。
本发明实施例中，所述确定出与所述寄存器值对应的boot操作，并对配置字段信息进行检查；检查通过后，启动所述对应的boot操作读取数据，并对所述数据进行安全认证，包括：
从串行外设接口闪存(spinandflash，serial peripheral interface nandflash)中读取配置字段信息；
基于所述配置字段信息，执行字段信息检查；
当检查通过后，执行spinandflash boot操作，并对所述spinandflash boot操作读取的数据进行安全检查；
当安全检查通过后，正常执行读取的数据、启动操作；当安全检查通过后，执行usb device boot操作。
本发明实施例中，所述确定出与所述寄存器值对应的boot操作，并对配置字段信息进行检查；检查通过后，启动所述对应的boot操作读取数据，并对所述数据进行安全认证，包括：
从spinandflash中读取配置字段信息，获取usb超时时间值；
执行usb device boot操作，并对所述usb device boot操作读取的数据进行安全检查；
当安全检查通过后，正常执行读取的数据、启动操作；当安全检查未通过后，执行spinandflash boot过程。
本发明实施例中，所述确定出与所述寄存器值对应的boot操作，并对配置字段信息进行检查；检查通过后，启动所述对应的boot操作读取数据，并对所述数据进行安全认证，包括：
基于通用同步/异步收发传输器引导(uart boot，universal asynchronous  receiver/transmitter boot)启动boot操作。
本发明实施例提供的支持多安全boot的芯片，包括：
第一读取单元，配置为当系统初始化后，从寄存器中读取寄存器值；
认证单元，配置为确定出与述寄存器对应的boot操作，并对配置字段信息进行检查；
第二读取单元，配置为检查通过后，启动所述对应的boot操作读取数据；
执行单元，配置为对所述数据进行安全认证。
本发明实施例中，所述执行单元，包括：
第一执行子单元，配置为基于Nandflash boot启动boot操作，读取配置字段信息；基于所述配置字段信息，执行字段信息检查；当检查通过后，执行Nandflash boot操作，并对所述Nandflash boot操作读取的数据进行安全检查；当安全检查通过后，正常执行读取的数据、启动操作；当安全检查未通过后，执行usb device boot操作。
本发明实施例中，所述执行单元包括：
第二执行子单元，配置为从Nandflash中读取配置字段信息，获取usb超时时间值；执行usb device boot操作，并对所述usb device boot操作读取的数据进行安全检查；当安全检查通过后，正常执行读取的数据、启动操作；当安全检查未通过后，执行Nandflash boot操作。
本发明实施例中，所述执行单元包括：
第三执行子单元，配置为执行usb hsic boot操作，并对所述usb hsic boot操作读取的数据进行安全检查；当安全检查通过后，正常执行读取的数据、启动操作；当安全检查未通过后，执行复位操作。
本发明实施例中，所述执行单元包括：
第四执行子单元，配置为执行sdio slave boot操作，并对所述sdio slave  boot操作读取的数据进行安全检查；当安全检查通过后，正常执行读取的数据、启动操作；当安全检查未通过后，执行复位操作。
本发明实施例中，所述执行单元包括：
第五执行子单元，配置为基于emmc boot启动boot操作，读取配置字段信息；基于所述配置字段信息，执行字段信息检查；当检查通过后，执行emmc boot操作，并对所述emmc boot操作读取的数据进行安全检查；当安全检查通过后，正常执行读取的数据、启动操作；当安全检查未通过后，执行usb device boot操作。
本发明实施例中，所述执行单元包括：
第六执行子单元，配置为从emmc中读取配置字段信息，获取usb超时时间值；执行usb device boot操作，并对所述usb device boot操作读取的数据进行安全检查；当安全检查通过后，正常执行读取的数据、启动操作；当安全检查未通过后，执行emmc boot操作。
本发明实施例中，所述执行单元包括：
第七执行子单元，配置为从spinandflash中读取配置字段信息；基于所述配置字段信息，执行字段信息检查；当检查通过后，执行spinandflash boot操作，并对所述spinandflash boot操作读取的数据进行安全检查；当安全检查通过后，正常执行读取的数据、启动操作；当安全检查通过后，执行usb device boot操作。
本发明实施例中，所述执行单元包括：
第八执行子单元，配置为从spinandflash中读取配置字段信息，获取usb超时时间值；执行usb device boot操作，并对所述usb device boot操作读取的数据进行安全检查；当安全检查通过后，正常执行读取的数据、启动操作；当安全检查未通过后，执行spinandflash boot过程。
本发明实施例中，所述执行单元包括：
第九执行子单元，配置为基于uart boot启动boot操作。
本发明提供的一种存储介质，所述存储介质中存储有计算机程序，所述计算机程序配置为执行所述的支持多安全引导boot的芯片启动方法。
本发明实施例的技术方案中，系统初始化后，从寄存器中读取寄存器值；确定出与所述寄存器值对应的boot操作，并对配置字段信息进行检查；检查通过后，启动所述对应的boot操作读取数据，并对所述数据进行安全认证。芯片的bootrom支持多安全boot启动方式，且支持usb boot方式进行版本下载功能，达到了对应多种产品应用及软件版本烧录效果，节省了产品硬件成本及软件版本烧录成本，提高了不同产品使用率及软件版本生产/维修效率、提高了整个系统的安全性等。
附图说明
图1为本发明实施例的支持多安全boot的芯片启动方法的流程示意图；
图2为本发明实施例的支持多安全boot的芯片的结构组成示意图；
图3是本发明实施例的nandflash boot启动流程图；
图4是本发明实施例的usb device boot启动的流程图；
图5是本发明实施例的emmc boot启动流程图；
图6是本发明实施例的sdio slave boot启动流程图；
图7是本发明实施例的spinandflash boot启动流程图；
图8是本发明实施例的usb hsic boot启动流程图；
图9是本发明实施例的bootrom的安全检查流程图。
具体实施方式
为了能够更加详尽地了解本发明实施例的特点与技术内容，下面结合附图对本发明实施例的实现进行详细阐述，所附附图仅供参考说明之用，并非用来限定本发明实施例。
为了克服现有技术中存在的数据卡使用单一boot方式、系统安全性不够和烧录不方便等问题和缺陷，本发明实施例提供了一种支持多安全boot的芯片及其启动方法。在智能机产品中，需求usb hsic boot、sdio slave boot、uart boot等通讯接口方式与应用处理器(AP，Application Processer)芯片对接启动；在数据卡和uFi产品中，需求nandflash boot、emmc boot、spinandflash等外存储方式启动，并使用安全流程检查，具有许可信息才能运行。
另外，芯片在调试生产，测试及市场应用中，会涉及软件版本烧录或更新问题，一般采用烧录器烧录或者使用仿真器烧录，对于烧录器烧录方式，一般都需要特定的硬件设备和软件支持，适用于存储器件(nandflash，emmc等)出厂烧录，对于仿真器烧录，适用于实验室调试阶段使用。而在软件版本烧录或版本更新时，在bootrom中实现usb device boot方式，通过usb口与PC机相连，实现版本烧录和版本更新功能。
图1为本发明实施例的支持多安全boot的芯片启动方法的流程示意图，如图1所示，所述支持多安全boot的芯片启动方法包括以下步骤：
步骤101：系统初始化后，从寄存器中读取寄存器值。
本发明实施例中，芯片复位释放后，芯片中的中央处理器(CPU，Center Processing Unit)从内存(ROM)中开始执行bootrom程序，进行关中断，初始化栈，设置数据段，初始化计时器和uart。这里，bootrom程序由一些列的bootrom指令组成。
本发明实施例中，从寄存器中读取寄存器值的目的是为了获取与所述寄存器值对应的boot操作。
步骤102：确定出与所述寄存器值对应的boot操作，并对配置字段信息进行检查。
步骤103：检查通过后，启动所述对应的boot操作读取数据，并对所 述数据进行安全认证。
本发明实施例中，寄存器值与boot操作间的配置关系不做限定。
下面以其中一种寄存器值与boot操作间的配置关系为例进行说明。
寄存器值为0000：基于Nandflash boot启动boot操作，读取配置字段信息；基于所述配置字段信息，执行字段信息检查；当检查通过后，执行Nandflash boot操作，并对所述Nandflash boot操作读取的数据进行安全检查；当安全检查通过后，正常执行读取的数据、启动操作；当安全检查未通过后，执行通用串行总线设备引导usb device boot操作。。
具体地，芯片系统直接从Nandflash boot启动，读取配置字段信息，对配置字段信息进行判断，如配置字段信息符合，进入Nandflash boot过程，进行安全检查，否则跳转到usb device boot过程。芯片usb接口与PC机对接，用于软件版本下载烧录。
寄存器值为0001：从闪存Nandflash中读取配置字段信息，获取usb超时时间值；执行usb device boot操作，并对所述usb device boot操作读取的数据进行安全检查；当安全检查通过后，正常执行读取的数据、启动操作；当安全检查未通过后，执行Nandflash boot操作。
具体地，芯片系统从Nandflash读取配置字段信息，获取usb超时时间值，进入usb device boot过程，芯片usb接口与PC机对接，用于软件版本下载烧录，如果usb超时，则返回nandflash boot过程。
寄存器值为0010：执行usb hsic boot操作，并对所述usb hsic boot操作读取的数据进行安全检查；当安全检查通过后，正常执行读取的数据、启动操作；当安全检查未通过后，执行复位操作。
具体地，进入usb hsic boot方式，进行安全检查，否则复位芯片。在做智能机调制解调器(Modem)时，芯片支持无外存启动，通过usb hsic从AP芯片侧下载版本到本芯片内部随机存储器(IRAM，Inner Random Access  Memory)中执行。
寄存器值为0011：执行sdio slave boot操作，并对所述sdio slave boot操作读取的数据进行安全检查；当安全检查通过后，正常执行读取的数据、启动操作；当安全检查未通过后，执行复位操作。
具体地，进入sdio slave boot方式，进行安全检查，否则复位芯片。在做智能机Modem时，芯片支持无外存启动，通过sdio slave从AP芯片侧下载版本到本芯片IRAM中运行。
寄存器值为0100：基于emmc boot启动boot操作，读取配置字段信息；基于所述配置字段信息，执行字段信息检查；当检查通过后，执行emmc boot操作，并对所述emmc boot操作读取的数据进行安全检查；当安全检查通过后，正常执行读取的数据、启动操作；当安全检查未通过后，执行usb device boot操作。
具体地，芯片系统直接从emmc boot启动，读取配置字段信息进行判断，如配置字段信息符合，则进入emmc boot过程，并进行安全检查，否则跳转到usb device boot过程。芯片usb接口与PC机对接，用于软件版本下载烧录。
寄存器值为0101：从emmc中读取配置字段信息，获取usb超时时间值；执行usb device boot操作，并对所述usb device boot操作读取的数据进行安全检查；当安全检查通过后，正常执行读取的数据、启动操作；当安全检查未通过后，执行emmc boot操作。
具体地，芯片系统从emmc读取配置字段信息，获取usb超时时间值，进入usb device boot过程。芯片usb接口与PC机对接，用于软件版本下载烧录，如果usb超时，则返回emmc boot过程。
寄存器值为1000：从spinandflash中读取配置字段信息；基于所述配置字段信息，执行字段信息检查；当检查通过后，执行spinandflash boot操作， 并对所述spinandflash boot操作读取的数据进行安全检查；当安全检查通过后，正常执行读取的数据、启动操作；当安全检查通过后，执行usb device boot操作。
具体地，芯片系统直接从spinandflash读取配置字段信息进行判断，如配置字段信息符合，进入spinandflash boot过程，并进行安全检查，否则跳转到usb device boot过程，芯片usb接口与PC机对接，用于软件版本下载烧录。
寄存器值为1001：从spinandflash中读取配置字段信息，获取usb超时时间值；执行usb device boot操作，并对所述usb device boot操作读取的数据进行安全检查；当安全检查通过后，正常执行读取的数据、启动操作；当安全检查未通过后，执行spinandflash boot过程。
具体地，芯片系统从spinandflash读取配置字段信息，获取usb超时时间值，进入usb device boot过程，芯片usb接口与PC机对接，用于软件版本下载烧录，如果usb超时，则返回spinandflash boot过程。
寄存器值为其它：基于uart boot启动boot操作。
具体地，进入uart boot方式，采用1K modem协议，通过uart与PC控制台程序交互，便于调试与下载，也可支持通过uart接口外接AP芯片，通过uart从AP芯片侧下载版本到本芯片IRAM启动。
本发明实施例中，以存储外设作为boot方式时，支持与usb device boot作为组合boot方式，便于存储外设在无软件版本或错误软件版本时用于usb device boot启动实现软件版本烧录。
图2为本发明实施例的支持多安全boot的芯片的结构组成示意图，如图2所示，所述支持多安全boot的芯片包括：
第一读取单元21，配置为当系统初始化后，从寄存器中读取寄存器值；
认证单元22，配置为确定出与述寄存器对应的boot操作，并对配置字 段信息进行检查；
第二读取单元23，配置为当检查通过后，启动所述对应的boot操作读取数据；
执行单元24，配置为对所述数据进行安全认证。
在一种实施方式中，所述执行单元24，包括：
第一执行子单元241，配置为基于Nandflash boot启动boot操作，读取配置字段信息；基于所述配置字段信息，执行字段信息检查；当检查通过后，执行Nandflash boot操作，并对所述Nandflash boot操作读取的数据进行安全检查；当安全检查通过后，正常执行读取的数据、启动操作；当安全检查未通过后，执行usb device boot操作。
在一种实施方式中，所述执行单元24包括：
第二执行子单元242，配置为从Nandflash中读取配置字段信息，获取usb超时时间值；执行usb device boot操作，并对所述usb device boot操作读取的数据进行安全检查；当安全检查通过后，正常执行读取的数据、启动操作；当安全检查未通过后，执行Nandflash boot操作。
在一种实施方式中，所述执行单元24包括：
第三执行子单元243，配置为执行usb hsic boot操作，并对所述usb hsic boot操作读取的数据进行安全检查；当安全检查通过后，正常执行读取的数据、启动操作；当安全检查未通过后，执行复位操作。
在一种实施方式中，所述执行单元24包括：
第四执行子单元244，配置为执行sdio slave boot操作，并对所述sdio slave boot操作读取的数据进行安全检查；当安全检查通过后，正常执行读取的数据、启动操作；当安全检查未通过后，执行复位操作。
在一种实施方式中，所述执行单元24包括：
第五执行子单元245，配置为基于emmc boot启动boot操作，读取配 置字段信息；基于所述配置字段信息，执行字段信息检查；当检查通过后，执行emmc boot操作，并对所述emmc boot操作读取的数据进行安全检查；当安全检查通过后，正常执行读取的数据、启动操作；当安全检查未通过后，执行usb device boot操作。
在一种实施方式中，所述执行单元24包括：
第六执行子单元246，配置为从emmc中读取配置字段信息，获取usb超时时间值；执行usb device boot操作，并对所述usb device boot操作读取的数据进行安全检查；当安全检查通过后，正常执行读取的数据、启动操作；当安全检查未通过后，执行emmc boot操作。
在一种实施方式中，所述执行单元24包括：
第七执行子单元247，配置为从spinandflash中读取配置字段信息；基于所述配置字段信息，执行字段信息检查；当检查通过后，执行spinandflash boot操作，并对所述spinandflash boot操作读取的数据进行安全检查；当安全检查通过后，正常执行读取的数据、启动操作；当安全检查通过后，执行usb device boot操作。
在一种实施方式中，所述执行单元24包括：
第八执行子单元248，配置为从spinandflash中读取配置字段信息，获取usb超时时间值；执行usb device boot操作，并对所述usb device boot操作读取的数据进行安全检查；当安全检查通过后，正常执行读取的数据、启动操作；当安全检查未通过后，执行spinandflash boot过程。
在一种实施方式中，所述执行单元24包括：
第九执行子单元249，配置为基于uart boot启动boot操作。
下面结合具体应用场景对本发明实施例的技术方案再做详细描述。
图3是本发明实施例的nandflash boot启动流程图，包括：
步骤301：配置nandflash需要的系统时钟等配置。
步骤302：配置nandflash控制器，并使能nandflash。
步骤303：bootrom模块根据引脚确定nandflash位宽和页大小以及页地址周期数。
步骤304：用解析的数据位宽和页大小配置nandflash控制。
步骤306：读nandflash的代码数据到IRAM。
步骤307：跳转到IRAM中执行。
图4是本发明实施例的usb device boot启动的流程图，包括：
步骤401：配置usb需要的锁相环(PLL，Phase Lock Loop)以及分频寄存器。
步骤402：配置使能usb模块。
步骤403：检测usb插入时间内是否有usb连接的reset命令。收到说明有usb连接，超时则认为无usb连接(如果无连接跳转到emmc boot)。
步骤404：开始usb枚举过程(usb host和device按照协议的同步过程)。
步骤405：在usb枚举时间内枚举成功(如果超时(host端没有设备驱动)，跳转到emmc boot)。
步骤406：在usb同步时间内等待同步字符，超时退出usb device boot，开始emmc boot。
步骤407：收到同步字符，等待配置寄存器标志字符，后面为配置数据。
步骤408：第一个数据是寄存器地址。
步骤409：第二个数据是配置数据。
步骤410：当收到寄存器地址为0时退出寄存器配置。
步骤411：等待下载数据标志字符，后面为下载数据。
步骤412：第一个为下载地址。
步骤413：第二个数据为下载数据长度。
步骤414：接收下载数据直到达到数据长度。
步骤415：可以连续多次下载数据执行9-12步的下载过程。
步骤416：如果收到执行同步字符，后面为执行地址。
步骤417：把收到执行地址赋给Image_addr，并跳转到Image_addr执行。
图5是本发明实施例的emmc boot启动流程图，包括：
步骤501：配置emmc需要的系统时钟等配置。
步骤502：配置emmc控制器，初始化emmc驱动程序。
步骤503：读emmc设备寄存器参数，使emmc控制器参数和emmc设备参数相互匹配。
步骤504：根据Loaded_size配置需要从emmc加载的数据大小(Loaded_size根据不同的场景有不同的值，需要提前根据场景计算出loaded_size值)。
步骤505：发送多块读命令从main area加载Loaded_size数据到指定地址。
步骤506：把指定地址值赋值给Image_addr，并跳转到Image_addr执行。
图6是本发明实施例的sdio slave boot启动流程图，包括：
步骤601：配置sdio slave需要的PLL以及分频寄存器。
步骤602：配置sdio slave模块，并使能sdio slave。
步骤603：检测是否有sdio slave连接。如果没有连接则继续等待。
步骤604：如果有连接开始sdio slave初始化过程，并根据sdio slave连接的sdio host的配置进行初始化配置。
步骤605：如果初始化失败则重新进入检查sdio连接流程。
步骤606：sdio slave接收代码数据到IRAM_RM_BASE地址。
步骤607：把IRAM_RM_BASE赋值给Image_addr，并跳转到Image_addr执行。
图7是本发明实施例的spinandflash boot启动流程图，包括：
步骤701：配置spifc需要的系统时钟等配置。
步骤702：配置spifc控制器。
步骤703：根据外部管脚确定spinandflash的page大小。
步骤704：根据页大小配置控制器。
步骤705：通过spifc接口读spinandflash数据到IRAM中。
步骤706：跳转到IRAM中执行。
图8是本发明实施例的usb hsic boot启动流程图，包括：
步骤801：配置usb hsic需要的PLL以及分频寄存器。
步骤802：配置usb hsic模块，并使能usb hsic。
步骤803：检测是否有usb hsic连接的reset命令。收到说明有usb连接，超时则认为无usb hsic连接则继续等待。
步骤804：开始usb hsic枚举过程(usb host和device按照协议的同步过程)。
步骤805：枚举失败则进入等待reset命令流程重新等待连接。
步骤806：如果成功则等待同步字符，如果没收到同步字则继续等待。
步骤807：收到同步字符，等待配置寄存器标志字符，后面为配置数据。
步骤808：第一数据是寄存器地址。
步骤809：第二数据是配置数据。
步骤810：当收到寄存器地址为0时退出寄存器配置。
步骤811：等待下载数据标志字符，后面为下载数据。
步骤812：第一个数据为下载地址。
步骤813：第二个数据为下载数据长度。
步骤814：接收下载数据直到达到数据byte数。
步骤815：可以连续多次下载数据执行步骤809-812的下载过程。
步骤816：如果收到执行同步字符，后面为执行地址。
步骤817：把收到执行地址付给Image_addr，并跳转到Image_addr执行。
图9是本发明实施例的bootrom的安全检查流程图，包括：
步骤901：读取efuse_bypass的pin对应的值，如果为0则开启安全boot功能，否则不开启安全功能，直接认为安全检查通过。
步骤902：读取安全boot使能值。
步骤903：根据安全boot使能值判断是否为安全boot,如果安全boot使能值不等于0xff则不开启安全boot。
步骤904：安全boot使能值等于0xff，读取安全boot的PUK HASH值。
步骤905：判断安全boot PUK的HASH值是否大于0，如果大于0启用安全boot，否则不启用安全boot。
步骤906：如果不开启安全boot，则直接跳转到安全检查通过流程。
步骤907：如果是安全boot，调用HASH模块计算PUK的HASH值，并与安全boot PUK的HASH值比较是否相等，如果不相等则说明不是有效的PUK。
步骤908：如果相等则调用HASH模块计算一级boot的HASH值HASH_X，否则安全检查失败，重新进入USB boot过程。
步骤909：读取一级boot的加密的HASH数据。
步骤910：调用rsa模块解密得到HASH_Y。
步骤911：比较HASH_X是否等于HASH_Y。
步骤912：如果相等则安全检查通过。
步骤913：如果不相等则安全检查失败。
本发明实施例所记载的技术方案之间，在不冲突的情况下，可以任意组合。下面列出几种组合方式。
第一种组合方式：图3，图10组合实现的功能
从Nandflash器件中读取二级boot代码后，采用图10描述的安全检查流程对二级boot代码进行加解密处理验证，验证通过后执行二级boot代码。
第二种组合方式：图3，图4，图9组合实现的功能
从Nandflash器件中读取二级boot代码后，读取配置字段信息，进行判断，如信息符合，采用图9描述的安全检查流程对二级boot代码进行加解密处理验证，验证通过后执行二级boot代码；如果信息不符合，通过usb slave device接口下载二级boot代码后，采用图9描述的安全检查流程对二级boot代码进行加解密处理验证，验证通过后执行下载的二级boot代码。
第三种组合方式：图4，图9组合实现的功能
通过usb slave device接口下载二级boot代码后，采用图9描述的安全检查流程对二级boot代码进行加解密处理验证，验证通过后执行二级boot代码。
第四种组合方式：图5，图9组合实现的功能
从emmc器件中读取二级boot代码后，采用图9描述的安全检查流程对二级boot代码进行加解密处理验证，验证通过后执行二级boot代码。
第五种组合方式：图6，图9组合实现的功能
通过sdio接口下载二级boot代码后，采用图9描述的安全检查流程对二级boot代码进行加解密处理验证，验证通过后执行二级boot代码。
第六种组合方式：图7，图9组合实现的功能
从spinandflash器件中读取二级boot代码后，采用图9描述的安全检查流程对二级boot代码进行加解密处理验证，验证通过后执行二级boot代码。
第七种组合方式：图8，图9组合实现的功能
通过usb hsic device接口下载二级boot代码后，采用图9描述的安全检查流程对二级boot代码进行加解密处理验证，验证通过后执行二级boot代码。
本发明实施例还记载了一种存储介质，所述存储介质中存储有计算机程序，所述计算机程序配置为执行前述各实施例的支持多安全引导boot的芯片启动方法。
在本发明所提供的几个实施例中，应该理解到，所揭露的方法和智能设备，可以通过其它的方式实现。以上所描述的设备实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，如：多个单元或组件可以结合，或可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的各组成部分相互之间的耦合、或直接耦合、或通信连接可以是通过一些接口，设备或单元的间接耦合或通信连接，可以是电性的、机械的或其它形式的。
上述作为分离部件说明的单元可以是、或也可以不是物理上分开的，作为单元显示的部件可以是、或也可以不是物理单元，即可以位于一个地方，也可以分布到多个网络单元上；可以根据实际的需要选择其中的部分或全部单元来实现本实施例方案的目的。
另外，在本发明各实施例中的各功能单元可以全部集成在一个第二处理单元中，也可以是各单元分别单独作为一个单元，也可以两个或两个以上单元集成在一个单元中；上述集成的单元既可以采用硬件的形式实现，也可以采用硬件加软件功能单元的形式实现。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。
工业实用性
本发明的芯片的bootrom支持多安全boot启动方式，且支持usb boot方式进行版本下载功能，达到了对应多种产品应用及软件版本烧录效果，节省了产品硬件成本及软件版本烧录成本，提高了不同产品使用率及软件版本生产/维修效率、提高了整个系统的安全性等。

Claims (21)

  1. 一种支持多安全引导boot的芯片启动方法，所述方法包括：
    系统初始化后，从寄存器中读取寄存器值；
    确定出与所述寄存器值对应的boot操作，并对配置字段信息进行检查；
    检查通过后，启动所述对应的boot操作读取数据，并对所述数据进行安全认证。
  2. 根据权利要求1所述的支持多安全引导boot的芯片启动方法，其中，所述确定出与所述寄存器值对应的boot操作，并对配置字段信息进行检查；检查通过后，启动所述对应的boot操作读取数据，并对所述数据进行安全认证，包括：
    基于闪存引导Nandflash boot启动boot操作，读取配置字段信息；
    基于所述配置字段信息，执行字段信息检查；
    当检查通过后，执行Nandflash boot操作，并对所述Nandflash boot操作读取的数据进行安全检查；
    当安全检查通过后，正常执行读取的数据、启动操作；当安全检查未通过后，执行通用串行总线设备引导usb device boot操作。
  3. 根据权利要求1所述的支持多安全引导boot的芯片启动方法，其中，所述确定出与所述寄存器值对应的boot操作，并对配置字段信息进行检查；检查通过后，启动所述对应的boot操作读取数据，并对所述数据进行安全认证，包括：
    从闪存Nandflash中读取配置字段信息，获取通用串行总线usb超时时间值；执行usb device boot操作，并对所述usb device boot操作读取的数据进行安全检查；
    当安全检查通过后，正常执行读取的数据、启动操作；当安全检查未通过后，执行Nandflash boot操作。
  4. 根据权利要求1所述的支持多安全引导boot的芯片启动方法，其中，所述确定出与所述寄存器值对应的boot操作，并对配置字段信息进行检查；检查通过后，启动所述对应的boot操作读取数据，并对所述数据进行安全认证，包括：
    执行通用串行总线高速集成电路引导usb hsic boot操作，并对所述usb hsic boot操作读取的数据进行安全检查；
    当安全检查通过后，正常执行读取的数据、启动操作；当安全检查未通过后，执行复位操作。
  5. 根据权利要求1所述的支持多安全引导boot的芯片启动方法，其中，所述确定出与所述寄存器值对应的boot操作，并对配置字段信息进行检查；检查通过后，启动所述对应的boot操作读取数据，并对所述数据进行安全认证，包括：
    执行同步动态输入输出引导sdio slave boot操作，并对所述sdio slave boot操作读取的数据进行安全检查；
    当安全检查通过后，正常执行读取的数据、启动操作；当安全检查未通过后，执行复位操作。
  6. 根据权利要求1所述的支持多安全引导boot的芯片启动方法，其中，所述确定出与所述寄存器值对应的boot操作，并对配置字段信息进行检查；检查通过后，启动所述对应的boot操作读取数据，并对所述数据进行安全认证，包括：
    基于嵌入式多媒体卡引导emmc boot启动boot操作，读取配置字段信息；
    基于所述配置字段信息，执行字段信息检查；
    当检查通过后，执行emmc boot操作，并对所述emmc boot操作读取的数据进行安全检查；
    当安全检查通过后，正常执行读取的数据、启动操作；当安全检查未通过后，执行usb device boot操作。
  7. 根据权利要求1所述的支持多安全引导boot的芯片启动方法，其中，所述确定出与所述寄存器值对应的boot操作，并对配置字段信息进行检查；检查通过后，启动所述对应的boot操作读取数据，并对所述数据进行安全认证，包括：
    从emmc中读取配置字段信息，获取usb超时时间值；执行usb device boot操作，并对所述usb device boot操作读取的数据进行安全检查；
    当安全检查通过后，正常执行读取的数据、启动操作；当安全检查未通过后，执行emmc boot操作。
  8. 根据权利要求1所述的支持多安全引导boot的芯片启动方法，其中，所述确定出与所述寄存器值对应的boot操作，并对配置字段信息进行检查；检查通过后，启动所述对应的boot操作读取数据，并对所述数据进行安全认证，包括：
    从串行外设接口闪存spinandflash中读取配置字段信息；
    基于所述配置字段信息，执行字段信息检查；
    当检查通过后，执行spinandflash boot操作，并对所述spinandflash boot操作读取的数据进行安全检查；
    当安全检查通过后，正常执行读取的数据、启动操作；当安全检查通过后，执行usb device boot操作。
  9. 根据权利要求1所述的支持多安全引导boot的芯片启动方法，其中，所述确定出与所述寄存器值对应的boot操作，并对配置字段信息进行检查；检查通过后，启动所述对应的boot操作读取数据，并对所述数据进行安全认证，包括：
    从spinandflash中读取配置字段信息，获取usb超时时间值；
    执行usb device boot操作，并对所述usb device boot操作读取的数据进行安全检查；
    当安全检查通过后，正常执行读取的数据、启动操作；当安全检查未通过后，执行spinandflash boot过程。
  10. 根据权利要求1所述的支持多安全引导boot的芯片启动方法，其中，所述确定出与所述寄存器值对应的boot操作，并对配置字段信息进行检查；检查通过后，启动所述对应的boot操作读取数据，并对所述数据进行安全认证，包括：
    基于通用同步/异步收发传输器引导uart boot启动boot操作。
  11. 一种支持多安全boot的芯片，所述芯片包括：
    第一读取单元，配置为当系统初始化后，从寄存器中读取寄存器值；
    认证单元，配置为确定出与述寄存器对应的boot操作，并对配置字段信息进行检查；
    第二读取单元，配置为当检查通过后，启动所述对应的boot操作读取数据；
    执行单元，配置为对所述数据进行安全认证。
  12. 根据权利要求11所述的支持多安全boot的芯片，其中，所述执行单元，包括：
    第一执行子单元，配置为基于Nandflash boot启动boot操作，读取配置字段信息；基于所述配置字段信息，执行字段信息检查；当检查通过后，执行Nandflash boot操作，并对所述Nandflash boot操作读取的数据进行安全检查；当安全检查通过后，正常执行读取的数据、启动操作；当安全检查未通过后，执行usb device boot操作。
  13. 根据权利要求11所述的支持多安全boot的芯片，其中，所述执行单元包括：
    第二执行子单元，配置为从Nandflash中读取配置字段信息，获取usb超时时间值；执行usb device boot操作，并对所述usb device boot操作读取的数据进行安全检查；当安全检查通过后，正常执行读取的数据、启动操作；当安全检查未通过后，执行Nandflash boot操作。
  14. 根据权利要求11所述的支持多安全boot的芯片，其中，所述执行单元包括：
    第三执行子单元，配置为执行usb hsic boot操作，并对所述usb hsic boot操作读取的数据进行安全检查；当安全检查通过后，正常执行读取的数据、启动操作；当安全检查未通过后，执行复位操作。
  15. 根据权利要求11所述的支持多安全boot的芯片，其中，所述执行单元包括：
    第四执行子单元，配置为执行sdio slave boot操作，并对所述sdio slave boot操作读取的数据进行安全检查；当安全检查通过后，正常执行读取的数据、启动操作；当安全检查未通过后，执行复位操作。
  16. 根据权利要求11所述的支持多安全boot的芯片，其中，所述执行单元包括：
    第五执行子单元，配置为基于emmc boot启动boot操作，读取配置字段信息；基于所述配置字段信息，执行字段信息检查；当检查通过后，执行emmc boot操作，并对所述emmc boot操作读取的数据进行安全检查；当安全检查通过后，正常执行读取的数据、启动操作；当安全检查未通过后，执行usb device boot操作。
  17. 根据权利要求11所述的支持多安全boot的芯片，其中，所述执行单元包括：
    第六执行子单元，配置为从emmc中读取配置字段信息，获取usb超时时间值；执行usb device boot操作，并对所述usb device boot操作读取的数 据进行安全检查；当安全检查通过后，正常执行读取的数据、启动操作；当安全检查未通过后，执行emmc boot操作。
  18. 根据权利要求11所述的支持多安全boot的芯片，其中，所述执行单元包括：
    第七执行子单元，配置为从spinandflash中读取配置字段信息；基于所述配置字段信息，执行字段信息检查；当检查通过后，执行spinandflash boot操作，并对所述spinandflash boot操作读取的数据进行安全检查；当安全检查通过后，正常执行读取的数据、启动操作；当安全检查通过后，执行usb device boot操作。
  19. 根据权利要求11所述的支持多安全boot的芯片，其中，所述执行单元包括：
    第八执行子单元，配置为从spinandflash中读取配置字段信息，获取usb超时时间值；执行usb device boot操作，并对所述usb device boot操作读取的数据进行安全检查；当安全检查通过后，正常执行读取的数据、启动操作；当安全检查未通过后，执行spinandflash boot过程。
  20. 根据权利要求11所述的支持多安全boot的芯片，其中，所述执行单元包括：
    第九执行子单元，配置为基于uart boot启动boot操作。
  21. 一种存储介质，所述存储介质中存储有计算机程序，所述计算机程序配置为执行权利要求1至10任一项所述的支持多安全引导boot的芯片启动方法。
PCT/CN2016/096743 2015-12-21 2016-08-25 一种支持多安全引导的芯片及其启动方法、存储介质 WO2017107528A1 (zh)

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