WO2017098581A1

WO2017098581A1 - Storage device and data error correction method

Info

Publication number: WO2017098581A1
Application number: PCT/JP2015/084406
Authority: WO
Inventors: 顕義橋本; 森野　東海; 水島　永雅
Original assignee: 株式会社日立製作所
Priority date: 2015-12-08
Filing date: 2015-12-08
Publication date: 2017-06-15

Abstract

Provided is a storage device, comprising a non-volatile memory, a rank modulation circuit, an error checking and correction (ECC) coding circuit, a memory control circuit, an ECC decoding circuit, and a rank demodulation circuit. The rank modulation circuit rank modulates inputted data so as to generate modulated data. The ECC coding circuit generates redundant data based on error correction coding from the modulated data, and rank modulates the redundant data so as to generate modulated redundant data. The memory control circuit carries out writing and reading upon the non-volatile memory of a set of the modulated data and the modulated redundant data. The ECC decoding circuit rank demodulates the modulated redundant data from among the set of the modulated data and modulated redundant data which has been read from the non-volatile memory so as to generate the redundant data, and carries out error correction of the modulated data using the redundant data. The rank demodulation circuit rank demodulates the modulated data whereupon the error correction has been carried out.

Description

Storage device and data error correction method

The present invention relates to a technique for error correction of data stored in a storage device.

In recent years, NAND-type flash memory (hereinafter referred to as flash memory) has been drastically improved in recording density and is being used as a secondary storage device in computers. Flash memory is non-volatile, and its access latency is very short compared to HDD (Hard Disk Drive). However, the flash memory has the following drawbacks.

(1) There is a writing life. Whenever data is written, the recording element (hereinafter referred to as cell) is damaged, and if the data is written more than a certain number of times, the cell cannot hold the data.
(2) Data cannot be changed. In order to change the data, it is necessary to perform an operation of damaging the cell called erasure.
(3) The error probability of data is higher than that of Dynamic Random Access Memory (DRAM).

Such defects are caused by the recording principle of flash memory. The flash memory records information by storing electrons in a minute floating gate (= cell) surrounded by a silicon oxide film. That is, a state where electrons are accumulated is interpreted as “1”, and a state where electrons are not accumulated is interpreted as “0”. A silicon oxide film is an insulator, and serves as a kind of quantum mechanical potential wall in order to prevent the transmission of electrons. The “height” of this potential wall is said to be about 1 eV. When writing “1” to the cell, a voltage of about several volts is applied to the cell. Then, the electrons can obtain energy of about several eV and overcome the potential wall. Electrons that cross the potential barrier enter the cell. When a sufficient amount of electrons enter the cell, the voltage is restored. Then, the electrons are blocked by the potential wall and confined in the cell. Based on such a principle, the flash memory operates as a nonvolatile storage medium that can retain information even when the power is turned off.

In order to simplify the circuit, when removing the accumulated electrons from the cell, a voltage of “−10V” is applied to many cells at once. As a result, the cell information is erased. Since this erasing operation takes time, the flash memory control software does not directly change the data to be changed in the data change process, writes new data to an empty cell, and writes old data. Invalidate the stored cell. Such a memory having a large overhead difference between writing and erasing data is referred to as a write asymmetric memory (hereinafter referred to as WAM).

Since electrons can enter the cell across the wall of the silicon oxide film of several eV, the electrons constituting the crystal of the silicon oxide film can similarly gain energy and jump out of the crystal and enter the cell. it can. The part where the electrons constituting the crystal of the silicon oxide film jump out in this way is called a lattice defect or a hole. The hole behaves like a positively charged electron, so it attracts the electron. When there are many such holes, electrons in the cell move from hole to hole in the silicon oxide film and jump out of the cell. If the amount of leakage of electrons increases, information cannot be recorded. This is the reason why the flash memory has a long life. Further, since erasing applies a higher voltage to the cell than writing, the deterioration of the silicon oxide film further proceeds. This is one of the reasons why writing and erasing are asymmetric.

Furthermore, as quantum mechanics teaches, there is a tunnel effect in which electrons can pass through walls with a higher potential than their energy with a certain probability. As the miniaturization of the flash memory proceeds, the silicon oxide film surrounding the flash memory cell becomes thinner and can be transmitted by the tunnel effect. Therefore, electrons existing in the cell leak out of the cell. As described above, errors occur in the written data due to the lattice defects and the tunnel effect of the silicon oxide film. The error probability is very high compared to DRAM. For this reason, it is necessary to correct an error using a data protection mechanism called an error correcting code (ECC). The error correction code will be described later.

A technology called “multi-value” is known which further increases the recording density of flash memory. In the above binarization, information is recorded at two levels, “0” where electrons are accumulated and “1” where electrons are not accumulated. In multi-value processing, the amount of accumulated electrons is divided into four levels, and 2-bit information is recorded in one cell. Such a flash memory that records four values is referred to as a multi-level cell (hereinafter referred to as MLC) flash memory. In contrast, a flash memory that records one bit per cell is referred to as a single level cell (hereinafter SLC) flash memory. This multi-level processing has further progressed, and a triple level cell (hereinafter referred to as TLC) flash memory has emerged that divides the amount of accumulated electrons into 8 levels and stores 3-bit information in one cell. Compared to the two levels of the SLC flash memory, the difference in the amount of electrons between the levels of the four-level MLC flash memory and the eight-level TLC flash memory is small. Therefore, in the case of multi-value, only a small number of electrons leak from the cell, and the information is changed to another information. Therefore, the MLC and TLC flash memory has a higher data error probability than the SLC flash memory.

US Pat. No. 8,245,094

As the flash memory becomes more multi-valued, the data error probability increases. By the way, Patent Document 1 discloses a rank modulation technique. However, since the value after rank modulation is a digital quantity, soft decoding that corrects the analog quantity cannot be applied. Also, since the digital amount has a shorter code length than the analog amount, the error correction capability of the value after rank modulation is lower than the error correction capability of the analog amount.

Therefore, an object of the present invention is to improve the error correction capability of data in a storage device including rank modulation.

A storage device according to an embodiment includes a nonvolatile memory, an error checking and correcting (ECC) encoding circuit, a memory control circuit, an ECC decoding circuit, and a rank demodulation circuit. The rank modulation circuit rank-modulates input data to generate modulation data. The ECC encoding circuit generates redundant data based on the error correction code from the modulated data, and rank-modulates the redundant data to generate modulated redundant data. The memory control circuit writes and reads a set of modulated data and modulated redundant data with respect to the nonvolatile memory. The ECC decoding circuit rank-demodulates the modulated redundant data from the set of modulated data and modulated redundant data read from the nonvolatile memory to generate redundant data, and uses the redundant data to correct the error of the modulated data I do. The rank demodulating circuit rank-demodulates the modulated data subjected to error correction.

According to the present invention, the error correction capability of data in a storage device including rank modulation can be improved.

The structural example of the memory | storage device which concerns on an Example is shown. It is a figure which shows the state of a cell. It is a figure for demonstrating matching with the state of a cell, and a numerical value. It is a flowchart which shows the example of a state transition process. An example of a finite state transition diagram is shown. It is a figure for demonstrating quantization. It is a figure for demonstrating the correction capability of a LDPC code. The structural example of the conventional memory | storage device is shown. It is a figure which shows the state of a cell. 6 is a flowchart illustrating an example of a data writing process according to the first embodiment. 3 is a flowchart illustrating an example of a data read process according to the first embodiment. 12 is a flowchart illustrating an example of a data writing process according to the second embodiment. 12 is a flowchart illustrating an example of a data read process according to the second embodiment.

Hereinafter, the rank modulation technique will be described with reference to the drawings. The flash memory is assumed to be multi-valued (4, 8, 16 levels,...).

FIG. 2 shows the states of cell 1 (2002), cell 2 (2003), cell 3 (2004), and cell 4 (2005).

One set (2001) includes cell 1 (2002), cell 2 (2003), cell 3 (2004), and cell 4 (2005). One cylindrical shape in FIG. 2 indicates that one level of electrons has accumulated in the cell. Accordingly, in FIG. 2, electrons for three levels are accumulated in the cell 1, electrons for two levels are accumulated in the cell 2, electrons for one level are accumulated in the cell 3, and electrons in the cell 4 are accumulated. Indicates that does not accumulate. The numerical value “1” is associated with this state set (2001).

When it was desired to write another numerical value from this state, conventionally, it was necessary to perform erasure that caused a large damage to the cell. However, rank modulation does not require erasure. By simply injecting two levels of electrons into the cell 2 of FIG. 2, it can be rewritten to other data. A state set (2006) indicates a state after the rewriting. If another numerical value can be assigned to the state set (2006), the data can be rewritten without performing erasure that causes large damage to the flash memory. Therefore, the lifetime of the flash memory can be extended.

FIG. 3 is a diagram for explaining the correspondence between cell states and numerical values.

In FIG. 3, the number of the cell with the most charge is written in the leftmost column 3001. Next, write the number of the cell where the electric charge is accumulated to the right of the number written earlier. By repeating this process, a string of numbers “1234” is created. In short, cell numbers are written in descending order for the amount of electrons. Next, when electrons for two levels are injected into the cell 2 (2003), the order is changed. In the column 3002, a string of numbers “2134” is written. If a numerical value a is assigned to the state “1234” and a numerical value b is assigned to the state “2134”, a numerical value “4! = 24” can be stored at the maximum. If the upper limit for storing electrons is sufficiently large, the data can be rewritten by simply injecting electrons from an arbitrary numerical value to another numerical value without erasing. As described above, rank modulation is expected to reduce the number of erasures and to rewrite data only by applying a write pulse, thereby extending the life of the flash memory. Then, by injecting electrons into the cell, the order of the cells is changed, which is called permutation in algebraic terms. Hereinafter, the replacement will be described.

A set of finite numbers

And Then, consider a state in which elements of _Xn are arranged in ascending order. This mapping for rearranging the order is called permutation. If one of the permutations is σ, various permutations are possible, so permutations also form a set. This, written as _{S n.} Any sigma, relative Tau∈S _n, is the composite mapping tau · sigma, since it is not subjected twice a substituent, which is also one of the substituents, the S _n original. Mathematically speaking

It is. clearly,

It is. This is called bond law. A mapping that does not change the order of _Xn may also be considered a replacement. Here, it is written as “e”. Clearly, for any σ∈S _n

It is. Such an "e" that the unity of the S _n. Furthermore, the operation of undoing the replacement performed once is also the replacement. Thus, for any Shiguma∈S _n, exist sigma ^-1 ∈S _n,

Is established. Such σ ⁻¹ is called an inverse element of σ. Thus, in the set _{S n,} (1) holds the binding law, there are (2) unity, there are (3) inverse. Such a set is generally called a group. That is, the set of substitutions _Sn is a group. The group _{S n} permutation group is called the (Permutation Group), the properties have been investigated in the past.

Here, an expression (Representation) of a general group G including a replacement group will be described. Hereinafter, the group operation symbol “•” is omitted. The expression of the group G is a mapping D from the group G to a reversible N × N matrix set GL (N) that satisfies the following properties. For any g ₁ , g ₂ εG, D (g ₁ g ₂ ) = D (g ₁ ) D (g ₂ ) holds. In other words, the expression can be said to be a homomorphism from the group G to the matrix set GL (N). The matrix D (g) is referred to as an expression matrix of “g”. As described above, there exists an inverse element g ⁻¹ for any gεG. Therefore, D (g ⁻¹ ) = D ⁻¹ (g). For this reason, GL (N) must be a reversible set of matrices. Further, when the size of the matrix is N, it is called N-dimensional representation.

Now consider the representation of a permutation group. Vertical column of numbers

To line up with. Then the permutation matrix is

It consists of 24 pieces. It matches the number of substitutions “4! = 24”. The unit element “e” of “Equation 24” has a unit matrix.

Note that is supported. Furthermore, since these are 4 × 4 matrices, they are four-dimensional representations. Such an expression that replaces the positions of elements is called a regular expression.

By injecting electrons into the cell in this way, it was found that this changed the state of the set of cells and this was mathematically replaced. However, in order to extend the life of the flash memory, the following conditions are desirable. .
(First condition) The amount of electrons in any cell is increased uniformly.
(Second condition) It is possible to transition to all states by replacement.

The first condition is that if electrons are injected only into a specific cell, the upper limit of the amount of electrons that can be injected immediately is reached and erasure is required, so it is desirable to avoid it.

The second condition is that it is desirable to maximize the amount of information stored in a set of cells. That is, an algorithm that cannot make a transition to a specific state cannot assign a numerical value to that state, and the amount of information that can be stored decreases.

FIG. 4 is a flowchart showing an example of state transition processing that satisfies the first and second conditions.

Step 4001: The controller of the flash memory starts processing.
Step 4002: The controller determines whether or not the cell 1 is the head (the largest amount of electrons). If cell 1 is at the top (YES), go to step 4003; otherwise (NO) go to step 4004.
Step 4003: The controller determines whether or not the amount of electrons in the cell 2 is minimum. If the amount of electrons in cell 2 is the minimum (YES), the controller proceeds to step 4004, otherwise proceeds to step 4005.
Step 4004: The controller injects electrons into the cell with the least amount of electrons to maximize the amount of electrons. Then, this process ends.
Step 4005: The controller injects electrons into the cell with the second largest amount of electrons to maximize the amount of electrons. Then, this process ends.

FIG. 5 shows a finite state transition diagram of 4 cells obtained as a result of injecting electrons according to the process of FIG.

The numbers in the box in Fig. 5 indicate cell number columns. Cell numbers are listed from left to right in descending order of the amount of electrons. Since there are “4! = 24” boxes in FIG. 5, the process of FIG. 4 satisfies the above second condition. Further, since the state transition diagram of FIG. 5 is a one-stroke drawing, the process of FIG. 4 uniformly injects electrons into any cell. That is, the process of FIG. 4 satisfies the first condition.

The example of FIG. 5 shows that it is possible to start from the state “1234” and return to the state “1234” again through all the states once. Its mathematical counterpart is the primitive n-th root of 1 (primitive n-th root). ^Let ω be a non-one root of the equation x ⁿ −1 = 0. Multiply 1 by ω to get ω. However, ω ≠ 1. Further, ωω = ω ² ≠ ω. When this is repeated, ω ⁿ⁻¹ ω = ω ⁿ = 1 and the value returns to 1. In this way, it is possible to assign ω ^k (k = 0, 1,..., 23) to each state in FIG. Also referred to as cyclic permutation replacement to cycle as this has become subgroup of permutation group S _n. Since ω is a scalar and considered as a 1 × 1 matrix, ω is a one-dimensional representation of a cyclic permutation group.

As described above, the flash memory has a problem that an error occurs in the data stored in the flash memory. Therefore, an error correction coding technique for correcting an error is used. When receiving the data, the encoding circuit (Encoder) generates redundant data based on a predetermined calculation rule, adds the redundant data to the data, and writes the data in the flash memory. On the other hand, the decoding circuit (Decoder) reads the data and the redundant data, estimates the correct data from the redundant data and the above calculation rule, and corrects the error.

There are two types of error correction codes. One is an algebraic error correction code, which includes a BCH (Bose-Chauduri-Hocquenhem) code, a Reed-Solomon code, and an algebraic geometric code (Algebric Geometric Code). In general, these codes are codes that specify a wrong bit or symbol (a set of bits) in data and correct it to a correct value by a decoding circuit solving an algebraic equation. Refer to

Non-Patent Documents

2 and 3 for details. The other is a code that corrects an error according to probability, and there is a low density parity check code (Low-Density Parity Check Code, hereinafter referred to as LDPC code). See Non-Patent Document 2 for the low-density parity check code.

By the way, when reading data from the flash memory, in FIG. 2, it was explained that the data can be obtained as a discrete amount of electrons. However, in practice, the amount of electrons in the flash memory cell is not a discrete amount but a continuous amount. The input / output circuit in the flash memory quantizes the amount of electrons in the flash memory cell and outputs it as a discrete amount.

FIG. 6 is a diagram for explaining quantization.

FIG. 6 shows the amount of electrons (6001, 6002, 6003, 6004) of the cell. The input / output circuit in the flash memory has threshold values (6005, 6006, 6007, 6008). If the amount of electrons is less than the threshold value (6005), the amount of electrons is zero, the amount of electrons is equal to or greater than the threshold value (6005), and the threshold value (6006). ) Is determined to be 1 level of electron content. The same applies to the threshold values (6007) and (6008). By such an operation of the input / output circuit, a continuous electron quantity (6001, 6002, 6003, 6004) is converted into a discrete digital quantity (6009, 6010, 6011, 6012).

Typically, the LDPC code correction capability is higher when the input is an analog amount than when the input is a digital amount. This will be briefly described with reference to FIG.

FIG. 7 is a diagram for explaining the correction capability of the LDPC code.

Since the amount of electrons (7001) of the cell 1 is slightly below the threshold (6008), it is quantized to level 3. Since the amount of electrons (7002) in the cell 2 is significantly higher than the threshold (6008), it is quantized to level 4. However, according to the principle of the LDPC code, the electron amount (7001) of the cell 1 is slightly smaller than the threshold value (6008), so it is determined that there is a high possibility that it is actually level 4, and is corrected to level 4. Then, the amount of electrons (7002) in the cell 2 is much higher than the threshold value, so there is little possibility of an error, so it is left as it is. However, such a determination cannot be made with the input after quantization. Therefore, the correction capability of the LDPC code is higher when the input is an analog amount than when the input is a digital amount.

Correcting the input of the analog quantity is called soft decoding (soft-decode). Non-Patent Document 4 describes an example of performing error correction of data in a flash memory by narrowing the quantization threshold (6005, 6006, 6007, 6008) to be close to analog input. When the LDPC code is applied to error correction of data in the flash memory, soft decoding is necessary. Non-Patent Document 1 describes an example in which an LDPC code is applied to a system in which data is written in a flash memory by rank modulation.

FIG. 8 shows a configuration example of a conventional storage device 1011.

8 includes a nonvolatile memory (8001) and a memory controller (8002) for controlling the nonvolatile memory (8001). The memory controller (8002) includes an ECC encoding circuit (8003), a rank modulation circuit (8004), a rank demodulation circuit (8005), and an ECC decoding circuit (8006).

The ECC encoding circuit (8003) generates redundant data from the input data and transfers the input data and the redundant data together as a code word to the rank modulation circuit (8004).

The rank modulation circuit (8004) converts the above code word into an electron quantity level, and the nonvolatile memory control circuit (8005) changes the electron quantity of the cells of the nonvolatile memory (8001).

When the memory controller (8002) reads data from the nonvolatile memory (flash memory) (8001), the nonvolatile memory control circuit (8005) reads the amount of electrons in the nonvolatile memory (flash memory) (8001) and performs rank demodulation. The circuit (8006) converts the amount of electrons into a numerical value as described above and transfers it to the ECC decoding circuit (8007).

The ECC decoding circuit (8007) corrects an error in the obtained numerical sequence according to a predetermined algorithm.

However, since this method cannot perform soft decoding, there is a problem that the correction capability of the LDPC code is greatly reduced. This is because the ECC decoding circuit (8006) receives only the numerical value after rank demodulation, and therefore cannot obtain an analog quantity and must perform decoding (correction) from only the digital quantity, so that so-called soft decoding cannot be performed. Because.

Furthermore, there is a problem when the ECC is not an LDPC code but an algebraic ECC such as a Reed-Solomon code. Hereinafter, a description will be given with reference to FIG.

In FIG. 9, the amount of electrons (9001) in cell 1 is 3 levels, the amount of electrons in cell 2 (9002) is 4 levels, the amount of electrons in cell 3 (9003) is 1 level, and the amount of electrons in cell 4 (9004) is 0. Examples of levels are shown.

With Reed-Solomon code, the amount of electrons in each cell can be encoded as one symbol. That is, the sequence “3410” is encoded. When this is rank-modulated, it is simply a numerical value “2”. That is, this numerical value “2” is encoded. Typically, the longer the code length, the higher the correction capability. Therefore, as shown in this example, when the code length becomes ¼ due to rank modulation, the correction capability decreases. Non-Patent Document 5 describes a method of encoding before rank modulation and correcting after rank modulation.

That is, if rank modulation is performed, only digital information can be obtained, so that soft decoding cannot be performed and the code length is shortened, resulting in a decrease in correction capability. Hereinafter, examples for solving the problem will be described.

FIG. 1 shows a configuration example of the storage device (1001).

The storage device (1001) includes a nonvolatile memory (1002) and a memory controller (1003). The non-volatile memory (1002) may be a WAM using a flash memory as an example. The memory controller (1003) includes a rank modulation circuit (1004), an ECC encoding circuit (1005), a nonvolatile memory control circuit (1007), an ECC decoding circuit (1008), and a rank demodulation circuit (1010).

The ECC encoding circuit (1005) includes a redundant part rank modulation circuit (1006). The ECC demodulation circuit (1008) includes a redundant part rank demodulation circuit (1009). The memory controller also has a data path (1012) that connects these circuits. This is because it is necessary to know the amount of electrons in the previous state when performing rank modulation.

The maximum value of the amount of electrons in the nonvolatile memory (1002) is assumed to be q. When writing data to the nonvolatile memory (1002), the rank modulation circuit (1004) receives and modulates the data. At this time, the data is converted into a string of numbers d ₁ d ₂ ... D _k by the rank modulation circuit (1004). d _i represents the electron content level of each cell.

The rank modulation circuit (1004) passes this numeric string to the ECC encoding circuit (1005). In the present embodiment, a 1-symbol log ₂ q-bit q-element LDPC code is employed as the ECC. The ECC encoding circuit (1005) multiplies d ₁ d ₂ ... D _k by a generation matrix (not shown) to generate redundant data. However, the redundant data cannot be written in the nonvolatile memory as it is. This is because rank modulation is not performed. Therefore, the redundant part rank modulation circuit (1006) rank-modulates the redundant data to generate the sequence r ₁ r ₂ ... R _N−k . This rank-modulated redundant data may be referred to as modulated redundant data. Thereafter, the ECC encoding circuit (1005) transfers the codewords d ₁ d ₂ ... D _k r ₁ r ₂ ... R _N−k to the nonvolatile memory control circuit (1007).

The nonvolatile memory control circuit (1007) that has received the code word injects electrons into each cell. Typically, for cell 1, to inject electrons to the level d _1. For cell 2, to inject electrons to a level d _2. The same applies hereinafter.

Next, the operation when the memory controller (1003) reads data from the nonvolatile memory (1002) will be described.

A nonvolatile memory control circuit (1007) in the memory controller (1003) reads the amount of electrons in a read target cell (not shown) in the nonvolatile memory (1002). This will _be the _{_{y 1 y 2 ... y k y}} 'k + 1 ... y' N. y ₁ , y ₂ ,..., y _k , y ′ _{k + 1} ,..., y ′ _N are analog quantities. However, it cannot be corrected as it is. This is because y ′ _{k + 1} , y ′ _{k + 2} ,..., Y ′ _N are not redundant data itself but rank-modulated values. Therefore, the nonvolatile memory control circuit (1007) transfers the read amount of electrons (= data) to the ECC decoding circuit (1008).

Rank demodulation circuit in the ECC decoding circuit (1008) (1009) _{_{is, y 1, y 2, ...}} , y k, y 'k + 1, ..., y' ranks demodulated in _{_N,} _{y k + 1 y k + 2} ... y n Convert. ECC decoding circuit (1009), the column _y 1 _y 2 _... of values obtained in this way to correct the _{_{y k y k + 1 ... y}} n. Then, the rank demodulation circuit (1010) demodulates the corrected data, and transfers it to the host device (not shown) via the interface (1011) with the host device.

Next, the operation of the ECC decoding circuit will be described.

In this embodiment, since one symbol of the code word takes a q value, it is decoded (corrected) by a q-ary LDPC code (q-ary LDPC Code).

^Let q = 2 ^p , and the parity check matrix be an m × n matrix H = (h _ij ). Here, i = {1, 2,..., M} and j = {1, 2,. Furthermore, l = {0,1,2, ..., p}, a = {0,1, ω, ω 2, ..., ω q-2} to. Where ω is the primitive q-1 power root of 1. In this embodiment, a systematic code obtained by adding a redundant part to input data is employed.

When decoding an LDPC code, it is necessary to assume a communication channel. q original target communication channel (q-ary Symmetric Channel) and white Gaussian noise communication channel (Additive White Gaussian Noise Channel, hereinafter referred to as AWGN communication channel).

In the LDPC code, it is assumed that the probability of erroneous data on each communication path is known in advance. In order to emphasize this meaning, the above probability is referred to as a priori probability (a priori probability). The formula for prior probabilities depends on the channel.

Among the received data y, y ₁ , y ₂ ,..., Y _k are analog quantities because they are the amount of electrons in the cells of the nonvolatile memory (1002). In the present embodiment, it is assumed that the communication channels y ₁ , y ₂ ,..., Y _k are AWGN communication channels that are typical analog communication channels. Of course, the error characteristics of the nonvolatile memory (1002) are not necessarily the same as those of the AWGN communication path. In that case, it is necessary to experimentally measure the characteristics of the nonvolatile memory (1002), create a suitable communication channel model, and apply it to decoding. Of the received data, y _{k + 1} , y _{k + 2} ,..., Y _n are digital quantities, and a q-ary symmetric channel is assumed.

In the present embodiment, a logarithmic domain Sum-Product method (Logarithmic Domain Sum-Product Algorithm) is used in a decoding method of an LDPC code. In the log domain Sum-Product method, a priori log likelihood ratio (a priori log-likelihood ratio) is used based on prior probabilities. Of the received words, the prior log likelihood ratio for y ₁ , y ₂ ,..., Y _k is

Given in. F ^a _j represents a prior log likelihood ratio in which the j-th symbol takes the value a. y ^l _j indicates the value of the l-th bit in the binary representation of the j-th received symbol. a _l indicates the value of the l-th bit of the binary representation of the symbol a. δ (x) is the Dirac delta function

It is. [sigma] is a scale indicating the probability of error in variance of the AWGN channel. _{_{y k + 1, y k +}} 2, ..., with respect to the _{y n,} suppose q-ary symmetric channel. If the error probability per bit is p,

So the prior log likelihood ratio is

It is.

The q-element logarithm domain Sum-Product method may consist of the following steps.

(1) Initialization Initialize a post-logarithmic likelihood ratio Q ^a _ij and R ^a _ij . The following processing is executed for each i, j, a.

In this way, there are two cases because the data portion is an analog amount and the redundant portion is a digital amount.

(2) Column processing This is the same as the column processing of a normal q-element LDPC code.

(3) Row processing The same as row processing of a normal q-element LDPC code.

(4) Calculation of temporary estimated word The calculation is the same as the calculation of the temporary estimated word of a normal q-element LDPC code.

(5) Parity check This is the same as the parity check calculation of a normal q-element LDPC code.

If the memory controller (1001) has not been corrected even after repeating a predetermined number of times, it outputs a temporary estimated word and ends.

Thus, when correcting an error of rank-modulated WAM, an analog amount can be used for input, and therefore the LDPC code correction capability can be improved as compared with Non-Patent Document 1.

FIG. 10 is a flowchart illustrating an example of data write processing in the storage device (1001) according to the first embodiment.

Hereinafter, an example of a method of modulating a single digit value with 4 cells will be described.
Step 10001: Start processing.
Step 10002: The storage device (1001) receives data (10011) from the host device.
Step 10003: The rank modulation circuit (1004) measures the amount of electrons in the write target cell of the nonvolatile memory (1002). This is because, in rank modulation, it is necessary to measure the amount of electrons in the write target cell once in order to determine which cell the electron is injected into.
Step 10004: The rank modulation circuit (1004) determines the amount of electrons in each cell according to a predetermined rule. At this time, the information is information on the amount of electrons in four cells (10012). Then, the rank modulation circuit (1004) transfers the information on the amount of electrons (10012) to the ECC encoding circuit (1005).
Step 10005: The ECC encoding circuit (1005) generates redundant data (10013) based on the information on the amount of electrons (10012).
Step 10006: The redundant part rank modulation circuit (1006) measures the amount of electrons in the write target cell of the nonvolatile memory (1002). This is because, in rank modulation, it is necessary to measure the amount of electrons in the write target cell once in order to determine which cell the electron is injected into.
Step 10007: The redundant part rank modulation circuit (1006) determines the amount of electrons of each cell in accordance with a predetermined rule. At this time, the information is information on the amount of electrons in four cells (10014).
Step 10008: The ECC encoding circuit (1005) transfers the information on the amount of electrons (10013, 10014) to the nonvolatile memory control circuit (1007).
Step 10009: The nonvolatile memory control circuit (1007) injects electrons into the cell to be written in accordance with the information on the amount of electrons (10013, 10014).
Step 10010: The process ends.

Through the above processing, data is written in the nonvolatile memory 1002 of the storage device (1001).

FIG. 11 is a flowchart illustrating an example of data read processing in the storage device (1001) according to the first embodiment.

Step 11001: The process is started.
Step 11002: The nonvolatile memory control circuit (1007) measures the amount of electrons in the read target cell. FIG. 11 shows that in this measurement result, the amount of electrons in the ECC data portion is 2.8, 4.2, 1.4, 1.1 (11011), and the amount of electrons in the redundant portion is 2, 3, 4, 1 An example of (11012) is shown. Here, the amount of electrons (11011) in the data portion is an analog amount, and the amount of electrons (11012) in the redundant portion is a digital amount. The nonvolatile memory control circuit (1007) transfers these pieces of information to the ECC decoding circuit (1008).
Step 11003: The redundant part rank demodulating circuit (1009) built in the ECC decoding circuit (1008) rank-demodulates the information (11012) of the electron quantity of the redundant part. FIG. 11 shows an example in which a numerical value “2” (11013) is obtained by this processing.
Step 11004: The ECC decoding circuit (1008) corrects the errors in the information (11011) and (11013) on the amount of electrons according to the processing of the ECC decoding circuit described above. Since the information on the amount of electrons (11011) is an analog amount, the ECC decoding circuit (1008) of this embodiment has a higher correction capability than that of Non-Patent Document 1.
Step 11005: The ECC decoding circuit (1008) determines whether or not the correction is successful. If the correction fails, the ECC decoding circuit (1008) reports the fact to the upper apparatus (step 11006). When the correction is successful, it is assumed that the ECC decoding circuit (1009) has obtained information on the amount of electrons (11014).
Step 11007: The ECC decoding circuit (1008) transfers the information on the amount of electrons (11014) to the rank demodulation circuit (1010).
Step 11008: The rank demodulation circuit (1010) converts the information on the amount of electrons (11014) into a numerical value. FIG. 11 shows an example in which a numerical value “3” (11015) is obtained by this processing.
Step 11009: The rank demodulation circuit (1010) transfers the numerical value “3” (11015) obtained by the conversion to the higher-level device.
Step 11010: The process ends.

Through the above processing, data is read from the nonvolatile memory 1002 of the storage device (1001).

In Non-Patent Document 5, a Reed-Solomon code is constructed on the premise of a configuration similar to that in FIG. 8, and its correction capability is discussed. For example, assume that rank modulation is performed so that one cell represents one symbol. At this time, the minimum distance (minimum distance) of the Reed-Solomon code of code length n symbols, dimension (= data size) k symbols is d _min = n− (k−1). On the other hand, in this embodiment, since a Reed-Solomon code can be configured with one symbol per cell, the minimum distance is d _min = nl− (kl−1). That is, the minimum distance of the present embodiment is about 1 times larger than that of Non-Patent Document 5.

The relationship between the correction symbol number t and the minimum distance is given by t = (d _min −1) / 2. If the minimum distance increases by a factor of l, the correction capability increases by a factor of l / 2. Thus, it can be seen that the correction capability is improved by this embodiment.

FIG. 12 is a flowchart illustrating an example of data write processing in the storage device (1001) according to the second embodiment.

Hereinafter, an example of a method of modulating a single digit value with 4 cells will be described.
Step 12001: Start processing.
Step 12002: The storage device (1001) receives data (10011) from the host device.
Step 12003: The rank modulation circuit (1004) measures the amount of electrons in the write target cell of the nonvolatile memory (1002). This is because in rank modulation, it is necessary to measure the amount of electrons in the writing target cell once in order to determine which cell the electron is injected into.
Step 12004: The rank modulation circuit (1004) determines the amount of electrons in each cell according to a predetermined rule. At this time, the information is information on the amount of electrons in the four cells (12012). Then, the rank modulation circuit (1004) transfers the information on the amount of electrons (12012) to the ECC encoding circuit (1005).
Step 12005: The ECC encoding circuit (1005) generates a redundant part (12013) from the information (12012) of the electron quantity.
Step 12006: The redundant part rank modulation circuit (1006) measures the amount of electrons in the write target cell of the nonvolatile memory (1002). This is because, in rank modulation, it is necessary to measure the amount of electrons in the write target cell once in order to determine which cell the electron is injected into.
Step 12007: The redundant part rank modulation circuit (1006) determines the amount of electrons of each cell according to a predetermined rule. At this time, the information is information on the amount of electrons in four cells (12014).
Step 12008: The ECC encoding circuit (1005) transfers the information on the amount of electrons (12013, 12014) to the nonvolatile memory control circuit (1007).
Step 12009: The nonvolatile memory control circuit (1007) injects electrons into the cell to be written in accordance with the information on the amount of electrons (12013, 12014).
Step 12010: The process ends.

Through the above processing, data is written in the storage device (1001).

FIG. 13 is a flowchart illustrating an example of data read processing in the storage device (1001) according to the second embodiment.

Step 13001: The process is started.
Step 13002: The nonvolatile memory control circuit (1007) measures the amount of electrons in the read target cell. FIG. 13 shows an example in which the amount of electrons in the ECC data portion is 3, 4, 1, 1 (13011) and the amount of electrons in the redundant portion is 2, 3, 4, 1 (13012) in this measurement result. . The amount of electrons in the data portion (13011) is a digital amount, and the amount of electrons in the redundant portion (13012) is also a digital amount. The nonvolatile memory control circuit (1007) transfers these pieces of information to the ECC decoding circuit (1008).
Step 13003: The redundant part rank demodulating circuit (1009) built in the ECC decoding circuit (1008) rank-demodulates the information (13012) of the electron quantity of the data in the redundant part. FIG. 11 shows an example in which a numerical value “2” (13013) is obtained by this processing.
Step 13004: The ECC decoding circuit (1008) corrects the error in the information on the amount of electrons (13011, 13013) according to the processing of the ECC decoding circuit described above. Since the information (13011) of the amount of electrons is a numerical value of 8 digits, the code length becomes long, and the ECC decoding circuit (1008) of this embodiment has a higher correction capability than that of Non-Patent Document 1.
Step 13005: The ECC decoding circuit (1008) determines whether or not the correction is successful. When the correction fails, the ECC decoding circuit (1008) reports the fact to the upper apparatus (step 13006). When the correction is successful, it is assumed that the ECC decoding circuit (1008) has obtained information on the amount of electrons (13014).
Step 13007: The ECC decoding circuit (1008) transfers the information on the amount of electrons (13014) to the rank demodulation circuit (1010).
Step 13008: The rank demodulation circuit (1010) converts the information on the amount of electrons (13014) into a numerical value. FIG. 11 shows an example in which a numerical value “3” (13015) is obtained by this processing.
Step 13009: The rank demodulation circuit (1010) transfers the numerical value “3” (13015) obtained by the conversion to the host device.
Step 13010: The process ends.

According to the present embodiment, since the code word can be composed of a 4-digit numerical value from the one-digit numerical value in Non-Patent Document 1, the code length becomes long and the correction capability is improved.

The above-described embodiments are examples for explaining the present invention, and are not intended to limit the scope of the present invention only to the embodiments. Those skilled in the art can implement the present invention in various other modes without departing from the gist of the present invention. For example, in the above-described embodiments, the circuit is the execution subject, but software (program) may be the execution subject.

1001: Storage device 1002: Non-volatile memory 1003: Non-volatile memory controller 1004: Rank modulation circuit 1005: ECC encoding circuit 1006: Redundant part rank modulation circuit 1007: Non-volatile memory control circuit 1008: ECC decoding circuit 1009: Redundant part Rank demodulation circuit 1010: Rank demodulation circuit

Claims

Non-volatile memory;
A rank modulation circuit that rank-modulates input data to generate modulation data;
An error checking and correcting (ECC) encoding circuit that generates redundant data based on an error correction code from the modulated data and rank-modulates the redundant data to generate modulated redundant data;
A memory control circuit for writing and reading the set of modulated data and modulated redundant data to the nonvolatile memory;
ECC decoding that performs rank demodulation on the modulated redundant data to generate redundant data from the set of modulated data and modulated redundant data read from the nonvolatile memory, and performs error correction of the modulated data using the redundant data Circuit,
A rank demodulating circuit that rank-demodulates the modulated data subjected to error correction;
A storage device.
The storage device according to claim 1, wherein the nonvolatile memory is a flash memory.
The storage device according to claim 2, wherein the error correction code is configured with the amount of electrons in one cell of the flash memory as one symbol.
The storage device according to claim 3, wherein the error correction code is a low density parity check code.
The set of modulated data and modulated redundant data read from the nonvolatile memory is an analog amount related to the amount of electrons in the flash memory cell,
The storage device according to claim 4, wherein the ECC decoding circuit performs error correction using the analog amount.
The storage device according to claim 3, wherein the error correction code is a Reed-Solomon code.
The storage device according to claim 3, wherein the error correction code is a multiple Bose-Chaudhuri-Hocquenhem (BCH) code.
The storage device according to claim 3, wherein the error correction code is an algebraic geometric code.
An error correction method for data in a storage device, comprising:
The storage device includes a controller and a nonvolatile memory,
The controller is
The input data is rank-modulated to generate modulation data,
Generate redundant data based on an error correction code from the modulated data, rank-modulate the redundant data to generate modulated redundant data,
Writing and reading the set of modulated data and modulated redundant data to the non-volatile memory;
Of the set of modulated data and modulated redundant data read from the non-volatile memory, the modulated redundant data is rank demodulated to generate redundant data, and the redundant data is used to perform error correction of the modulated data,
A data error correction method for rank demodulating modulated data subjected to error correction.