US20130121084A1 - Method and apparatus to provide data including hard bit data and soft bit data to a rank modulation decoder - Google Patents
Method and apparatus to provide data including hard bit data and soft bit data to a rank modulation decoder Download PDFInfo
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- US20130121084A1 US20130121084A1 US13/293,988 US201113293988A US2013121084A1 US 20130121084 A1 US20130121084 A1 US 20130121084A1 US 201113293988 A US201113293988 A US 201113293988A US 2013121084 A1 US2013121084 A1 US 2013121084A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5642—Sensing or reading circuits; Data output circuits
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1072—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in multilevel memories
Definitions
- the present disclosure is generally related to decoding data at a rank modulation decoder.
- Non-volatile memory devices such as universal serial bus (USB) flash memory devices or removable storage cards, have allowed for increased portability of data and software applications. Flash memory devices can enhance data storage density by storing multiple bits in each flash memory cell. For example, Multi-Level Cell (MLC) flash memory devices provide increased storage density by storing 3 bits per cell, 4 bits per cell, or more.
- MLC Multi-Level Cell
- Storing multiple bits of information in a single flash memory cell typically includes mapping sequences of bits to states of the flash memory cell. For example, a first sequence of bits “110” may correspond to a first state of a flash memory cell and a second sequence of bits “010” may correspond to a second state of the flash memory cell. After determining that a sequence of bits is to be stored into a particular flash memory cell, the flash memory cell may be programmed to a state that corresponds to the sequence of bits.
- multiple bits of information in a single flash memory cell may be stored as relative voltage levels of multiple cells of the memory rather than as absolute voltage levels in each cell.
- each storage element of the memory may have a threshold voltage corresponding to a state of the storage element.
- a group of storage elements may store data based on relative threshold voltages of the storage elements in the group. Data may be read from the group of storage elements by ranking the storage elements according to threshold voltages and mapping the ranking to a corresponding data value at a rank modulation decoder.
- data may be read from the memory cells by sensing the programming states of the memory cells.
- sensed programming states can sometimes vary from the written programming states due to one or more factors.
- Error correction decoding can be used to correct data errors resulting from sensed programming states that do not match written programming states.
- Improved error correction capability of a rank modulation decoder may be achieved by decoding data using soft bits and hard bits.
- soft bits and hard bits may be used as an input to a rank modulation decoder to enhance error correction capability in a multi-level-cell (MLC) memory system, as compared to a decoding scheme that is based on using hard bits only as an input to the rank modulation decoder.
- MLC multi-level-cell
- FIG. 1 is a block diagram of a first illustrative embodiment of a system that provides data including hard bit data and soft bit data to a rank modulation decoder;
- FIG. 2 is a diagram illustrating use of soft bits and hard bits in rank modulation decoding
- FIG. 3 is a general diagram illustrating a particular embodiment of a sensing scheme and includes a graphical depiction of cell state distributions and threshold read voltages for hard bits and additional sensed (soft) bits provided to a rank modulation decoder;
- FIG. 4 is a general diagram graphically illustrating states of a three-cell rank modulation group
- FIG. 5 is a general diagram illustrating an example of hard bit thresholds in a three-cell group using rank modulation decoding
- FIG. 6 is a general diagram illustrating an example of soft bit thresholds in a three-cell group using rank modulation decoding
- FIG. 7 is a general diagram illustrating an example of soft bit thresholds in a four cell group using rank modulation decoding
- FIG. 8 is a general diagram illustrating an example of one soft bit threshold per hard bit region in a two cell group using rank modulation decoding.
- FIG. 9 is a flow diagram illustrating a particular embodiment of a method of providing data including hard bit data and soft bit data to a rank modulation decoder.
- Systems and methods of providing data including hard bit data and soft bit data to a rank modulation decoder include a capability to provide data including hard bit data and soft bit data read from a memory of a data storage device to the rank modulation decoder.
- the system 100 includes a data storage device 102 coupled to a host device 130 .
- the data storage device 102 includes a memory 104 coupled to a controller 106 via a bus 150 .
- the memory 104 may be a non-volatile memory of a flash device, such as a NAND flash device, a NOR flash device, or any other type of flash device.
- the memory 104 includes a memory portion 110 and read thresholds 120 .
- the memory portion 110 includes a plurality of storage elements, such as memory cells of a multi-level cell (MLC) memory.
- MLC multi-level cell
- a group of storage elements 112 may include multiple MLC storage elements, such as representative storage elements 113 , 115 , 117 of a word line 119 of a flash memory device.
- Each storage element 113 - 117 may have a threshold voltage corresponding to a state of the storage element (e.g., a predefined state corresponding to a particular range of threshold voltage values).
- the group of storage elements 112 may store data based on relative threshold voltages (or states) of the storage elements 113 - 117 .
- the states of the storage elements 113 - 117 may be read by comparing the threshold voltages to one or more of the read thresholds 120 .
- the read thresholds 120 include a hard bits threshold 122 and a soft bits threshold 124 .
- the hard bits threshold 122 may include threshold read voltages for hard bits (e.g., voltages AR, BR, . . . GR in FIG. 3 ) and the soft bits threshold 124 may include threshold read voltages for additional sensed bits or soft bits (e.g., voltages AR-V 1 , AR+V 2 , AR-V 3 , AR+V 4 , in FIG. 3 ).
- the storage elements 113 - 117 may each be programmed to one of multiple predefined states. Each of the predefined states may be mapped to a particular bit value (e.g.
- a soft bit can be used by an error correction coding (ECC) engine 108 within a rank modulation decoder 116 in conjunction with one or more hard bits to enhance a reading operation by indicating a relative reliability of the hard bits read from the memory 104 .
- ECC error correction coding
- the controller 106 includes the ECC engine 108 and the rank modulation decoder 116 .
- the ECC engine 108 may be configured to detect errors in the read data corresponding to the storage elements 112 .
- An output of the rank modulation decoder 116 may be provided to the host device 130 while the data storage device 102 is operatively coupled to the host device 130 .
- a threshold voltage within a defined range of values may indicate a particular state that is represented by a bit pattern.
- the hard bit values and the soft bit values of the bit patterns of each storage element of the group of storage elements 112 may correspond to the representation of the rank modulation codeword read from the MLC memory.
- the host device 130 may instruct the controller 106 to retrieve data corresponding to the group of storage elements 112 , such as the storage elements 113 - 117 , from the memory 104 .
- the memory 104 may be configured to read the representation of the rank modulation codeword 140 from the group of storage elements 112 by comparing cell threshold voltages in the memory portion 110 to the hard bit thresholds 122 to generate the hard bit values 152 and to the soft bit thresholds 124 to generate the soft bit values 154 .
- each storage element 113 - 117 may have a threshold voltage corresponding to a state of the storage element.
- the rank modulation decoder 116 may be configured to map the hard bit values 152 to an ECC codeword that is decodable by the ECC engine 108 .
- the ECC engine may be a Reed Solomon ECC engine, a Bose-Chaudhuri-Hocquenghem (BCH) ECC engine, a low-density parity-check ECC engine, one or more other ECC engines, or any combination thereof.
- the rank modulation decoder 116 may convert the hard bit values 152 to an ECC codeword that is input to the ECC engine 108 .
- the soft bit values 154 may provide reliability information about the states read from the storage elements 113 - 117 in the memory portion 110 .
- the reliability information may include, for each storage element 113 - 117 that is read, a value that indicates a likelihood that the hard bit values for that storage element are correct.
- the soft bit values 154 may be used by the rank modulation decoder 116 to obtain a reliability indicator for each bit of the ECC codeword provided to the ECC engine 108 , such as a log-likelihood ratio (LLR).
- LLR log-likelihood ratio
- the rank modulation decoder 116 may be configured to use the reliability information to guide error correction processing at the ECC engine 108 to generate decoded data bits based on the received hard bit values 152 and the soft bit values 154 .
- the ECC engine 108 may perform probabilistic decoding by iteratively updating bit estimates and LLRs of the bit estimates based on bit estimates and LLRs of the bit estimates of a prior iteration of a decoding process to converge to a most probable ECC codeword.
- the soft bit values 154 enable the rank modulation decoder 116 to establish initial reliability values (e.g., LLRs) that are more accurate than default LLRs that may be used by conventional decoders that use hard bits only. Using more accurate initial reliability values (e.g. LLRs based on the soft bit values 154 ) enables the rank modulation decoder 116 to converge more quickly and/or more accurately. As a result, decoding of a representation of an ECC codeword may be performed with reduced latency, with improved error correction capability, or a combination thereof.
- Table 1 illustrates a number of bits that can be stored in an M-cell unit.
- user data when writing information to a memory, user data may be mapped to one of the twenty four combinations by some predefined mapping, such as a Gray mapping, and the voltage cell may be programmed according to the predefined voltage rank among the four cells. For example, if the chosen rank combination is 3-4-1-2, the voltage may be programmed such that V 3 >V 4 >V 1 >V 2 .
- the relative voltages of the four cells may be sensed and a ranking may be determined.
- U 1 , U 2 , U 3 , and U 4 denote the sensed voltages of the cells 1 , 2 , 3 , and 4 , respectively, and if it is determined that U 3 >U 4 >U 1 >U 2 , then it may be determined that the 3-4-1-2 combination is correctly read among the twenty four possible combinations. If other ranks, such as 4-3-1-2 or 3-1-4-2 were read, a read error may be detected and handled using error correction coding. Either binary or non-binary error correction codes may be used.
- the memory 104 (shown with dashed lines) includes a table 210 , the first representative storage element 113 , and the second representative storage element 115 .
- the table 210 may include hard bit data and soft bit data, such as hard bits 260 and soft bits 262 , respectively, stored in latches or registers of the memory 104 .
- the hard bit data and the soft bit data indicates a threshold voltage range for each storage element, enabling determination of a relative voltage level (i.e., a ranking) of the storage elements that indicates stored information at the first storage element 113 and at the second storage element 115 .
- each of the storage elements 113 , 115 may have a corresponding threshold voltage.
- the first storage element 113 may have a first threshold voltage V 1 230 in a first voltage range VT 1 250 and the second storage element 115 may have a second threshold voltage V 2 232 in a second voltage range VT 2 252 .
- the first voltage range VT 1 250 may be from zero volts to two volts and the second voltage range VT 2 252 may also be from zero volts to two volts.
- the hard bits 260 may indicate results of comparing the threshold voltage of each particular cell (e.g., the first threshold voltage V 1 230 and the second threshold voltage V 2 232 ) to one or more hard bit thresholds. For example, data may be read from the first storage element 113 and from the second storage element 115 by comparing a threshold voltage of each storage elements to a first hard bit threshold or read voltage VR 1 242 and to a second hard bit threshold or read voltage VR 2 246 . As illustrated, the first hard bit read voltage VR 1 242 is less than the second hard bit read voltage VR 2 246 .
- the hard bits 260 (i.e., HB 1 , HB 2 ) having a value of “11” may correspond to a threshold voltage value greater than the second hard bit read voltage VR 2 246 .
- the hard bits 260 having a value of “10” may correspond to a threshold voltage value between the first hard bit read voltage VR 1 242 and the second hard bit read voltage VR 2 246 .
- the hard bits 260 having a value of “00” may correspond to a threshold voltage value less than the first hard bit read voltage VR 1 242 .
- the first threshold voltage V 1 230 is greater than the first hard bit read voltage VR 1 242 and less than the second hard bit read voltage VR 2
- the hard bits 260 having a value of “00” indicates that the second threshold voltage V 2 232 is less than the first hard bit read voltage VR 1 242 and less than the second hard bit read voltage VR 2 246 .
- the soft bits 262 may indicate results of comparing the threshold voltage of each particular cell (e.g., the first threshold voltage V 1 230 and the second threshold voltage V 2 232 ) to one or more soft bit thresholds. For example, the threshold voltage of the first storage element 113 and of the second storage element 115 may be compared to a first soft bit threshold or read voltage S 1 240 , a second soft bit threshold or read voltage S 2 244 , and a third soft bit threshold or read voltage S 3 248 . As illustrated, the first soft bit read voltage S 1 240 may be less than the second soft bit read voltage S 2 244 , and the second soft bit read voltage S 2 244 may be less than the third soft bit read voltage S 3 248 .
- first hard bit read voltage VR 1 242 may be less than the second soft bit read voltage S 2 244 and greater than the first soft bit read voltage S 1 240
- second hard bit read voltage VR 2 246 may be greater than the second soft bit read voltage S 2 244 and less than the third soft bit read voltage S 3 248
- a first difference between the first soft bit read voltage S 1 240 and the first hard bit read voltage VR 1 242 may be substantially equal to a second difference between the first hard bit read voltage VR 1 242 and the second soft bit read voltage S 2 244 .
- the soft bits 262 (i.e., SB 1 , SB 2 ) having a value of “11” may correspond to a threshold voltage value greater than the third soft bit read voltage S 3 248 .
- the soft bits 262 having a value of “10” may correspond to a threshold voltage value between the third soft bit read voltage S 3 248 and the second soft bit read voltage S 2 244 .
- the soft bits 262 having a value of “01” may correspond to a threshold voltage value between the second soft bit read voltage S 2 244 and the first soft bit read voltage S 1 240 .
- the soft bits 262 having a value of “00” may correspond to a threshold voltage value less than the first soft bit read voltage S 1 240 .
- the soft bits 262 for storage element 113 having a value of “10” indicates that the first threshold voltage V 1 230 has a value between the third soft bit read voltage S 3 248 and the second soft bit read voltage S 2 244 .
- the soft bits 262 for storage element 115 having a value of “01” indicates that the second threshold voltage V 2 232 has a value between the second soft bit read voltage S 2 244 and the first soft bit read voltage S 1 240 .
- the controller 106 (shown with dashed lines) includes the rank modulation decoder 116 that includes a mapper 220 , a reliability indicator 222 , and the error correction engine 108 .
- the controller 106 may be configured to provide data read from the memory 104 to the rank modulation decoder 116 .
- the data may include hard bit data, such as the hard bits 260 , and soft bit data, such as the soft bits 262 .
- the controller 106 may receive data from the table 210 and provide the HB 1 , HB 2 , SB 1 , and SB 2 values for each cell to the rank modulation decoder 116 .
- the mapper 220 may be configured to logically partition the data into groups of bits. Each group of bits may correspond to a group of cells in the memory 104 . For example, the first storage element 113 and the second storage element 115 may correspond to one group of bits.
- the mapper 220 may be further configured to rank cells of each particular group of cells according to cell threshold voltages. For example, the mapper 220 may compare the first threshold voltage V 1 230 and the second threshold voltage V 2 232 and generate a ranking based on the comparison. For example, if the first threshold voltage V 1 230 is greater than the second threshold voltage V 2 232 , a ranking of “1-2” may be generated by the mapper 220 . Similarly, if the second threshold voltage V 2 232 is greater than the first threshold voltage V 1 230 , a ranking of “2-1” may be generated by the mapper 220 .
- the mapper 220 may be further configured to map each group of bits to a data value according to the cell ranking of the group of cells corresponding to the group of bits. For example, the mapper 220 may generate a single bit symbol or data value (e.g., a “1” or a “0”) based on a comparison of the first threshold voltage V 1 230 and the second threshold voltage V 2 232 . If the first threshold voltage V 1 230 is greater than the second threshold voltage V 2 232 , a data value of “1” may be generated by the mapper 220 . If the second threshold voltage V 2 232 is greater than the first threshold voltage V 1 230 , a value of “0” may be generated by the mapper 220 .
- a single bit symbol or data value e.g., a “1” or a “0”
- more than two storage elements can correspond to the group of bits.
- four cells or storage elements may be used to represent the data.
- the mapper 220 may generate a multi-bit symbol or data value (e.g., a 5-bit data value of “11001”, “01100, etc.) based on a comparison of the threshold voltages of each cell.
- the mapper 220 may send the data values based on cell ranking to the ECC engine 108 as an ECC codeword 270 .
- the reliability indicator 222 may be configured to indicate a relative reliability of bit values in the ECC codeword 270 generated by the mapper 220 and may send relative reliability values to the ECC engine 108 as ECC soft bits 272 .
- the relative reliability may be based at least in part on a difference between the threshold voltages of the cells of each particular group as determined based on the soft bit thresholds S 1 -S 3 .
- the relative reliability may increase as a difference between cell threshold voltages increases. To illustrate, if the difference between the first threshold voltage V 1 230 and the second threshold voltage V 2 232 is large, the relative reliability of the data value generated by the mapper 220 may be higher than if the difference between the first threshold voltage V 1 230 and the second threshold voltage V 2 232 is small.
- a reliability indicator of “1” may indicate that the difference between the first threshold voltage V 1 230 and the second threshold voltage V 2 232 is large, and a reliability indicator of “0” may indicate that the difference between the first threshold voltage V 1 230 and the second threshold voltage V 2 232 is small.
- the reliability indicator 222 may be configured to determine whether the first threshold voltage V 1 230 and the second threshold voltage V 2 232 are in adjacent sub-regions. For example, the first hard bit read voltage VR 1 242 and the second hard bit read voltage VR 2 246 may divide the first voltage range VT 1 250 into three regions. The first soft bit read voltage S 1 240 , the second soft bit read voltage S 2 244 , and the third soft bit read voltage S 3 248 may divide each region into two sub-regions. Based on the hard bits 260 and the soft bits 262 , the reliability indicator 222 can determine which of the six sub-regions the first threshold voltage V 1 230 is in and which of the six sub-regions the second threshold voltage V 2 232 is in.
- a “0” may be output by the reliability indicator 222 .
- a “1” (or a larger number) may be output by the reliability indicator 222 .
- the controller 106 may be configured to initiate an ECC procedure on the ECC codeword 270 by providing the ECC codeword 270 and the ECC soft bits 272 to the ECC engine 108 .
- the ECC engine 108 may employ an ECC decoding scheme, such as a Reed Solomon ECC decoding scheme, a Bose-Chaudhuri-Hocquenghem (BCH) ECC decoding scheme, a low-density parity-check ECC decoding scheme, one or more other ECC decoding schemes, or any combination thereof.
- the ECC engine 108 may provide output data indicating that the ECC codeword 270 was correctly decoded.
- the controller 106 may be instructed by the host device (not shown) to retrieve data corresponding to the storage elements 113 , 115 from the memory 104 .
- the controller 106 may provide data including hard bit data, such as hard bits 260 (i.e., HB 1 , HB 2 ), and soft bit data, such as soft bits 262 (i.e., SB 1 , SB 2 ), to the rank modulation decoder 116 .
- the rank modulation decoder 116 may be configured to logically partition the data into groups of bits, where each group of bits may correspond to a group of cells in the memory 104 .
- the mapper 220 may compare the first threshold voltage V 1 230 and the second threshold voltage V 2 232 and generate a ranking based on the comparison.
- the rank modulation decoder 116 may be further configured to map each group of bits to a data value according to the cell ranking of the group of cells corresponding to the group of bits.
- the mapper 220 may generate a data value based on a comparison of the first threshold voltage V 1 230 and the second threshold voltage V 2 232 and may send the data value based on cell ranking to the ECC engine 108 as the ECC codeword 270 .
- a relative reliability of bit values in the ECC codeword 270 generated by the mapper 220 may be determined by the reliability indicator 222 and relative reliability values may be sent to the ECC engine 108 as the ECC soft bits 272 . For example, if the difference between the first threshold voltage V 1 230 and the second threshold voltage V 2 232 is large, the relative reliability of the data value generated by the mapper 220 may be higher than if the difference between the first threshold voltage V 1 230 and the second threshold voltage V 2 232 is small.
- the controller 106 may be configured to initiate an ECC procedure on the ECC codeword 270 by providing the ECC codeword 270 and the ECC soft bits 272 to the ECC engine 108 .
- the ECC engine 108 may provide output data indicating that the ECC codeword 270 was correctly decoded.
- FIG. 3 shows an embodiment 300 of a sensing scheme and includes a graphical depiction 302 of cell distributions for voltage regions (i.e. states) (Er, A, . . . G) of a storage element of a memory, such as a representative memory cell 310 , and threshold read voltages for hard bits (e.g., voltages AR, BR, . . . GR) and for additional sensed soft bits (e.g., voltages AR-V 1 , AR+V 2 , AR-V 3 , AR+V 4 , . . . ).
- voltage regions i.e. states
- a storage element of a memory such as a representative memory cell 310
- threshold read voltages for hard bits (e.g., voltages AR, BR, . . . GR) and for additional sensed soft bits (e.g., voltages AR-V 1 , AR+V 2 , AR-V 3 , AR+V 4 , . . .
- soft bits e.g., voltages AR-V 1 , AR+V 2 , AR-V 3 , AR+V 4 , . . .
- soft bits e.g., voltages AR-V 1 , AR+V 2 , AR-V 3 , AR+V 4 , . . .
- the hard bits 314 indicate which state (Er-G) the threshold voltage 312 is in, and the soft bits 316 indicate whether the threshold voltage 312 is within a center of the state's voltage range or near an edge of the state's voltage range (e.g., indicates a proximity to voltage CR).
- a first voltage difference (V 1 ) between a first soft bit threshold (e.g., CR-V 1 ) and a particular hard bit threshold (e.g., CR) is substantially equal to a second voltage difference (V 2 ) between the particular hard bit threshold (e.g., CR) and a second soft bit threshold (e.g., CR+V 2 ).
- a third voltage difference (V 3 ) between a third soft bit threshold and the particular hard bit threshold (CR) is substantially equal to a fourth voltage difference (V 4 ) between the particular hard bit threshold (CR) and a fourth soft bit threshold.
- the first voltage difference (V 1 ) is different than the third voltage difference (V 3 ).
- the threshold voltage 312 is between BR and CR, indicating that the cell 310 is in state “B”, corresponding to hard bits “100”.
- the threshold voltage 312 is also in a sub-region between CR-V 1 and CR, corresponding to a soft bit value of “001”.
- the controller 106 may provide the hard bits 314 and the soft bits 316 to an input of a rank modulation decoder 320 to obtain decoded data.
- the soft bits 316 may include reliability information about the hard bits read from the memory cell 310 .
- the rank modulation decoder 320 may be configured to use the soft bits 316 indicating a sub-region of the cell's state (i.e., the sub-region of the state “B” closest to the voltage CR) to guide error correction processing based on the received soft bits, such as by generating ECC soft bits to be input to an ECC decoder, such as the ECC soft bits 272 of FIG. 2 .
- FIG. 4 a general diagram graphically illustrating states of a three-cell rank modulation group is depicted and generally designated 400 .
- the states of the three-cell rank modulation group may correspond to states of a three-cell group including cell 1 , cell 2 , and cell 3 (e.g. the storage elements 113 , 115 , and 117 of FIG. 1 , respectively) where U 1 is a threshold voltage of cell 1 (e.g. the storage element 113 ), U 2 is a threshold voltage of cell 2 (e.g. the storage element 115 ), and U 3 is a threshold voltage of cell 3 (e.g. the storage element 117 ).
- Each region A-F corresponds to a different data value stored in the three-cell rank modulation group.
- region E corresponds to the state U 1 >U 3 >U 2 .
- a general diagram 500 illustrates an example of hard bit thresholds of the three-cell rank modulation group of FIG. 4 .
- An upper portion or top line 510 corresponds to a region where u 1 ⁇ u 2
- a lower portion or bottom line 520 corresponds to a region where u 1 >u 2 .
- the voltage measurements u 1 and u 2 may correspond to voltage thresholds that may be used to determine hard bit values.
- a threshold voltage (u 1 ) of cell 1 and a threshold voltage (u 2 ) of cell 2 may be measured (or otherwise determined).
- the threshold voltages u 1 and u 2 may be used as hard bit thresholds to compare to a threshold voltage (u 3 ) of cell 3 . If u 1 ⁇ u 2 and the threshold voltage of cell 3 is less than u 1 , then a hard bit may indicate that a measure point (e.g., a threshold voltage of cell 3 ) is within region A. If u 1 ⁇ u 2 and the threshold voltage of cell 3 is between u 1 and u 2 , then a hard bit may indicate that the measure point is within region B.
- a hard bit may indicate that the measure point is within region C.
- a hard bit may indicate that the measure point is within region D.
- a hard bit may indicate that the measure point is within region E.
- a hard bit may indicate that the measure point is within region F.
- a hard bit that corresponds to a hard bit threshold may only provide information as to which particular region among the six regions the measure point belongs to.
- FIG. 6 a general diagram illustrating an example of soft bit thresholds in a three-cell group in rank modulation decoding is depicted and generally designated 600 .
- the diagram 600 illustrates dividing each hard bit region of FIG. 5 (i.e., hard bit regions A, B, C, D, E, and F) into smaller sub-regions (i.e., sub-regions A 1 , A 2 , B 1 , B 2 , C 1 , C 2 , D 1 , D 2 , E 1 , E 2 , F 1 , F 2 ).
- soft bit thresholds denoteted by T 1 , T 2 , . . .
- FIG. 7 a general diagram illustrating an example of soft bit thresholds in a four cell group in rank modulation decoding is depicted and generally designated 700 .
- a top line 710 illustrates using hard bits only
- a middle line 720 illustrates the addition of one soft bit threshold per hard bit region
- a bottom line 730 illustrates the addition of two soft bit thresholds per hard bit region.
- top line 710 there are four regions shown in the top line 710 (i.e., using hard bits only), where each of the four regions has six possible combinations, for a total of twenty four possible combinations. Accordingly, five bits may be used to represent the twenty four combinations.
- middle line 720 i.e., adding one soft bit threshold per hard bit region of line 710
- each of the eight regions has six possible combinations, for a total of forty eight possible combinations. Accordingly, six bits may be used to represent the forty eight combinations.
- bottom line 730 i.e., adding two soft bit thresholds per hard bit region of line 710 ), where each of the twelve regions has six possible combinations, for a total of seventy two possible combinations.
- a voltage U 1 may be sensed in cell 1 and a voltage U 2 may be sensed in cell 2 .
- a transition probability matrix can be illustrated for a hard bit only case as follows:
- the overall noise variance is M times each cell's noise variance. That is, the M-cell noise sigma (i.e., standard deviation) will be ⁇ square root over (M) ⁇ times the noise sigma of one cell.
- the transition probability matrix for hard bits may be used to compare a cell information capacity using hard bits only to rank modulation cell information capacity using hard bits and soft bits, as explained with respect to FIG. 8 .
- a first soft bit threshold T 1 and a second soft bit threshold T 2 are illustrated defining sub-regions R 1 , R 2 , R 3 , and R 4 .
- a transition probability matrix may be determined
- Each memory cell such as the memory cell 310 of FIG. 3 , has a theoretical storage capacity to store an amount of information, referred to as an information capacity (C).
- the information capacity (C) is a function of probabilities that particular data values are stored to a cell and probabilities of errors occurring to the stored data values due to noise or other effects in the cell.
- a theoretical lower bound of a cell's information capacity occurs when all data values are equally probable to be stored in the cell (known as “information capacity with scrambler assumption”—data is assumed to be scrambled prior to storage and therefore all data values are equally probable).
- An information capacity (C) in bits/cell and a lower bound information capacity with scrambler assumption (C scramble ) may be calculated as follows:
- X is the original hard bits that were written in a writing operation
- R is a voltage region that is sensed during a read operation
- is the number of possible hard bits.
- 6) and R may be one of the 6 voltage regions.
- X) may be given as the transition probability matrix Q soft1 as illustrated above.
- Table 2 illustrates, for several values of cell error rate (CER) and voltage spacing (d) between program states of cells in a rank modulation scheme, examples of soft bit threshold shift (h) values, cell information capacity values, and cell lifetime capacity values.
- CER cell error rate
- d voltage spacing
- h soft bit threshold shift
- Table 2 provides examples for cells that can be programmed to a threshold voltage in a 2 volt (V) range from ⁇ 1V to 1V and having a 0.002% CER, a 0.2% CER, and a 1% CER in a conventional SLC scheme not using rank modulation (the CER corresponding to a noise standard deviation (sigma) of 0.2435, 0.3474, and 0.4299, respectively).
- Information capacity is provided for the cells using hard bits only and using one soft bit for comparison purposes.
- FIG. 9 depicts a flowchart that illustrates an embodiment of a method of providing data including hard bit data and soft bit data to a rank modulation decoder.
- the method 900 may be performed in a data storage device having a flash multi-level cell (MLC) memory.
- MLC flash multi-level cell
- the method 900 may be performed in the data storage device 102 of FIG. 1 .
- Hard bit data and soft bit data may be read from a flash memory, at 902 .
- the memory 104 may be configured to read the representation of the rank modulation codeword 140 from the group of storage elements 112 by comparing cell threshold voltages in the memory portion 110 to the hard bit thresholds 122 to generate the hard bit values 152 and to the soft bit thresholds 124 to generate the soft bit values 154 .
- Data including hard bit data (e.g. the hard bit values 152 of FIG. 1 ) and soft bit data (e.g. the soft bit values 154 of FIG. 1 ), may be provided to a rank modulation decoder, at 904 .
- the memory 104 may include read circuitry configured to compare cell threshold voltages to one or more hard bit thresholds to generate the hard bit values 152 and to one or more soft bit thresholds to generate the soft bit values 154 , latches configured to latch results of the comparisons, and a bus interface configured to provide the the hard bit values 152 and the soft bit values 154 to the rank modulation decoder 116 .
- the data may be read from multiple cells of a memory, such as the storage elements 113 - 117 of the memory 104 , where each particular cell of the multiple cells has a threshold voltage, and where the hard bit data includes hard bits that indicate results of comparing the threshold voltage of each particular cell to one or more hard bit thresholds and where the soft bit data includes soft bits that indicate results of comparing the threshold voltage of each particular cell to one or more soft bit thresholds.
- the first storage element 113 may have the first threshold voltage V 1 230 in the first voltage range VT 1 250 and the second storage element 115 may have the second threshold voltage V 2 232 in the second voltage range VT 2 252 .
- Data may be read from the first storage element 113 and from the second storage element 115 based on comparisons of threshold voltages of the first storage element 113 and the second storage element 115 to the first hard bit threshold VR 1 242 and to the second hard bit threshold VR 2 246 to generate the hard bits 260 .
- the hard bits 260 may indicate results of the comparisons of the threshold voltage of each particular cell (e.g., the first threshold voltage V 1 230 and the second threshold voltage V 2 232 ) and may indicate whether the first threshold voltage V 1 230 is greater than or less than the second threshold voltage V 2 232 .
- the hard bits 260 i.e., HB 1 , HB 2
- the hard bits 260 having a value of “11” may correspond to a threshold voltage value greater than the second hard bit read voltage VR 2 246 .
- the hard bits 260 having a value of “10” may correspond to a threshold voltage value between the first hard bit read voltage VR 1 242 and the second hard bit read voltage VR 2 246 .
- the hard bits 260 having a value of “00” may correspond to a threshold voltage value less than the first hard bit read voltage VR 1 242 .
- the soft bits may indicate results of comparing the threshold voltage of each particular cell (e.g., the first threshold voltage V 1 230 and the second threshold voltage V 2 232 ) to one or more soft bit thresholds (also referred to as soft bit read voltages) and may indicate whether the first threshold voltage V 1 230 is greater than or less than the first soft bit read voltage (e.g., threshold S 1 240 ).
- the threshold voltage of the first storage element 113 and of the second storage element 115 may be compared to the first soft bit read voltage or threshold S 1 240 , to the second soft bit read voltage or threshold S 2 244 , and to the third soft bit read voltage or threshold S 3 248 .
- the soft bits may indicate whether the first threshold voltage V 1 230 is greater than or less than the second soft bit read voltage S 2 244 , where the first soft bit read voltage S 1 240 is less than the second threshold voltage V 2 232 , and where the second soft bit read voltage S 2 244 is greater than the second threshold voltage V 2 232 .
- the method 900 may be performed on a multi-cell rank modulation group, such as a three-cell rank modulation group.
- the flash memory 104 may include a third cell (i.e., the storage element 117 ) having a third threshold voltage.
- the hard bit data may further indicate whether the third threshold voltage is in a first range of voltages that are less than the first threshold voltage V 1 230 and the second threshold voltage V 2 232 , in a second range of voltages that are between the first threshold voltage V 1 230 and the second threshold voltage V 2 232 , or in a third range of voltages that are greater than the first threshold voltage V 1 230 and the second threshold voltage V 2 232 .
- the soft bit data may indicate whether the third threshold voltage is in one or more sub-ranges of the first range of voltages, the second range of voltages, or the third range of voltages.
- the controller 106 may be configured to provide data read from the memory 104 to the rank modulation decoder 116 .
- the controller 106 may receive the data via a bus interface and may provide the received data to an input of the rank modulation decoder 116 .
- the data may include the hard bits 260 and the soft bits 262 .
- the rank modulation decoder 116 may be configured to logically partition the data into groups of bits, where each group of bits corresponds to a group of cells in the memory 104 , and may rank cells of each particular group of cells according to cell threshold voltages to produce a cell ranking of the particular group of cells.
- the mapper 220 may compare the first threshold voltage V 1 230 and the second threshold voltage V 2 232 and generate a ranking based on the comparison.
- the rank modulation decoder 116 may be configured to map each group of bits to a data value according to the cell ranking of the group of cells corresponding to the group of bits.
- the mapper 220 may generate a data value based on a comparison of the first threshold voltage V 1 230 and the second threshold voltage V 2 232 and may send the data value based on cell ranking to the ECC engine 108 as the ECC codeword 270 .
- error correction at the rank modulation decoder may be performed more quickly and/or accurately as compared to rank modulation decoding using hard bits only.
- cell information capacity may be increased by using rank modulation decoding using hard bits and soft bits as compared to rank modulation decoding using hard bits only.
- the rank modulation decoder 116 of FIG. 1 and FIG. 2 may represent physical components, such as controllers, processors, state machines, logic circuits, or other structures to logically partition the data into groups of bits, where each group of bits corresponds to a group of cells in a flash memory, to rank cells of each particular group of cells, and to map each group of bits to a data value according to the cell ranking of the group of cells corresponding to the group of bits.
- the rank modulation decoder 116 may be implemented using a microprocessor or microcontroller programmed to generate data from rank modulated data using soft bits.
- the controller 106 includes a processor executing instructions that are stored at the memory 104 .
- executable instructions that are executed by the processor may be stored at a separate memory location that is not part of the memory 104 , such as at a read-only memory (ROM) (not shown).
- ROM read-only memory
- the data storage device 102 includes a non-volatile memory, such as a Flash memory (e.g., NAND, NOR, Multi-Level Cell (MLC), Divided bit-line NOR (DINOR), AND, high capacitive coupling ratio (HiCR), asymmetrical contactless transistor (ACT), or other Flash memories), an erasable programmable read-only memory (EPROM), an electrically-erasable programmable read-only memory (EEPROM), a read-only memory (ROM), a one-time programmable memory (OTP), or any other type of memory.
- a Flash memory e.g., NAND, NOR, Multi-Level Cell (MLC), Divided bit-line NOR (DINOR), AND, high capacitive coupling ratio (HiCR), asymmetrical contactless transistor (ACT), or other Flash memories
- EPROM erasable programmable read-only memory
- EEPROM electrically-erasable programmable read-only memory
- ROM read-only memory
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Abstract
Description
- The present disclosure is generally related to decoding data at a rank modulation decoder.
- Non-volatile memory devices, such as universal serial bus (USB) flash memory devices or removable storage cards, have allowed for increased portability of data and software applications. Flash memory devices can enhance data storage density by storing multiple bits in each flash memory cell. For example, Multi-Level Cell (MLC) flash memory devices provide increased storage density by storing 3 bits per cell, 4 bits per cell, or more.
- Storing multiple bits of information in a single flash memory cell typically includes mapping sequences of bits to states of the flash memory cell. For example, a first sequence of bits “110” may correspond to a first state of a flash memory cell and a second sequence of bits “010” may correspond to a second state of the flash memory cell. After determining that a sequence of bits is to be stored into a particular flash memory cell, the flash memory cell may be programmed to a state that corresponds to the sequence of bits.
- Alternatively, multiple bits of information in a single flash memory cell may be stored as relative voltage levels of multiple cells of the memory rather than as absolute voltage levels in each cell. For example, each storage element of the memory may have a threshold voltage corresponding to a state of the storage element. A group of storage elements may store data based on relative threshold voltages of the storage elements in the group. Data may be read from the group of storage elements by ranking the storage elements according to threshold voltages and mapping the ranking to a corresponding data value at a rank modulation decoder.
- Once the memory cells in the memory device have been programmed, data may be read from the memory cells by sensing the programming states of the memory cells. However, sensed programming states can sometimes vary from the written programming states due to one or more factors. Error correction decoding can be used to correct data errors resulting from sensed programming states that do not match written programming states.
- Improved error correction capability of a rank modulation decoder may be achieved by decoding data using soft bits and hard bits. To illustrate, soft bits and hard bits may be used as an input to a rank modulation decoder to enhance error correction capability in a multi-level-cell (MLC) memory system, as compared to a decoding scheme that is based on using hard bits only as an input to the rank modulation decoder.
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FIG. 1 is a block diagram of a first illustrative embodiment of a system that provides data including hard bit data and soft bit data to a rank modulation decoder; -
FIG. 2 is a diagram illustrating use of soft bits and hard bits in rank modulation decoding; -
FIG. 3 is a general diagram illustrating a particular embodiment of a sensing scheme and includes a graphical depiction of cell state distributions and threshold read voltages for hard bits and additional sensed (soft) bits provided to a rank modulation decoder; -
FIG. 4 is a general diagram graphically illustrating states of a three-cell rank modulation group; -
FIG. 5 is a general diagram illustrating an example of hard bit thresholds in a three-cell group using rank modulation decoding; -
FIG. 6 is a general diagram illustrating an example of soft bit thresholds in a three-cell group using rank modulation decoding; -
FIG. 7 is a general diagram illustrating an example of soft bit thresholds in a four cell group using rank modulation decoding; -
FIG. 8 is a general diagram illustrating an example of one soft bit threshold per hard bit region in a two cell group using rank modulation decoding; and -
FIG. 9 is a flow diagram illustrating a particular embodiment of a method of providing data including hard bit data and soft bit data to a rank modulation decoder. - Decoding techniques may provide improved error correction as data storage device dimensions decrease and storage density increases. Using soft bits and hard bits as an input to a rank modulation decoder in multi-level-cell (MLC) memory systems can enhance error correction capability.
- Systems and methods of providing data including hard bit data and soft bit data to a rank modulation decoder include a capability to provide data including hard bit data and soft bit data read from a memory of a data storage device to the rank modulation decoder.
- Referring to
FIG. 1 , a particular illustrative embodiment of a system of providing data including hard bit data and soft bit data to a rank modulation decoder is depicted and generally designated 100. Thesystem 100 includes adata storage device 102 coupled to ahost device 130. Thedata storage device 102 includes amemory 104 coupled to acontroller 106 via a bus 150. - The
data storage device 102 may be a memory card, such as a Secure Digital SD® card, a microSD® card, a miniSD™ card (trademarks of SD-3C LLC, Wilmington, Del.), a MultiMediaCard™ (MMC™) card (trademark of JEDEC Solid State Technology Association, Arlington, Va.), or a CompactFlash® (CF) card (trademark of SanDisk Corporation, Milpitas, Calif.). As another example, thedata storage device 102 may be embedded memory in thehost device 130, such as eMMC® (trademark of JEDEC Solid State Technology Association, Arlington, Va.) memory and eSD memory, as illustrative examples. - The
memory 104 may be a non-volatile memory of a flash device, such as a NAND flash device, a NOR flash device, or any other type of flash device. Thememory 104 includes amemory portion 110 and readthresholds 120. Thememory portion 110 includes a plurality of storage elements, such as memory cells of a multi-level cell (MLC) memory. A group ofstorage elements 112 may include multiple MLC storage elements, such asrepresentative storage elements word line 119 of a flash memory device. Each storage element 113-117 may have a threshold voltage corresponding to a state of the storage element (e.g., a predefined state corresponding to a particular range of threshold voltage values). The group ofstorage elements 112 may store data based on relative threshold voltages (or states) of the storage elements 113-117. The states of the storage elements 113-117 may be read by comparing the threshold voltages to one or more of theread thresholds 120. - The
read thresholds 120 include ahard bits threshold 122 and asoft bits threshold 124. As described in further detail with respect toFIG. 3 , thehard bits threshold 122 may include threshold read voltages for hard bits (e.g., voltages AR, BR, . . . GR inFIG. 3 ) and thesoft bits threshold 124 may include threshold read voltages for additional sensed bits or soft bits (e.g., voltages AR-V1, AR+V2, AR-V3, AR+V4, inFIG. 3 ). To illustrate, the storage elements 113-117 may each be programmed to one of multiple predefined states. Each of the predefined states may be mapped to a particular bit value (e.g. a single bit value (“0” or “1”) or a multi-bit value, such as “101”). The bit value that corresponds to the determined MLC state is referred to as “hard bit(s)”. Additional information that can be used to indicate a reliability of the reading of the storage element is referred to as a “soft bit”. A soft bit can be used by an error correction coding (ECC)engine 108 within arank modulation decoder 116 in conjunction with one or more hard bits to enhance a reading operation by indicating a relative reliability of the hard bits read from thememory 104. - The
controller 106 includes theECC engine 108 and therank modulation decoder 116. TheECC engine 108 may be configured to detect errors in the read data corresponding to thestorage elements 112. An output of therank modulation decoder 116 may be provided to thehost device 130 while thedata storage device 102 is operatively coupled to thehost device 130. - To write data to the
memory 104, thecontroller 106 may provide arank modulation codeword 140 to thememory 104 via the bus 150. For example, the bus 150 may be a Secure Digital (SD) bus. Thememory 104 is configured to store the representation of therank modulation codeword 140 in thememory portion 110. Therank modulation codeword 140 may be based on a non-binary symbol, such as symbol indicating a ranking of cells in one or more groups of cells according to relative threshold voltages of the cells. A number of cells in each group may equal the size of the non-binary symbol. A ranking of cells in each group (i.e., a relative threshold voltage each cell is programmed to) indicates a value of the non-binary symbol. For example, a three-cell group may have six possible rankings and each possible ranking may correspond to a value of a non-binary symbol. For agroup including cell 1,cell 2, andcell 3, having threshold voltages V1, V2, and V3, respectively, values of the non-binary symbol can correspond to rankings of the cells according to: V1>V2>V3=000, V1>V3>V2=001, V2>V1>V3=010, V2>V3>V1=011, V3>V1>V2=100, and V3>V2>V1=101, as an illustrative, non-limiting example. - The
controller 106 may be configured to receive memory access requests from thehost device 130 and to process data read from thememory 104. Thecontroller 106 may be configured to receive hard bit values 152 and soft bit values 154 from thememory 104. For example, the hard bit values 152 and the soft bit values 154 may correspond to a representation of a rank modulation codeword read from thememory 104 and may include information about the representation of therank modulation codeword 140 stored in thememory portion 110. To illustrate, each of the storage elements 113-117 may be programmed to a particular state to have relative values of the threshold voltages of the storage elements 113-117 set to a particular ranking order. For example, a threshold voltage within a defined range of values may indicate a particular state that is represented by a bit pattern. The hard bit values and the soft bit values of the bit patterns of each storage element of the group ofstorage elements 112 may correspond to the representation of the rank modulation codeword read from the MLC memory. - The
host device 130 may be configured to provide data to be stored at thememory 104 or to request data to be read from thememory 104. For example, thehost device 130 may include a mobile telephone, a music or video player, a gaming console, an electronic book reader, a personal digital assistant (PDA), a computer, such as a laptop computer, a notebook computer, or a tablet, any other electronic device, or any combination thereof. - During operation, the
host device 130 may instruct thecontroller 106 to retrieve data corresponding to the group ofstorage elements 112, such as the storage elements 113-117, from thememory 104. Thememory 104 may be configured to read the representation of therank modulation codeword 140 from the group ofstorage elements 112 by comparing cell threshold voltages in thememory portion 110 to thehard bit thresholds 122 to generate the hard bit values 152 and to thesoft bit thresholds 124 to generate the soft bit values 154. For example, each storage element 113-117 may have a threshold voltage corresponding to a state of the storage element. The state of each storage element 113-117 (i.e., a range of threshold voltage values) may be read by comparing the threshold voltage of each of the storage elements 113-117 to thehard bit thresholds 122 to generate the hard bit values 152 and a sub-range of threshold voltage values may be read by comparing the threshold voltage of each of the storage elements 113-117 to thesoft bit thresholds 124 to generate the soft bit values 154. Thecontroller 106 may provide the hard bit values 152 and the soft bit values 154 as an input to therank modulation decoder 116. - The
rank modulation decoder 116 may be configured to map the hard bit values 152 to an ECC codeword that is decodable by theECC engine 108. For example, the ECC engine may be a Reed Solomon ECC engine, a Bose-Chaudhuri-Hocquenghem (BCH) ECC engine, a low-density parity-check ECC engine, one or more other ECC engines, or any combination thereof. Therank modulation decoder 116 may convert the hard bit values 152 to an ECC codeword that is input to theECC engine 108. - The soft bit values 154 may provide reliability information about the states read from the storage elements 113-117 in the
memory portion 110. The reliability information may include, for each storage element 113-117 that is read, a value that indicates a likelihood that the hard bit values for that storage element are correct. For example, the soft bit values 154 may be used by therank modulation decoder 116 to obtain a reliability indicator for each bit of the ECC codeword provided to theECC engine 108, such as a log-likelihood ratio (LLR). Therank modulation decoder 116 may be configured to use the reliability information to guide error correction processing at theECC engine 108 to generate decoded data bits based on the received hard bit values 152 and the soft bit values 154. For example, theECC engine 108 may perform probabilistic decoding by iteratively updating bit estimates and LLRs of the bit estimates based on bit estimates and LLRs of the bit estimates of a prior iteration of a decoding process to converge to a most probable ECC codeword. The soft bit values 154 enable therank modulation decoder 116 to establish initial reliability values (e.g., LLRs) that are more accurate than default LLRs that may be used by conventional decoders that use hard bits only. Using more accurate initial reliability values (e.g. LLRs based on the soft bit values 154) enables therank modulation decoder 116 to converge more quickly and/or more accurately. As a result, decoding of a representation of an ECC codeword may be performed with reduced latency, with improved error correction capability, or a combination thereof. - Rank modulation is a technique in which information may be stored as relative voltage levels of multiple cells of the memory rather than as absolute voltage levels in each cell. For example, in a single level cell (SLC) memory having four cells, four bits may be stored as absolute voltage levels in each cell of the cells. In a two-bits-per-cell (2-BPC) memory having four cells, 8 bits (e.g., 2×4) may be stored.
- In contrast to storing data as absolute voltage levels, rank modulation using four cells to represent information may be described by denoting the four cells as 1, 2, 3, and 4, respectively. Each of the four cells 1-4 may have a corresponding threshold voltage denoted by V1, V2, V3, and V4, respectively. The four cells 1-4 may be ranked or represented in descending order of their respective voltage levels. For example, a 3-4-1-2 ranking of voltage levels may represent that V3>V4>V1>V2.
- Accordingly, there are 4! (i.e., 4 factorial)=24 combinations (i.e., rankings of voltage levels) for the four cells. By using four memory cells in a rank modulation scheme, log2 24=4.585 bits may be represented. This number is slightly higher than that of a conventional SLC memory using four cells but lower than a conventional 2-BPC memory having four cells.
- Table 1 illustrates a number of bits that can be stored in an M-cell unit.
-
TABLE 1 Rank Modulation 1-BPC 2-BPC 3-BPC M cells log2 (M!) M 2M 3M 2 cells 1 2 4 6 3 cells 2.585 3 6 9 4 cells 4.585 4 8 12 - If four cells are used together for rank modulation, when writing information to a memory, user data may be mapped to one of the twenty four combinations by some predefined mapping, such as a Gray mapping, and the voltage cell may be programmed according to the predefined voltage rank among the four cells. For example, if the chosen rank combination is 3-4-1-2, the voltage may be programmed such that V3>V4>V1>V2. When the user data is read back, the relative voltages of the four cells may be sensed and a ranking may be determined. For example, if U1, U2, U3, and U4 denote the sensed voltages of the
cells - An illustrative example of using rank modulation in a two cell unit is shown in
FIG. 2 .FIG. 2 depicts a general diagram 200 illustrating a use of soft bits and hard bits in rank modulation decoding. The diagram 200 includes thememory 104 coupled to thecontroller 106 via the bus 150. - The memory 104 (shown with dashed lines) includes a table 210, the first
representative storage element 113, and the secondrepresentative storage element 115. The table 210 may include hard bit data and soft bit data, such ashard bits 260 andsoft bits 262, respectively, stored in latches or registers of thememory 104. The hard bit data and the soft bit data indicates a threshold voltage range for each storage element, enabling determination of a relative voltage level (i.e., a ranking) of the storage elements that indicates stored information at thefirst storage element 113 and at thesecond storage element 115. - To illustrate, each of the
storage elements first storage element 113 may have a firstthreshold voltage V 1 230 in a firstvoltage range VT 1 250 and thesecond storage element 115 may have a second threshold voltage V2 232 in a secondvoltage range VT 2 252. For example, the firstvoltage range VT 1 250 may be from zero volts to two volts and the secondvoltage range VT 2 252 may also be from zero volts to two volts. - The
hard bits 260 may indicate results of comparing the threshold voltage of each particular cell (e.g., the firstthreshold voltage V 1 230 and the second threshold voltage V2 232) to one or more hard bit thresholds. For example, data may be read from thefirst storage element 113 and from thesecond storage element 115 by comparing a threshold voltage of each storage elements to a first hard bit threshold or readvoltage VR 1 242 and to a second hard bit threshold or readvoltage VR 2 246. As illustrated, the first hard bit readvoltage VR 1 242 is less than the second hard bit readvoltage VR 2 246. - The hard bits 260 (i.e., HB1, HB2) having a value of “11” may correspond to a threshold voltage value greater than the second hard bit read
voltage VR 2 246. Thehard bits 260 having a value of “10” may correspond to a threshold voltage value between the first hard bit readvoltage VR 1 242 and the second hard bit readvoltage VR 2 246. Thehard bits 260 having a value of “00” may correspond to a threshold voltage value less than the first hard bit readvoltage VR 1 242. - As illustrated, the first
threshold voltage V 1 230 is greater than the first hard bit readvoltage VR 1 242 and less than the second hard bit read voltage VR2 - 246. The second threshold voltage V2 232 is less than the first hard bit read
voltage VR 1 242 and less than the second hard bit readvoltage VR 2 246. Accordingly, thehard bits 260 having a value of “10” (i.e., illustrated as HB1=1 and HB2=0 in the table 210) indicates that the firstthreshold voltage V 1 230 is greater than the first hard bit readvoltage VR 1 242 and less than the second hard bit readvoltage VR 2 246. Similarly, thehard bits 260 having a value of “00” (i.e., illustrated as HB1=0 and HB2=0 in the table 210) indicates that the second threshold voltage V2 232 is less than the first hard bit readvoltage VR 1 242 and less than the second hard bit readvoltage VR 2 246. - The
soft bits 262 may indicate results of comparing the threshold voltage of each particular cell (e.g., the firstthreshold voltage V 1 230 and the second threshold voltage V2 232) to one or more soft bit thresholds. For example, the threshold voltage of thefirst storage element 113 and of thesecond storage element 115 may be compared to a first soft bit threshold or readvoltage S 1 240, a second soft bit threshold or readvoltage S 2 244, and a third soft bit threshold or readvoltage S 3 248. As illustrated, the first soft bit readvoltage S 1 240 may be less than the second soft bit readvoltage S 2 244, and the second soft bit readvoltage S 2 244 may be less than the third soft bit readvoltage S 3 248. In addition, the first hard bit readvoltage VR 1 242 may be less than the second soft bit readvoltage S 2 244 and greater than the first soft bit readvoltage S 1 240, and the second hard bit readvoltage VR 2 246 may be greater than the second soft bit readvoltage S 2 244 and less than the third soft bit readvoltage S 3 248. A first difference between the first soft bit readvoltage S 1 240 and the first hard bit readvoltage VR 1 242 may be substantially equal to a second difference between the first hard bit readvoltage VR 1 242 and the second soft bit readvoltage S 2 244. - The soft bits 262 (i.e., SB1, SB2) having a value of “11” may correspond to a threshold voltage value greater than the third soft bit read
voltage S 3 248. Thesoft bits 262 having a value of “10” may correspond to a threshold voltage value between the third soft bit readvoltage S 3 248 and the second soft bit readvoltage S 2 244. Thesoft bits 262 having a value of “01” may correspond to a threshold voltage value between the second soft bit readvoltage S 2 244 and the first soft bit readvoltage S 1 240. Thesoft bits 262 having a value of “00” may correspond to a threshold voltage value less than the first soft bit readvoltage S 1 240. Accordingly, thesoft bits 262 forstorage element 113 having a value of “10” indicates that the firstthreshold voltage V 1 230 has a value between the third soft bit readvoltage S 3 248 and the second soft bit readvoltage S 2 244. Similarly, thesoft bits 262 forstorage element 115 having a value of “01” indicates that the second threshold voltage V2 232 has a value between the second soft bit readvoltage S 2 244 and the first soft bit readvoltage S 1 240. - The controller 106 (shown with dashed lines) includes the
rank modulation decoder 116 that includes amapper 220, areliability indicator 222, and theerror correction engine 108. Thecontroller 106 may be configured to provide data read from thememory 104 to therank modulation decoder 116. The data may include hard bit data, such as thehard bits 260, and soft bit data, such as thesoft bits 262. For example, thecontroller 106 may receive data from the table 210 and provide the HB1, HB2, SB1, and SB2 values for each cell to therank modulation decoder 116. - The
mapper 220 may be configured to logically partition the data into groups of bits. Each group of bits may correspond to a group of cells in thememory 104. For example, thefirst storage element 113 and thesecond storage element 115 may correspond to one group of bits. Themapper 220 may be further configured to rank cells of each particular group of cells according to cell threshold voltages. For example, themapper 220 may compare the firstthreshold voltage V 1 230 and the second threshold voltage V2 232 and generate a ranking based on the comparison. For example, if the firstthreshold voltage V 1 230 is greater than the second threshold voltage V2 232, a ranking of “1-2” may be generated by themapper 220. Similarly, if the second threshold voltage V2 232 is greater than the firstthreshold voltage V 1 230, a ranking of “2-1” may be generated by themapper 220. - The
mapper 220 may be further configured to map each group of bits to a data value according to the cell ranking of the group of cells corresponding to the group of bits. For example, themapper 220 may generate a single bit symbol or data value (e.g., a “1” or a “0”) based on a comparison of the firstthreshold voltage V 1 230 and the second threshold voltage V2 232. If the firstthreshold voltage V 1 230 is greater than the second threshold voltage V2 232, a data value of “1” may be generated by themapper 220. If the second threshold voltage V2 232 is greater than the firstthreshold voltage V 1 230, a value of “0” may be generated by themapper 220. As another example, more than two storage elements can correspond to the group of bits. For example and as explained above, four cells or storage elements may be used to represent the data. In that case, themapper 220 may generate a multi-bit symbol or data value (e.g., a 5-bit data value of “11001”, “01100, etc.) based on a comparison of the threshold voltages of each cell. Themapper 220 may send the data values based on cell ranking to theECC engine 108 as anECC codeword 270. - The
reliability indicator 222 may be configured to indicate a relative reliability of bit values in theECC codeword 270 generated by themapper 220 and may send relative reliability values to theECC engine 108 as ECCsoft bits 272. The relative reliability may be based at least in part on a difference between the threshold voltages of the cells of each particular group as determined based on the soft bit thresholds S1-S3. For example, the relative reliability may increase as a difference between cell threshold voltages increases. To illustrate, if the difference between the firstthreshold voltage V 1 230 and the second threshold voltage V2 232 is large, the relative reliability of the data value generated by themapper 220 may be higher than if the difference between the firstthreshold voltage V 1 230 and the second threshold voltage V2 232 is small. For example, a reliability indicator of “1” may indicate that the difference between the firstthreshold voltage V 1 230 and the second threshold voltage V2 232 is large, and a reliability indicator of “0” may indicate that the difference between the firstthreshold voltage V 1 230 and the second threshold voltage V2 232 is small. - The
reliability indicator 222 may be configured to determine whether the firstthreshold voltage V 1 230 and the second threshold voltage V2 232 are in adjacent sub-regions. For example, the first hard bit readvoltage VR 1 242 and the second hard bit readvoltage VR 2 246 may divide the firstvoltage range VT 1 250 into three regions. The first soft bit readvoltage S 1 240, the second soft bit readvoltage S 2 244, and the third soft bit readvoltage S 3 248 may divide each region into two sub-regions. Based on thehard bits 260 and thesoft bits 262, thereliability indicator 222 can determine which of the six sub-regions the firstthreshold voltage V 1 230 is in and which of the six sub-regions the second threshold voltage V2 232 is in. When the firstthreshold voltage V 1 230 and the second threshold voltage V2 232 are in adjacent sub-regions, a “0” may be output by thereliability indicator 222. When the firstthreshold voltage V 1 230 and the second threshold voltage V2 232 are not in adjacent sub-regions, a “1” (or a larger number) may be output by thereliability indicator 222. - The
controller 106 may be configured to initiate an ECC procedure on theECC codeword 270 by providing theECC codeword 270 and the ECCsoft bits 272 to theECC engine 108. For example, theECC engine 108 may employ an ECC decoding scheme, such as a Reed Solomon ECC decoding scheme, a Bose-Chaudhuri-Hocquenghem (BCH) ECC decoding scheme, a low-density parity-check ECC decoding scheme, one or more other ECC decoding schemes, or any combination thereof. TheECC engine 108 may provide output data indicating that theECC codeword 270 was correctly decoded. - During operation, the
controller 106 may be instructed by the host device (not shown) to retrieve data corresponding to thestorage elements memory 104. Thecontroller 106 may provide data including hard bit data, such as hard bits 260 (i.e., HB1, HB2), and soft bit data, such as soft bits 262 (i.e., SB1, SB2), to therank modulation decoder 116. Therank modulation decoder 116 may be configured to logically partition the data into groups of bits, where each group of bits may correspond to a group of cells in thememory 104. For example, themapper 220 may compare the firstthreshold voltage V 1 230 and the second threshold voltage V2 232 and generate a ranking based on the comparison. Therank modulation decoder 116 may be further configured to map each group of bits to a data value according to the cell ranking of the group of cells corresponding to the group of bits. For example, themapper 220 may generate a data value based on a comparison of the firstthreshold voltage V 1 230 and the second threshold voltage V2 232 and may send the data value based on cell ranking to theECC engine 108 as theECC codeword 270. A relative reliability of bit values in theECC codeword 270 generated by themapper 220 may be determined by thereliability indicator 222 and relative reliability values may be sent to theECC engine 108 as the ECCsoft bits 272. For example, if the difference between the firstthreshold voltage V 1 230 and the second threshold voltage V2 232 is large, the relative reliability of the data value generated by themapper 220 may be higher than if the difference between the firstthreshold voltage V 1 230 and the second threshold voltage V2 232 is small. Thecontroller 106 may be configured to initiate an ECC procedure on theECC codeword 270 by providing theECC codeword 270 and the ECCsoft bits 272 to theECC engine 108. TheECC engine 108 may provide output data indicating that theECC codeword 270 was correctly decoded. - As illustrated by being shown with dashed lines, one or more components of
FIG. 2 may be moved from a location as shown to a different location. For example, themapper 220, thereliability indicator 222, or both, may be within thememory 104. -
FIG. 3 shows anembodiment 300 of a sensing scheme and includes agraphical depiction 302 of cell distributions for voltage regions (i.e. states) (Er, A, . . . G) of a storage element of a memory, such as arepresentative memory cell 310, and threshold read voltages for hard bits (e.g., voltages AR, BR, . . . GR) and for additional sensed soft bits (e.g., voltages AR-V1, AR+V2, AR-V3, AR+V4, . . . ). A table 304 illustrates a mapping of each voltage interval between adjacent threshold read voltages to a set of six bits including three hard bits (HB1, HB2, HB3) and three soft bits (SB1, SB2, SB3). A pattern of hard bits and soft bits at thememory cell 310 may have athreshold voltage 312 corresponding to a state of thememory cell 310. A pattern of hard bits and soft bits at thememory cell 310 may be generated by comparing thethreshold voltage 312 to the threshold read voltages for hard bits (e.g., voltages AR, BR, . . . GR) to generatehard bits 314 and to the threshold read voltages for soft bits (e.g., voltages AR-V1, AR+V2, AR-V3, AR+V4, . . . ) to generatesoft bits 316. - The
hard bits 314 indicate which state (Er-G) thethreshold voltage 312 is in, and thesoft bits 316 indicate whether thethreshold voltage 312 is within a center of the state's voltage range or near an edge of the state's voltage range (e.g., indicates a proximity to voltage CR). As an example, a first voltage difference (V1) between a first soft bit threshold (e.g., CR-V1) and a particular hard bit threshold (e.g., CR) is substantially equal to a second voltage difference (V2) between the particular hard bit threshold (e.g., CR) and a second soft bit threshold (e.g., CR+V2). Further, as illustrated inFIG. 3 , a third voltage difference (V3) between a third soft bit threshold and the particular hard bit threshold (CR) is substantially equal to a fourth voltage difference (V4) between the particular hard bit threshold (CR) and a fourth soft bit threshold. As illustrated, the first voltage difference (V1) is different than the third voltage difference (V3). As illustrated, thethreshold voltage 312 is between BR and CR, indicating that thecell 310 is in state “B”, corresponding to hard bits “100”. Thethreshold voltage 312 is also in a sub-region between CR-V1 and CR, corresponding to a soft bit value of “001”. - The
controller 106 may provide thehard bits 314 and thesoft bits 316 to an input of arank modulation decoder 320 to obtain decoded data. Thesoft bits 316 may include reliability information about the hard bits read from thememory cell 310. Therank modulation decoder 320 may be configured to use thesoft bits 316 indicating a sub-region of the cell's state (i.e., the sub-region of the state “B” closest to the voltage CR) to guide error correction processing based on the received soft bits, such as by generating ECC soft bits to be input to an ECC decoder, such as the ECCsoft bits 272 ofFIG. 2 . - Referring to
FIG. 4 , a general diagram graphically illustrating states of a three-cell rank modulation group is depicted and generally designated 400. The diagram 400 illustrates three axes labeled as U1, U2, and U3 that define a space (U1, U2, U3). Planes U1=U2, U2=U3, and U3=U1 are illustrated that partition the space (U1, U2, U3) into 3!=6 regions. Four of the six regions (i.e., regions C, D, E, and F) are shown and two of the six regions (i.e., regions A and B) are hidden by the planes. For example, the states of the three-cell rank modulation group may correspond to states of a three-cellgroup including cell 1,cell 2, and cell 3 (e.g. thestorage elements FIG. 1 , respectively) where U1 is a threshold voltage of cell 1 (e.g. the storage element 113), U2 is a threshold voltage of cell 2 (e.g. the storage element 115), and U3 is a threshold voltage of cell 3 (e.g. the storage element 117). Each region A-F corresponds to a different data value stored in the three-cell rank modulation group. To illustrate, region E corresponds to the state U1>U3>U2. - Referring to
FIG. 5 , a general diagram 500 illustrates an example of hard bit thresholds of the three-cell rank modulation group ofFIG. 4 . The diagram 500 illustrates intersections between the line U3 ofFIG. 4 and each of two surfaces: U3=U1 at U1=u1 and U3=U2 at U2=u2, where u1 and u2 correspond to voltage measurements of one of the three cells (i.e., cell 1) and another one of the three cells (i.e., cell 2), respectively. An upper portion ortop line 510 corresponds to a region where u1<u2, and a lower portion orbottom line 520 corresponds to a region where u1>u2. The voltage measurements u1 and u2 may correspond to voltage thresholds that may be used to determine hard bit values. - For example, a threshold voltage (u1) of
cell 1 and a threshold voltage (u2) ofcell 2 may be measured (or otherwise determined). The threshold voltages u1 and u2 may be used as hard bit thresholds to compare to a threshold voltage (u3) ofcell 3. If u1<u2 and the threshold voltage ofcell 3 is less than u1, then a hard bit may indicate that a measure point (e.g., a threshold voltage of cell 3) is within region A. If u1<u2 and the threshold voltage ofcell 3 is between u1 and u2, then a hard bit may indicate that the measure point is within region B. If u1>u2 and the threshold voltage ofcell 3 is greater than u2, then a hard bit may indicate that the measure point is within region C. Similarly, If u2<u1 and the threshold voltage ofcell 3 is less than u2, then a hard bit may indicate that the measure point is within region D. If u2<u1 and the threshold voltage ofcell 3 is between u1 and u2, then a hard bit may indicate that the measure point is within region E. If u2<u1 and the threshold voltage ofcell 3 is greater than u1, then a hard bit may indicate that the measure point is within region F. As illustrated, a hard bit that corresponds to a hard bit threshold may only provide information as to which particular region among the six regions the measure point belongs to. - Referring to
FIG. 6 , a general diagram illustrating an example of soft bit thresholds in a three-cell group in rank modulation decoding is depicted and generally designated 600. The diagram 600 illustrates dividing each hard bit region ofFIG. 5 (i.e., hard bit regions A, B, C, D, E, and F) into smaller sub-regions (i.e., sub-regions A1, A2, B1, B2, C1, C2, D1, D2, E1, E2, F1, F2). For example, soft bit thresholds (denoted by T1, T2, . . . T6) may be added between the values of u1 and u2 to divide each hard bit region into smaller regions. As illustrated inFIG. 5 , six regions or possible results from voltage sensing may be achieved using only hard bits, and three bits may be used to represent this result. If soft bits and hard bits are used as shown inFIG. 6 , twelve possible results from voltage sensing may be achieved, and four bits may be used to represent this result. - Referring to
FIG. 7 , a general diagram illustrating an example of soft bit thresholds in a four cell group in rank modulation decoding is depicted and generally designated 700. Atop line 710 illustrates using hard bits only, amiddle line 720 illustrates the addition of one soft bit threshold per hard bit region, and abottom line 730 illustrates the addition of two soft bit thresholds per hard bit region. The variables w1, w2, w3, and w4 may correspond to voltage measurements u1, u2, u3, and u4 in ascending order of voltage. Accordingly, there are 3!=6 possible combinations (i.e., for w1, w2, and w3) for comparison to w4. As illustrated, there are four regions shown in the top line 710 (i.e., using hard bits only), where each of the four regions has six possible combinations, for a total of twenty four possible combinations. Accordingly, five bits may be used to represent the twenty four combinations. There are eight regions shown in the middle line 720 (i.e., adding one soft bit threshold per hard bit region of line 710), where each of the eight regions has six possible combinations, for a total of forty eight possible combinations. Accordingly, six bits may be used to represent the forty eight combinations. There are twelve regions shown in the bottom line 730 (i.e., adding two soft bit thresholds per hard bit region of line 710), where each of the twelve regions has six possible combinations, for a total of seventy two possible combinations. Accordingly, seven bits may be used to represent the seventy two combinations. Similarly, another number of soft bit thresholds per hard bit region, such as three soft bit thresholds or more, may also be added per hard bit region. Alternatively, the number of soft bit thresholds per hard bit region may not be uniform. For example, the number of soft bit thresholds may differ between a hard bit region defined by w1 and w2 and a hard bit region defined by w2 and w3. - Each line shown in
FIG. 5 (i.e.,line 510, line 520),FIG. 6 (i.e.,line 610, line 620), andFIG. 7 (i.e.,line 710,line 720, line 730) may be referred to as a projection line. For M-cell rank modulation, if L soft bit thresholds are added per projection line, a number of bits that can represent a voltage sensing result may be represented as log2(M-1)!(M+L) (rounded up to a nearest integer value), where (M-1)! is the number of cases (projection lines). For example, for M=3 as illustrated inFIG. 6 , the number of projection lines is (3-1)!=2 (i.e. a line for the case U1>U2 and a line for the case U1<U2), and for M=4 as illustrated inFIG. 7 , the number of cases is (4−1)!=6 (i.e. a line for each of the cases W1>W2>W3, W1>W3>W2, W2>W1>W3, W2>W3>W1, W3>W1>W1, and W3>W2>W1). (M+L) is the number of regions per projection line. - For example, when writing data to a memory when M=2, a first cell (cell 1) may be programmed at a voltage V1 and a second cell (cell 2) may be programmed at a voltage V2 to store a hard bit X such that V1>V2 if X=0, and V1<V2 if X=1. When reading the data, a voltage U1 may be sensed in
cell 1 and a voltage U2 may be sensed incell 2. A hard bit Y (an estimate of X) may be read such that Y=0 if U1>U2, and Y=1 if U1<U2. - An uncertainty due to physical effects may be modeled such that U1=V1+N1, and U2=V2+N2, where N1 and N2 are random variables that describe the uncertainty. Any arbitrary random variables may be used, including zero-mean Gaussian random variables.
- For example, a transition probability matrix can be illustrated for a hard bit only case as follows:
-
- where P(A|B) indicates the probability of A given B. For example, P(U1>U21V1>V2) indicates the probability that
cell 1 is read as having a greater threshold voltage thancell 2 given thatcell 1 is programmed to have a greater threshold thancell 2. If programming occurs such that |V1-V2|=d, then the transition probability matrix in terms of the uncertainty or noise variables and the voltage spacing d may be illustrated as -
- N may be defined as N=N1−N2 to simplify the notation
-
- Note that an expectation of N(E(N))=E(N1)−E(N2) and a variance of N(Var(N))=Var(N1)+Var(N2).
- If the M cells have identical noise variances, the overall noise variance is M times each cell's noise variance. That is, the M-cell noise sigma (i.e., standard deviation) will be √{square root over (M)} times the noise sigma of one cell. The transition probability matrix for hard bits may be used to compare a cell information capacity using hard bits only to rank modulation cell information capacity using hard bits and soft bits, as explained with respect to
FIG. 8 . - Referring to
FIG. 8 , a general diagram illustrating an example of one soft bit threshold per hard bit region in a two cell (i.e., M=2) group is depicted and generally designated 800. A first soft bit threshold T1 and a second soft bit threshold T2 are illustrated defining sub-regions R1, R2, R3, and R4. - Using
FIG. 8 , a transition probability matrix may be determined -
- If h1 and h2 are defined such that U1−T1=h1 and T2−U1=h2, then
-
- In terms of noise variables:
-
- Each memory cell, such as the
memory cell 310 ofFIG. 3 , has a theoretical storage capacity to store an amount of information, referred to as an information capacity (C). The information capacity (C) is a function of probabilities that particular data values are stored to a cell and probabilities of errors occurring to the stored data values due to noise or other effects in the cell. A theoretical lower bound of a cell's information capacity occurs when all data values are equally probable to be stored in the cell (known as “information capacity with scrambler assumption”—data is assumed to be scrambled prior to storage and therefore all data values are equally probable). An information capacity (C) in bits/cell and a lower bound information capacity with scrambler assumption (Cscramble) may be calculated as follows: -
- where X is the original hard bits that were written in a writing operation, R is a voltage region that is sensed during a read operation, and |X| is the number of possible hard bits.
- For example, in 3-cell rank modulation with hard bits only, X may be one of the 3!=6 combinations (|X|=6) and R may be one of the 6 voltage regions. A conditional probability mass function (PMF) p(R|X) may be given as the transition probability matrix Qsoft1 as illustrated above.
- Table 2 (below) illustrates, for several values of cell error rate (CER) and voltage spacing (d) between program states of cells in a rank modulation scheme, examples of soft bit threshold shift (h) values, cell information capacity values, and cell lifetime capacity values. Table 2 provides examples for cells that can be programmed to a threshold voltage in a 2 volt (V) range from −1V to 1V and having a 0.002% CER, a 0.2% CER, and a 1% CER in a conventional SLC scheme not using rank modulation (the CER corresponding to a noise standard deviation (sigma) of 0.2435, 0.3474, and 0.4299, respectively). For M=2, it may be assumed that the noise component in each cell is independent and identically distributed zero-mean Gaussian random variables with variance σ2. Accordingly, E(N)=0 and Var(N)=2σ2. A symmetric scheme h1=h2 may be used.
- For each CER, examples are given for d=2V (i.e. the cells are programmed to −1V or to 1V), d=1V (i.e. the cells are programmed to −1V, 0V, or 1V), d=⅔V (i.e. the cells are programmed to −1V, −⅓V, ⅓V, or 1V), and d=0.5V (i.e. the cells are programmed to −1V, —⅓V, 0V, ½V, or 1V). For each value of d, an “optimal” soft-bit threshold shift (e.g. h1=h2) is provided as a value calculated to provide a theoretical maximum information capacity per cell. Information capacity is provided for the cells using hard bits only and using one soft bit for comparison purposes.
- In addition, Table 2 provides examples of a lifetime information capacity of cells as the information capacity multiplied by (2/d), where 2/d indicates a number of data values that may be sequentially written to a group of cells without erasing the cells. For example, when d=2, each cell is programmed to −1V or to 1V, and a group of cells is erased each time a new data value is written to the group (i.e. changing a ranking from “1-2” to “2-1” or from “2-1” to “1-2”). In contrast, when d=½, the group of cells may be written four times without erasing. To illustrate:
- Write #1:
Program cell 1 to −1V,cell 2 to −½V; rank =“0-1”; data=0 - Write #2:
Program cell 1 to 0V,cell 2 to −½V; rank=“1-0”; data=1 - Write #3:
Program cell 1 to 0V,cell 2 to ½V; rank=“0-1”; data=0 - Write #4:
Program cell 1 to 1V,cell 2 to ½V; rank=“1-0”; data=1 - Because using d=½ may result in four times fewer cell erasures than using d=2, a cell lifetime that may otherwise be limited by a number of erase cycles may be extended by a factor of four by using d=½ as compared to d=2.
-
TABLE 2 optimal Lifetime capacity: CER (%) w/o Noise voltage soft-bit capacity capacity * (2/d) Rank Mod, sigma for spacing: d = threshold Hard bit Hard bit SLC +/− 1 V single cell |V1 − V2| shift: h only 1 Soft bit only 1 Soft bit 0.002% 0.2435 2 0.2856 0.9997 0.9999 0.9997 0.9999 0.002% 0.2435 1 0.3622 0.8586 0.9099 1.7171 1.8198 0.002% 0.2435 ⅔ 0.3928 0.5788 0.6709 1.7365 2.0127 0.002% 0.2435 0.5 0.4234 0.3846 0.4723 1.5383 1.8893 0.2% 0.3474 2 0.4541 0.9792 0.9897 0.9792 0.9897 0.2% 0.3474 1 0.5459 0.6155 0.7055 1.2309 1.4110 0.2% 0.3474 ⅔ 0.6072 0.3453 0.4291 1.0360 1.2874 0.2% 0.3474 0.5 0.6378 0.2118 0.2741 0.8474 1.0965 1% 0.4299 2 0.6072 0.9192 0.9527 0.9192 0.9527 1% 0.4299 1 0.7144 0.4638 0.5564 0.9277 1.1128 1% 0.4299 ⅔ 0.7603 0.2416 0.3098 0.7248 0.9293 1% 0.4299 0.5 0.7909 0.1440 0.1903 0.5759 0.7612 - As illustrated in Table 2, information capacity is improved using one soft bit as compared to using hard bits only. In addition, although cell information capacity is reduced as d is increased, cell lifetime information capacity may instead increase as d is increased. A similar analysis for rank modulation of M>2 cells may also be performed.
-
FIG. 9 depicts a flowchart that illustrates an embodiment of a method of providing data including hard bit data and soft bit data to a rank modulation decoder. Themethod 900 may be performed in a data storage device having a flash multi-level cell (MLC) memory. For example, themethod 900 may be performed in thedata storage device 102 ofFIG. 1 . - Hard bit data and soft bit data may be read from a flash memory, at 902. For example, the
memory 104 may be configured to read the representation of therank modulation codeword 140 from the group ofstorage elements 112 by comparing cell threshold voltages in thememory portion 110 to thehard bit thresholds 122 to generate the hard bit values 152 and to thesoft bit thresholds 124 to generate the soft bit values 154. - Data, including hard bit data (e.g. the hard bit values 152 of
FIG. 1 ) and soft bit data (e.g. the soft bit values 154 ofFIG. 1 ), may be provided to a rank modulation decoder, at 904. For example, thememory 104 may include read circuitry configured to compare cell threshold voltages to one or more hard bit thresholds to generate the hard bit values 152 and to one or more soft bit thresholds to generate the soft bit values 154, latches configured to latch results of the comparisons, and a bus interface configured to provide the the hard bit values 152 and the soft bit values 154 to therank modulation decoder 116. - To illustrate, the data may be read from multiple cells of a memory, such as the storage elements 113-117 of the
memory 104, where each particular cell of the multiple cells has a threshold voltage, and where the hard bit data includes hard bits that indicate results of comparing the threshold voltage of each particular cell to one or more hard bit thresholds and where the soft bit data includes soft bits that indicate results of comparing the threshold voltage of each particular cell to one or more soft bit thresholds. - For example, the
first storage element 113 may have the firstthreshold voltage V 1 230 in the firstvoltage range VT 1 250 and thesecond storage element 115 may have the second threshold voltage V2 232 in the secondvoltage range VT 2 252. Data may be read from thefirst storage element 113 and from thesecond storage element 115 based on comparisons of threshold voltages of thefirst storage element 113 and thesecond storage element 115 to the first hardbit threshold VR 1 242 and to the second hardbit threshold VR 2 246 to generate thehard bits 260. Thehard bits 260 may indicate results of the comparisons of the threshold voltage of each particular cell (e.g., the firstthreshold voltage V 1 230 and the second threshold voltage V2 232) and may indicate whether the firstthreshold voltage V 1 230 is greater than or less than the second threshold voltage V2 232. For example, the hard bits 260 (i.e., HB1, HB2) having a value of “11” may correspond to a threshold voltage value greater than the second hard bit readvoltage VR 2 246. Thehard bits 260 having a value of “10” may correspond to a threshold voltage value between the first hard bit readvoltage VR 1 242 and the second hard bit readvoltage VR 2 246. Thehard bits 260 having a value of “00” may correspond to a threshold voltage value less than the first hard bit readvoltage VR 1 242. - The soft bits may indicate results of comparing the threshold voltage of each particular cell (e.g., the first
threshold voltage V 1 230 and the second threshold voltage V2 232) to one or more soft bit thresholds (also referred to as soft bit read voltages) and may indicate whether the firstthreshold voltage V 1 230 is greater than or less than the first soft bit read voltage (e.g., threshold S1 240). For example, the threshold voltage of thefirst storage element 113 and of thesecond storage element 115 may be compared to the first soft bit read voltage orthreshold S 1 240, to the second soft bit read voltage orthreshold S 2 244, and to the third soft bit read voltage orthreshold S 3 248. In addition, the soft bits may indicate whether the firstthreshold voltage V 1 230 is greater than or less than the second soft bit readvoltage S 2 244, where the first soft bit readvoltage S 1 240 is less than the second threshold voltage V2 232, and where the second soft bit readvoltage S 2 244 is greater than the second threshold voltage V2 232. - The
method 900 may be performed on a multi-cell rank modulation group, such as a three-cell rank modulation group. For example, theflash memory 104 may include a third cell (i.e., the storage element 117) having a third threshold voltage. The hard bit data may further indicate whether the third threshold voltage is in a first range of voltages that are less than the firstthreshold voltage V 1 230 and the second threshold voltage V2 232, in a second range of voltages that are between the firstthreshold voltage V 1 230 and the second threshold voltage V2 232, or in a third range of voltages that are greater than the firstthreshold voltage V 1 230 and the second threshold voltage V2 232. The soft bit data may indicate whether the third threshold voltage is in one or more sub-ranges of the first range of voltages, the second range of voltages, or the third range of voltages. - The
controller 106 may be configured to provide data read from thememory 104 to therank modulation decoder 116. For example, thecontroller 106 may receive the data via a bus interface and may provide the received data to an input of therank modulation decoder 116. The data may include thehard bits 260 and thesoft bits 262. Therank modulation decoder 116 may be configured to logically partition the data into groups of bits, where each group of bits corresponds to a group of cells in thememory 104, and may rank cells of each particular group of cells according to cell threshold voltages to produce a cell ranking of the particular group of cells. For example, themapper 220 may compare the firstthreshold voltage V 1 230 and the second threshold voltage V2 232 and generate a ranking based on the comparison. Therank modulation decoder 116 may be configured to map each group of bits to a data value according to the cell ranking of the group of cells corresponding to the group of bits. For example, themapper 220 may generate a data value based on a comparison of the firstthreshold voltage V 1 230 and the second threshold voltage V2 232 and may send the data value based on cell ranking to theECC engine 108 as theECC codeword 270. - By providing data including hard bit data and soft bit data to a rank modulation decoder, error correction at the rank modulation decoder may be performed more quickly and/or accurately as compared to rank modulation decoding using hard bits only. As explained with reference to Table 2, cell information capacity may be increased by using rank modulation decoding using hard bits and soft bits as compared to rank modulation decoding using hard bits only.
- Although various components depicted herein are illustrated as block components and described in general terms, such components may include one or more microprocessors, state machines, or other circuits configured to enable a data storage device, such as the
data storage device 102 ofFIG. 1 , to perform the particular functions attributed to such components, or any combination thereof. For example, therank modulation decoder 116 ofFIG. 1 andFIG. 2 may represent physical components, such as controllers, processors, state machines, logic circuits, or other structures to logically partition the data into groups of bits, where each group of bits corresponds to a group of cells in a flash memory, to rank cells of each particular group of cells, and to map each group of bits to a data value according to the cell ranking of the group of cells corresponding to the group of bits. - The
rank modulation decoder 116 may be implemented using a microprocessor or microcontroller programmed to generate data from rank modulated data using soft bits. In a particular embodiment, thecontroller 106 includes a processor executing instructions that are stored at thememory 104. Alternatively, or in addition, executable instructions that are executed by the processor may be stored at a separate memory location that is not part of thememory 104, such as at a read-only memory (ROM) (not shown). - In a particular embodiment, the
data storage device 102 may be a portable device configured to be selectively coupled to one or more external devices. For example, thedata storage device 102 may be a removable device such as a Universal Serial Bus (USB) flash drive or a removable memory card, as illustrative examples. However, in other embodiments, thedata storage device 102 may be attached or embedded within one or more host devices, such as within a housing of a portable communication device. For example, thedata storage device 102 may be within a packaged apparatus, such as a wireless telephone, a personal digital assistant (PDA), a gaming device or console, a portable navigation device, a computer, or other device that uses internal non-volatile memory. In a particular embodiment, thedata storage device 102 includes a non-volatile memory, such as a Flash memory (e.g., NAND, NOR, Multi-Level Cell (MLC), Divided bit-line NOR (DINOR), AND, high capacitive coupling ratio (HiCR), asymmetrical contactless transistor (ACT), or other Flash memories), an erasable programmable read-only memory (EPROM), an electrically-erasable programmable read-only memory (EEPROM), a read-only memory (ROM), a one-time programmable memory (OTP), or any other type of memory. - The illustrations of the embodiments described herein are intended to provide a general understanding of the various embodiments. Other embodiments may be utilized and derived from the disclosure, such that structural and logical substitutions and changes may be made without departing from the scope of the disclosure. This disclosure is intended to cover any and all subsequent adaptations or variations of various embodiments.
- The above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, which fall within the scope of the present disclosure. Thus, to the maximum extent allowed by law, the scope of the present invention is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.
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PCT/US2012/063086 WO2013070493A1 (en) | 2011-11-10 | 2012-11-01 | Method and apparatus to provide data including hard bit data and soft bit data to a rank modulation decoder |
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WO (1) | WO2013070493A1 (en) |
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Also Published As
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CN103918033A (en) | 2014-07-09 |
TW201330001A (en) | 2013-07-16 |
WO2013070493A1 (en) | 2013-05-16 |
US8456919B1 (en) | 2013-06-04 |
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