WO2017096706A1 - 液晶显示面板结构 - Google Patents

液晶显示面板结构 Download PDF

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Publication number
WO2017096706A1
WO2017096706A1 PCT/CN2016/072650 CN2016072650W WO2017096706A1 WO 2017096706 A1 WO2017096706 A1 WO 2017096706A1 CN 2016072650 W CN2016072650 W CN 2016072650W WO 2017096706 A1 WO2017096706 A1 WO 2017096706A1
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Prior art keywords
common voltage
electrically connected
thin film
film transistor
liquid crystal
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Ceased
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PCT/CN2016/072650
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English (en)
French (fr)
Inventor
王聪
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US14/912,603 priority Critical patent/US10073312B2/en
Publication of WO2017096706A1 publication Critical patent/WO2017096706A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor
    • G02F2202/104—Materials and properties semiconductor poly-Si
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a liquid crystal display panel structure.
  • LCD Liquid Crystal Display
  • advantages such as thin body, power saving, no radiation, etc., such as: LCD TV, mobile phone, personal digital assistant (PDA), digital camera, computer screen or Laptop screens, etc., dominate the field of flat panel display.
  • PDA personal digital assistant
  • liquid crystal displays which include a liquid crystal display panel and a backlight module.
  • the working principle of the liquid crystal display panel is to fill liquid crystal molecules between a Thin Film Transistor Array Substrate (TFT Array Substrate) and a Color Filter (CF) substrate, and apply driving on the two substrates.
  • TFT Array Substrate Thin Film Transistor Array Substrate
  • CF Color Filter
  • the liquid crystal display panel includes a plurality of pixels arranged in an array, each of which includes a plurality of sub-pixels.
  • Each sub-pixel is electrically connected to a thin film transistor (TFT), a gate of the TFT is connected to the horizontal scan line, a source is connected to the data line in the vertical direction, and a source is connected to the pixel electrode.
  • TFT thin film transistor
  • Applying a sufficient voltage on the horizontal scanning line causes all the TFTs electrically connected to the scanning line to be turned on, so that the signal voltage on the data line can be written into the sub-pixels, and the transmittance of the liquid crystal is controlled to achieve a display effect.
  • the polarity inversion is often driven on the pixel array to drive.
  • frame inversion or column inversion mode is often implemented.
  • the frame inversion or column inversion mode often causes problems of image sticking (IS), crosstalk, and flicker of the liquid crystal display panel, especially in a liquid crystal display panel in which low temperature polysilicon is a semiconductor material.
  • IS image sticking
  • crosstalk is easily caused, which affects the display quality of the picture.
  • FIG. 1 is a schematic diagram of a structure of a conventional liquid crystal display panel, including a plurality of scanning lines that are parallel to each other and distributed in a lateral direction (eg, G(1), G(2), G(3), G(4).
  • a plurality of data lines such as D(1), D(2), D(3), D(4), etc.
  • a plurality of sub-pixels P arranged in a matrix
  • a plurality of horizontal common voltage branch traces such as L(1), L(2), L(3), L(4), etc.
  • Each of the common voltage branch traces is directly electrically connected to the common voltage bus Com such that the common voltage of all the pixels in the entire liquid crystal display panel is a constant potential Vcom.
  • the driving mode of the scan line is a bilateral progressive scan.
  • V PE represents the pixel voltage of a certain sub-pixel
  • Vcom represents a common voltage.
  • ⁇ V>0 it means that the driving voltage of the sub-pixel is positive polarity
  • ⁇ V ⁇ 0 it means that the driving voltage of the sub-pixel is negative polarity.
  • An object of the present invention is to provide a liquid crystal display panel structure, which can realize a driving display mode of line inversion or dot inversion, improve image sticking, crosstalk, and flicker of a liquid crystal display panel, and improve display performance of the liquid crystal display panel. .
  • the present invention provides a liquid crystal display panel structure.
  • the liquid crystal display panel structure of the present invention comprises a plurality of mutually parallel and laterally distributed scan lines disposed in the effective display area, a plurality of parallel and longitudinally distributed data lines, and a matrix arrangement.
  • Each sub-pixel includes a thin film transistor, and a storage capacitor and a liquid crystal capacitor connected in parallel with each other;
  • s be a positive integer, and the source of the thin film transistor of all sub-pixels of the sth column is correspondingly connected to the sth data line;
  • n be a positive integer
  • the nth scan line corresponding to the nth row of subpixels
  • the nth common voltage branch trace corresponding to the nth row of subpixels
  • the nth row of all subpixels of the thin film transistor The poles are connected to the nth scan line;
  • the storage capacitor of any sub-pixel of the i-th row is electrically connected to one end of the liquid crystal capacitor to correspond to the drain of the thin film transistor, and the other end is electrically connected to the corresponding ith common voltage branch.
  • the corresponding ith common voltage branch trace is electrically connected to the second common voltage bus through a first switching thin film transistor; the gate of the first switching thin film transistor is electrically connected to the corresponding ith scan a line, the source is electrically connected to the second common voltage bus, and the drain is electrically connected to the corresponding ith common voltage branch trace;
  • the storage capacitor of any sub-pixel of the i+1th row is electrically connected to one end of the liquid crystal capacitor corresponding to the drain of the thin film transistor, and the other end is electrically connected to the corresponding i+1th common voltage branch trace; the corresponding The i+1th common voltage branch trace is electrically connected to the first common voltage bus through a second switching thin film transistor; the gate of the second switching thin film transistor is electrically connected to the corresponding i+1th scan line, The source is electrically connected to the first common voltage bus, and the drain is electrically connected to the corresponding i+1th common voltage branch trace.
  • One of the first common voltage Vcom1 transmitted by the first common voltage bus and the second common voltage Vcom2 transmitted by the second common voltage bus is greater than the pixel voltage, and the other is smaller than the pixel voltage.
  • the values of the first common voltage Vcom1 transmitted by the first common voltage bus and the second common voltage Vcom2 transmitted by the second common voltage bus are exchanged to implement a line inversion mode.
  • Each of the thin film transistors is a low temperature polysilicon thin film transistor.
  • the liquid crystal display panel structure of the present invention comprises a plurality of mutually parallel and laterally distributed scan lines disposed in the effective display area, a plurality of parallel and longitudinally distributed data lines, and a matrix arrangement. a plurality of sub-pixels, a plurality of horizontal common voltage branch lines respectively corresponding to each row of sub-pixels, and longitudinal first common voltage buses and second common voltage buses respectively disposed on both sides of the effective display area, and disposed outside the effective display area a zeroth scan line of the lateral direction, and a horizontal zeroth common voltage branch trace disposed outside the effective display area; the first common voltage Vcom1 transmitted by the first common voltage bus is different from the second common voltage bus transmission Second common voltage Vcom2;
  • Each sub-pixel includes a thin film transistor, and a storage capacitor and a liquid crystal capacitor connected in parallel with each other;
  • s be a positive integer, and the source of the thin film transistor of all sub-pixels of the sth column is correspondingly connected to the sth data line;
  • n be a positive integer
  • the nth scan line corresponding to the nth row of subpixels
  • the nth common voltage branch trace corresponding to the nth row of subpixels
  • the nth row of all subpixels of the thin film transistor The poles are connected to the nth scan line;
  • the storage capacitor of any sub-pixel of the i-th row is electrically connected to one end of the liquid crystal capacitor corresponding to the drain of the thin film transistor, and the storage capacitor of the odd-numbered sub-pixel of the i-th row is electrically connected to the other end of the liquid crystal capacitor
  • Corresponding ith common voltage branch trace even row sub-pixel of ith row
  • the storage capacitor and the other end of the liquid crystal capacitor are electrically connected to the i-1th common voltage branch trace;
  • the corresponding ith common voltage branch trace is electrically connected to the first common voltage bus through a first switching thin film transistor
  • the i-1th common voltage branch trace is electrically connected to the second common voltage bus through a second switching thin film transistor;
  • the storage capacitor of any sub-pixel of the i+1th row is electrically connected to one end of the liquid crystal capacitor corresponding to the drain of the thin film transistor, and the storage capacitor of the odd-numbered sub-pixel of the i+1th row is electrically connected to the other end of the liquid crystal capacitor.
  • the i+1th common voltage branch trace, the storage capacitor of the even column sub-pixel of the i+1th row and the other end of the liquid crystal capacitor are electrically connected to the i-th common voltage branch trace; the corresponding i+1
  • the common voltage branch trace is electrically connected to the second common voltage bus through a second switching thin film transistor;
  • the gate of the first switching thin film transistor is electrically connected to the corresponding odd-numbered scan lines, the source is electrically connected to the first common voltage bus, and the drain is electrically connected to the corresponding odd-numbered common voltage branch traces;
  • the gate of the second switching thin film transistor is electrically connected to the corresponding even-numbered scanning lines or the zeroth scanning line, the source is electrically connected to the second common voltage bus, and the drain is electrically connected to the corresponding even-numbered common voltage branches. Trace, or the zeroth common voltage branch trace.
  • One of the first common voltage Vcom1 transmitted by the first common voltage bus and the second common voltage Vcom2 transmitted by the second common voltage bus is greater than the pixel voltage, and the other is smaller than the pixel voltage.
  • the value of the first common voltage Vcom1 transmitted by the first common voltage bus and the second common voltage Vcom2 transmitted by the second common voltage bus are exchanged to implement a dot inversion mode.
  • Each of the thin film transistors is a low temperature polysilicon thin film transistor.
  • the present invention also provides a liquid crystal display panel structure comprising a plurality of mutually parallel and laterally distributed scan lines disposed in an effective display area, a plurality of parallel and longitudinally distributed data lines, arranged in a matrix. a plurality of sub-pixels, a plurality of horizontal common voltage branch lines respectively corresponding to each row of sub-pixels, and longitudinal first common voltage buses and second common voltage buses respectively disposed on both sides of the effective display area; the first common The first common voltage Vcom1 transmitted by the voltage bus is different from the second common voltage Vcom2 transmitted by the second common voltage bus;
  • Each sub-pixel includes a thin film transistor, and a storage capacitor and a liquid crystal capacitor connected in parallel with each other;
  • s be a positive integer, and the source of the thin film transistor of all sub-pixels of the sth column is correspondingly connected to the sth data line;
  • n be a positive integer
  • the nth scan line corresponding to the nth row of subpixels
  • the nth common voltage branch trace corresponding to the nth row of subpixels
  • the nth row of all subpixels of the thin film transistor The poles are connected to the nth scan line;
  • the storage capacitor of any sub-pixel of the i-th row is electrically connected to one end of the liquid crystal capacitor corresponding to the drain of the thin film transistor, and the other end is electrically connected to the corresponding ith common voltage branch trace;
  • the corresponding The ith common voltage branch trace is electrically connected to the second common voltage bus through a first switching thin film transistor;
  • the gate of the first switching thin film transistor is electrically connected to the corresponding ith scan line, and the source is electrically Connected to the second common voltage bus, and the drain is electrically connected to the corresponding ith common voltage branch trace;
  • the storage capacitor of any sub-pixel of the i+1th row is electrically connected to one end of the liquid crystal capacitor corresponding to the drain of the thin film transistor, and the other end is electrically connected to the corresponding i+1th common voltage branch trace;
  • the corresponding The i+1th common voltage branch trace is electrically connected to the first common voltage bus through a second switching thin film transistor;
  • the gate of the second switching thin film transistor is electrically connected to the corresponding i+1th scan line,
  • the source is electrically connected to the first common voltage bus, and the drain is electrically connected to the corresponding i+1th common voltage branch trace;
  • one of the first common voltage Vcom1 transmitted by the first common voltage bus and the second common voltage Vcom2 transmitted by the second common voltage bus is greater than a pixel voltage, and the other is smaller than a pixel voltage;
  • the first common voltage Vcom1 transmitted by the first common voltage bus and the second common voltage Vcom2 transmitted by the second common voltage bus are exchanged in a two-frame picture adjacent to each other to implement a line inversion mode.
  • Each of the thin film transistors is a low temperature polysilicon thin film transistor.
  • the present invention provides a liquid crystal display panel structure in which a first common voltage bus and a second common voltage bus are respectively disposed on both sides of an effective display area of a liquid crystal display panel, and the first common voltage bus
  • the transmitted first common voltage Vcom1 is different from the second common voltage Vcom2 transmitted by the second common voltage bus.
  • the driving display mode of row inversion or dot inversion can be realized, and the image of the liquid crystal display panel is improved.
  • Adverse problems such as residual, crosstalk, and flicker improve the display of the LCD panel.
  • 1 is a schematic view showing the structure of a conventional liquid crystal display panel
  • FIG. 2 and 3 are schematic diagrams showing the polarities of the liquid crystal display panel shown in FIG. 1 when displayed on two adjacent frames;
  • FIG. 4 is a schematic view showing a first embodiment of a liquid crystal display panel structure of the present invention.
  • FIG. 5 and FIG. 6 are respectively schematic diagrams showing the polarities of the liquid crystal display panel shown in FIG. 4 when displayed on two adjacent frames;
  • Figure 7 is a schematic view showing a second embodiment of the structure of the liquid crystal display panel of the present invention.
  • FIG. 8 and 9 are schematic diagrams showing the polarities of the liquid crystal display panel shown in FIG. 7 when displayed on two adjacent frames.
  • the invention provides a liquid crystal display panel structure.
  • FIG. 4, FIG. 5, and FIG. 6, which are the first embodiment of the structure of the liquid crystal display panel of the present invention.
  • the first embodiment includes a plurality of mutually parallel and laterally distributed in the effective display area AA. a scan line, a plurality of data lines that are parallel to each other and distributed in the longitudinal direction, a plurality of sub-pixels P arranged in a matrix, a plurality of horizontal common voltage branch lines respectively corresponding to each row of sub-pixels P, and are respectively set to be effective
  • the longitudinal first common voltage bus Com1 and the second common voltage bus Com2 on both sides of the area AA are displayed.
  • each sub-pixel P includes a thin film transistor T and a storage capacitor C1 and a liquid crystal capacitor C2 connected in parallel with each other.
  • s be a positive integer
  • the source of the thin film transistor T of all the sub-pixels P of the sth column is correspondingly connected to the sth data line D(s)
  • the source of the thin film transistor T of all the sub-pixels P of the first column corresponds to
  • the source of the thin film transistor T connecting the first data line D(1) and all the sub-pixels P of the second column is connected to the second data line D(2), and so on.
  • n be a positive integer
  • the nth scan line G(n) is located above the nth row of subpixels P
  • the nth common voltage branch trace L(n) is located below the nth row of subpixels P
  • the gates of the thin film transistors T of all the sub-pixels P of n rows are connected to the nth scanning line G(n).
  • the first scan line G(1) is located above the first row of sub-pixels P, and the first common voltage branch trace L(1) is located below the first row of sub-pixels P;
  • the gates of the thin film transistors T of the pixels P are respectively connected to the first scanning line G(1);
  • the second scanning lines G(2) are correspondingly located above the second row of sub-pixels P, and the second common voltage branching line L(2) corresponds to the lower side of the second row of sub-pixels P;
  • the gates of the thin film transistors T of all the sub-pixels P of the second row are correspondingly connected to the second scanning line G(2), and so on.
  • the gate of the first switching thin film transistor T10 is electrically connected to the corresponding ith scan line G(i), the source is electrically connected to the second common voltage bus Com2, and the drain is electrically connected to the corresponding ith common voltage.
  • the storage capacitor C1 of any sub-pixel P of the i+1 row is electrically connected to one end of the liquid crystal capacitor C2 to the drain of the thin film transistor T, and the other end is electrically connected to the corresponding i+1th common voltage branch.
  • the line L(i+1) is connected; the corresponding i+1th common voltage branch line L(i+1) is electrically connected to the first common voltage bus Com1 through a second switching thin film transistor T20.
  • the gate of the second switching thin film transistor T20 is electrically connected to the corresponding i+1th scan line G(i+1), the source is electrically connected to the first common voltage bus Com1, and the drain is electrically connected to the corresponding i+1 common voltage branch traces L(i+1).
  • each of the thin film transistors is a low temperature polysilicon thin film transistor.
  • first common voltage Vcom1 transmitted by the first common voltage bus Com1 is different from the second common voltage Vcom2 transmitted by the second common voltage bus Com2. Further, one of the first common voltage Vcom1 transmitted by the first common voltage bus Com1 and the second common voltage Vcom2 transmitted by the second common voltage bus Com2 is greater than the pixel voltage, and the other is smaller than the pixel voltage, and is in front of and behind In the two adjacent frames, the value of the first common voltage Vcom1 transmitted by the first common voltage bus Com1 and the second common voltage Vcom2 transmitted by the second common voltage bus Com2 are exchanged.
  • the thin film transistors T in all the sub-pixels of the i-th row are all turned on, and the first switching thin film transistor corresponding to the i-th row of sub-pixels is provided.
  • T10 is turned on, turning on the ith common voltage branch trace L(i) and the second common voltage bus Com2, so that the driving voltage ⁇ V of the i-th row sub-pixel is the transmission of the pixel voltage V PE and the second common voltage bus Com2
  • the difference between the two common voltages Vcom2, that is, ⁇ V V PE -Vcom2.
  • the thin film transistors T in all the sub-pixels of the i-th row are turned off, and the pixel voltage V of the i-th row of sub-pixels
  • the voltage difference between the PE and the second common voltage Vcom2 transmitted by the second common voltage bus Com2 remains unchanged, and the thin film transistors T in all the sub-pixels of the i+1th row are all turned on, corresponding to the i+1th row of sub-pixels.
  • the second switching thin film transistor T20 is turned on to turn on the i+1th common voltage branch trace L(i+1) and the first common voltage bus Com1, so that the driving voltage ⁇ V of the i+1th row sub-pixel is a pixel.
  • the difference between the voltage V PE and the first common voltage Vcom1 transmitted by the first common voltage bus Com1, that is, ⁇ V V PE -Vcom1.
  • V PE output pixel voltage
  • Vcom2 is 0V
  • Vcom1 is +10V
  • the polarity of the i-th row, that is, the odd-numbered sub-pixels is +5V
  • the i+1th row is even.
  • the polarity of the sub-pixels of the row is -5V.
  • the polarity of the i-th row that is, the odd-numbered sub-pixels is - 5V
  • the polarity of the sub-pixel of the i+1th row that is, the even row is +5V.
  • the line inversion mode is implemented in the two frames before and after, and the problem of image sticking, crosstalk, and flicker of the liquid crystal display panel can be improved, and the display effect of the liquid crystal display panel is improved.
  • FIG. 7 , FIG. 8 , and FIG. 9 are second embodiments of the liquid crystal display panel structure of the present invention.
  • the second embodiment includes a plurality of parallel and laterally distributed portions disposed in the effective display area AA.
  • each sub-pixel P includes a thin film transistor T and a storage capacitor C1 and a liquid crystal capacitor C2 connected in parallel with each other.
  • s be a positive integer
  • the source of the thin film transistor T of all the sub-pixels P of the sth column is correspondingly connected to the sth data line D(s)
  • the source of the thin film transistor T of all the sub-pixels P of the first column corresponds to
  • the source of the thin film transistor T connecting the first data line D(1) and all the sub-pixels P of the second column is connected to the second data line D(2), and so on.
  • n be a positive integer
  • the nth scan line G(n) is located above the nth row of subpixels P
  • the nth common voltage branch trace L(n) is located below the nth row of subpixels P
  • the gates of the thin film transistors T of all the sub-pixels P of n rows are connected to the nth scanning line G(n).
  • the first scan line G(1) is located above the first row of sub-pixels P, and the first common voltage branch trace L(1) is located below the first row of sub-pixels P;
  • the gates of the thin film transistors T of the pixels P are respectively connected to the first scanning line G(1);
  • the second scanning lines G(2) are correspondingly located above the second row of sub-pixels P, and the second common voltage branching line L(2) corresponds to the lower side of the second row of sub-pixels P;
  • the gates of the thin film transistors T of all the sub-pixels P of the second row are correspondingly connected to the second scanning line G(2), and so on.
  • i be an odd number
  • the storage capacitor C1 of any sub-pixel P of the i-th row that is, the odd-numbered row, and one end of the liquid crystal capacitor C2 are electrically connected to the drain of the thin film transistor T
  • the storage capacitor C1 of the odd-numbered sub-pixel P of the i-th row The ith common voltage component corresponding to the other end of the liquid crystal capacitor C2
  • the storage line C1 of the even-numbered column sub-pixel P of the i-th row is electrically connected to the other end of the liquid crystal capacitor C2 to the i-th common voltage branch trace L(i-1);
  • the ith common voltage branch trace L(i) is electrically connected to the first common voltage bus Com1 through a first switching thin film transistor T10, the i-1th common voltage branch trace L(i-1) It is electrically connected to the second common voltage bus Com2 through a second switching thin film transistor T20.
  • the storage capacitor C1 of any sub-pixel P of the first row and the one end of the liquid crystal capacitor C2 are electrically connected to the drain of the thin film transistor T, and the storage capacitor C1 of the odd-numbered sub-pixel P of the first row and the liquid crystal capacitor C2 One end is electrically connected to the corresponding first common voltage branch trace L(1), and the storage capacitor C1 of the even-numbered column sub-pixel P of the first row and the other end of the liquid crystal capacitor C2 are electrically connected to the zeroth common voltage branch trace L (0); the corresponding first common voltage branch trace L(1) is electrically connected to the first common voltage bus Com1 through a first switching thin film transistor T10, the zeroth common voltage branch trace L (0) is electrically connected to the second common voltage bus Com2 through a second switching thin film transistor T20.
  • the storage capacitor C1 of any sub-pixel P of the third row is electrically connected to one end of the liquid crystal capacitor C2 to correspond to the drain of the thin film transistor T, and the storage capacitor C1 of the odd-numbered sub-pixel P of the third row is electrically connected to the other end of the liquid crystal capacitor C2.
  • the third common voltage branch line L(3) corresponding to the sexual connection, the storage capacitor C1 of the even-numbered column sub-pixel P of the third row and the other end of the liquid crystal capacitor C2 are electrically connected to the second common voltage branch line L (2)
  • the corresponding third common voltage branch trace L(3) is electrically connected to the first common voltage bus Com1 through a first switching thin film transistor T10, and the second common voltage branch trace L (2) ) is electrically connected to the second common voltage bus Com2 through a second switching thin film transistor T20. And so on.
  • the storage capacitor C1 of the sub-pixel P of the i+1 row is electrically connected to one end of the liquid crystal capacitor C2 to the drain of the thin film transistor T, and the storage capacitor C1 of the odd-numbered sub-pixel P of the i+1th row is The other end of the liquid crystal capacitor C2 is electrically connected to the corresponding i+1th common voltage branch trace L(i+1), and the storage capacitor C1 of the even column subpixel P of the i+1th row is electrically connected to the other end of the liquid crystal capacitor C2.
  • Connecting the ith common voltage branch trace L(i); the corresponding i+1th common voltage branch trace L(i+1) is electrically connected to the second common through a second switching thin film transistor T20 Voltage bus Com2.
  • the storage capacitor C1 of any sub-pixel P of the second row is electrically connected to one end of the liquid crystal capacitor C2 to correspond to the drain of the thin film transistor T, and the storage capacitor C1 of the odd-numbered sub-pixel P of the second row and the liquid crystal capacitor C2 are One end is electrically connected to the corresponding second common voltage branch line L(2), and the storage capacitor C1 of the even-numbered column sub-pixel P of the second row is electrically connected to the other end of the liquid crystal capacitor C2 to the first common voltage branch line L.
  • the corresponding second common voltage branch trace L(2) is electrically connected to the second common voltage bus Com2 through a second switching thin film transistor T20.
  • the gate of the first switching thin film transistor T10 is electrically connected to the corresponding odd-numbered scan lines G(i), the source is electrically connected to the first common voltage bus Com1, the drain is electrically connected to the corresponding odd-numbered common voltage branch traces L(i); and the gate of the second switching thin film transistor T20 is electrically Connecting the corresponding even-numbered scan lines G(i+1) or the zero-th scan lines G(0), the source is electrically connected to the second common voltage bus Com2, and the drain is electrically connected to the corresponding even-numbered common voltages Branch trace L(i+1), or zeroth common voltage branch trace L(0).
  • each of the thin film transistors is a low temperature polysilicon thin film transistor.
  • first common voltage Vcom1 transmitted by the first common voltage bus Com1 is different from the second common voltage Vcom2 transmitted by the second common voltage bus Com2. Further, one of the first common voltage Vcom1 transmitted by the first common voltage bus Com1 and the second common voltage Vcom2 transmitted by the second common voltage bus Com2 is greater than the pixel voltage, and the other is smaller than the pixel voltage, and is in front of and behind In the two adjacent frames, the value of the first common voltage Vcom1 transmitted by the first common voltage bus Com1 and the second common voltage Vcom2 transmitted by the second common voltage bus Com2 are exchanged.
  • the second switch thin film transistor T20 corresponding to the zeroth common voltage branch trace L(0) is turned on, turning on the zeroth common voltage branch trace L (0) and the second common voltage bus Com2 such that the common voltage of the first row even column sub-pixels is the second common voltage Vcom2 transmitted by the second common voltage bus Com2.
  • the first scan line G(1) provides a scan signal
  • the thin film transistors T in all the sub-pixels of the first row are all turned on, corresponding to the first switch set by the first common voltage branch trace L(1).
  • the thin film transistor T10 is turned on to turn on the first common voltage branch trace L(1) and the first common voltage bus Com1, so that the common voltage of the first row of odd-numbered column sub-pixels is the first common voltage transmitted by the first common voltage bus Com1.
  • Vcom1 at the same time, causes the common voltage of the second row even column sub-pixels to be the first common voltage Vcom1 transmitted by the first common voltage bus Com1.
  • the driving voltage ⁇ V of the first row of odd-numbered column sub-pixels is the transmission of the pixel voltage V PE and the first common voltage bus Com1.
  • the second scan line G(2) provides a scan signal, and the thin film transistors T in all the sub-pixels of the second row are all turned on, corresponding to the second switch film disposed on the second common voltage branch trace L(2).
  • the transistor T20 is turned on to turn on the second common voltage branch trace L(2) and the second common voltage bus Com2, so that the common voltage of the second row of odd-numbered column sub-pixels is the second common voltage Vcom2 transmitted by the second common voltage bus Com2.
  • the common voltage of the third row even column sub-pixels is the second common voltage Vcom2 transmitted by the second common voltage bus Com2.
  • the driving voltage ⁇ V of the second row of odd-numbered sub-pixels is the transmission of the pixel voltage V PE and the second common voltage bus Com2.
  • the second embodiment can make the polarity of the odd column sub-pixels of all odd rows of the liquid crystal display panel in the previous frame picture be +5V, the polarity of the even column sub-pixels is -5V, and the odd numbers of all even rows
  • the column sub-pixels have a polarity of -5V, and the even-numbered column sub-pixels have a polarity of +5V.
  • the odd column sub-pixels of the row have a polarity of -5V
  • the even column sub-pixels have a polarity of +5V
  • the odd-column sub-pixels of all even rows have a polarity of +5V
  • the even-column sub-pixels have a polarity of -5V.
  • the dot inversion mode is implemented in the front and rear two frames, which can improve the image sticking, crosstalk, and flicker of the liquid crystal display panel, and improve the display effect of the liquid crystal display panel.
  • the liquid crystal display panel structure of the present invention has a first common voltage bus and a second common voltage bus respectively disposed on both sides of the effective display area of the liquid crystal display panel, and the first common voltage bus is transmitted first.
  • the common voltage Vcom1 is different from the second common voltage Vcom2 transmitted by the second common voltage bus.

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Abstract

一种液晶显示面板结构，在液晶显示面板的有效显示区域（AA）两侧分别设置第一公共电压总线（Com1）与第二公共电压总线（Com2），且第一公共电压总线（Com1）传输的第一公共电压Vcom1不同于第二公共电压总线（Com2）传输的第二公共电压Vcom2，搭配不同的子像素布线方式，能够实现行反转或点反转的驱动显示模式，改善液晶显示面板的图像残留、串扰、以及闪烁等不良问题，提升液晶显示面板的显示效果。

Description

液晶显示面板结构 技术领域
本发明涉及显示技术领域，尤其涉及一种液晶显示面板结构。
背景技术
液晶显示器(Liquid Crystal Display，LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用，如：液晶电视、移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等，在平板显示领域中占主导地位。
现有市场上的液晶显示器大部分为背光型液晶显示器，其包括液晶显示面板及背光模组(backlight module)。液晶显示面板的工作原理是在薄膜晶体管阵列基板(Thin Film Transistor Array Substrate，TFT Array Substrate)与彩色滤光片(Color Filter，CF)基板之间灌入液晶分子，并在两片基板上施加驱动电压来控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面。
液晶显示面板包括多个呈阵列式排布的像素，每一像素又包括多个子像素。每个子像素电性连接一个薄膜晶体管(TFT)，TFT的栅极(Gate)连接至水平扫描线，源极(Drain)连接至竖直方向的数据线，漏极(Source)则连接至像素电极。在水平扫描线上施加足够的电压，会使得电性连接至该条扫描线上的所有TFT打开，从而数据线上的信号电压能够写入子像素，控制液晶的透光度，实现显示效果。
传统的液晶面板在设计时，为了提升面板的显示效果跟性能，往往在像素阵列上实现极性反转的方式来驱动。通常的做法，为了降低驱动器(IC)的驱动功耗，往往实现的是帧反转(Frame Inversion)，或列反转(Column Inversion)模式。但是，帧反转或列反转模式常会引起液晶显示面板的图像残留(Image Sticking，IS)、串扰(crosstalk)、以及闪烁(Flicker)的问题，尤其是在低温多晶硅为半导体材料的液晶显示面板中，帧反转或列反转的反转模式很容易引起串扰，影响画面的显示质量。
请参阅图1，为一种现有的液晶显示面板结构的示意图，包括数条相互平行且沿横向分布的扫描线(如G(1)、G(2)、G(3)、G(4)等)、数条相互平行且沿纵向分布的数据线(如D(1)、D(2)、D(3)、D(4)等)、呈矩阵式排布的多个子像素P、分别对应每一行子像素P设置的横向的数条公共电压分支 走线(如L(1)、L(2)、L(3)、L(4)等)、以及纵向的公共电压总线Com，每一条公共电压分支走线均直接电性连接公共电压总线Com，使得整个液晶显示面板内所有像素的公共电压均为一个恒定电位Vcom。扫描线的驱动方式是双边逐行扫描，由于整个液晶显示面板内所有像素的公共电压均为一个恒定电位Vcom，所以当阵列子像素P中的TFT开启时，驱动液晶旋转的驱动电压ΔV＝VPE-Vcom，其中VPE表示某个子像素的像素电压，Vcom表示公共电压。任意一个子像素内，如果ΔV＞0，表示子像素的驱动电压为正极性，ΔV＜0，则表示子像素的驱动电压为负极性。例如，当整个IC在某一帧全部输出的电压值使得ΔV＞0时，液晶显示面板的极性显示效果如图2所示，在该帧画面内，所有子像素的驱动电压均为正极性；直到下一帧的时间内，IC给出的信号使得ΔV＜0时，液晶显示面板内部进行整帧的极性切换，所有子像素的驱动电压均为负极性(如图3所示)，即实现了帧反转模式，但是帧反转模式存在较严重的图像残留、串扰、以及闪烁的问题，画面的显示质量较差。
发明内容
本发明的目的在于提供一种液晶显示面板结构，能够实现行反转或点反转的驱动显示模式，改善液晶显示面板的图像残留、串扰、以及闪烁等不良问题，提升液晶显示面板的显示效果。
为实现上述目的，本发明提供一种液晶显示面板结构。可选的，本发明的液晶显示面板结构包括于有效显示区域内设置的多条相互平行且沿横向分布的扫描线、多条相互平行且沿纵向分布的数据线、呈矩阵式排布的多个子像素、分别对应每一行子像素设置的横向的数条公共电压分支走线、以及分别设置于有效显示区域两侧的纵向的第一公共电压总线与第二公共电压总线；所述第一公共电压总线传输的第一公共电压Vcom1不同于第二公共电压总线传输的第二公共电压Vcom2；
每一子像素包括一薄膜晶体管、及相互并联的存储电容与液晶电容；
设s为正整数，第s列所有子像素的薄膜晶体管的源极均对应连接第s条数据线；
设n为正整数，第n条扫描线对应位于第n行子像素的上方，第n条公共电压分支走线对应位于第n行子像素的下方；第n行所有子像素的薄膜晶体管的栅极均对应连接第n条扫描线；
设i为奇数，第i行的任一子像素的存储电容与液晶电容的一端电性连接对应薄膜晶体管的漏极，另一端电性连接对应的第i条公共电压分支走 线；所述对应的第i条公共电压分支走线通过一第一开关薄膜晶体管电性连接至第二公共电压总线；所述第一开关薄膜晶体管的栅极电性连接对应的第i条扫描线，源极电性连接第二公共电压总线，漏极电性连接对应的第i条公共电压分支走线；
第i+1行的任一子像素的存储电容与液晶电容的一端电性连接对应薄膜晶体管的漏极，另一端电性连接对应的第i+1条公共电压分支走线；所述对应的第i+1条公共电压分支走线通过一第二开关薄膜晶体管电性连接至第一公共电压总线；所述第二开关薄膜晶体管的栅极电性连接对应的第i+1条扫描线，源极电性连接第一公共电压总线，漏极电性连接对应的第i+1条公共电压分支走线。
所述第一公共电压总线传输的第一公共电压Vcom1与第二公共电压总线传输的第二公共电压Vcom2的其中之一大于像素电压，另一个小于像素电压。
在前后相邻的两帧画面内，所述第一公共电压总线传输的第一公共电压Vcom1与第二公共电压总线传输的第二公共电压Vcom2的值进行调换，实现行反转模式。
各个薄膜晶体管均为低温多晶硅薄膜晶体管。
可选的，本发明的液晶显示面板结构包括于有效显示区域内设置的多条相互平行且沿横向分布的扫描线、多条相互平行且沿纵向分布的数据线、呈矩阵式排布的多个子像素、分别对应每一行子像素设置的横向的数条公共电压分支走线、分别设置于有效显示区域两侧的纵向的第一公共电压总线与第二公共电压总线、于有效显示区域外设置的横向的第零条扫描线、以及于有效显示区域外设置的横向的第零条公共电压分支走线；所述第一公共电压总线传输的第一公共电压Vcom1不同于第二公共电压总线传输的第二公共电压Vcom2；
每一子像素包括一薄膜晶体管、及相互并联的存储电容与液晶电容；
设s为正整数，第s列所有子像素的薄膜晶体管的源极均对应连接第s条数据线；
设n为正整数，第n条扫描线对应位于第n行子像素的上方，第n条公共电压分支走线对应位于第n行子像素的下方；第n行所有子像素的薄膜晶体管的栅极均对应连接第n条扫描线；
设i为奇数，第i行的任一子像素的存储电容与液晶电容的一端电性连接对应薄膜晶体管的漏极，第i行的奇数列子像素的存储电容与液晶电容的另一端电性连接对应的第i条公共电压分支走线，第i行的偶数列子像素的 存储电容与液晶电容的另一端电性连接第i-1条公共电压分支走线；所述对应的第i条公共电压分支走线通过一第一开关薄膜晶体管电性连接至第一公共电压总线，所述第i-1条公共电压分支走线通过一第二开关薄膜晶体管电性连接至第二公共电压总线；
第i+1行的任一子像素的存储电容与液晶电容的一端电性连接对应薄膜晶体管的漏极，第i+1行的奇数列子像素的存储电容与液晶电容的另一端电性连接对应的第i+1条公共电压分支走线，第i+1行的偶数列子像素的存储电容与液晶电容的另一端电性连接第i条公共电压分支走线；所述对应的第i+1条公共电压分支走线通过一第二开关薄膜晶体管电性连接至第二公共电压总线；
所述第一开关薄膜晶体管的栅极电性连接对应的第奇数条扫描线，源极电性连接第一公共电压总线，漏极电性连接对应的第奇数条公共电压分支走线；所述第二开关薄膜晶体管的栅极电性连接对应的第偶数条扫描线、或第零条扫描线，源极电性连接第二公共电压总线，漏极电性连接对应的第偶数条公共电压分支走线、或第零条公共电压分支走线。
所述第一公共电压总线传输的第一公共电压Vcom1与第二公共电压总线传输的第二公共电压Vcom2的其中之一大于像素电压，另一个小于像素电压。
在前后相邻的两帧画面内，所述第一公共电压总线传输的第一公共电压Vcom1与第二公共电压总线传输的第二公共电压Vcom2的值进行调换，实现点反转模式。
各个薄膜晶体管均为低温多晶硅薄膜晶体管。
本发明还提供一种液晶显示面板结构，包括于有效显示区域内设置的多条相互平行且沿横向分布的扫描线、多条相互平行且沿纵向分布的数据线、呈矩阵式排布的多个子像素、分别对应每一行子像素设置的横向的数条公共电压分支走线、以及分别设置于有效显示区域两侧的纵向的第一公共电压总线与第二公共电压总线；所述第一公共电压总线传输的第一公共电压Vcom1不同于第二公共电压总线传输的第二公共电压Vcom2；
每一子像素包括一薄膜晶体管、及相互并联的存储电容与液晶电容；
设s为正整数，第s列所有子像素的薄膜晶体管的源极均对应连接第s条数据线；
设n为正整数，第n条扫描线对应位于第n行子像素的上方，第n条公共电压分支走线对应位于第n行子像素的下方；第n行所有子像素的薄膜晶体管的栅极均对应连接第n条扫描线；
设i为奇数，第i行的任一子像素的存储电容与液晶电容的一端电性连接对应薄膜晶体管的漏极，另一端电性连接对应的第i条公共电压分支走线；所述对应的第i条公共电压分支走线通过一第一开关薄膜晶体管电性连接至第二公共电压总线；所述第一开关薄膜晶体管的栅极电性连接对应的第i条扫描线，源极电性连接第二公共电压总线，漏极电性连接对应的第i条公共电压分支走线；
第i+1行的任一子像素的存储电容与液晶电容的一端电性连接对应薄膜晶体管的漏极，另一端电性连接对应的第i+1条公共电压分支走线；所述对应的第i+1条公共电压分支走线通过一第二开关薄膜晶体管电性连接至第一公共电压总线；所述第二开关薄膜晶体管的栅极电性连接对应的第i+1条扫描线，源极电性连接第一公共电压总线，漏极电性连接对应的第i+1条公共电压分支走线；
其中，所述第一公共电压总线传输的第一公共电压Vcom1与第二公共电压总线传输的第二公共电压Vcom2的其中之一大于像素电压，另一个小于像素电压；
其中，在前后相邻的两帧画面内，所述第一公共电压总线传输的第一公共电压Vcom1与第二公共电压总线传输的第二公共电压Vcom2的值进行调换，实现行反转模式；
其中，各个薄膜晶体管均为低温多晶硅薄膜晶体管。
本发明的有益效果：本发明提供的一种液晶显示面板结构，通过在液晶显示面板的有效显示区域两侧分别设置第一公共电压总线与第二公共电压总线，且所述第一公共电压总线传输的第一公共电压Vcom1不同于第二公共电压总线传输的第二公共电压Vcom2，搭配不同的子像素布线方式，能够实现行反转或点反转的驱动显示模式，改善液晶显示面板的图像残留、串扰、以及闪烁等不良问题，提升液晶显示面板的显示效果。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为一种现有的液晶显示面板结构的示意图；
图2、图3分别为图1所示的液晶显示面板在相邻两帧画面显示时的极性示意图；
图4为本发明的液晶显示面板结构的第一实施例的示意图；
图5、图6分别为图4所示的液晶显示面板在相邻两帧画面显示时的极性示意图；
图7为本发明的液晶显示面板结构的第二实施例的示意图；
图8、图9分别为图7所示的液晶显示面板在相邻两帧画面显示时的极性示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
本发明提供一种液晶显示面板结构。请同时参阅图4、图5、与图6，为本发明的液晶显示面板结构的第一实施例，该第一实施例包括于有效显示区域AA内设置的多条相互平行且沿横向分布的扫描线、多条相互平行且沿纵向分布的数据线、呈矩阵式排布的多个子像素P、分别对应每一行子像素P设置的横向的数条公共电压分支走线、以及分别设置于有效显示区域AA两侧的纵向的第一公共电压总线Com1与第二公共电压总线Com2。
如图4所示，每一子像素P包括一薄膜晶体管T、及相互并联的存储电容C1与液晶电容C2。
设s为正整数，第s列所有子像素P的薄膜晶体管T的源极均对应连接第s条数据线D(s)，例如：第一列所有子像素P的薄膜晶体管T的源极对应连接第一条数据线D(1)、第二列所有子像素P的薄膜晶体管T的源极对应连接第二条数据线D(2)，依次类推。
设n为正整数，第n条扫描线G(n)对应位于第n行子像素P的上方，第n条公共电压分支走线L(n)对应位于第n行子像素P的下方；第n行所有子像素P的薄膜晶体管T的栅极均对应连接第n条扫描线G(n)。例如：第一条扫描线G(1)对应位于第一行子像素P的上方，第一条公共电压分支走线L(1)对应位于第一行子像素P的下方；第一行所有子像素P的薄膜晶体管T的栅极均对应连接第一条扫描线G(1)；第二条扫描线G(2)对应位于第二行子像素P的上方，第二条公共电压分支走线L(2)对应位于第二行子像素P的下方；第二行所有子像素P的薄膜晶体管T的栅极均对应连接第二条扫描线G(2)，依次类推。
设i为奇数，第i行即奇数行的任一子像素P的存储电容C1与液晶电容C2的一端电性连接对应薄膜晶体管T的漏极，另一端电性连接对应的第i条公共电压分支走线L(i)；所述对应的第i条公共电压分支走线L(i)通过 一第一开关薄膜晶体管T10电性连接至第二公共电压总线Com2。所述第一开关薄膜晶体管T10的栅极电性连接对应的第i条扫描线G(i)，源极电性连接第二公共电压总线Com2，漏极电性连接对应的第i条公共电压分支走线L(i)。
第i+1行即偶数行的任一子像素P的存储电容C1与液晶电容C2的一端电性连接对应薄膜晶体管T的漏极，另一端电性连接对应的第i+1条公共电压分支走线L(i+1)；所述对应的第i+1条公共电压分支走线L(i+1)通过一第二开关薄膜晶体管T20电性连接至第一公共电压总线Com1。所述第二开关薄膜晶体管T20的栅极电性连接对应的第i+1条扫描线G(i+1)，源极电性连接第一公共电压总线Com1，漏极电性连接对应的第i+1条公共电压分支走线L(i+1)。
具体地，各个薄膜晶体管均为低温多晶硅薄膜晶体管。
特别需要说明的是：所述第一公共电压总线Com1传输的第一公共电压Vcom1不同于第二公共电压总线Com2传输的第二公共电压Vcom2。进一步地，所述第一公共电压总线Com1传输的第一公共电压Vcom1与第二公共电压总线Com2传输的第二公共电压Vcom2的其中之一大于像素电压，另一个小于像素电压，且在前后相邻的两帧画面内，所述第一公共电压总线Com1传输的第一公共电压Vcom1与第二公共电压总线Com2传输的第二公共电压Vcom2的值进行调换。
结合图4与图5，在前后相邻的两帧画面的前一帧画面内：
当第i行即奇数行像素所对应的第i条扫描线提供扫描信号时，第i行的所有子像素内的薄膜晶体管T全部打开，对应于第i行子像素设置的第一开关薄膜晶体管T10打开，导通第i条公共电压分支走线L(i)与第二公共电压总线Com2，使得第i行子像素的驱动电压ΔV为像素电压VPE与第二公共电压总线Com2传输的第二公共电压Vcom2之差，即ΔV＝VPE-Vcom2。
当第i+1行即偶数行像素所对应的第i+1条扫描线提供扫描信号时，第i行的所有子像素内的薄膜晶体管T全部关闭,且第i行子像素的像素电压VPE与第二公共电压总线Com2传输的第二公共电压Vcom2之间的压差保持不变，第i+1行的所有子像素内的薄膜晶体管T全部打开，对应于第i+1行子像素设置的第二开关薄膜晶体管T20打开，导通第i+1条公共电压分支走线L(i+1)与第一公共电压总线Com1，使得第i+1行子像素的驱动电压ΔV为像素电压VPE与第一公共电压总线Com1传输的第一公共电压Vcom1之差，即ΔV＝VPE-Vcom1。
例如，当所有的数据线输出的像素电压VPE为+5V，Vcom2为0V，Vcom1 为+10V，则第i行即奇数行的子像素的极性为+5V，第i+1行即偶数行的子像素的极性为-5V。
结合图4与图6，在前后相邻的两帧画面的后一帧画面内：
由于所述第一公共电压总线Com1传输的第一公共电压Vcom1与第二公共电压总线Com2传输的第二公共电压Vcom2的值进行调换，则第i行即奇数行的子像素的极性为-5V，第i+1行即偶数行的子像素的极性为+5V。
前后两帧画面实现了行反转模式，能够改善液晶显示面板的图像残留、串扰、以及闪烁等不良问题，提升液晶显示面板的显示效果。
请同时参阅图7、图8、与图9，为本发明的液晶显示面板结构的第二实施例，该第二实施例包括于有效显示区域AA内设置的多条相互平行且沿横向分布的扫描线、多条相互平行且沿纵向分布的数据线、呈矩阵式排布的多个子像素P、分别对应每一行子像素P设置的横向的数条公共电压分支走线、分别设置于有效显示区域AA两侧的纵向的第一公共电压总线Com1与第二公共电压总线Com2、于有效显示区域AA外设置的横向的第零条扫描线G(0)、以及于有效显示区域AA外设置的横向的第零条公共电压分支走线L(0)。
如图7所示，每一子像素P包括一薄膜晶体管T、及相互并联的存储电容C1与液晶电容C2。
设s为正整数，第s列所有子像素P的薄膜晶体管T的源极均对应连接第s条数据线D(s)，例如：第一列所有子像素P的薄膜晶体管T的源极对应连接第一条数据线D(1)、第二列所有子像素P的薄膜晶体管T的源极对应连接第二条数据线D(2)，依次类推。
设n为正整数，第n条扫描线G(n)对应位于第n行子像素P的上方，第n条公共电压分支走线L(n)对应位于第n行子像素P的下方；第n行所有子像素P的薄膜晶体管T的栅极均对应连接第n条扫描线G(n)。例如：第一条扫描线G(1)对应位于第一行子像素P的上方，第一条公共电压分支走线L(1)对应位于第一行子像素P的下方；第一行所有子像素P的薄膜晶体管T的栅极均对应连接第一条扫描线G(1)；第二条扫描线G(2)对应位于第二行子像素P的上方，第二条公共电压分支走线L(2)对应位于第二行子像素P的下方；第二行所有子像素P的薄膜晶体管T的栅极均对应连接第二条扫描线G(2)，依次类推。
设i为奇数，第i行即奇数行的任一子像素P的存储电容C1与液晶电容C2的一端电性连接对应薄膜晶体管T的漏极，第i行的奇数列子像素P的存储电容C1与液晶电容C2的另一端电性连接对应的第i条公共电压分 支走线L(i)，第i行的偶数列子像素P的存储电容C1与液晶电容C2的另一端电性连接第i-1条公共电压分支走线L(i-1)；所述对应的第i条公共电压分支走线L(i)通过一第一开关薄膜晶体管T10电性连接至第一公共电压总线Com1，所述第i-1条公共电压分支走线L(i-1)通过一第二开关薄膜晶体管T20电性连接至第二公共电压总线Com2。
例如：第一行的任一子像素P的存储电容C1与液晶电容C2的一端电性连接对应薄膜晶体管T的漏极，第一行的奇数列子像素P的存储电容C1与液晶电容C2的另一端电性连接对应的第一条公共电压分支走线L(1)，第一行的偶数列子像素P的存储电容C1与液晶电容C2的另一端电性连接第零条公共电压分支走线L(0)；所述对应的第一条公共电压分支走线L(1)通过一第一开关薄膜晶体管T10电性连接至第一公共电压总线Com1，所述第零条公共电压分支走线L(0)通过一第二开关薄膜晶体管T20电性连接至第二公共电压总线Com2。第三行的任一子像素P的存储电容C1与液晶电容C2的一端电性连接对应薄膜晶体管T的漏极，第三行的奇数列子像素P的存储电容C1与液晶电容C2的另一端电性连接对应的第三条公共电压分支走线L(3)，第三行的偶数列子像素P的存储电容C1与液晶电容C2的另一端电性连接第二条公共电压分支走线L(2)；所述对应的第三条公共电压分支走线L(3)通过一第一开关薄膜晶体管T10电性连接至第一公共电压总线Com1，所述第二条公共电压分支走线L(2)通过一第二开关薄膜晶体管T20电性连接至第二公共电压总线Com2。依次类推。
第i+1行即偶数行的任一子像素P的存储电容C1与液晶电容C2的一端电性连接对应薄膜晶体管T的漏极，第i+1行的奇数列子像素P的存储电容C1与液晶电容C2的另一端电性连接对应的第i+1条公共电压分支走线L(i+1)，第i+1行的偶数列子像素P的存储电容C1与液晶电容C2的另一端电性连接第i条公共电压分支走线L(i)；所述对应的第i+1条公共电压分支走线L(i+1)通过一第二开关薄膜晶体管T20电性连接至第二公共电压总线Com2。
例如：第二行的任一子像素P的存储电容C1与液晶电容C2的一端电性连接对应薄膜晶体管T的漏极，第二行的奇数列子像素P的存储电容C1与液晶电容C2的另一端电性连接对应的第二条公共电压分支走线L(2)，第二行的偶数列子像素P的存储电容C1与液晶电容C2的另一端电性连接第一条公共电压分支走线L(1)；所述对应的第二条公共电压分支走线L(2)通过一第二开关薄膜晶体管T20电性连接至第二公共电压总线Com2。
所述第一开关薄膜晶体管T10的栅极电性连接对应的第奇数条扫描线 G(i)，源极电性连接第一公共电压总线Com1，漏极电性连接对应的第奇数条公共电压分支走线L(i)；所述第二开关薄膜晶体管T20的栅极电性连接对应的第偶数条扫描线G(i+1)、或第零条扫描线G(0)，源极电性连接第二公共电压总线Com2，漏极电性连接对应的第偶数条公共电压分支走线L(i+1)、或第零条公共电压分支走线L(0)。
具体地，各个薄膜晶体管均为低温多晶硅薄膜晶体管。
特别需要说明的是：所述第一公共电压总线Com1传输的第一公共电压Vcom1不同于第二公共电压总线Com2传输的第二公共电压Vcom2。进一步地，所述第一公共电压总线Com1传输的第一公共电压Vcom1与第二公共电压总线Com2传输的第二公共电压Vcom2的其中之一大于像素电压，另一个小于像素电压，且在前后相邻的两帧画面内，所述第一公共电压总线Com1传输的第一公共电压Vcom1与第二公共电压总线Com2传输的第二公共电压Vcom2的值进行调换。
结合图7与图8，在前后相邻的两帧画面的前一帧画面内：
当第零条扫描线G(0)提供扫描信号时，对应于第零条公共电压分支走线L(0)设置的第二开关薄膜晶体管T20打开，导通第零条公共电压分支走线L(0)与第二公共电压总线Com2，使得第一行偶数列子像素的公共电压为第二公共电压总线Com2传输的第二公共电压Vcom2。
紧接着，第一条扫描线G(1)提供扫描信号，第一行的所有子像素内的薄膜晶体管T全部打开，对应于第一条公共电压分支走线L(1)设置的第一开关薄膜晶体管T10打开，导通第一条公共电压分支走线L(1)与第一公共电压总线Com1，使得第一行奇数列子像素的公共电压为第一公共电压总线Com1传输的第一公共电压Vcom1，同时使得第二行偶数列子像素的公共电压为第一公共电压总线Com1传输的第一公共电压Vcom1。假设所有的数据线输出的像素电压VPE为+5V，Vcom2为+10V，Vcom1为0V，则第一行奇数列子像素的驱动电压ΔV为像素电压VPE与第一公共电压总线Com1传输的第一公共电压Vcom1之差，即ΔV＝VPE-Vcom1＝+5V；而第一行偶数列子像素的驱动电压ΔV为像素电压VPE与第二公共电压总线Com2传输的第二公共电压Vcom2之差，即ΔV＝VPE-Vcom2＝-5V。即第一行奇数列子像素的极性为+5V，第一行偶数列子像素的极性为-5V。
然后，第二条扫描线G(2)提供扫描信号，第二行的所有子像素内的薄膜晶体管T全部打开，对应于第二条公共电压分支走线L(2)设置的第二开关薄膜晶体管T20打开，导通第二条公共电压分支走线L(2)与第二公共电压总线Com2，使得第二行奇数列子像素的公共电压为第二公共电压总线 Com2传输的第二公共电压Vcom2，同时使得第三行偶数列子像素的公共电压为第二公共电压总线Com2传输的第二公共电压Vcom2。假设所有的数据线输出的像素电压VPE为+5V，Vcom2为+10V，Vcom1为0V，则第二行奇数列子像素的驱动电压ΔV为像素电压VPE与第二公共电压总线Com2传输的第二公共电压Vcom2之差，即ΔV＝VPE-Vcom2＝-5V；而第二行偶数列子像素的驱动电压ΔV为像素电压VPE与第一公共电压总线Com1传输的第一公共电压Vcom1之差，即ΔV＝VPE-Vcom1＝+5V。即第二行奇数列子像素的极性为-5V，第二行偶数列子像素的极性为+5V。
依次类推，该第二实施例能够使得液晶显示面板在前一帧画面内的所有奇数行的奇数列子像素的极性为+5V，偶数列子像素的极性为-5V，而所有偶数行的奇数列子像素的极性为-5V，偶数列子像素的极性为+5V。
结合图7与图9，在前后相邻的两帧画面的后一帧画面内：
由于所述第一公共电压总线Com1传输的第一公共电压Vcom1与第二公共电压总线Com2传输的第二公共电压Vcom2的值进行调换，则能够使得液晶显示面板在后一帧画面内的所有奇数行的奇数列子像素的极性为-5V，偶数列子像素的极性为+5V，而所有偶数行的奇数列子像素的极性为+5V，偶数列子像素的极性为-5V。
前后两帧画面实现了点反转模式，能够改善液晶显示面板的图像残留、串扰、以及闪烁等不良问题，提升液晶显示面板的显示效果。
综上所述，本发明的液晶显示面板结构，通过在液晶显示面板的有效显示区域两侧分别设置第一公共电压总线与第二公共电压总线，且所述第一公共电压总线传输的第一公共电压Vcom1不同于第二公共电压总线传输的第二公共电压Vcom2，搭配不同的子像素布线方式，能够实现行反转或点反转的驱动显示模式，改善液晶显示面板的图像残留、串扰、以及闪烁等不良问题，提升液晶显示面板的显示效果。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (9)

  1. 一种液晶显示面板结构，包括于有效显示区域内设置的多条相互平行且沿横向分布的扫描线、多条相互平行且沿纵向分布的数据线、呈矩阵式排布的多个子像素、分别对应每一行子像素设置的横向的数条公共电压分支走线、以及分别设置于有效显示区域两侧的纵向的第一公共电压总线与第二公共电压总线；所述第一公共电压总线传输的第一公共电压Vcom1不同于第二公共电压总线传输的第二公共电压Vcom2；
    每一子像素包括一薄膜晶体管、及相互并联的存储电容与液晶电容；
    设s为正整数，第s列所有子像素的薄膜晶体管的源极均对应连接第s条数据线；
    设n为正整数，第n条扫描线对应位于第n行子像素的上方，第n条公共电压分支走线对应位于第n行子像素的下方；第n行所有子像素的薄膜晶体管的栅极均对应连接第n条扫描线；
    设i为奇数，第i行的任一子像素的存储电容与液晶电容的一端电性连接对应薄膜晶体管的漏极，另一端电性连接对应的第i条公共电压分支走线；所述对应的第i条公共电压分支走线通过一第一开关薄膜晶体管电性连接至第二公共电压总线；所述第一开关薄膜晶体管的栅极电性连接对应的第i条扫描线，源极电性连接第二公共电压总线，漏极电性连接对应的第i条公共电压分支走线；
    第i+1行的任一子像素的存储电容与液晶电容的一端电性连接对应薄膜晶体管的漏极，另一端电性连接对应的第i+1条公共电压分支走线；所述对应的第i+1条公共电压分支走线通过一第二开关薄膜晶体管电性连接至第一公共电压总线；所述第二开关薄膜晶体管的栅极电性连接对应的第i+1条扫描线，源极电性连接第一公共电压总线，漏极电性连接对应的第i+1条公共电压分支走线。
  2. 如权利要求1所述的液晶显示面板结构，其中，所述第一公共电压总线传输的第一公共电压Vcom1与第二公共电压总线传输的第二公共电压Vcom2的其中之一大于像素电压，另一个小于像素电压。
  3. 如权利要求2所述的液晶显示面板结构，其中，在前后相邻的两帧画面内，所述第一公共电压总线传输的第一公共电压Vcom1与第二公共电压总线传输的第二公共电压Vcom2的值进行调换，实现行反转模式。
  4. 如权利要求1所述的液晶显示面板结构，其中，各个薄膜晶体管均 为低温多晶硅薄膜晶体管。
  5. 一种液晶显示面板结构，包括于有效显示区域内设置的多条相互平行且沿横向分布的扫描线、多条相互平行且沿纵向分布的数据线、呈矩阵式排布的多个子像素、分别对应每一行子像素设置的横向的数条公共电压分支走线、分别设置于有效显示区域两侧的纵向的第一公共电压总线与第二公共电压总线、于有效显示区域外设置的横向的第零条扫描线、以及于有效显示区域外设置的横向的第零条公共电压分支走线；所述第一公共电压总线传输的第一公共电压Vcom1不同于第二公共电压总线传输的第二公共电压Vcom2；
    每一子像素包括一薄膜晶体管、及相互并联的存储电容与液晶电容；
    设s为正整数，第s列所有子像素的薄膜晶体管的源极均对应连接第s条数据线；
    设n为正整数，第n条扫描线对应位于第n行子像素的上方，第n条公共电压分支走线对应位于第n行子像素的下方；第n行所有子像素的薄膜晶体管的栅极均对应连接第n条扫描线；
    设i为奇数，第i行的任一子像素的存储电容与液晶电容的一端电性连接对应薄膜晶体管的漏极，第i行的奇数列子像素的存储电容与液晶电容的另一端电性连接对应的第i条公共电压分支走线，第i行的偶数列子像素的存储电容与液晶电容的另一端电性连接第i-1条公共电压分支走线；所述对应的第i条公共电压分支走线通过一第一开关薄膜晶体管电性连接至第一公共电压总线，所述第i-1条公共电压分支走线通过一第二开关薄膜晶体管电性连接至第二公共电压总线；
    第i+1行的任一子像素的存储电容与液晶电容的一端电性连接对应薄膜晶体管的漏极，第i+1行的奇数列子像素的存储电容与液晶电容的另一端电性连接对应的第i+1条公共电压分支走线，第i+1行的偶数列子像素的存储电容与液晶电容的另一端电性连接第i条公共电压分支走线；所述对应的第i+1条公共电压分支走线通过一第二开关薄膜晶体管电性连接至第二公共电压总线；
    所述第一开关薄膜晶体管的栅极电性连接对应的第奇数条扫描线，源极电性连接第一公共电压总线，漏极电性连接对应的第奇数条公共电压分支走线；所述第二开关薄膜晶体管的栅极电性连接对应的第偶数条扫描线、或第零条扫描线，源极电性连接第二公共电压总线，漏极电性连接对应的第偶数条公共电压分支走线、或第零条公共电压分支走线。
  6. 如权利要求5所述的液晶显示面板结构，其中，所述第一公共电压 总线传输的第一公共电压Vcom1与第二公共电压总线传输的第二公共电压Vcom2的其中之一大于像素电压，另一个小于像素电压。
  7. 如权利要求6所述的液晶显示面板结构，其中，在前后相邻的两帧画面内，所述第一公共电压总线传输的第一公共电压Vcom1与第二公共电压总线传输的第二公共电压Vcom2的值进行调换，实现点反转模式。
  8. 如权利要求5所述的液晶显示面板结构，其中，各个薄膜晶体管均为低温多晶硅薄膜晶体管。
  9. 一种液晶显示面板结构，包括于有效显示区域内设置的多条相互平行且沿横向分布的扫描线、多条相互平行且沿纵向分布的数据线、呈矩阵式排布的多个子像素、分别对应每一行子像素设置的横向的数条公共电压分支走线、以及分别设置于有效显示区域两侧的纵向的第一公共电压总线与第二公共电压总线；所述第一公共电压总线传输的第一公共电压Vcom1不同于第二公共电压总线传输的第二公共电压Vcom2；
    每一子像素包括一薄膜晶体管、及相互并联的存储电容与液晶电容；
    设s为正整数，第s列所有子像素的薄膜晶体管的源极均对应连接第s条数据线；
    设n为正整数，第n条扫描线对应位于第n行子像素的上方，第n条公共电压分支走线对应位于第n行子像素的下方；第n行所有子像素的薄膜晶体管的栅极均对应连接第n条扫描线；
    设i为奇数，第i行的任一子像素的存储电容与液晶电容的一端电性连接对应薄膜晶体管的漏极，另一端电性连接对应的第i条公共电压分支走线；所述对应的第i条公共电压分支走线通过一第一开关薄膜晶体管电性连接至第二公共电压总线；所述第一开关薄膜晶体管的栅极电性连接对应的第i条扫描线，源极电性连接第二公共电压总线，漏极电性连接对应的第i条公共电压分支走线；
    第i+1行的任一子像素的存储电容与液晶电容的一端电性连接对应薄膜晶体管的漏极，另一端电性连接对应的第i+1条公共电压分支走线；所述对应的第i+1条公共电压分支走线通过一第二开关薄膜晶体管电性连接至第一公共电压总线；所述第二开关薄膜晶体管的栅极电性连接对应的第i+1条扫描线，源极电性连接第一公共电压总线，漏极电性连接对应的第i+1条公共电压分支走线；
    其中，所述第一公共电压总线传输的第一公共电压Vcom1与第二公共电压总线传输的第二公共电压Vcom2的其中之一大于像素电压，另一个小于像素电压；
    其中，在前后相邻的两帧画面内，所述第一公共电压总线传输的第一公共电压Vcom1与第二公共电压总线传输的第二公共电压Vcom2的值进行调换，实现行反转模式；
    其中，各个薄膜晶体管均为低温多晶硅薄膜晶体管。
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