WO2017092617A1 - Procédé d'estimation d'erreurs, station de base, et terminal - Google Patents

Procédé d'estimation d'erreurs, station de base, et terminal Download PDF

Info

Publication number
WO2017092617A1
WO2017092617A1 PCT/CN2016/107298 CN2016107298W WO2017092617A1 WO 2017092617 A1 WO2017092617 A1 WO 2017092617A1 CN 2016107298 W CN2016107298 W CN 2016107298W WO 2017092617 A1 WO2017092617 A1 WO 2017092617A1
Authority
WO
WIPO (PCT)
Prior art keywords
crc
eec
check
bit
code
Prior art date
Application number
PCT/CN2016/107298
Other languages
English (en)
Chinese (zh)
Inventor
蔺同宇
王浩
望育梅
田春长
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Publication of WO2017092617A1 publication Critical patent/WO2017092617A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W28/00—Network traffic management; Network resource management
    • H04W28/02—Traffic management, e.g. flow control or congestion control
    • H04W28/04—Error control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0075—Transmission of coding parameters to receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0078—Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location
    • H04L1/0079—Formats for control data
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W64/00—Locating users or terminals or network equipment for network management purposes, e.g. mobility management

Definitions

  • the present invention relates to the field of communications technologies, and in particular, to a method, a base station, and a terminal for error estimation.
  • FEC Forward Error Correction
  • HARQ Hybrid Automatic Repeat Quest
  • retransmission of the entire codeword undoubtedly wastes additional transmission resources, and in multimedia applications with high real-time requirements, excessive retransmission may affect the user experience. If the wrong position of the coded bits can be located, the error can be corrected by transmitting the relevant data in a targeted manner. Compared with automatic retransmission, the latter can guarantee the reliability of data transmission with a small amount of redundancy.
  • the embodiment of the invention provides a method, a base station and a terminal for erroneous estimation, so as to solve the problem that the transmission resource utilization and the transmission reliability are unbalanced in the video data service.
  • a first aspect of the present invention provides a method of erroneous estimation, comprising:
  • the base station constructs a first code block, the first code block including information bits, error estimation coding EEC check Bit and cyclic redundancy CRC check bits;
  • the performing, by the base station, the first code block includes:
  • the highest index of the CRC generating polynomial is 8, and the sequence of the CRC generating polynomial is the following Any one:
  • a second aspect of the present invention provides a method of erroneous estimation, comprising:
  • the terminal performs error estimation on the corresponding data according to the EEC check bit and the CRC check code.
  • the method further includes:
  • the EEC packet miss detection is checked based on the absolute value of the soft information generated by the decision at the time of channel decoding.
  • a third aspect of the embodiments of the present invention provides a base station, including:
  • a constructing unit configured to construct a first code block, where the first code block includes an information bit, an error estimation coding EEC check bit, and a cyclic redundancy CRC check bit;
  • a configuration unit configured to configure a CRC generator polynomial, generate a CRC check code according to the CRC generation polynomial, the CRC generation polynomial first coefficient and the last bit coefficient are both 1 and the number of items in the CRC generation polynomial with a coefficient of 1 is even;
  • a modulating unit configured to perform a CRC check according to the CRC check code and complete channel coding to form a second code block, and the second code block is modulated and sent to a terminal, so that the terminal is configured according to the EEC
  • the bit check and the CRC check code are used for error estimation.
  • the constructing unit is specifically configured to:
  • the highest index of the CRC generating polynomial is 8, and the sequence of the CRC generating polynomial is Any one:
  • a fourth aspect of the embodiments of the present invention provides a terminal, including:
  • a receiving unit configured to receive a second code block sent by the base station
  • a demodulation unit configured to demodulate the second code block to obtain an error estimate included in the second code block a coded EEC check bit and a cyclic redundancy CRC check bit, wherein the CRC check code is generated by the base station according to a CRC generator polynomial whose first coefficient and the last bit coefficient are both 1 and the number of terms of the coefficient is even;
  • an estimating unit configured to perform error estimation on the corresponding data according to the EEC check bit and the CRC check code.
  • the terminal further includes:
  • the checking unit is configured to check the condition of the EEC packet miss detection according to the absolute value of the soft information generated by the decision at the time of channel decoding after the EEC decoding.
  • the EEC coded parity is added on the basis of the conventional CRC check, and by configuring a new CRC generator polynomial, the redundant information can be reduced, and the probability of CRC miss detection is further reduced. Therefore, data retransmission can be reduced, and the reliability of data transmission is ensured on the basis of improving the utilization of transmission resources.
  • FIG. 1 is a schematic flow chart of a first embodiment of a method for erroneous estimation according to the present invention
  • FIG. 2 is a schematic flow chart of a second embodiment of a method for erroneous estimation according to the present invention
  • FIG. 3 is a schematic structural diagram of a MAC frame constructed according to an embodiment of the present invention.
  • FIG. 4 is a schematic flow chart of a third embodiment of a method for erroneous estimation according to the present invention.
  • FIG. 5 is a schematic structural diagram of a first embodiment of a base station according to the present invention.
  • FIG. 6 is a schematic structural diagram of a second embodiment of a base station according to the present invention.
  • FIG. 7 is a schematic structural diagram of a first embodiment of a terminal according to the present invention.
  • FIG. 8 is a schematic diagram of the composition of a second embodiment of a terminal according to the present invention.
  • the network element involved in the embodiment of the present invention mainly includes a MAC layer and a physical layer (PHY) layer in the mobile communication system.
  • the MAC layer Between the PHY layer and the Radio Link Control (RLC) layer, it is the bridge between the PHY layer and the RLC layer.
  • the MAC layer implements many functions related to data processing, including channel management and mapping, packet encapsulation and decapsulation of data packets, HARQ process, data scheduling, and priority management of logical channels.
  • the LTE PHY layer mainly provides the following functional services for data transmission at the MAC layer: Transport Block (TB) error checking and error correction, rate matching, and HARQ.
  • Transport Block (TB) error checking and error correction mainly provides the following functional services for data transmission at the MAC layer: Transport Block (TB) error checking and error correction, rate matching, and HARQ.
  • Soft combining mapping of transport channels to physical channels, power control or allocation, modulation and demodulation, frequency domain time domain synchronization, physical layer measurement, multi-antenna space-time signal processing, radio frequency processing, etc.
  • CRC check When using CRC check, the sender and receiver use the same generator polynomial g(x), and the first and last bits of g(x) must have a coefficient of 1.
  • the processing method of the CRC is that the sender removes (modulo di-division) g(x) with the information data to be transmitted, and the obtained remainder is added as check data to the original data.
  • the receiver removes the received data with g(x). If the remainder is zero, it means that the transmission process has no error; if the remainder is not zero, there must be an error during the transmission.
  • the LTE system uses four formats of CRC: CRC-24A, CRC-24B, CRC-l6, and CRC-8. Its generator polynomial is as follows:
  • the CRC-24A and CRC-24B of length 24 are mainly used for shared channel data transmission.
  • the CRC-l6 of length 16 is mainly used for downlink control channel and broadcast channel data transmission, and the CRC-8 of length 8 is mainly used for channel. Transmission of Channel Quality Information (CQI) information.
  • CQI Channel Quality Information
  • the video data is taken as an example for video data, and the video data sequence needs to be compressed and encoded before the network transmission.
  • the video compression coding standard currently used is H. .264/Advanced Video Coding (AVC) or Scalable Video Coding (SVC).
  • AVC Advanced Video Coding
  • SVC Scalable Video Coding
  • the general transmission process of packaging the video data into a Media Access Control (MAC) Protocol Data Unit (PDU) and transmitting the feedback to the receiving end includes:
  • the video data is framed by the MAC layer, and then Cyclic Redundancy Check (CRC) and channel coding are performed at the physical layer (PHY), and then physical layer framing, modulation mapping, and then transmitted through the antenna.
  • CRC Cyclic Redundancy Check
  • the receiving end demodulates the data, performs channel decoding and CRC check, and determines feedback Acknowledgement (ACK) or Not-Acknowledgement (NACK) information.
  • the CRC check + channel coding is used for error detection and error correction, and the feedback ACK/NACK is used to indicate whether the current MAC PDU is successfully transmitted.
  • the invention provides an Error Estimating Coding (EEC) and CRC joint error location estimation mechanism.
  • EEC Error Estimating Coding
  • FIG. 1 is a schematic flowchart of a first embodiment of a method for estimating a fault according to the present invention.
  • the method includes:
  • the base station constructs a first code block.
  • the first code block includes an information bit, an error estimation coded EEC check bit, and a cyclic redundancy CRC check bit.
  • the first code block may be included in a MAC frame.
  • S102 configuring a CRC generator polynomial according to The CRC generation polynomial generates a CRC check code.
  • the CRC generation polynomial first coefficient and the last coefficient are both 1 and the number of terms having a coefficient of 1 in the CRC generation polynomial is an even number.
  • the probability of misjudgment in the actual environment is related to the bit error rate.
  • the CRC-24A and CRC-24B used in LTE contain the least error pattern with an even number of 1, due to the low bit error rate (10 -5 ). The more the error pattern contains 1, the lower the probability of occurrence, the false positive probability is negligible, so do not consider these error patterns too much here.
  • the CRC polynomial used in this scheme is based on the principle of the smallest even maximum odd number, that is, the odd number 1 error pattern can be detected by the EEC, and only the even number of 1 error patterns can be considered.
  • CRC-8 the minimum error pattern with 1 has 6 1s, and the CRC-24 has 1 minimum.
  • the error pattern has 10 ones.
  • the overall error probability of CRC-8 and CRC-24 is calculated first: under CRC-8, the probability of occurrence of 6-bit error is about 0.1%, assuming 32 packets, if a codeword has 3200 bits, then all cases of a 6-bit error are Then the probability of a 6-bit error misjudgment is The overall error probability is on the order of 10-17.
  • the probability of a 10-bit error occurring is about 0.01%, and the probability of a 10-bit error misjudging is The overall error probability is on the order of 10-25.
  • the overall error probability can be reduced, which is sufficient compared with the degree of error probability of CRC-24.
  • the present embodiment obtains some CRC-8 generator polynomials by ensuring that the coefficients of the first and last bits of the generator polynomial g(x) must be 1, and the intermediate items can be 0 or 1. Make them have a minimum of 1 error pattern with 6 1s, so the recommended generator polynomial is:
  • S104 Perform a CRC check according to the CRC check code and complete channel coding to form a second code block, and then modulate the second code block and send the second code block to the terminal, so that the terminal according to the EEC check bit and The CRC check code is error estimated.
  • the EEC coded parity is added on the basis of the conventional CRC check, and by configuring a new CRC generator polynomial, the redundant information can be reduced and further reduced.
  • the probability of CRC miss detection can reduce data retransmission and ensure the reliability of data transmission on the basis of improving the utilization of transmission resources.
  • FIG. 2 is a schematic flowchart of a second embodiment of a method for estimating errors according to the present invention.
  • the method includes:
  • S201 Determine an EEC packet size according to a preset accuracy of the EEC error estimation.
  • the EEC code is added.
  • This embodiment redesigns the corresponding first code block, corresponding to the new MAC frame structure.
  • the first code block is composed of three parts, the information bit, The CRC check bit and the EEC check bit are shown in Figure 9.
  • the value range of s is set to s ⁇ (0,512) bits, and each packet contains a 1-bit EEC check bit.
  • s take the maximum value that can be taken in the above range (if you want to make the EEC estimation more accurate, you can take s smaller), thus reducing the EEC check overhead, and the number of EEC packets is 8*m, the EEC packet size is known.
  • S203 Perform CRC check calculation on the information bit, configure the CRC check bit after the information bit, and compare the information bit and the CRC check bit according to the number of the EEC packets.
  • the lengths are equally divided, and the EEC check bits of each EEC packet are inserted at the equally divided positions.
  • FIG. 3 is a schematic diagram of the composition of the MAC frame constructed by the embodiment of the present invention, including information bits, CRC check bits, and shadows. 1-bit EEC check digit.
  • the CRC generation polynomial first coefficient and the last coefficient are both 1 and the number of terms having a coefficient of 1 in the CRC generation polynomial is an even number.
  • S205 Perform a CRC check according to the CRC check code and complete channel coding to form a second code block, and then modulate the second code block and send the second code block to the terminal, so that the terminal according to the EEC check bit and The CRC check code is error estimated.
  • the terminal may further check the EEC packet leak according to the absolute value of the soft information generated by the channel decoding after performing the EEC decoding. The situation of the inspection.
  • the value of the soft information is generally 100 or more or -100 or less. A value close to 0 indicates that the soft information of this bit is unreliable, so a threshold (such as an absolute value of 1) can be determined to determine which bits are in error.
  • the information bit soft information SI of the decoding error in the code word is close to 0, and the information bit of the error in the packet and the packet for estimating the EEC check miss may be determined according to this feature. The specific judgment is as follows:
  • the EEC has more than one error and it is found that there may be a missed packet when decoding, then whether the absolute soft packet contains the absolute value smaller than the absolute value of the error packet, if there are multiple such packets in the packet. The soft information bit is considered to be wrong.
  • This embodiment combines the CRC checksum EEC algorithm to reduce the probability of false positives.
  • the theoretical verification is as follows:
  • the error that appears in the defined codeword is the error pattern E. For example, if the correct codeword is 10101010101 and the transmitted codeword is 10101010011, the error pattern E is 00000000110.
  • the code length is n
  • the CRC check bit length is r
  • the number of error patterns that can be divisible by g (x) is 2 n , except An all-zero error pattern indicates no error, and the remaining error patterns can cause missed detection.
  • the number of these error patterns is 2 n -1
  • the probability of CRC miss detection is For example, the error pattern that cannot be detected by CRC-24 only accounts for the total possible error pattern. The longer the CRC number, the stronger the error detection capability, but the lower the coding efficiency.
  • the EEC (parity) length is m
  • the EEC divides the codeword into m equal length segments. If the EEC is independent of the CRC check, the missed detection probability is It can be seen that the insertion of PCE ⁇ PCRC, EEC check digit can effectively improve the accuracy of CRC check.
  • the embodiment of the invention performs CRC check on the information bits first, then performs EEC packet parity check, combines the advantages of the two coding methods, reduces the false positive rate, and determines the approximate location of the error by the result of each group check.
  • the length of the information bit, the CRC check bit, and the EEC check bit are reasonably allocated by determining the EEC packet size and the number of EEC packets, thereby ensuring that the MAC PDU can perform CRC check and EEC encoding simultaneously.
  • FIG. 4 it is a schematic flowchart of a third embodiment of a method for estimating errors according to the present invention.
  • the method includes:
  • the terminal receives a second code block sent by the base station.
  • the first code block includes an information bit, a cyclic redundancy CRC check bit, and an error estimation coding EEC check bit.
  • the CRC check code is determined by the base station according to the first bit coefficient and the last bit coefficient, and the coefficient is 1.
  • the number of items is an even number of CRC generator polynomial generation.
  • the highest index of the CRC generator polynomial is 8, and the sequence of the CRC generator polynomial is any one of the following:
  • S402. Demodulate the second code block to obtain an error estimation coded EEC check bit and a cyclic redundancy CRC check bit included in the second code block.
  • the terminal performs error estimation on the corresponding data according to the EEC check bit and the CRC check code.
  • the value of the soft information is generally 100 or more or -100 or less. A value close to 0 indicates that the soft information of this bit is unreliable, so a threshold (such as an absolute value of 1) can be determined to determine which bits are in error.
  • the information bit soft information SI of the decoding error in the code word is close to 0, and the information bit of the error in the packet and the packet for estimating the EEC check miss may be determined according to this feature. The specific judgment is as follows:
  • the two packets in which the soft information minimum value exists may be selected as an error
  • the EEC has more than one error and it is found that there may be a missed packet when decoding, then whether the absolute soft packet contains the absolute value smaller than the absolute value of the error packet, if there are multiple such packets in the packet. The soft information bit is considered to be wrong.
  • the EEC check bit and the CRC check code in the first code block are obtained by demodulation to ensure the smooth progress of the EEC and the CRC check, and the CRC generator polynomial adapted to the joint mechanism is redesigned, and finally received.
  • the soft information on the side further improves the accuracy of the error estimate.
  • FIG. 5 is a schematic structural diagram of a first embodiment of a base station according to the present invention.
  • the base station includes:
  • the constructing unit 100 is configured to construct a first code block, where the first code block includes an information bit, an error estimation coding EEC check bit, and a cyclic redundancy CRC check bit;
  • the configuration unit 200 is configured to configure a CRC generation polynomial, and generate a CRC check code according to the CRC generation polynomial, where the CRC generation polynomial first coefficient and the last coefficient are both 1 and the number of the coefficient in the CRC generation polynomial is 1. Even number;
  • the modulating unit 300 is configured to perform a CRC check according to the CRC check code and complete channel coding to form a second code block, and the second code block is modulated and sent to the terminal, so that the terminal according to the EEC
  • the check digit and the CRC check code are used for error estimation.
  • the constructing unit 100 is specifically configured to:
  • the highest index of the CRC generator polynomial is 8, and the sequence of the CRC generator polynomial is any one of the following:
  • the foregoing configuration unit 100, the configuration unit 200, and the modulation unit 300 may exist independently or may be integrated, and the configuration unit 100, the configuration unit 200, or the modulation unit 300 in the above base station embodiment may be independent of hardware.
  • the processor of the base station is separately provided and can be in the form of a microprocessor; it can also be embedded in the processor of the base station in hardware, or can be stored in the memory of the base station in software to facilitate the processor of the base station.
  • the operations corresponding to the above construction unit 100, configuration unit 200, and modulation unit 300 are invoked.
  • the construction unit 100 may be a processor of the base station, and the functions of the configuration unit 200 and the modulation unit 300 may be embedded in the processor. It can also be set independently of the processor, or it can be stored in the memory in the form of software, and its function can be called by the processor.
  • the above processor may be a central processing unit (CPU), a microprocessor, a single chip microcomputer, or the like.
  • the base station includes:
  • the input device 110 the output device 120, the memory 130, and the processor 140.
  • the memory 130 is configured to store a set of program codes
  • the processor 140 is configured to invoke program code stored in the memory 130, perform the method of error estimation according to the present invention, and perform any operation in the first and second embodiments. Work.
  • FIG. 7 is a schematic structural diagram of a first embodiment of a terminal according to the present invention.
  • the terminal includes:
  • the receiving unit 400 is configured to receive a second code block sent by the base station
  • Demodulation unit 500 configured to demodulate the second code block to obtain an error estimation coded EEC check bit included in the second code block, and a cyclic redundancy CRC check bit, where the CRC check code is used by the base station
  • a CRC generator polynomial is generated according to an even number of items whose first coefficient and last bit coefficient are both and whose coefficient is 1;
  • the estimating unit 600 is configured to perform error estimation on the corresponding data according to the EEC check bit and the CRC check code.
  • the terminal may further include a checking unit 700 (not shown in FIG. 7), for performing an EEC packet miss check according to an absolute value of the soft information generated by the decision at the time of channel decoding after performing EEC decoding. .
  • a checking unit 700 for performing an EEC packet miss check according to an absolute value of the soft information generated by the decision at the time of channel decoding after performing EEC decoding.
  • the foregoing receiving unit 400, the demodulating unit 500, the estimating unit 600, and the checking unit 700 may exist independently or may be integrated, and the receiving unit 400, the demodulating unit 500, the estimating unit 600 or the above terminal embodiment
  • the verification unit 700 can be separately set in the form of hardware independently of the processor of the base station, and can be in the form of a microprocessor; it can also be embedded in the processor of the terminal in hardware, or can be stored in the terminal in software. In the memory, the processor of the terminal is called to perform operations corresponding to the above receiving unit 400, demodulating unit 500, estimating unit 600, and verifying unit 700.
  • the estimating unit 600 may be a processor of the terminal, and the functions of the receiving unit 400, the demodulating unit 500, and the checking unit 700 may be embedded.
  • the processor it can also be set separately from the processor, or can be stored in the memory in the form of software, and the function is called by the processor.
  • the above processor may be a central processing unit (CPU), a microprocessor, a single chip microcomputer, or the like.
  • the receiving unit 400 can also be used as a transceiver circuit of the estimating unit 600, and is integrated with the estimating unit 600.
  • FIG. 8 is a schematic structural diagram of a fourth embodiment of a terminal according to the present invention.
  • the base station includes:
  • the input device 210 the output device 220, the memory 230, and the processor 240.
  • the memory 230 is configured to store a set of program codes
  • the processor 240 is configured to invoke the program code stored in the memory 230 to perform any operation in the third embodiment of the method for estimating the error of the present invention.
  • the present invention has the following advantages:
  • the storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

Selon un mode de réalisation, l'invention concerne un procédé d'estimation d'erreurs comprenant : la construction d'un premier bloc de code par une station de base, le premier bloc de code comprenant des bits d'informations, des bits de vérification de code correcteur d'erreurs (EEC) et des bits de vérification de vérification de redondance cyclique (CRC) ; la configuration d'un polynôme générateur de CRC pour générer un code de vérification CRC conformément au polynôme générateur de CRC, les premier et dernier coefficients du polynôme générateur de CRC étant 1 et le nombre de termes ayant un coefficient égal à 1 dans le polynôme générateur de CRC étant un nombre pair ; la réalisation d'une vérification CRC selon le code de vérification CRC et la formation d'un second bloc de code après codage de canal, et la modulation et l'envoi du second bloc de code à un terminal pour une estimation d'erreurs par le terminal en fonction des bits de vérification EEC et du code de vérification CRC. Grâce à l'invention, l'utilisation des ressources de transmission dans un service de données vidéo peut être améliorée et la fiabilité de transmission de données est garantie.
PCT/CN2016/107298 2015-11-30 2016-11-25 Procédé d'estimation d'erreurs, station de base, et terminal WO2017092617A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510859520.2A CN106817192B (zh) 2015-11-30 2015-11-30 一种错误估计的方法、基站及终端
CN201510859520.2 2015-11-30

Publications (1)

Publication Number Publication Date
WO2017092617A1 true WO2017092617A1 (fr) 2017-06-08

Family

ID=58796272

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/107298 WO2017092617A1 (fr) 2015-11-30 2016-11-25 Procédé d'estimation d'erreurs, station de base, et terminal

Country Status (2)

Country Link
CN (1) CN106817192B (fr)
WO (1) WO2017092617A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116346278A (zh) * 2021-12-22 2023-06-27 华为技术有限公司 发送方法、接收方法、装置、系统、设备及存储介质

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019041306A1 (fr) * 2017-09-01 2019-03-07 Nokia Solutions And Networks Oy Traitement de messages et appareil correspondant
CN108418658B (zh) * 2017-09-08 2019-03-26 华为技术有限公司 编码方法及装置
WO2019047788A1 (fr) * 2017-09-08 2019-03-14 华为技术有限公司 Procédé et dispositif de codage
US10425190B2 (en) 2017-09-08 2019-09-24 Huawei Technologies Co., Ltd. Channel encoding method and apparatus in wireless communications
CN109474383B (zh) * 2017-09-08 2022-05-24 华为技术有限公司 编码方法及装置
CN109474378B (zh) * 2017-09-08 2022-07-29 华为技术有限公司 编码方法及装置
US10594439B2 (en) 2017-09-08 2020-03-17 Huawei Technologies Co., Ltd. Channel encoding method and apparatus in wireless communications to output a polar encoded bit sequence
CN109474376B (zh) * 2017-09-08 2022-02-18 华为技术有限公司 编码方法及装置
CN109981382B (zh) * 2017-12-27 2022-08-26 华为技术有限公司 一种检测误码的方法及装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994015407A1 (fr) * 1992-12-29 1994-07-07 Codex Corporation Dispositif et procede efficaces de generation et verification des coefficients de restes du controle de redondance cyclique
CN1333950A (zh) * 1999-11-15 2002-01-30 三菱电机株式会社 使用循环码的错误控制装置与方法
CN101431388A (zh) * 2007-11-08 2009-05-13 联发科技股份有限公司 译码编码数据帧的方法及其译码器
CN101622604A (zh) * 2007-09-26 2010-01-06 株式会社东芝 半导体存储器件及其控制方法
CN102571294A (zh) * 2012-03-12 2012-07-11 北京理工大学 一种基于crc编码的卫星导航电文纠错方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006031884A (ja) * 2004-07-20 2006-02-02 Toshiba Corp 情報記憶媒体、情報記録再生装置、情報再生装置、情報記録方法、情報再生方法
US8555148B2 (en) * 2007-09-18 2013-10-08 Samsung Electronics Co., Ltd. Methods and apparatus to generate multiple CRCs

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994015407A1 (fr) * 1992-12-29 1994-07-07 Codex Corporation Dispositif et procede efficaces de generation et verification des coefficients de restes du controle de redondance cyclique
CN1333950A (zh) * 1999-11-15 2002-01-30 三菱电机株式会社 使用循环码的错误控制装置与方法
CN101622604A (zh) * 2007-09-26 2010-01-06 株式会社东芝 半导体存储器件及其控制方法
CN101431388A (zh) * 2007-11-08 2009-05-13 联发科技股份有限公司 译码编码数据帧的方法及其译码器
CN102571294A (zh) * 2012-03-12 2012-07-11 北京理工大学 一种基于crc编码的卫星导航电文纠错方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116346278A (zh) * 2021-12-22 2023-06-27 华为技术有限公司 发送方法、接收方法、装置、系统、设备及存储介质

Also Published As

Publication number Publication date
CN106817192A (zh) 2017-06-09
CN106817192B (zh) 2020-08-14

Similar Documents

Publication Publication Date Title
WO2017092617A1 (fr) Procédé d'estimation d'erreurs, station de base, et terminal
WO2020156468A1 (fr) Procédé, dispositif et système de transmission adaptative pour communication par satellite
US6700867B2 (en) Method and system for reduced memory hybrid automatic repeat request
JP3634800B2 (ja) パリティチェック結合を用いたハイブリッド自動再送要求を実施するシステム及び方法
JP4703310B2 (ja) 通信方法および通信システム
CN106899390B (zh) 基于harq传输的方法、装置及系统
US7650560B2 (en) Packet transmission apparatus and method using optimized punctured convolution codes
US8495474B2 (en) Method and system for data transmission in a data network
US20070259665A1 (en) Error detection and retransmission methods and devices for communication systems
WO2010115295A1 (fr) Procédé de demande de retransmission, procédé de retransmission et dispositifs correspondants
CN103201976A (zh) 聚合分组传输中的分组级擦除保护编码
KR101490249B1 (ko) 연판정을 이용한 통신방법 및 장치
WO2012151976A1 (fr) Procédé et dispositif permettant de déterminer une détection d'erreur
TW200536303A (en) Method and arrangement for arq in packet data transmission
CN101689972B (zh) 用于指示使用捎带的ack/nack字段的临时块流的方法和设备
WO2003092209A1 (fr) Dispositif et procede de transmission
CN107733573B (zh) 数据处理方法、装置及节点
CN113316922B (zh) 用于传输数据分组的设备、方法、装置以及计算机可读存储介质
EP3797483A1 (fr) Dispositifs, procédés et programmes informatiques pour la retransmission sélective de façon adaptative dans les communications sans fil
WO2010035844A1 (fr) Dispositif de communication et procédé de communication
WO2019064378A1 (fr) Procédé de communication sans fil, système de communication sans fil et station de base
WO2024007224A1 (fr) Procédé de transmission adaptative basé sur une rétroaction
WO2023046029A1 (fr) Procédé et appareil de transmission de données et support de stockage lisible
Barukang et al. Packet header FEC
WO2019064377A1 (fr) Procédé de communication sans fil, système de communication sans fil, station de base et terminal sans fil

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16869927

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 16869927

Country of ref document: EP

Kind code of ref document: A1