WO2017092078A1 - 削角线路及显示面板 - Google Patents

削角线路及显示面板 Download PDF

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Publication number
WO2017092078A1
WO2017092078A1 PCT/CN2015/097877 CN2015097877W WO2017092078A1 WO 2017092078 A1 WO2017092078 A1 WO 2017092078A1 CN 2015097877 W CN2015097877 W CN 2015097877W WO 2017092078 A1 WO2017092078 A1 WO 2017092078A1
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WIPO (PCT)
Prior art keywords
electrical switch
chamfering
adjustment units
sets
switch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2015/097877
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English (en)
French (fr)
Inventor
张先明
曹丹
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US14/905,799 priority Critical patent/US20170278449A1/en
Publication of WO2017092078A1 publication Critical patent/WO2017092078A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/066—Waveforms comprising a gently increasing or decreasing portion, e.g. ramp
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness

Definitions

  • the present invention relates to the field of display, and in particular to a chamfer line and a display panel.
  • the same chamfer voltage and slope are generally used in the fixed mode and the fixed screen. If it is necessary to change the slope of the chamfering voltage to change the display effect of the display panel, it is necessary to change the size of the chamfering resistor.
  • such a method cannot perform combined control according to actual conditions to realize different chamfering waveforms in different situations, thereby improving the display effect.
  • the invention provides a chamfering line and a display panel to improve the display effect of the display panel.
  • the invention provides a chamfering line, comprising a chamfering module, a first electric switch and at least two sets of adjusting units, the chamfering module being connected to the first end of the first electric switch to control the first electric Opening and closing of the switch, the second end of the first electrical switch receives a voltage signal, the second end of the first electrical switch is connected to the at least two sets of adjusting units, and the second end of the first electrical switch is a node between the at least two sets of adjustment units outputs an angled waveform as an output of the chamfer line, the chamfering module is further connected to the at least two sets of adjustment units to control the at least two sets of adjustment units The chamfering waveform is adjusted such that the slope of the chamfering waveform is a combined slope.
  • the at least two sets of adjustment units include a first group of adjustment units, a second group of adjustment units, and a third group of adjustment units, wherein the first to third groups of adjustment units are connected in parallel to the second of the first electrical switches Between the end and the ground, the chamfering module is connected to the first to third adjusting units to respectively control the first to third adjusting units.
  • the first group of adjustment units includes a first resistor and a second electrical switch
  • the second group of adjustments The unit includes a second resistor and a third electrical switch
  • the third group of adjusting units includes a third resistor and a fourth electrical switch
  • a control end of the second electrical switch is coupled to the chamfering module
  • the second electrical a first end of the switch is connected to the second end of the first electrical switch by a first resistor
  • a third end of the second electrical switch is grounded
  • a control end of the third electrical switch is connected to the chamfering module
  • the first end of the third electrical switch is connected to the second end of the first electrical switch by a second resistor
  • the third end of the third electrical switch is grounded
  • the control end of the fourth electrical switch is connected To the chamfering module
  • the first end of the fourth electrical switch is connected to the second end of the first electrical switch through a third resistor
  • the third end of the fourth electrical switch is grounded.
  • the first to fourth electrical switches are triodes.
  • the first electrical switch is an NMOS transistor
  • the second to fourth electrical switches are PMOS transistors
  • the control ends, the first ends, and the second ends of the first to fourth electrical switches are respectively gates. Drain and source.
  • the invention also provides a display panel comprising a circuit board, a glass plate and a chamfer line disposed on the circuit board, the chamfering line comprising a chamfering module, a first electric switch and at least two sets of adjusting units,
  • the chamfering module is connected to the first end of the first electrical switch to control the opening and closing of the first electrical switch, the second end of the first electrical switch receives a voltage signal, and the first electrical switch a second end connected to the at least two sets of adjustment units, a node between the second end of the first electrical switch and the at least two sets of adjustment units as an output end of the chamfer line to output a chamfering waveform
  • the chamfering module is further coupled to the at least two sets of adjustment units to control the at least two sets of adjustment units to adjust the chamfering waveform such that the slope of the chamfering waveform is a combined slope.
  • the at least two sets of adjustment units include a first group of adjustment units, a second group of adjustment units, and a third group of adjustment units, wherein the first to third groups of adjustment units are connected in parallel to the second of the first electrical switches Between the end and the ground, the chamfering module is connected to the first to third adjusting units to respectively control the first to third adjusting units.
  • the first group of adjustment units includes a first resistor and a second electrical switch
  • the second group of adjustment units includes a second resistor and a third electrical switch
  • the third group of adjustment units includes a third resistor and a fourth An electric switch
  • a control end of the second electric switch is connected to the chamfering module
  • a first end of the second electric switch is connected to a second end of the first electric switch by a first resistor
  • the The third end of the second electric switch is grounded
  • the control end of the third electric switch is connected to the chamfering module
  • the first end of the third electric switch Connected to the second end of the first electrical switch by a second resistor
  • the third end of the third electrical switch is grounded
  • the control end of the fourth electrical switch is connected to the chamfering module
  • the fourth The first end of the electrical switch is connected to the second end of the first electrical switch through a third resistor
  • the third end of the fourth electrical switch is grounded.
  • the display panel further includes a pulse width modulation chip, wherein the chamfering module and the first electrical switch are disposed in the pulse width modulation chip, and the at least two sets of adjustment units are disposed outside the pulse width modulation chip. .
  • the pulse width modulation chip has a register therein, and the register user controls the at least two sets of adjusting units to adjust the chamfering waveform such that the slope of the chamfering waveform is a combined slope.
  • the chamfering line of the present invention comprises a chamfering module, a first electrical switch and at least two sets of adjusting units, the chamfering module being connected to the first end of the first electrical switch to control the first electrical switch Opened and closed, the second end of the first electrical switch receives a voltage signal, the second end of the first electrical switch is connected to the at least two sets of adjusting units, the second end of the first electrical switch is a node between the two sets of adjustment units as an output of the chamfer line to output a chamfering waveform, the chamfering module being further connected to the at least two sets of adjustment units to control the at least two sets of adjustment units to adjust
  • the chamfering waveform is described such that the slope of the chamfered waveform is a combined slope. Therefore, the curve of the chamfering waveform at the position of the chamfer is approximated, so that the display effect of the display panel is better, and the present invention improves the display effect of the display panel.
  • FIG. 1 is a block diagram of a chamfer line provided by a preferred embodiment of the first aspect of the present invention.
  • FIG. 2 is a circuit diagram of a chamfer line provided by a preferred embodiment of the first aspect of the present invention.
  • FIG. 3 is a block diagram of a display panel according to a preferred embodiment of the second aspect of the present invention.
  • a preferred embodiment of the first aspect of the present invention provides a chamfer line 100.
  • the chamfering line 100 includes a chamfering module 10, a first electrical switch 20, and at least two sets of adjustment units 30.
  • the chamfering module 10 is connected to the first end of the first electrical switch 20 to control the opening and closing of the first electrical switch 20.
  • the second end of the first electrical switch 20 receives a voltage signal.
  • the second end of the first electrical switch 20 is coupled to the at least two sets of adjustment units 30.
  • a node between the second end of the first electrical switch 20 and the at least two sets of adjustment units serves as an output end of the chamfering line 100 to output a chamfering waveform
  • the chamfering module 10 is further connected to the at least two
  • the group adjusting unit 30 controls the at least two sets of adjusting units 30 to adjust the chamfering waveform such that the slope of the chamfering waveform is a combined slope.
  • the combined slope is a combination of multiple slopes, that is, the chamfered waveform has a curved shape at the position of the chamfer.
  • the number of the adjustment units 30 reaches a certain number, and the curve of the chamfering waveform at the position of the chamfer is closer to the sine wave curve, so that the display effect of the display panel is better.
  • the chamfer line 100 includes a chamfering module 10, a first electrical switch 20, and at least two sets of adjustment units 30.
  • the chamfering module 10 is connected to the first end of the first electrical switch 20 to control the opening and closing of the first electrical switch 20.
  • the second end of the first electrical switch 20 receives a voltage signal.
  • the second end of the first electrical switch 20 is coupled to the at least two sets of adjustment units 30.
  • a node between the second end of the first electrical switch 20 and the at least two sets of adjustment units serves as an output end of the chamfering line 100 to output a chamfering waveform
  • the chamfering module 10 is further connected to the at least two
  • the group adjusting unit 30 controls the at least two sets of adjusting units 30 to adjust the chamfering waveform such that the slope of the chamfering waveform is a combined slope. Therefore, the curve of the chamfering waveform at the position of the chamfer is approximated, so that the display effect of the display panel is better, and the present invention improves the display effect of the display panel.
  • the at least two groups of adjustment units 30 include a first group of adjustment units 31 , a second group of adjustment units 32 , and a third group of adjustment units 33 .
  • the first to third sets of adjustment units 31-33 are connected in parallel between the second end of the first electrical switch 20 and the ground.
  • the chamfering module 10 is coupled to the first to third adjusting units 31-33 to control the first to third adjusting units 31-33, respectively.
  • the first group of adjusting units 31 includes a first resistor R1 and a second electrical switch Q1.
  • Place The second group of adjustment units 32 includes a second resistor R2 and a third electrical switch Q2.
  • the third group of adjusting units 33 includes a third resistor R3 and a fourth electrical switch Q3.
  • the control end of the second electrical switch Q1 is connected to the chamfering module 10.
  • the first end of the second electrical switch Q1 is connected to the second end of the first electrical switch 20 through a first resistor R1.
  • the third end of the second electrical switch Q1 is grounded.
  • the control end of the third electrical switch Q2 is connected to the chamfering module 10.
  • the first end of the third electrical switch Q2 is coupled to the second end of the first electrical switch 20 via a second resistor R2.
  • the third end of the third electrical switch Q2 is grounded.
  • the control end of the fourth electrical switch Q3 is connected to the chamfering module 10.
  • the first end of the fourth electrical switch Q3 is connected to the second end of the first electrical switch 20 through a third resistor R3, and the third end of the fourth electrical switch Q3 is grounded.
  • the first to fourth electrical switches 20 and Q1-Q3 are all triodes.
  • the first electrical switch 20 is an NMOS transistor.
  • the second to fourth electrical switches Q1-Q3 are PMOS transistors.
  • the control terminals, the first terminals and the second terminals of the first to fourth electrical switches 20 and Q1-Q3 are respectively a gate, a drain and a source. pole.
  • the at least two sets of adjustment units 30 include first to third sets of adjustment units 31-33.
  • the number of groups of the adjustment unit can be adjusted according to actual needs.
  • a second aspect of the present invention further provides a display panel.
  • the display panel 300 includes a circuit board 310, a glass plate 320, and a chamfer line disposed on the circuit board 310.
  • the chamfer line is the chamfer line 100 in the first aspect described above. Since the chamfered line 100 is described in detail in the above first embodiment, it will not be described again.
  • the display panel 300 includes the chamfer line 100.
  • the chamfering line 100 includes a chamfering module 10, a first electrical switch 20, and at least two sets of adjustment units 30.
  • the chamfering module 10 is connected to the first end of the first electrical switch 20 to control the opening and closing of the first electrical switch 20.
  • the second end of the first electrical switch 20 receives a voltage signal.
  • the second end of the first electrical switch 20 is coupled to the at least two sets of adjustment units 30.
  • a node between the second end of the first electrical switch 20 and the at least two sets of adjustment units serves as an output end of the chamfering line 100 to output a chamfering waveform
  • the chamfering module 10 is further connected to the at least two
  • the group adjusting unit 30 controls the at least two sets of adjusting units 30 to adjust the chamfering waveform such that the slope of the chamfering waveform is a combined slope. Therefore, the curve of the chamfered waveform at the position of the chamfer is approximated, so that the display effect of the display panel 300 is better, and the present invention improves the display effect of the display panel 300.
  • the display panel 300 further includes a pulse width modulation chip (not shown).
  • the chamfering module 10 and the first electrical switch 20 are both disposed in the pulse width modulation chip.
  • the at least two sets of adjustment units 30 are disposed outside the pulse width modulation chip.
  • the pulse width modulation chip has a register therein.
  • the register is configured to control the at least two sets of adjustment units 30 to adjust the chamfering waveform such that the slope of the chamfered waveform is a combined slope.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种削角线路（100），包括削角模块（10）、第一电开关（20）及至少两组调节单元（30），所述削角模块（10）连接至所述第一电开关（20）的第一端，以控制所述第一电开关（20）的启闭，所述第一电开关（20）的第二端接收电压信号，所述第一电开关（20）的第二端连接至所述至少两组调节单元（30），所述第一电开关（20）的第二端与所述至少两组调节单元（30）之间的节点作为削角线路（100）的输出端来输出削角波形，所述削角模块（10）还连接至所述至少两组调节单元（30），以控制所述至少两组调节单元（30）来调节所述削角波形，使削角波形的斜率为组合斜率。因此，所述削角波形在削角的位置的曲线概呈曲线，这样使得显示面板的显示效果越好，进而提高了显示面板的显示效果。

Description

削角线路及显示面板
本发明要求2015年11月30日递交的发明名称为“削角线路及显示面板”的申请号201510856823.9的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及显示领域，尤其涉及一种削角线路及显示面板。
背景技术
在显示面板驱动中一般都会在固定模式以及固定画面下使用相同的削角电压和斜率，如果需要改变削角电压的斜率来改变显示面板的显示效果则需要改变削角电阻的大小。但是，这样的方式无法根据实际情况进行组合控制来实现不同的情况下不同的削角波形，从而来提高显示效果。
发明内容
本发明提供一种削角线路及显示面板，以提高显示面板的显示效果。
本发明提供一种削角线路，包括削角模块、第一电开关及至少两组调节单元，所述削角模块连接至所述第一电开关的第一端，以控制所述第一电开关的启闭，所述第一电开关的第二端接收电压信号，所述第一电开关的第二端连接至所述至少两组调节单元，所述第一电开关的第二端与所述至少两组调节单元之间的节点作为削角线路的输出端来输出削角波形，所述削角模块还连接至所述至少两组调节单元，以控制所述至少两组调节单元来调节所述削角波形，使削角波形的斜率为组合斜率。
其中，所述至少两组调节单元包括第一组调节单元、第二组调节单元及第三组调节单元，所述第一至第三组调节单元并联连接在所述第一电开关的第二端与地之间，所述削角模块连接至所述第一至第三调节单元，以分别对所述第一至第三调节单元进行控制。
其中，所述第一组调节单元包括第一电阻及第二电开关，所述第二组调节 单元包括第二电阻及第三电开关，所述第三组调节单元包括第三电阻及第四电开关，所述第二电开关的控制端连接至所述削角模块，所述第二电开关的第一端通过第一电阻连接至所述第一电开关的第二端，所述第二电开关的第三端接地，所述第三电开关的控制端连接至所述削角模块，所述第三电开关的第一端通过第二电阻连接至所述第一电开关的第二端，所述第三电开关的第三端接地，所述第四电开关的控制端连接至所述削角模块，所述第四电开关的第一端通过第三电阻连接至所述第一电开关的第二端，所述第四电开关的第三端接地。
其中，所述第一至第四电开关为三极管。
其中，所述第一电开关为NMOS三极管，所述第二至第四电开关为PMOS三极管，所述第一至第四电开关的控制端、第一端及第二端分别为栅极、漏极及源极。
本发明还提供一种显示面板，包括电路板、玻璃板及设置于所述电路板上的削角线路，所述削角线路包括削角模块、第一电开关及至少两组调节单元，所述削角模块连接至所述第一电开关的第一端，以控制所述第一电开关的启闭，所述第一电开关的第二端接收电压信号，所述第一电开关的第二端连接至所述至少两组调节单元，所述第一电开关的第二端与所述至少两组调节单元之间的节点作为削角线路的输出端来输出削角波形，所述削角模块还连接至所述至少两组调节单元，以控制所述至少两组调节单元来调节所述削角波形，使削角波形的斜率为组合斜率。
其中，所述至少两组调节单元包括第一组调节单元、第二组调节单元及第三组调节单元，所述第一至第三组调节单元并联连接在所述第一电开关的第二端与地之间，所述削角模块连接至所述第一至第三调节单元，以分别对所述第一至第三调节单元进行控制。
其中，所述第一组调节单元包括第一电阻及第二电开关，所述第二组调节单元包括第二电阻及第三电开关，所述第三组调节单元包括第三电阻及第四电开关，所述第二电开关的控制端连接至所述削角模块，所述第二电开关的第一端通过第一电阻连接至所述第一电开关的第二端，所述第二电开关的第三端接地，所述第三电开关的控制端连接至所述削角模块，所述第三电开关的第一端 通过第二电阻连接至所述第一电开关的第二端，所述第三电开关的第三端接地，所述第四电开关的控制端连接至所述削角模块，所述第四电开关的第一端通过第三电阻连接至所述第一电开关的第二端，所述第四电开关的第三端接地。
其中，所述显示面板还包括脉冲宽度调制芯片，所述削角模块及第一电开关均设置于所述脉冲宽度调制芯片内，所述至少两组调节单元设置于所述脉冲宽度调制芯片外。
其中，所述脉冲宽度调制芯片内具有寄存器，所述寄存器用户控制所述至少两组调节单元来调节所述削角波形，使削角波形的斜率为组合斜率。
本发明的削角线路，包括削角模块、第一电开关及至少两组调节单元，所述削角模块连接至所述第一电开关的第一端，以控制所述第一电开关的启闭，所述第一电开关的第二端接收电压信号，所述第一电开关的第二端连接至所述至少两组调节单元，所述第一电开关的第二端与所述至少两组调节单元之间的节点作为削角线路的输出端来输出削角波形，所述削角模块还连接至所述至少两组调节单元，以控制所述至少两组调节单元来调节所述削角波形，使削角波形的斜率为组合斜率。因此，所述削角波形在削角的位置的曲线概呈曲线，这样使得显示面板的显示效果越好，进而本发明提高了显示面板的显示效果。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明第一方案较佳实施例提供的削角线路的框图。
图2为本发明第一方案较佳实施例提供的削角线路的电路图。
图3为本发明第二方案较佳实施例提供的显示面板的框图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清 楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1，本发明第一方案较佳实施例提供了一种削角线路100。所述削角线路100包括削角模块10、第一电开关20及至少两组调节单元30。所述削角模块10连接至所述第一电开关20的第一端，以控制所述第一电开关20的启闭。所述第一电开关20的第二端接收电压信号。所述第一电开关20的第二端连接至所述至少两组调节单元30。所述第一电开关20的第二端与所述至少两组调节单元之间的节点作为削角线路100的输出端来输出削角波形，所述削角模块10还连接至所述至少两组调节单元30，以控制所述至少两组调节单元30来调节所述削角波形，使削角波形的斜率为组合斜率。
需要说明的是，组合斜率为多个斜率的组合，即削角波形在削角的位置概呈现曲线状。当然所述调节单元30的数量达到一定数量，所述削角波形在削角的位置的曲线越接近弦波曲线，这样使得显示面板的显示效果越好。
在本实施例中，所述削角线路100包括削角模块10、第一电开关20及至少两组调节单元30。所述削角模块10连接至所述第一电开关20的第一端，以控制所述第一电开关20的启闭。所述第一电开关20的第二端接收电压信号。所述第一电开关20的第二端连接至所述至少两组调节单元30。所述第一电开关20的第二端与所述至少两组调节单元之间的节点作为削角线路100的输出端来输出削角波形，所述削角模块10还连接至所述至少两组调节单元30，以控制所述至少两组调节单元30来调节所述削角波形，使削角波形的斜率为组合斜率。因此，所述削角波形在削角的位置的曲线概呈曲线，这样使得显示面板的显示效果越好，进而本发明提高了显示面板的显示效果。
请参阅图2，进一步地，所述至少两组调节单元30包括第一组调节单元31、第二组调节单元32及第三组调节单元33。所述第一至第三组调节单元31-33并联连接在所述第一电开关20的第二端与地之间。所述削角模块10连接至所述第一至第三调节单元31-33，以分别对所述第一至第三调节单元31-33进行控制。
具体地，所述第一组调节单元31包括第一电阻R1及第二电开关Q1。所 述第二组调节单元32包括第二电阻R2及第三电开关Q2。所述第三组调节单元33包括第三电阻R3及第四电开关Q3。所述第二电开关Q1的控制端连接至所述削角模块10。所述第二电开关Q1的第一端通过第一电阻R1连接至所述第一电开关20的第二端。所述第二电开关Q1的第三端接地。所述第三电开关Q2的控制端连接至所述削角模块10。所述第三电开关Q2的第一端通过第二电阻R2连接至所述第一电开关20的第二端。所述第三电开关Q2的第三端接地。所述第四电开关Q3的控制端连接至所述削角模块10。所述第四电开关Q3的第一端通过第三电阻R3连接至所述第一电开关20的第二端，所述第四电开关Q3的第三端接地。
在本实施例中，所述第一至第四电开关20及Q1-Q3均为三极管。所述第一电开关20为NMOS三极管。所述第二至第四电开关Q1-Q3为PMOS三极管.所述第一至第四电开关20及Q1-Q3的控制端、第一端及第二端分别为栅极、漏极及源极。
在本实施方式中，所述至少两组调节单元30包括第一至第三组调节单元31-33。在其他的实施例中，所述调节单元的组数可以根据实际需要进行调整。
请参阅图3，本发明第二方案还提供一种显示面板。所述显示面板300包括电路板310、玻璃板320及设置于所述电路板310上的削角线路。所述削角线路为上述第一方案中的削角线路100。由于在上述第一方案中对削角线路100进行了详细地描述，故在此不再赘述。
在本实施例中，所述显示面板300包括所述削角线路100。所述削角线路100包括削角模块10、第一电开关20及至少两组调节单元30。所述削角模块10连接至所述第一电开关20的第一端，以控制所述第一电开关20的启闭。所述第一电开关20的第二端接收电压信号。所述第一电开关20的第二端连接至所述至少两组调节单元30。所述第一电开关20的第二端与所述至少两组调节单元之间的节点作为削角线路100的输出端来输出削角波形，所述削角模块10还连接至所述至少两组调节单元30，以控制所述至少两组调节单元30来调节所述削角波形，使削角波形的斜率为组合斜率。因此，所述削角波形在削角的位置的曲线概呈曲线，这样使得显示面板300的显示效果越好，进而本发明提高了显示面板300的显示效果。
进一步地，所述显示面板300还包括脉冲宽度调制芯片(未示出)。所述削角模块10及第一电开关20均设置于所述脉冲宽度调制芯片内。所述至少两组调节单元30设置于所述脉冲宽度调制芯片外。
所述脉冲宽度调制芯片内具有寄存器。所述寄存器用于控制所述至少两组调节单元30来调节所述削角波形，使削角波形的斜率为组合斜率。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (10)

  1. 一种削角线路，包括削角模块、第一电开关及至少两组调节单元，所述削角模块连接至所述第一电开关的第一端，以控制所述第一电开关的启闭，所述第一电开关的第二端接收电压信号，所述第一电开关的第二端连接至所述至少两组调节单元，所述第一电开关的第二端与所述至少两组调节单元之间的节点作为削角线路的输出端来输出削角波形，所述削角模块还连接至所述至少两组调节单元，以控制所述至少两组调节单元来调节所述削角波形，使削角波形的斜率为组合斜率。
  2. 如权利要求1所述的削角线路，其中，所述至少两组调节单元包括第一组调节单元、第二组调节单元及第三组调节单元，所述第一至第三组调节单元并联连接在所述第一电开关的第二端与地之间，所述削角模块连接至所述第一至第三调节单元，以分别对所述第一至第三调节单元进行控制。
  3. 如权利要求2所述的削角线路，其中，所述第一组调节单元包括第一电阻及第二电开关，所述第二组调节单元包括第二电阻及第三电开关，所述第三组调节单元包括第三电阻及第四电开关，所述第二电开关的控制端连接至所述削角模块，所述第二电开关的第一端通过第一电阻连接至所述第一电开关的第二端，所述第二电开关的第三端接地，所述第三电开关的控制端连接至所述削角模块，所述第三电开关的第一端通过第二电阻连接至所述第一电开关的第二端，所述第三电开关的第三端接地，所述第四电开关的控制端连接至所述削角模块，所述第四电开关的第一端通过第三电阻连接至所述第一电开关的第二端，所述第四电开关的第三端接地。
  4. 如权利要求3所述的削角线路，其中，所述第一至第四电开关为三极管。
  5. 如权利要求4所述的削角线路，其中，所述第一电开关为NMOS三极管，所述第二至第四电开关为PMOS三极管，所述第一至第四电开关的控制端、第一端及第二端分别为栅极、漏极及源极。
  6. 一种显示面板，包括电路板、玻璃板及设置于所述电路板上的削角线路，所述削角线路包括削角模块、第一电开关及至少两组调节单元，所述削角模块连接至所述第一电开关的第一端，以控制所述第一电开关的启闭，所述第一电 开关的第二端接收电压信号，所述第一电开关的第二端连接至所述至少两组调节单元，所述第一电开关的第二端与所述至少两组调节单元之间的节点作为削角线路的输出端来输出削角波形，所述削角模块还连接至所述至少两组调节单元，以控制所述至少两组调节单元来调节所述削角波形，使削角波形的斜率为组合斜率。
  7. 如权利要求6所述的显示面板，其中，所述至少两组调节单元包括第一组调节单元、第二组调节单元及第三组调节单元，所述第一至第三组调节单元并联连接在所述第一电开关的第二端与地之间，所述削角模块连接至所述第一至第三调节单元，以分别对所述第一至第三调节单元进行控制。
  8. 如权利要求7所述的显示面板，其中，所述第一组调节单元包括第一电阻及第二电开关，所述第二组调节单元包括第二电阻及第三电开关，所述第三组调节单元包括第三电阻及第四电开关，所述第二电开关的控制端连接至所述削角模块，所述第二电开关的第一端通过第一电阻连接至所述第一电开关的第二端，所述第二电开关的第三端接地，所述第三电开关的控制端连接至所述削角模块，所述第三电开关的第一端通过第二电阻连接至所述第一电开关的第二端，所述第三电开关的第三端接地，所述第四电开关的控制端连接至所述削角模块，所述第四电开关的第一端通过第三电阻连接至所述第一电开关的第二端，所述第四电开关的第三端接地。
  9. 如权利要求6所述的显示面板，其中，所述显示面板还包括脉冲宽度调制芯片，所述削角模块及第一电开关均设置于所述脉冲宽度调制芯片内，所述至少两组调节单元设置于所述脉冲宽度调制芯片外。
  10. 如权利要求7所述的显示面板，其中，所述脉冲宽度调制芯片内具有寄存器，所述寄存器用户控制所述至少两组调节单元来调节所述削角波形，使削角波形的斜率为组合斜率。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101917179A (zh) * 2010-07-08 2010-12-15 友达光电股份有限公司 栅极脉冲调制电路及其削角调制方法
CN102034440A (zh) * 2009-09-24 2011-04-27 瑞鼎科技股份有限公司 栅极驱动器及其操作方法
CN102110405A (zh) * 2009-12-24 2011-06-29 乐金显示有限公司 显示装置及控制其栅极脉冲调制的方法
US20120038610A1 (en) * 2010-08-13 2012-02-16 Au Optronics Corp Gate pulse modulating circuit and method
CN102956216A (zh) * 2012-11-23 2013-03-06 深圳市华星光电技术有限公司 液晶面板驱动系统中的切角电路及均齐度调整系统、方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5424708B2 (ja) * 2009-05-15 2014-02-26 キヤノン株式会社 焦点検出装置
CN102956215B (zh) * 2012-11-23 2015-09-09 深圳市华星光电技术有限公司 液晶面板的驱动方法及驱动电路
US9754555B2 (en) * 2015-08-06 2017-09-05 Mediatek Inc. Method for adjusting display of electronic device and electronic device capable of adjusting display

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102034440A (zh) * 2009-09-24 2011-04-27 瑞鼎科技股份有限公司 栅极驱动器及其操作方法
CN102110405A (zh) * 2009-12-24 2011-06-29 乐金显示有限公司 显示装置及控制其栅极脉冲调制的方法
CN101917179A (zh) * 2010-07-08 2010-12-15 友达光电股份有限公司 栅极脉冲调制电路及其削角调制方法
US20120038610A1 (en) * 2010-08-13 2012-02-16 Au Optronics Corp Gate pulse modulating circuit and method
CN102956216A (zh) * 2012-11-23 2013-03-06 深圳市华星光电技术有限公司 液晶面板驱动系统中的切角电路及均齐度调整系统、方法

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