WO2017075820A1 - 一种分担电容器、包括该分担电容器的像素及阵列基板 - Google Patents

一种分担电容器、包括该分担电容器的像素及阵列基板 Download PDF

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WO2017075820A1
WO2017075820A1 PCT/CN2015/094035 CN2015094035W WO2017075820A1 WO 2017075820 A1 WO2017075820 A1 WO 2017075820A1 CN 2015094035 W CN2015094035 W CN 2015094035W WO 2017075820 A1 WO2017075820 A1 WO 2017075820A1
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electrode layer
dielectric layer
layer
pixel
shared capacitor
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French (fr)
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刘桓
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/711—Electrodes having non-planar surfaces, e.g. formed by texturisation
    • H10D1/714—Electrodes having non-planar surfaces, e.g. formed by texturisation having horizontal extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/411—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by materials, geometry or structure of the substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio

Definitions

  • the present invention relates to the field of thin film transistor liquid crystal displays, and in particular to a shared capacitor, a pixel including the shared capacitor, and an array substrate.
  • pixels are generally divided into a main region and a sub-region, by making the pixel voltage of the sub-region lower than the pixel voltage of the main region.
  • the liquid crystal orientation of the sub-region is different from the liquid crystal orientation of the main region, thereby improving the bias of the large-view character.
  • the pixel In order to make the pixel voltage of the sub-region lower than the pixel voltage of the main region, a charge-sharing technique is usually employed.
  • a pixel structure employing a charge sharing technique is shown in FIG.
  • the pixel includes a main region (Main region) and a sub-region (Sub region) and includes a main thin film transistor 2, a sub-thin film transistor 3, a charging gate line 4, a shared gate line 5, and a shared thin film transistor 6.
  • the charging gate line 4 When the charging gate line 4 is turned on, after the signal line is charged to the pixel electrode ITO of the main area and the sub-area, the charging gate line 4 is turned off, and the sharing gate line 5 is turned on, so that the shared capacitor 1 and the pixel electrode ITO of the sub-area are turned on, thereby The shared capacitor 1 is caused to share a portion of the charge on the pixel electrode of the sub-region. Therefore, the voltage of the pixel electrode in the sub-region is lowered to an appropriate ratio, and the voltage values of the sub-region and the main region are different.
  • the shared capacitors in the prior art generally include two structures of an MII structure and an MIS structure.
  • the shared capacitor 100 includes a first metal layer 101, a first dielectric layer 102, a second dielectric layer 103, and a pixel electrode layer 104 which are sequentially disposed on the array substrate 110.
  • the first metal layer 101 and the pixel electrode layer 104 are respectively two plates of the shared capacitor 100, and the pixel electrode layer 104 may be formed of indium tin oxide. As shown in FIG.
  • the first metal plate 101 is connected to the V common potential, and since the pixel electrode layer 104 is connected to the second metal layer 105 through the via 106, the sub-region charge of the pixel passes through the shared thin film transistor 6 (see FIG. 1) When the pixel electrode layer 104 is shared, the potential of the pixel electrode layer 104 is V- shared .
  • FIG. 4 is a cross-sectional view showing a MIS structure of a shared capacitor according to the prior art
  • FIG. 5 is a circuit diagram of the shared capacitor of FIG.
  • the shared capacitor 200 includes a first metal layer 201, a first dielectric layer 202, and a second metal layer 203 which are sequentially disposed on the array substrate 210. Further, a second metal layer 203 is further disposed on the second metal layer 203. Two dielectric layers 220.
  • the first metal layer 201 and the second metal layer 203 are respectively two plates of the capacitor 200.
  • the first metal layer 201 is connected to the V common potential
  • the second metal layer is connected to the shared thin film transistor 6 (see FIG. 1), and its potential is V- shared .
  • the shared capacitor In order to reduce the sub-region voltage to an appropriate value, the shared capacitor must be able to share the appropriate charge amount Q.
  • the amount of charge shared by the shared capacitor can be expressed by the following formula (1):
  • Equation 2 Equation 2
  • ⁇ is the electrolyte dielectric constant
  • A is the plate area
  • d is the distance between the plates.
  • the pixel aperture ratio can be increased.
  • the capacitance of the shared capacitor is also reduced, so that a sufficient charge cannot be shared.
  • the present invention provides a shared capacitor, a pixel including the shared capacitor, and an array substrate.
  • the shared capacitor of the present invention includes: a first electrode layer; a first dielectric layer disposed on the first electrode layer a second electrode layer disposed on the first dielectric layer and electrically insulated from the first electrode layer by the first dielectric layer; a second dielectric layer disposed on the second electrode layer; and a third electrode layer disposed And electrically insulated from the second electrode layer by the second dielectric layer on the second dielectric layer; wherein the third electrode layer is electrically connected to the first electrode layer.
  • the shared capacitor may further include a through hole disposed over the first electrode layer, and the third electrode layer is electrically connected to the first electrode layer through the through hole.
  • the via may extend through the first dielectric layer and/or the second dielectric layer.
  • the first dielectric layer may comprise silicon nitride (SiNx).
  • the second dielectric layer may comprise silicon nitride.
  • the third electrode layer may include indium tin oxide.
  • the present invention also provides a pixel including the above-described shared capacitor.
  • the pixel may further include a main area and a sub-area, and the shared capacitor is electrically connected to the sub-area such that the pixel voltage of the sub-area is lower than the pixel voltage of the main area.
  • the invention also provides an array substrate, wherein the shared capacitor can be disposed on the array substrate.
  • the array substrate may be a glass substrate.
  • the pixel aperture ratio can be improved, thereby improving the product quality of the thin film transistor liquid crystal display.
  • Figure 1 shows a schematic diagram of a pixel structure employing charge sharing techniques.
  • Figure 2 shows a cross-sectional view of the MII structure of a shared capacitor in accordance with the prior art.
  • FIG. 3 is a circuit diagram of the shared capacitor of FIG. 2.
  • FIG. 4 shows a cross-sectional view of a MIS structure of a shared capacitor according to the prior art.
  • FIG. 5 is a circuit diagram of the shared capacitor of FIG. 4.
  • FIG. 5 is a circuit diagram of the shared capacitor of FIG. 4.
  • Figure 6 shows a cross-sectional view of a shared capacitor in accordance with an embodiment of the present invention.
  • Fig. 7 is a circuit diagram of the shared capacitor of Fig. 6.
  • first, second, etc. may be used to describe various elements, components, regions, layers and/or portions, these elements, components, regions, layers and/or portions are not limited to these Limitation of terminology. These terms are only used to distinguish one element, component, region, layer, and / Thus, a first element, component, region, layer, or section, which is discussed below, may be referred to as a second element, component, region, layer, or section, without departing from the teachings of the invention.
  • the shared capacitor of the present invention includes: a first electrode layer; a first dielectric layer disposed on the first electrode layer; and a second electrode layer disposed on the first dielectric layer and passing through the first dielectric layer and the first electrode
  • the layer is electrically insulated; the second dielectric layer is disposed on the second electrode layer; the third electrode layer is disposed on the second dielectric layer and electrically insulated from the second electrode layer by the second dielectric layer; wherein, the third layer The electrode layer is electrically connected to the first electrode layer.
  • the plate area can be reduced while maintaining the same capacitance value, thereby increasing the aperture ratio of the pixel.
  • FIG. 6 is a cross-sectional view of a shared capacitor 300 according to an embodiment of the present invention
  • FIG. 7 is a circuit diagram of the shared capacitor 300 of FIG. As shown in FIG.
  • the shared capacitor includes a first electrode layer 301 disposed on the array substrate 310, a first dielectric layer 302 disposed on the first electrode layer 301, and a first dielectric layer disposed on the first dielectric layer a second electrode layer 303 on 302, a second dielectric layer 304 disposed on the second electrode layer 303, and a third electrode layer 305 disposed on the second dielectric layer 304, wherein the second electrode layer 303 passes
  • the first dielectric layer 302 is electrically insulated from the first electrode layer 301
  • the third electrode layer 305 is electrically insulated from the second electrode layer 303 by the second dielectric layer 304
  • the third electrode layer 305 passes through the via 306 and the first electrode layer. 301 electrical connection.
  • the array substrate 310 in the present invention may be a glass substrate, but the present invention is not limited thereto.
  • the via 306 penetrates the first dielectric layer 302 and the second dielectric layer 304 such that the first electrode layer 301 is exposed in the third electrode layer 305, so that the third electrode layer 305 and the third electrode layer An electrode layer 301 is electrically connected.
  • the through hole 306 only needs to electrically connect the third electrode layer 305 and the second electrode layer 303 to ensure that the third electrode layer 305 is electrically connected to the first electrode layer 301, and the shape and the position thereof are not provided. Special restrictions.
  • the first dielectric layer 302 may include silicon nitride (SiNx).
  • the second dielectric layer 304 can also include silicon nitride.
  • the third electrode layer 305 may function as a pixel electrode layer and include indium tin oxide (ITO).
  • the shared capacitor according to the present embodiment is completely different from the conventional shared capacitor structure.
  • the shared capacitor according to this embodiment uses a three-layer capacitor structure such as a first electrode layer 301 (M1)
  • the three electrode layer 305 is connected to the first electrode layer 301.
  • the third electrode layer 305 and the first electrode layer 301 are connected to the V common potential
  • the second electrode layer 303 is connected to the shared thin film transistor 6 (see Fig. 1) so as to be at the V- shared potential.
  • This "stacked" capacitor structure can reduce the plate area of the shared capacitor, thereby increasing the pixel aperture ratio and improving product penetration, thereby improving product quality.
  • the present invention also provides a pixel in which the shared capacitor of the present invention is provided.
  • the structure is substantially the same as that of the pixel shown in FIG. 1 except that the shared capacitor of the present invention is provided, and details are not described herein again.
  • the shared capacitor of the present invention employs an M1
  • the sub-capacitor C1 is formed between the first electrode layer 301 and the second electrode layer 303
  • the sub-capacitor C2 is formed between the second electrode layer 303 and the third electrode layer 305
  • C1 and C2 are substantially in parallel relationship, so the final sharing
  • C is greater than C1 or C2. Therefore, compared with the conventional shared capacitor structure, the shared capacitor structure of the present invention requires a smaller plate area for the same pixel, thereby increasing the aperture ratio of the pixel, thereby improving product penetration and improving product quality.
  • its implementation is very simple and does not require other new processes.
  • the shared capacitor provided by the present invention and the pixel including the shared capacitor can increase the pixel aperture ratio, thereby improving the product quality of the thin film transistor liquid crystal display.

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Abstract

提供一种分担电容器、包括该分担电容器的像素及阵列基板。该分担电容器（300）包括：第一电极层（301）；第一介电层（302），设置在第一电极层（301）上；第二电极层（303），设置在第一介电层（302）上并通过第一介电层（302）与第一电极层（301）电绝缘；第二介电层（304），设置在第二电极层（303）上；第三电极层（305），设置在第二介电层（304）上并且通过第二介电层（304）与第二电极层（303）电绝缘；其中，第三电极层（305）与第一电极层（301）电连接。该分担电容器及包括该分担电容器的像素，能够提高像素开口率，从而提高薄膜晶体管液晶显示器的产品品质。

Description

一种分担电容器、包括该分担电容器的像素及阵列基板 技术领域
本发明涉及薄膜晶体管液晶显示器领域，具体来说，涉及一种分担电容器、包括该分担电容器的像素及阵列基板。
背景技术
在采用垂直配向技术(即，VA技术)的薄膜晶体管液晶显示器(TFT-LCD)中，通常将像素分为主区与副区，通过使副区的像素电压低于主区的像素电压，使得副区的液晶取向与主区的液晶取向不同，从而改善大视角色偏。
为了使副区的像素电压低于主区的像素电压，通常采用电荷分担(Charge-sharing)技术。图1中示出了采用电荷分担技术的像素结构。如图1所示，像素包括主区(Main区)和副区(Sub区)并且包括主薄膜晶体管2、副薄膜晶体管3、充电栅线4、分担栅线5和分担薄膜晶体管6。当充电栅线4开启时，信号线向主区和副区的像素电极ITO充电后，充电栅线4关闭，分担栅线5开启，使得分担电容器1与副区的像素电极ITO导通，从而使分担电容器1分担一部分副区像素电极上原本充满的电荷，因此，副区的像素电极的电压降低到适当比例，实现副区与主区电压值不同。
现有技术中的分担电容器一般包括MII结构和MIS结构这两种结构。
图2示出了根据现有技术的分担电容器的MII结构的截面图，图3示出了图2的分担电容器的电路图。如图2所示，分担电容器100包括依次设置在阵列基板110上的第一金属层101、第一介电层102、第二介电层103和像素电极层104。其中，第一金属层101和像素电极层104分别是分担电容器100的两个极板，像素电极层104可以由氧化铟锡形成。如图3所示，第一金属板101连接到V共电位，并且，由于像素电极层104通过通孔106连接到第二金属层105，使得像素的副区电荷通过分担薄膜晶体管6(见图1)被分担到像素电极层104上，则像素电极层104的电位为V分担。
图4示出了根据现有技术的分担电容器的MIS结构的截面图，图5是图4 的分担电容器的电路图。如图4所示，分担电容器200包括依次设置在阵列基板210上的第一金属层201、第一介电层202和第二金属层203，另外，在第二金属层203上还设置有第二介电层220。其中，第一金属层201和第二金属层203分别是分担电容器200的两个极板。如图5所示，第一金属层201连接到V共电位，第二金属层连接到分担薄膜晶体管6(见图1)，其电位为V分担。
但是，在像素中设置以上分担电容器会损失像素的开口率，而且分担电容器的极板面积越大，像素开口率损失越大。
虽然在同样电容大小下减小极板面积能够提高像素开口率，从而提高TFT-LCD产品的穿透率，最终提升产品品质。但为了使副区电压降到合适的值，必须使分担电容器能够分担合适的电荷量Q。分担电容器分担的电荷量可以由下式(1)表示：
Q＝C·V  (式1)
其中，C为分担电容器的电容值，V为分担电容器的两极板的电位差。对于每一个固定的灰阶电压而言，V的值是固定的，因此需要将分担电容器的电容设计为合适的值，才能获得合适的大视角色偏效果。分担电容器的电容可以由下式2表示：
Figure PCTCN2015094035-appb-000001
  (式2)
其中，ε为电解质介电系数，A为极板面积，d为两极板间的距离。
因此，如果减小分担电容器的极板的面积，虽然能够增大像素开口率，但是，如上式可知，分担电容器的电容也会减小，从而无法分担足够的电荷。
发明内容
为克服现有技术的不足，本发明提供分担电容器、包括该分担电容器的像素及阵列基板。
本发明的分担电容器包括：第一电极层；第一介电层，设置在第一电极层 上；第二电极层，设置在第一介电层上并通过第一介电层与第一电极层电绝缘；第二介电层，设置在第二电极层上；第三电极层，设置在第二介电层上并且通过第二介电层与第二电极层电绝缘；其中，第三电极层与第一电极层电连接。
根据本发明的一个实施例，分担电容器还可以包括设置在第一电极层之上的通孔，第三电极层通过通孔与第一电极层电连接。
根据本发明的一个实施例，通孔可以贯穿第一介电层和/或第二介电层。
根据本发明的一个实施例，第一介电层可以包括氮化硅(SiNx)。
根据本发明的一个实施例，第二介电层可以包括氮化硅。
根据本发明的一个实施例，第三电极层可以包括氧化铟锡。
本发明还提供一种像素，该像素包括上述分担电容器。
根据本发明的一个实施例，像素还可以包括主区和副区，分担电容器电连接到副区，使得副区的像素电压低于主区的像素电压。
本发明还提供一种阵列基板，上述分担电容器可以设置在该阵列基板上。
根据本发明的一个实施例，上述阵列基板可以是玻璃基板。
通过本发明提供的分担电容器及包括该分担电容器的像素，能够提高像素开口率，从而提高薄膜晶体管液晶显示器的产品品质。
附图说明
通过下面结合附图进行的对实施例的描述，本发明的上述和/或其他目的和优点将会变得更加清楚，其中：
图1示出了采用电荷分担技术的像素结构的示意图。
图2示出了根据现有技术的分担电容器的MII结构的截面图。
图3是图2的分担电容器的电路图。
图4示出了根据现有技术的分担电容器的MIS结构的截面图。
图5是图4的分担电容器的电路图。
图6示出了根据本发明实施例的分担电容器的截面图。
图7是图6的分担电容器的电路图。
具体实施方式
现在在下文中将参照附图更充分地描述示例实施例，然而，示例实施例可以以不同的形式来实施，并不应该被解释为限于在此阐述的实施例。相反，提供这些实施例是为了使这公开将是彻底的和完整的，并将把示例性实施方式充分地传达给本领域技术人员。
将理解的是，当元件或层被称作“在”另一元件或层“上”、“连接到”或“结合到”另一元件或层时，它可以直接在另一元件或层上、直接连接到或直接结合到另一元件或层，或者可存在中间元件或中间层。相反，当元件被称作“直接在”另一元件或层上、“直接连接到”或“直接结合到”另一元件或层时，不存在中间元件或中间层。
将理解的是，尽管在这里可使用术语第一、第二等来描述不同的元件、组件、区域、层和/或部分，但是这些元件、组件、区域、层和/或部分并不受这些术语的限制。这些术语仅是用来将一个元件、组件、区域、层和/或部分与另一个元件、组件、区域、层和/或部分区分开来。因此，在不脱离本发明的教导的情况下，下面讨论的第一元件、组件、区域、层或部分可被命名为第二元件、组件、区域、层或部分。
在这里可使用空间相对术语，如“在…下方”、“在…下面”、“下面的”、“在…上方”、“上面的”等，用来轻松地描述如图中所示的一个元件或特征与其它元件或特征的关系。应该理解的是，空间相对术语意在包含除了在附图中描述的方位之外的装置在使用或操作中的不同方位。
本发明的分担电容器包括：第一电极层；第一介电层，设置在第一电极层上；第二电极层，设置在第一介电层上并通过第一介电层与第一电极层电绝缘；第二介电层，设置在第二电极层上；第三电极层，设置在第二介电层上并且通过第二介电层与第二电极层电绝缘；其中，第三电极层与第一电极层电连接。
而根据本发明提供的分担电容器，在保持相同的电容值的情况下，能够减小极板面积，从而增大像素的开口率。
下面将结合图6和图7来详细说明根据本发明实施例的分担电容器300的截面图和电路图。其中，图6示出了根据本发明实施例的分担电容器300的截面图，图7是图6的分担电容器300的电路图。如图6所示，根据本实施例的分担电容器包括设置在阵列基板310上的第一电极层301、设置在第一电极层301上的第一介电层302、设置在第一介电层302上的第二电极层303、设置在第二电极层303上的第二介电层304、以及设置在第二介电层304上的第三电极层305，其中，第二电极层303通过第一介电层302与第一电极层301电绝缘，第三电极层305通过第二介电层304与第二电极层303电绝缘，第三电极层305通过通孔306与第一电极层301电连接。
本发明中的阵列基板310可以是玻璃基板，但本发明不限于此。另外，在本实施例中，通孔306贯穿第一介电层302和第二介电层304，使得第一电极层301暴露在第三电极层305中，从而使第三电极层305与第一电极层301电连接。需要说明的是，通孔306只要在保证第三电极层305与第二电极层303绝缘的情况下，使得第三电极层305与第一电极层301电连接即可，其形状和设置位置没有特别的限制。
在本实施例中，第一介电层302可以包括氮化硅(SiNx)。第二介电层304也可以包括氮化硅。另外，第三电极层305可以用作像素电极层并包括氧化铟锡(ITO)。
由图6可知，根据本实施例的分担电容器与传统分担电容器结构完全不同。根据本实施例的分担电容器采用第一电极层301(M1)||第二电极层303(M2)||第三电极层305(ITO)这种三层的电容器结构，通过通孔306将第三电极层305连接至第一电极层301。这样，如图7所示，使第三电极层305和第一电极层301连接到V共电位，将第二电极层303连接分担薄膜晶体管6(见图1)，使其处于V分担电位。这种“层叠”的电容器结构能够减小分担电容器的极板面积，从而增大像素开口率，提升产品穿透率，从而提升产品品质。
本发明还提供一种像素，在该像素中，设置有本发明的分担电容器。在该像素中，除设置有本发明的分担电容器以外，其它结构与图1所示的像素基本相同，在此不再赘述。
如上所述，本发明分担电容器采用如图所示的M1||M2||ITO三层电容器结构。由此，第一电极层301与第二电极层303间形成子电容器C1，第二电极层303与第三电极层305间形成子电容器C2，C1与C2实质上呈并联关系，因此最终的分担电容器300的电容的大小为C＝C1+C2。这样，同样的极板面积下，C大于C1或者C2。因此，相比于传统的分担电容器结构，对于同样像素，本发明的分担电容器结构需要更小的极板面积，从而能够提高像素的开口率，从而提升产品穿透率，提升产品品质。另外，其实施也非常简单，不需要其他新增制程。
综上所述，通过本发明提供的分担电容器及包括该分担电容器的像素，能够提高像素开口率，从而提高薄膜晶体管液晶显示器的产品品质。
虽然已经参照本发明的示例性实施例具体地示出并描述了本发明，但是本领域普通技术人员将理解，在不脱离如所附权利要求和它们的等同物所限定的本发明的精神和范围的情况下，可以在此做出形式和细节上的各种改变。应当仅仅在描述性的意义上而不是出于限制的目的来考虑实施例。因此，本发明的范围不是由本发明的具体实施方式来限定，而是由权利要求书来限定，该范围内的所有差异将被解释为包括在本发明中。

Claims (10)

  1. 一种分担电容器，其中，所述分担电容器包括：
    第一电极层；
    第一介电层，设置在第一电极层上；
    第二电极层，设置在第一介电层上并通过第一介电层与第一电极层电绝缘；
    第二介电层，设置在第二电极层上；
    第三电极层，设置在第二介电层上并且通过第二介电层与第二电极层电绝缘；
    其中，第三电极层与第一电极层电连接。
  2. 根据权利要求1所述的分担电容器，其中，所述分担电容器还包括设置在第一电极层之上的通孔，所述第三电极层通过通孔与第一电极层电连接。
  3. 根据权利要求1所述的分担电容器，其中，所述通孔贯穿第一介电层和/或第二介电层。
  4. 根据权利要求1所述的分担电容器，其中，所述第一介电层包括氮化硅。
  5. 根据权利要求1所述的分担电容器，其中，所述第二介电层包括氮化硅。
  6. 根据权利要求1所述的分担电容器，其中，所述第三电极层包括氧化铟锡。
  7. 一种像素，其中，所述像素包括分担电容器，所述分担电容器包括：
    第一电极层；
    第一介电层，设置在第一电极层上；
    第二电极层，设置在第一介电层上并通过第一介电层与第一电极层电绝缘；
    第二介电层，设置在第二电极层上；
    第三电极层，设置在第二介电层上并且通过第二介电层与第二电极层电绝缘；
    其中，第三电极层与第一电极层电连接。
  8. 根据权利要求7所述的像素，其中，所述像素还包括主区和副区，分担电容器电连接到副区，使得副区的像素电压低于主区的像素电压。
  9. 一种阵列基板，其中，在所述阵列基板上设置分担电容器，所述分担电容器包括：
    第一电极层；
    第一介电层，设置在第一电极层上；
    第二电极层，设置在第一介电层上并通过第一介电层与第一电极层电绝缘；
    第二介电层，设置在第二电极层上；
    第三电极层，设置在第二介电层上并且通过第二介电层与第二电极层电绝缘；
    其中，第三电极层与第一电极层电连接。
  10. 根据权利要求9所述的阵列基板，其中，所述阵列基板是玻璃基板。
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