WO2017070886A1 - 传输数据的方法、发送端和接收端 - Google Patents

传输数据的方法、发送端和接收端 Download PDF

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Publication number
WO2017070886A1
WO2017070886A1 PCT/CN2015/093178 CN2015093178W WO2017070886A1 WO 2017070886 A1 WO2017070886 A1 WO 2017070886A1 CN 2015093178 W CN2015093178 W CN 2015093178W WO 2017070886 A1 WO2017070886 A1 WO 2017070886A1
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Prior art keywords
subcarriers
correspondence
loading
lines
bit loading
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PCT/CN2015/093178
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English (en)
French (fr)
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刘建华
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华为技术有限公司
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Priority to CN201580080714.0A priority Critical patent/CN107710707B/zh
Priority to PCT/CN2015/093178 priority patent/WO2017070886A1/zh
Publication of WO2017070886A1 publication Critical patent/WO2017070886A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes

Definitions

  • the embodiments of the present invention relate to the field of communications technologies, and in particular, to a method for transmitting data, a transmitting end, and a receiving end.
  • Digital Subscriber Line (DSL) technology is a high-speed transmission technology for data transmission over a telephone twisted pair, Unshielded Twist Pair (UTP), including Asymmetric Digital Subscriber Line (Asymmetrical Digital). Subscriber Line, ADSL), Very-high-bit-rate Digital Subscriber Line (VDSL), Very High-bit-rate Digital Subscriber Line 2 (VDSL2), based on synthesis The Digital Subscriber Line (IDSL) of the Integrated Services Digital Network (ISDN) and the Single-pair High-bit-rate Digital Subscriber Line (SHDSL).
  • xDSL digital subscriber line technologies
  • G.fast is currently the fastest xDSL technology. In theory, G.fast can provide a maximum speed of 1000 Mbps.
  • DSL deployment scenarios continue to evolve, from Exchange Central Office (CO) to Fiber To The Cabinet (FTTC), from FTTC to Fiber To The Distribute Point (FTTdp); From FTTdp to Fiber To The Door (FTTD) / Fiber To The Floor (FTTF).
  • CO Exchange Central Office
  • FTTC Fiber To The Cabinet
  • FTTdp Fiber To The Distribute Point
  • FTTD Fiber To The Door
  • FTTF Fiber To The Floor
  • the existing binding technology cannot provide the effect of 1 plus 1 or greater than 2 for two reasons: first, the binding is overhead, and the second DSL line is an unshielded twisted pair, and they have serious far-end crosstalk/ Far End crosstalk (FEXT), severe FEXT can cause a sharp drop in speed.
  • DSL introduces Vectoring technology to offset the effects of FEXT.
  • Vectorization technology can achieve a rate of around 95% without FEXT.
  • ITU-T defines a multi-pair pairing standard G.998.1 based on Asynchronous Transfer Mode (ATM), and Ethernet-based multi-pair binding G.998.2
  • ATM Asynchronous Transfer Mode
  • Ethernet-based multi-pair binding G.998.2
  • the multi-pair pairing based on time division inverse multiplexing is bound to G.998.3.
  • the embodiment of the invention provides a method for transmitting data, a transmitting end and a receiving end, and the method can improve binding efficiency.
  • a method for transmitting data for use in a digital subscriber line DSL, the method comprising:
  • the bit loading correspondence includes a sequence of loading bits of all subcarriers in the K lines and a correspondence between each subcarrier and the number of loading bits in all the subcarriers, where the K lines Each line includes N subcarriers, K is a positive integer greater than or equal to 2, and N is a positive integer;
  • the bits of the data to be transmitted are respectively loaded into K*N subcarriers in the K lines by the bit loading correspondence relationship, and the K*N subcarriers after the loading bits are transmitted to the receiving end.
  • the binding between multiple lines is realized by bit loading and arrangement between different line subcarriers, and the binding efficiency is improved.
  • the sender at the code block level needs to be cut, and the receiving party needs to reorder and combine, and the rate of each line is not the same, which may result in
  • the time-consuming delay is large, and the data carried by the sub-carriers in the embodiment of the present invention is bit-level, and the binding delay can be regarded as zero. Therefore, the embodiment of the present invention does not need to wait for delay, thereby improving Binding efficiency.
  • the embodiments of the present invention are not limited thereto.
  • bit loading correspondence may be a table, a matrix, a set of numbers, etc., as long as it can represent the sequence of loading bits of all subcarriers in the K lines and all subcarriers.
  • the correspondence between each subcarrier and the number of loaded bits may be used, and the embodiment of the present invention is not limited thereto.
  • the bit to be transmitted is respectively loaded into K*N subcarriers in the K lines according to the bit loading correspondence, including:
  • the bits of the data to be transmitted are respectively loaded into K*N subs of K lines according to the number of loading bits of each subcarrier in all subcarriers. In the carrier.
  • the determining a bit loading correspondence includes:
  • the bit loading correspondence is determined according to pre-stored rules.
  • the method further includes:
  • the indication message indicating that the bit is loaded with a correspondence, so that the receiving end determines the bit loading correspondence according to the indication message.
  • the determining a bit loading correspondence includes:
  • a method for transmitting data for use in a digital subscriber line DSL, the method comprising:
  • each of the K lines includes N subcarriers, K is a positive integer greater than or equal to 2, and N is a positive integer;
  • bit loading correspondence includes a sequence of loading bits of all subcarriers in the K lines and a correspondence between each subcarrier and a number of loading bits in all subcarriers;
  • the K*N subcarriers are combined according to the bit loading correspondence to obtain transmission data.
  • the embodiment of the present invention combines K*N subcarriers in K lines by bit loading correspondence to obtain transmission data.
  • the binding between multiple lines is realized by bit loading and arrangement between different line subcarriers, and the binding efficiency is improved.
  • the sender at the code block level needs to be cut, and the receiving party needs to reorder and combine, and the rate of each line is not the same, which may result in
  • the time-consuming delay is large, and the data carried by the sub-carriers in the embodiment of the present invention is bit-level, and the binding delay can be regarded as zero. Therefore, the embodiment of the present invention does not need to wait for delay, thereby improving Binding efficiency.
  • the combining the K*N subcarriers according to the bit loading correspondence to obtain the transmission data includes:
  • the loading bits of each of the subcarriers are combined to obtain transmission data.
  • the determining a bit loading correspondence includes:
  • the bit loading correspondence is determined according to pre-stored rules.
  • the method before receiving, by using the K lines, the K*N subcarriers sent by the sending end, the method further includes:
  • the determining a bit loading correspondence includes:
  • a transmitting end is provided, and the transmitting end is capable of implementing any one of the first aspect and an implementation manner thereof, where operations and/or functions of each module in the transmitting end are respectively implemented for
  • the corresponding method features in one aspect and its implementation are not described herein for brevity.
  • a receiving end is provided, and the receiving end is capable of implementing any one of the second aspect and an implementation manner thereof, where operations and/or functions of each module in the receiving end are respectively implemented
  • the corresponding method features in the two aspects and their implementation manners are not described herein for brevity.
  • a processing apparatus is provided, the processing apparatus being applied to a transmitting end or a receiving end.
  • the processing device can be one or more processors or chips. In other possible cases, the processing device can also be the transmitting end or the receiving end itself.
  • the processing device is configured to perform the method of transmitting data in the first aspect, the second aspect, and various implementations thereof.
  • a computer program product comprising: computing The program code, when the computer program code is executed by the computing unit, the processing unit or the processor of the transmitting end or the receiving end, causes the transmitting end or the receiving end to perform the above first aspect, the second aspect, and various implementation manners thereof Any of the methods of transmitting data.
  • a seventh aspect a computer readable storage medium storing a program, the program causing a transmitting end or a receiving end to perform the first aspect, the second aspect, and various implementations thereof Any method of transmitting data.
  • a program for causing a transmitting end or a receiving end to perform the method of transmitting data according to any one of the above first aspect, second aspect, and various implementations thereof.
  • the embodiment of the present invention loads the bits of the data to be transmitted into the K*N subcarriers in the K lines by using the bit loading correspondence, and sends the K*N subcarriers after the loading bit to the receiving end.
  • the binding between multiple lines is realized by bit loading and arrangement between different line subcarriers, and the binding efficiency is improved.
  • FIG. 1 is a schematic flow chart of a method of transmitting data in accordance with one embodiment of the present invention.
  • FIG. 2 is a schematic block diagram of an encoding process in accordance with one embodiment of the present invention.
  • FIG. 3 is a schematic flow chart of a method of transmitting data according to another embodiment of the present invention.
  • FIG. 4 is a schematic block diagram of a decoding process in accordance with one embodiment of the present invention.
  • Figure 5 is a schematic block diagram of a transmitting end in accordance with one embodiment of the present invention.
  • Figure 6 is a schematic block diagram of a receiving end in accordance with one embodiment of the present invention.
  • FIG. 7 is a schematic block diagram of a transmitting end according to another embodiment of the present invention.
  • FIG. 8 is a schematic block diagram of a receiving end according to another embodiment of the present invention.
  • GSM Global System of Mobile communication
  • CDMA Code Division Multiple Access
  • WCDMA Wideband Code Division Multiple Access
  • GPRS General Packet Radio Service
  • LTE Long Term Evolution
  • FDD Frequency Division Duplex
  • TDD Time Division Duplex
  • UMTS Universal Mobile Telecommunications System
  • WiMAX Worldwide Interoperability for Microwave Access
  • the transmitting end/receiving end includes but is not limited to a mobile station (MS, Mobile Station), a mobile terminal (Mobile Terminal), a mobile telephone (Mobile Telephone), a mobile phone (handset), and a portable device. (portable equipment), relay station, access point, in-vehicle device, wearable device, network side device in a future 5G network, or network device in a future public land mobile network (PLMN).
  • MS Mobile Station
  • Mobile Terminal Mobile Terminal
  • mobile telephone Mobile Telephone
  • handset mobile phone
  • portable device portable device.
  • relay station access point
  • in-vehicle device wearable device
  • network side device in a future 5G network or network device in a future public land mobile network (PLMN).
  • PLMN public land mobile network
  • the receiving end of the sending end of the embodiment of the present invention may also include, but is not limited to, an access terminal, a user equipment (User Equipment, UE), a subscriber unit, a subscriber station, a mobile station, a mobile station, a remote station, a remote terminal, a mobile device, User terminal, terminal, wireless communication device, user agent or user device.
  • the access terminal may be a cellular phone, a cordless phone, a Session Initiation Protocol (SIP) phone, a Wireless Local Loop (WLL) station, a Personal Digital Assistant (PDA), with wireless communication.
  • PLMN Public Land Mobile Network
  • FIG. 1 is a schematic flow chart of a method of transmitting data in accordance with one embodiment of the present invention.
  • the method shown in FIG. 1 can be performed by a transmitting end and applied to a digital subscriber line DSL.
  • the method 100 includes:
  • bit loading correspondence includes a sequence of loading bits of all subcarriers in the K lines and a correspondence between each subcarrier and a number of loading bits in all subcarriers, where the K lines
  • Each line in the line includes N subcarriers, K is a positive integer greater than or equal to 2, N is a positive integer;
  • the bits of the data to be transmitted are respectively loaded into K*N subcarriers in the K lines by the bit loading correspondence relationship, and the K*N subcarriers after the loading bits are transmitted to the receiving end.
  • the binding between multiple lines is realized by bit loading and arrangement between different line subcarriers, and the binding efficiency is improved.
  • the sender at the code block level needs to be cut, and the receiving party needs to reorder and combine, and the rate of each line is not the same, which may result in
  • the time-consuming delay is large, and the data carried by the sub-carriers in the embodiment of the present invention is bit-level, and the binding delay can be regarded as zero. Therefore, the embodiment of the present invention does not need to wait for delay, thereby improving Binding efficiency.
  • the embodiments of the present invention are not limited thereto.
  • bit loading correspondence may be a table, a matrix, a set of numbers, etc., as long as it can represent the sequence of loading bits of all subcarriers in the K lines and all subcarriers.
  • the correspondence between each subcarrier and the number of loaded bits may be used, and the embodiment of the present invention is not limited thereto.
  • the data to be transmitted is sequentially according to the number of loading bits of each subcarrier in all subcarriers.
  • the bits are respectively loaded into K*N subcarriers in the K lines.
  • each line of the K lines in the embodiment of the present invention has N subcarriers; each subcarrier in the line has an entry of a corresponding number of loading bits, so K lines have K bit loading.
  • Table; each bit loading table has N elements; therefore, the bit loading tables of the K lines together form an N*K bit loading matrix, wherein the number of rows 1 to N in the bit loading matrix represents a subcarrier index, column
  • the numbers 1 to K are line indexes.
  • the correspondence may be in the form of a table. For example, the correspondence is as shown in Table 1.
  • Table 1 The specific numerical values in Table 1 indicate the number of bits to be loaded on the corresponding subcarriers.
  • the value 3 of the second row and the second column indicates that the data transmitted on the first subcarrier of the first line is 3 Bits, and so on, are not described in detail here.
  • the order of loading bits of all subcarriers in all K lines can be loaded in the order of the first and last rows according to the above loading matrix, as shown in Table 1.
  • the first subcarrier of line 1 may be loaded first, then the second subcarrier is sequentially performed, then the first subcarrier of line 2 is loaded, and so on, and the bits are loaded in this order.
  • the embodiment of the present invention may also be loaded in the order of the first and last columns, that is, as shown in Table 1, the first subcarrier of the line 1 may be loaded first, and then the first subcarrier of the line 2 is loaded, sequentially, and then the line is loaded.
  • the second subcarrier of 1, followed by the second subcarrier of line 2, and so on, is loaded in the order; the sequence of the first and last columns is loaded with the better and the following modules (eg, constellation mapping, constellation normalization) , Vectorization,) to match, to shorten the processing of the latter module and wait for delay.
  • the loading bit may also be performed in other sequences in the embodiment of the present invention, and the embodiment of the present invention is not limited thereto.
  • each of the K lines in the embodiment of the present invention has its own: inverse Fourier transform (IFFT) module. , a time domain processing module (such as a cyclic expansion module, a windowing module) and an analog front end (AFE); and the K lines share a transport protocol related convergence sublayer (TPS-TC) module, a physical medium related convergence concentrator Layer (PMS-TC) module and some physical medium sublayer (PMD) modules, wherein these PMD modules may include trellis coding (Trellis) / Low Density Parity Check Code (LDPC) module, bit loading module and constellation mapping module, and constellation normalization module and crosstalk processing module (Vector). Among them, each module is used for corresponding processing, and the specific processing procedure is shown in FIG. 2 .
  • IFFT inverse Fourier transform
  • TPS-TC transport protocol related convergence sublayer
  • PMS-TC physical medium related convergence concentrator Layer
  • PMD physical medium sublayer
  • PMD physical medium sublayer
  • these PMD modules may include
  • the bit loading module may perform a rule based on trellis coded modulation (TCM) or low density parity check code modulation (LCM) and a bit loading matrix. All subcarriers in all bitload matrices are loaded with bits in a look-ahead manner. That is, the processing of the first subcarrier of the K line is completed first; then the processing of the second subcarrier of the K line is performed in sequence, and so on.
  • the constellation mapping module (mapper) and the constellation normalization module perform constellation mapping and normalization processing on all subcarriers in the bit loading matrix in the same order and send them to the crosstalk cancellation module.
  • the crosstalk cancellation module processes each line.
  • the crosstalk cancellation module can perform crosstalk cancellation as long as it receives a complete line, and each line is independently crosstalk canceled.
  • these subcarriers are sequentially sent to the IFFT module of their own line according to the bit loading matrix.
  • the IFFT module of each line is equal to all the subcarriers of Discrete Multi Tone (DMT)
  • DMT Discrete Multi Tone
  • bit loading module takes bits in the same data stream and loads it onto K different lines. This enables the sender to allocate a data stream to K different lines, that is, to implement binding of the sender's K different lines.
  • K different line bit streams need to be combined into one data stream to recover the data stream of the sender.
  • FIG. 2 is only intended to assist those skilled in the art to understand the embodiments of the present invention, and is not intended to limit the embodiments of the present invention to the specific numerical values or specific examples illustrated. A person skilled in the art will be able to make various modifications and changes in accordance with the example of FIG. 2, and such modifications or variations are also within the scope of the embodiments of the present invention.
  • the implementation of the present invention does not specifically limit the specific coding process, and may encode the K*N subcarriers in the embodiment of the present invention according to the existing coding method and the coding process, and the embodiment of the present invention is not limited thereto. .
  • the order in which the subcarriers are loaded with bits by the sender bit loading module and the order in which the receiver decoding module converts all subcarrier frequency domain signals into bit streams must be strictly consistent. Therefore, the system should synchronize the bit loading matrix between the sender and the receiver during initialization.
  • the synchronization mode can be sent by the sender to the receiver, or the receiver can be sent to the sender through the reverse channel.
  • the transmitting end may first determine the bit. The corresponding relationship is loaded, and then the sender sends the bit-loading correspondence to the receiving end to perform synchronization between the transmitting and receiving parties.
  • the receiving end first determines the bit loading correspondence, and then the receiving end sends the bit loading correspondence to the sending end through the reverse channel to perform synchronization between the transmitting and receiving parties.
  • the bit loading correspondence is determined according to a pre-stored rule.
  • the method may further include:
  • the indication message indicating that the bit is loaded with a correspondence, so that the receiving end determines the bit loading correspondence according to the indication message.
  • the indication message sent by the receiving end is received in 110, and the indication message indicates the bit loading correspondence relationship;
  • FIG. 3 is a schematic flow chart of a method of transmitting data according to another embodiment of the present invention. The method shown in Figure 3 can be performed by the receiving end.
  • the method for transmitting data performed by the receiving end in FIG. 3 corresponds to the sending end, and the step performed by the receiving end can be seen as the reverse process of sending, and each process that the receiving end can implement can refer to each implemented by the transmitting end. The process, in order to avoid repetition, the detailed description is omitted as appropriate herein.
  • the method 300 shown in FIG. 3 can include:
  • bit loading correspondence includes a sequence of loading bits of all subcarriers in the K lines and a correspondence between each subcarrier and a number of loading bits in all subcarriers;
  • the embodiment of the present invention combines K*N subcarriers in K lines by bit loading correspondence to obtain transmission data.
  • the binding between multiple lines is realized by bit loading and arrangement between different line subcarriers, and the binding efficiency is improved.
  • the sender at the code block level needs to be cut, and the receiving party needs to reorder and combine, and the rate of each line is not the same, which may result in
  • the time-consuming delay is large, and the data carried by the sub-carriers in the embodiment of the present invention is bit-level, and the binding delay can be regarded as zero. Therefore, the embodiment of the present invention does not need to wait for delay, thereby improving Binding efficiency.
  • the embodiments of the present invention are not limited thereto.
  • bit loading correspondence may be a table, a matrix, a set of numbers, etc., as long as it can represent the sequence of loading bits of all subcarriers in the K lines and all subcarriers.
  • the correspondence between each subcarrier and the number of loaded bits may be used, and the embodiment of the present invention is not limited thereto.
  • loading bits of each subcarrier in all subcarriers are combined according to a sequence of loading bits of all subcarriers in the K lines, to obtain transmission data.
  • each of the K lines has its own: an analog front end (AFE) and a time domain processing module (for example, de-circulating extended CE processing can be performed).
  • AFE analog front end
  • time domain processing module for example, de-circulating extended CE processing can be performed.
  • FFT module and frequency domain equalization FEQ processing module and the K lines share some physical medium sublayer PMD module, physical medium related convergence sublayer PMS-TC module and transmission protocol related convergence sublayer TPS-TC module;
  • PMD modules may include Trellis/LDPC modules, bit loading modules and constellation mapping modules, as well as constellation normalization modules and crosstalk processing modules (Vector). Among them, each module is used for corresponding processing, and the specific processing procedure is shown in FIG. 4 .
  • the transmitting end may transmit the subcarriers according to the procedure shown in FIG. 2, and then the receiving end needs to merge the K different line bit streams into one data stream to recover the data stream of the sender.
  • the decoding process performed by the receiver is shown in Figure 4.
  • the K lines collect and convert the signals of the respective lines into time domain data signals through their own AFEs, and the respective time domain processing modules process the time domain data signals (for example, The CE is removed, and then sent to the respective FFT module to become the frequency domain signal, and the output of the FFT is processed by the respective FEQ.
  • the FEQ processing After the FEQ processing is completed, it is sent to the crosstalk processing module for crosstalk processing; after the crosstalk processing is completed; the symbol decoder module is executed; (sym symbol decoder module, the crosstalk processing mode is common to K lines); the symbol decoder module is based on the sender
  • the bit loading module processes the subcarrier order and demaps the frequency domain signals of all subcarriers into a bit stream.
  • bit loading module takes bits in the same data stream and loads it onto K different lines. This enables the sender to allocate a data stream to k different lines, that is, to implement binding of the sender's K different lines.
  • FIG. 4 is only intended to assist those skilled in the art to understand the embodiments of the present invention, and is not intended to limit the embodiments of the present invention to the specific numerical values or specific examples illustrated. A person skilled in the art will be able to make various modifications or changes in the form of the embodiment of FIG. 4, and such modifications or variations are also within the scope of the embodiments of the present invention.
  • the implementation of the present invention does not specifically limit the specific decoding process, and the K*N subcarriers in the embodiment of the present invention may be decoded according to the existing decoding method and the decoding process. Not limited to this.
  • the order in which the subcarriers are loaded with bits by the sender bit loading module and the order in which the receiver decoding module converts all subcarrier frequency domain signals into bit streams must be strictly consistent. Therefore, the system should synchronize the bit loading matrix between the sender and the receiver during initialization.
  • the synchronization mode can be sent by the sender to the receiver, or the receiver can be sent to the sender through the reverse channel.
  • the transmitting end may first determine the bit loading correspondence, and then the sending end sends the bit loading correspondence to the receiving end to perform synchronization between the transmitting and receiving parties.
  • the receiving end first determines the bit loading correspondence, and then the receiving end sends the bit loading correspondence to the sending end through the reverse channel to perform synchronization between the transmitting and receiving parties.
  • an indication message sent by the sending end is received; the indication message indicates the bit loading correspondence, and the bit loading correspondence is determined according to the indication message.
  • bit loading correspondence is determined according to pre-stored rules.
  • the method may further include:
  • FIG. 5 is a schematic block diagram of a transmitting end in accordance with one embodiment of the present invention. It should be understood that the transmitting end 500 shown in FIG. 5 can implement the operations related to the transmitting end in the method embodiments of FIG. 1 to FIG. 4, and the operations and/or functions of the respective modules in the transmitting end 500, respectively, in order to implement FIG. 1 to FIG. 4 respectively.
  • the corresponding process in the method embodiment refer to the description in the foregoing method embodiment. To avoid repetition, the detailed description is omitted here.
  • the transmitting end 500 shown in FIG. 5 includes a determining unit 510, a loading unit 520, and a first transmitting unit 530.
  • the determining unit 510 is configured to determine a bit loading correspondence, where the bit loading correspondence includes a sequence of loading bits of all subcarriers in the K lines and a correspondence between each subcarrier and the number of loading bits in all subcarriers, Each of the K lines includes N subcarriers, K is a positive integer greater than or equal to 2, and N is a positive integer.
  • the loading unit 520 is configured to load the bits of the data to be transmitted according to the bit loading correspondence.
  • the first sending unit 530 is configured to send the K*N subcarriers after the loading bits to the receiving end.
  • the bits of the data to be transmitted are respectively loaded into K*N subcarriers in the K lines by the bit loading correspondence relationship, and the K*N subcarriers after the loading bits are transmitted to the receiving end.
  • the binding between multiple lines is realized by bit loading and arrangement between different line subcarriers, and the binding efficiency is improved.
  • the sender at the code block level needs to be cut, and the receiving party needs to reorder and combine, and the rate of each line is not the same, which may result in
  • the time-consuming delay is large, and the data carried by the sub-carriers in the embodiment of the present invention is bit-level, and the binding delay can be regarded as zero. Therefore, the embodiment of the present invention does not need to wait for delay, thereby improving Binding efficiency.
  • the loading unit 520 is specifically configured to sequentially select the number of loading bits of each subcarrier in all subcarriers according to a sequence of loading bits of all subcarriers in the K lines.
  • the bits of the data to be transmitted are respectively loaded into K*N subcarriers of the K lines.
  • the determining unit 510 is specifically configured to determine the bit loading correspondence according to a pre-stored rule.
  • the sending end 500 further includes: a second sending unit.
  • the second sending unit is configured to send an indication message to the receiving end, where the indication message indicates The bit loads the correspondence, so that the receiving end determines the bit loading correspondence according to the indication message.
  • the determining unit 510 is specifically configured to receive an indication message sent by the receiving end, where the indication message indicates the bit loading correspondence, and determine the bit loading correspondence according to the indication message.
  • FIG. 6 is a schematic block diagram of a receiving end in accordance with one embodiment of the present invention. It should be understood that the receiving end 600 shown in FIG. 6 can implement the processes involved in the receiving end in the method embodiments of FIG. 1 to FIG. 4, and the operations and/or functions of the respective modules in the receiving end 600, respectively, in order to implement FIG. 1 to FIG. 4 respectively.
  • the corresponding process in the method embodiment refer to the description in the foregoing method embodiment. To avoid repetition, the detailed description is omitted here.
  • the receiving end 600 shown in FIG. 6 includes a receiving unit 610, a determining unit 620, and a merging unit 630.
  • the receiving unit 610 is configured to receive, by using K lines, K*N subcarriers sent by the transmitting end, where each of the K lines includes N subcarriers, and K is a positive integer greater than or equal to 2, N Is a positive integer;
  • the determining unit 620 is configured to determine a bit loading correspondence, where the bit loading correspondence includes a sequence of loading bits of all subcarriers in the K lines and a correspondence between each subcarrier and a number of loading bits in all subcarriers;
  • the merging unit 630 is configured to combine the K*N subcarriers according to the bit loading correspondence to obtain transmission data.
  • the embodiment of the present invention combines K*N subcarriers in K lines by bit loading correspondence to obtain transmission data.
  • the binding between multiple lines is realized by bit loading and arrangement between different line subcarriers, and the binding efficiency is improved.
  • the sender at the code block level needs to be cut, and the receiving party needs to reorder and combine, and the rate of each line is not the same, which may result in
  • the time-consuming delay is large, and the data carried by the sub-carriers in the embodiment of the present invention is bit-level, and the binding delay can be regarded as zero. Therefore, the embodiment of the present invention does not need to wait for delay, thereby improving Binding efficiency.
  • the merging unit 630 is specifically configured to combine loading bits of each subcarrier in all subcarriers according to a sequence of loading bits of all subcarriers in the K lines to obtain transmission data. .
  • the determining unit 620 is specifically configured to follow the pre-stored rules. Determine the bit loading correspondence.
  • the receiving end 600 further includes: a sending unit.
  • the sending unit is configured to: before the receiving unit receives the K*N subcarriers sent by the sending end by using the K lines, send an indication message to the sending end, where the indication message indicates the bit loading correspondence, so that the sending end is configured according to the The indication message determines the bit loading correspondence.
  • the determining unit 620 is specifically configured to receive an indication message sent by the sending end, where the indication message indicates the bit loading correspondence, and determine the bit loading correspondence according to the indication message.
  • FIG. 7 is a schematic block diagram of a transmitting end according to another embodiment of the present invention. It should be understood that the transmitting end 700 shown in FIG. 7 can implement the processes involved in the sending end in the method embodiments of FIG. 1 to FIG. 4 .
  • the specific function of the sending end 700 refer to the description in the foregoing method embodiment, to avoid repetition, The detailed description is omitted as appropriate.
  • the transmitting end 700 shown in FIG. 7 includes a processor 710, a memory 720, a bus system 730, and a transceiver 740.
  • the processor 710, the memory 720, and the transceiver 740 are connected by a bus system 730, where the memory 720 is configured to store instructions, and the processor 710 is configured to execute an instruction stored in the memory 720 to determine a bit loading correspondence, the bit loading correspondence.
  • each of the K lines includes N subcarriers, and K is greater than Or a positive integer equal to 2, N is a positive integer; and the bits of the data to be transmitted are respectively loaded into K*N subcarriers in the K lines according to the bit loading correspondence; the transceiver 740 is configured to send the loading to the receiving end.
  • the bits of the data to be transmitted are respectively loaded into K*N subcarriers in the K lines by the bit loading correspondence relationship, and the K*N subcarriers after the loading bits are transmitted to the receiving end.
  • the binding between multiple lines is realized by bit loading and arrangement between different line subcarriers, and the binding efficiency is improved.
  • the sender at the code block level needs to be cut, and the receiving party needs to reorder and combine, and the rate of each line is not the same, which may result in
  • the time-consuming delay is large, and the data carried by the sub-carriers in the embodiment of the present invention is bit-level, and the binding delay can be regarded as zero. Therefore, the embodiment of the present invention does not need to wait for delay, thereby improving Binding efficiency.
  • Processor 710 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the foregoing method may be completed by an integrated logic circuit of hardware in the processor 710 or an instruction in a form of software.
  • the processor 710 may be a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a Field Programmable Gate Array (FPGA), or the like. Programmable logic devices, discrete gates or transistor logic devices, discrete hardware components.
  • DSP digital signal processor
  • ASIC application specific integrated circuit
  • FPGA Field Programmable Gate Array
  • the general purpose processor may be a microprocessor or the processor or any conventional processor or the like.
  • the steps of the method disclosed in the embodiments of the present invention may be directly implemented by the hardware decoding processor, or may be performed by a combination of hardware and software modules in the decoding processor.
  • the software module can be located in a random access memory (RAM), a flash memory, a read-only memory (ROM), a programmable read only memory or an electrically erasable programmable memory, a register, etc. In the storage medium.
  • the storage medium is located in the memory 720.
  • the processor 710 reads the information in the memory 720 and completes the steps of the foregoing method in combination with hardware.
  • the bus system 730 may include a power bus, a control bus, and a status signal bus in addition to the data bus. Wait. However, for clarity of description, various buses are labeled as bus system 730 in the figure.
  • the processor 710 sequentially, according to the sequence of loading bits of all the subcarriers in the K lines, sequentially according to the number of loading bits of each subcarrier in all subcarriers.
  • the bits are respectively loaded into K*N subcarriers in the K lines.
  • the processor 710 determines the bit loading correspondence according to a pre-stored rule.
  • the transceiver 740 is further configured to send an indication message to the receiving end, where the indication message indicates the bit loading correspondence, so that the receiving end determines the bit loading correspondence according to the indication message.
  • the processor 710 receives the indication message sent by the receiving end, where the indication message indicates the bit loading correspondence, and determines the bit loading correspondence according to the indication message.
  • FIG. 8 is a schematic block diagram of a receiving end according to another embodiment of the present invention. It should be understood that the receiving end 800 shown in FIG. 8 can implement the processes involved in the receiving end in the method embodiments of FIG. 1 to FIG. 4, and the operations and/or functions of the respective modules in the receiving end 800, respectively, in order to implement FIG. 1 to FIG. 4 respectively.
  • the corresponding process in the method embodiment refer to the description in the foregoing method embodiment, in order to avoid repetition, Detailed descriptions are omitted as appropriate herein.
  • the receiving end 800 shown in FIG. 8 includes a processor 810, a memory 820, a bus system 830, and a transceiver 840.
  • the processor 810, the memory 820, and the transceiver 840 are connected by a bus system 830, where the memory 820 is used to store instructions, and the transceiver 840 receives K*N subcarriers sent by the transmitting end through K lines, wherein the K lines Each of the lines includes N subcarriers, K is a positive integer greater than or equal to 2, and N is a positive integer.
  • the processor 810 is configured to execute an instruction stored in the memory 820 to determine a bit loading correspondence, where the bit loading correspondence includes The sequence of loading bits of all subcarriers in the K lines and the correspondence between each subcarrier and the number of loaded bits in all subcarriers; and combining the K*N subcarriers according to the bit loading correspondence to obtain transmission data.
  • the embodiment of the present invention combines K*N subcarriers in K lines by bit loading correspondence to obtain transmission data.
  • the binding between multiple lines is realized by bit loading and arrangement between different line subcarriers, and the binding efficiency is improved.
  • the sender at the code block level needs to be cut, and the receiving party needs to reorder and combine, and the rate of each line is not the same, which may result in
  • the time-consuming delay is large, and the data carried by the sub-carriers in the embodiment of the present invention is bit-level, and the binding delay can be regarded as zero. Therefore, the embodiment of the present invention does not need to wait for delay, thereby improving Binding efficiency.
  • Processor 810 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the foregoing method may be completed by an integrated logic circuit of hardware in the processor 810 or an instruction in a form of software.
  • the processor 810 may be a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a Field Programmable Gate Array (FPGA), or the like. Programmable logic devices, discrete gates or transistor logic devices, discrete hardware components.
  • DSP digital signal processor
  • ASIC application specific integrated circuit
  • FPGA Field Programmable Gate Array
  • the general purpose processor may be a microprocessor or the processor or any conventional processor or the like.
  • the steps of the method disclosed in the embodiments of the present invention may be directly implemented by the hardware decoding processor, or may be performed by a combination of hardware and software modules in the decoding processor.
  • the software module can be located in a random access memory (RAM), flash memory, read-only memory (ROM), programmable read only memory or electrically erasable programmable storage. , registers, etc. in the mature storage medium of the field.
  • the storage medium is located in the memory 820.
  • the processor 810 reads the information in the memory 820 and completes the steps of the foregoing method in combination with hardware.
  • the bus system 830 may include a power bus, a control bus, and a status signal bus in addition to the data bus. Wait. However, for clarity of description, various buses are labeled as bus system 830 in the figure.
  • the processor 810 combines the loading bits of each of the subcarriers according to the sequence of loading bits of all the subcarriers in the K lines to obtain transmission data.
  • the processor 810 determines the bit loading correspondence according to a pre-stored rule.
  • the transceiver 840 is further configured to: before the receiving unit receives the K*N subcarriers sent by the sending end by using the K lines, send an indication message to the sending end, where the indication message indicates that the bit loading corresponds to Relationship, so that the sending end determines the bit loading correspondence according to the indication message.
  • the processor 810 is configured to receive an indication message sent by the sending end, where the indication message indicates the bit loading correspondence, and determine the bit loading correspondence according to the indication message.
  • system and “network” are used interchangeably herein.
  • the term “and/or” in this context is merely an association describing the associated object, indicating that there may be three relationships, for example, A and / or B, which may indicate that A exists separately, and both A and B exist, respectively. B these three situations.
  • the character "/" in this article generally indicates that the contextual object is an "or" relationship.
  • B corresponding to A means that B is associated with A, and B can be determined according to A.
  • determining B from A does not mean that B is only determined based on A, and that B can also be determined based on A and/or other information.
  • the disclosed systems, devices, and methods may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of cells is only a logical function division.
  • multiple units or components may be combined or integrated. Go to another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, or an electrical, mechanical or other form of connection.
  • the units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the embodiments of the present invention.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.
  • Computer readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one location to another.
  • a storage medium may be any available media that can be accessed by a computer. Take this as an example but Without limitation, the computer readable medium can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage media or other magnetic storage device, or can be used to carry or store desired program code in the form of an instruction or data structure.
  • Any connection may suitably be a computer readable medium.
  • the software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave
  • coaxial cable , fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, wireless, and microwave are included in the fixing of the associated media.
  • a disk and a disc include a compact disc (CD), a laser disc, a compact disc, a digital versatile disc (DVD), a floppy disk, and a Blu-ray disc, wherein the disc is usually magnetically copied, and the disc is The laser is used to optically replicate the data. Combinations of the above should also be included within the scope of the computer readable media.

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Abstract

本发明实施例提供了一种传输数据的方法、发送端和接收端，应用于数字用户线路DSL中，该方法包括：确定比特加载对应关系，该比特加载对应关系包括K条线路中所有子载波的加载比特的先后顺序以及所有子载波中每个子载波与加载比特个数的对应关系，其中，该K条线路中的每条线路包括N个子载波，K为大于或等于2的正整数，N为正整数；按照该比特加载对应关系将待传输数据的比特分别加载到K条线路中的K*N个子载波中；向接收端发送加载比特后的该K*N个子载波。本发明实施例通过比特加载和不同线路子载波之间安排，实现了多条线路的绑定，提高了绑定效率。

Description

传输数据的方法、发送端和接收端 技术领域
本发明实施例涉及通信技术领域，特别涉及一种传输数据的方法、发送端和接收端。
背景技术
数字用户线(Digital Subscriber Line，DSL)技术是一种通过电话双绞线,即无屏蔽双绞线(Unshielded Twist Pair，UTP)进行数据传输的高速传输技术，包括非对称数字用户线(Asymmetrical Digital Subscriber Line，ADSL)、甚高速数字用户线(Very-high-bit-rate Digital Subscriber Line，VDSL)、甚高速数字用户线2(Very-high-bit-rate Digital Subscriber Line 2，VDSL2)、基于综合业务数字网(Integrated Services Digital Network，ISDN)的数字用户线(ISDN Digital Subscriber Line，IDSL)和单线对高速数字用户线(Single-pair High-bit-rate Digital Subscriber Line，SHDSL)等。在各种数字用户线技术(xDSL)中,G.fast是目前速度最快的xDSL技术，理论上G.fast能提供最大的1000Mbps的总速率。
DSL的部署场景不断演进，从Exchange中心局(Central Office，CO)到光纤到街边柜(Fiber To The Cabinet，FTTC)，从FTTC到光纤到配线点(Fiber To The Distribute Point，FTTdp)；从FTTdp到光纤到门口(Fiber To The Door，FTTD)/光纤到楼层(Fiber To The Floor，FTTF)。换句话说光进铜退，铜线越来越短。很多电信运营商在离用户最近的一段铺的电话线有两对双绞线，甚至使用四对双绞线的网线(CAT5)。为了充分利用存在的铜线资源，提供可比拟光纤速率的接入速率。提高速率的最简单的技术就是绑定(bonding)技术，把多对线绑在一起成为一个整体的信息管道。
现有绑定技术不能提供1加1大于等于2的效果，有两个原因：第一是绑定是有开销的，第二DSL线路是非屏蔽双绞线，他们存在着严重的远端串扰/串音(Far End crosstalk，FEXT)，严重的FEXT会导致速率急剧下降。为此，DSL引入矢量化(Vectoring)技术抵消FEXT的影响。矢量化技术能使速率达到没有FEXT时的95％左右。
一些地区和国家铺电话线的时候，从中心局CO到用户家CPE是铺了不 只一对电话线的。为了充分利用多对电话线的资源，ITU-T分别定义了基于异步传输模式(Asynchronous Transfer Mode，ATM)的多线对绑定标准G.998.1，基于以太网的多线对绑定G.998.2，基于时分反向复用的多线对绑定G.998.3，这三种绑定技术都是建立在DSL的传送协议相关汇聚子层TPS-TC层的上面。然而，现有的绑定技术均存在效率低的问题。
因此，如何高效地实现绑定成为亟待解决的问题。
发明内容
本发明实施例提供了一种传输数据的方法、发送端和接收端，该方法能够提高绑定效率。
第一方面，提供了一种传输数据的方法，应用于数字用户线路DSL中，该方法包括：
确定比特加载对应关系，该比特加载对应关系包括K条线路中所有子载波的加载比特的先后顺序以及所有子载波中每个子载波与加载比特个数的对应关系，其中，该K条线路中的每条线路包括N个子载波，K为大于或等于2的正整数，N为正整数；
按照该比特加载对应关系将待传输数据的比特分别加载到K条线路中的K*N个子载波中；
向接收端发送加载比特后的该K*N个子载波。
因此，本发明实施例通过比特加载对应关系将待传输数据的比特分别加载到K条线路中的K*N个子载波；并向接收端发送加载比特后的该K*N个子载波。本发明实施例通过比特加载和不同线路子载波之间安排，实现了多条线路的绑定，提高了绑定效率。
进一步地，由于，现有的绑定中每条线路中的数据是码块级别的，码块级别发送方需要切割，接收方要重新排序并合，每条线路的速率不一样等，会导致消耗大量时间，时延大，而本发明实施例中的子载波承载的数据是比特级别的，无需切割，绑定时延可以认为为零，因此，本发明实施例无需等待时延，进而提高了绑定效率。
应理解，本发明实施例中的K条线路可以是实际的K对双绞线，也可以是实际A对双绞线和幻影(Phantom)模式产生的B条线路，其中，K＝A+B，本发明实施例并不对此做限定。
应理解，该比特加载对应关系的具体形式可以是一个表格，也可以是一个矩阵，还可以是一组数字等，只要能够表示K条线路中所有子载波的加载比特的先后顺序以及所有子载波中每个子载波与加载比特个数的对应关系即可，本发明实施例并不限于此。
结合第一方面，在第一方面的一种实现方式中，该按照该比特加载对应关系将待传输数据的比特分别加载到K条线路中的K*N个子载波中，包括：
根据该K条线路中的所有的子载波的加载比特的先后顺序，依次按照所有子载波中每个子载波的加载比特个数将待传输数据的比特分别加载到K条线路中的K*N个子载波中。
结合第一方面及其上述实现方式，在第一方面的另一种实现方式中，该确定比特加载对应关系，包括：
按照预存储的规则确定该比特加载对应关系。
结合第一方面及其上述实现方式，在第一方面的另一种实现方式中，该方法还包括：
向该接收端发送指示消息，该指示消息指示该比特加载对应关系，以便该接收端根据该指示消息确定该比特加载对应关系。
结合第一方面及其上述实现方式，在第一方面的另一种实现方式中，该确定比特加载对应关系，包括：
接收该接收端发送的指示消息，该指示消息指示该比特加载对应关系；
根据该指示消息确定该比特加载对应关系。
第二方面，提供了一种传输数据的方法，应用于数字用户线路DSL中，该方法包括：
通过K条线路接收发送端发送的K*N个子载波，其中，该K条线路中的每条线路包括N个子载波，K为大于或等于2的正整数，N为正整数；
确定比特加载对应关系，该比特加载对应关系包括该K条线路中所有子载波的加载比特的先后顺序以及所有子载波中每个子载波与加载比特个数的对应关系；
按照该比特加载对应关系合并该K*N个子载波，获得传输数据。
因此，本发明实施例通过比特加载对应关系合并K条线路中的K*N子载波，获得传输数据。本发明实施例通过比特加载和不同线路子载波之间安排，实现了多条线路的绑定，提高了绑定效率。
进一步地，由于，现有的绑定中每条线路中的数据是码块级别的，码块级别发送方需要切割，接收方要重新排序并合，每条线路的速率不一样等，会导致消耗大量时间，时延大，而本发明实施例中的子载波承载的数据是比特级别的，无需切割，绑定时延可以认为为零，因此，本发明实施例无需等待时延，进而提高了绑定效率。
结合第二方面，在第二方面的一种实现方式中，该按照该比特加载对应关系合并该K*N个子载波，获得传输数据，包括：
根据该K条线路中的所有的子载波的加载比特的先后顺序，合并所有子载波中每个子载波的加载比特，获得传输数据。
结合第二方面及其上述实现方式，在第二方面的另一种实现方式中，该确定比特加载对应关系，包括：
按照预存储的规则确定该比特加载对应关系。
结合第二方面及其上述实现方式，在第二方面的另一种实现方式中，在通过K条线路接收发送端发送的K*N个子载波之前，该方法还包括：
向该发送端发送指示消息，该指示消息指示该比特加载对应关系，以便该发送端根据该指示消息确定该比特加载对应关系。
结合第二方面及其上述实现方式，在第二方面的另一种实现方式中，该确定比特加载对应关系，包括：
接收该发送端发送的指示消息，该指示消息指示该比特加载对应关系；
根据该指示消息确定该比特加载对应关系。
第三方面，提供了一种发送端，该发送端能够实现第一方面及其实现方式中的任一实现方式，该发送端中的各个模块的操作和/或功能，分别用于实现的第一方面及其实现方式中的相应方法特征，为了简洁，在此不再赘述。
第四方面，提供了一种接收端，该接收端能够实现第二方面及其实现方式中的任一实现方式，该接收端中的各个模块的操作和/或功能，分别用于实现的第二方面及其实现方式中的相应方法特征，为了简洁，在此不再赘述。
第五方面，提供了一种处理装置，该处理装置应用于发送端或接收端。该处理装置可以为一个或多个处理器或芯片。在其他可能情况下，该处理装置也可以为发送端或接收端本身。该处理装置被配置用于执行上述第一方面、第二方面，及其各种实现方式中的传输数据的方法。
第六方面，提供了一种计算机程序产品，该计算机程序产品包括：计算 机程序代码，当该计算机程序代码被发送端或接收端的计算单元、处理单元或处理器运行时，使得该发送端或接收端执行上述第一方面、第二方面，及其各种实现方式中的任一种传输数据的方法。
第七方面，提供了一种计算机可读存储介质，该计算机可读存储介质存储有程序，该程序使得发送端或接收端执行上述第一方面、第二方面，及其各种实现方式中的任一种传输数据的方法。
第八方面，提供了一种程序，使得发送端或接收端执行上述第一方面、第二方面，及其各种实现方式中的任一种传输数据的方法。
基于上述技术方案，本发明实施例通过比特加载对应关系将待传输数据的比特分别加载到K条线路中的K*N个子载波；并向接收端发送加载比特后的该K*N个子载波。本发明实施例通过比特加载和不同线路子载波之间安排，实现了多条线路的绑定，提高了绑定效率。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对本发明实施例中所需要使用的附图作简单地介绍，显而易见地，下面所描述的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是根据本发明一个实施例的传输数据的方法示意流程图。
图2是根据本发明一个实施例的编码处理过程的示意框图。
图3是根据本发明另一实施例的传输数据的方法示意流程图。
图4是根据本发明一个实施例的译码处理过程的示意框图。
图5是根据本发明一个实施例的发送端的示意框图。
图6是根据本发明一个实施例的接收端的示意框图。
图7是根据本发明另一实施例的发送端的示意框图。
图8是根据本发明另一实施例的接收端的示意框图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明的一部分实施例，而不是全部实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创 造性劳动的前提下所获得的所有其他实施例，都应属于本发明保护的范围。
应理解，本发明实施例的技术方案可以应用于各种通信系统，例如：全球移动通讯(Global System of Mobile communication，简称为“GSM”)系统、码分多址(Code Division Multiple Access，简称为“CDMA”)系统、宽带码分多址(Wideband Code Division Multiple Access，简称为“WCDMA”)系统、通用分组无线业务(General Packet Radio Service，简称为“GPRS”)、长期演进(Long Term Evolution，简称为“LTE”)系统、LTE频分双工(Frequency Division Duplex，简称为“FDD”)系统、LTE时分双工(Time Division Duplex，简称为“TDD”)、通用移动通信系统(Universal Mobile Telecommunicatio5 nSystem，简称为“UMTS”)、或全球互联微波接入(Worldwide Interoperabilityfor Microwave Access，简称为“WiMAX”)通信系统等。
还应理解，在本发明实施例中，发送端/接收端包括但不限于移动台(MS，Mobile Station)、移动终端(Mobile Terminal)、移动电话(Mobile Telephone)、手机(handset)及便携设备(portable equipment)、中继站、接入点、车载设备、可穿戴设备、未来5G网络中的网络侧设备或者未来演进的公共陆地移动网络(Public Land Mobile Network，PLMN)中的网络设备等。
本发明实施例中的发送端接收端也可以包括但不限于接入终端、用户设备(User Equipment，UE)、用户单元、用户站、移动站、移动台、远方站、远程终端、移动设备、用户终端、终端、无线通信设备、用户代理或用户装置。接入终端可以是蜂窝电话、无绳电话、会话启动协议(Session Initiation Protocol，SIP)电话、无线本地环路(Wireless Local Loop，WLL)站、个人数字处理(Personal Digital Assistant，PDA)、具有无线通信功能的手持设备、计算设备或连接到无线调制解调器的其它处理设备、车载设备、可穿戴设备、未来5G网络中的终端设备或者未来演进的公共陆地移动网络(Public Land Mobile Network，PLMN)中的终端设备
图1是根据本发明一个实施例的传输数据的方法示意流程图。如图1所示的方法，可以由发送端执行，应用于数字用户线路DSL中，该方法100包括：
110，确定比特加载对应关系，该比特加载对应关系包括K条线路中所有子载波的加载比特的先后顺序以及所有子载波中每个子载波与加载比特个数的对应关系，其中，该K条线路中的每条线路包括N个子载波，K为 大于或等于2的正整数，N为正整数；
120，按照该比特加载对应关系将待传输数据的比特分别加载到K条线路中的K*N个子载波中；
130，向接收端发送加载比特后的该K*N个子载波。
因此，本发明实施例通过比特加载对应关系将待传输数据的比特分别加载到K条线路中的K*N个子载波；并向接收端发送加载比特后的该K*N个子载波。本发明实施例通过比特加载和不同线路子载波之间安排，实现了多条线路的绑定，提高了绑定效率。
进一步地，由于，现有的绑定中每条线路中的数据是码块级别的，码块级别发送方需要切割，接收方要重新排序并合，每条线路的速率不一样等，会导致消耗大量时间，时延大，而本发明实施例中的子载波承载的数据是比特级别的，无需切割，绑定时延可以认为为零，因此，本发明实施例无需等待时延，进而提高了绑定效率。
应理解，本发明实施例中的K条线路可以是实际的K对双绞线，也可以是实际A对双绞线和幻影(Phantom)模式产生的B条线路，其中，K＝A+B，本发明实施例并不对此做限定。
应理解，该比特加载对应关系的具体形式可以是一个表格，也可以是一个矩阵，还可以是一组数字等，只要能够表示K条线路中所有子载波的加载比特的先后顺序以及所有子载波中每个子载波与加载比特个数的对应关系即可，本发明实施例并不限于此。
可选地，作为另一实施例，在120中，根据该K条线路中的所有的子载波的加载比特的先后顺序，依次按照所有子载波中每个子载波的加载比特个数将待传输数据的比特分别加载到K条线路中的K*N个子载波中。
例如，本发明实施例中的K条线路的每条线路都有N个子载波；每条线路中的子载波都有对应的加载比特个数的表项，所以K条线路就有K张比特加载表；每个比特加载表中有N个元素；因此K条线路的比特加载表一起形成N*K的比特加载矩阵，其中，该比特加载矩阵中的行数1～N表示子载波索引，列数1～K是线路索引。对应的，该对应关系可以是表格的形式，例如，该对应关系如表1所示。
其中，表1中的具体数值表示对应的子载波上需要加载的比特数。例如，第二行第二列的数值3，表示第一条线路的第一个子载波上传输的数据为3 比特，依次类推，此处不再详述，再有，所有K条线路中所有子载波的加载比特的先后顺序可以按照上述加载矩阵由先列后行的顺序进行加载，即如表1所示，可以先加载线路1的第一个子载波，之后第二个子载波，依次进行，然后再加载线路2的第一个子载波，依次类推，按照该顺序进行加载比特。本发明实施例也可以先行后列的顺序加载，即如表1所示，可以先加载线路1的第一个子载波，之后加载线路2的第一个子载波，依次进行，然后再加载线路1的第二个子载波，之后加载线路2的第二个子载波，依次类推，按照该顺序进行加载比特；先行后列的顺序加载更好底与后面的模块(例如，星座映射，星座归一化，矢量化Vectoring，)配合，以缩短后面模块的处理及等待时延。应理解，本发明实施例中也可以按照其他顺序进行加载比特，本发明实施例并不限于此。
表1
  线路1 线路2 … 线路k
子载波1 3 4 … 3
子载波2 4 6 … 5
子载波3 7 0 … 8
子载波4 5 9 … 10
… … … … …
子载波N 6 9 … 6
举例来说，如图2所示，发送端在进行数据编码时，本发明实施例中的K条线路中每条线路都对应有自己的：傅里叶逆变换(inverse Fourier transform，IFFT)模块，时域处理模块(例如循环扩展模块，加窗模块)和模拟前端(Analog Front End，AFE)；且这K条线路共用传送协议相关汇聚子层(TPS-TC)模块、物理媒质相关汇聚子层(PMS-TC)模块和一些物理媒质子层(PMD)模块，其中，这些PMD模块可以包括网格编码(Trellis) /低密度奇偶校验码(Low Density Parity Check Code，LDPC)模块，比特加载模块和星座映射模块，以及星座归一化模块和串扰处理模块(Vector)。其中，各个模块用于进行相对应的处理，具体的处理过程如图2所示。
具体而言，如图2所示，系统完成trellis编码或LDPC编码后，比特加载模块根据网格编码编码调制(TCM)或低密度奇偶校验码编码调制(LCM)的规则和比特加载矩阵可以按照先行后列的方式对所有比特加载矩阵中的所有子载波加载比特。即先依次完成K根线的第一个子载波的处理；然后是依次进行K根线的第二个子载波的处理，以此类推。星座映射模块(mapper)和星座归一化模块安照同样的顺序对比特加载矩阵中的所有子载波进行星座映射和归一化处理并送给串扰抵消模块。串扰抵消模块对每一行做处理，串扰抵消模块只要收到完整的一行就可以做串扰抵消，每行之间是独立做串扰抵消的。完成串扰抵消处理后，根据比特加载矩阵把这些子载波顺序送到自己线路的IFFT模块。每条线路的IFFT模块等齐一个离散多音频调制(Discrete Multi Tone，DMT)的所有子载波后，这K条线路做自己的IFFT处理和后面的时域处理。最后送到各自的线路上。
由于比特加载模块在同一数据流中取比特加载到K个不同的线路上。这就在发送方实现了把一个数据流分配到K个不同的线路中去，即实现了发送方K个不同的线路的绑定。
对应地，在接收端需要把K个不同的线路比特流合并成一个数据流，以恢复发送方的那个数据流。
应注意，图2的例子仅仅是为了帮助本领域技术人员理解本发明实施例，而非要将本发明实施例限于所例示的具体数值或具体场景。本领域技术人员根据所给出的图2的例子，显然可以进行各种等价的修改或变化，这样的修改或变化也落入本发明实施例的范围内。换句话说，本发明实施并不对具体的编码过程做具体的限定，可以按照现有的编码方法和编码过程对本发明实施例中的K*N个子载波进行编码，本发明实施例并不限于此。
由于发送方比特加载模块对子载波加载比特的顺序和接收方译码模块把所有子载波频域信号转为比特流的顺序必须严格一致。所以系统在初始化时应该发送方和接收方同步比特加载矩阵，当然同步方式可以发送方发送给接收方，也可以接收方通过反向通道发送给发送方。
换句话说，本发明实施例中，第一种情况，可以是发送端首先确定比特 加载对应关系，然后，发送端将该比特加载对应关系发送给接收端，以进行收发双方的同步。
第二种情况，也可以是接收端首先确定比特加载对应关系，然后，接收端通过反向通道将该比特加载对应关系发送给发送端，以进行收发双方的同步。
相应地，作为另一实施例，针对第一种情况，在110中，按照预存储的规则确定该比特加载对应关系。
进一步地，作为另一实施例，该方法还可以包括：
向该接收端发送指示消息，该指示消息指示该比特加载对应关系，以便该接收端根据该指示消息确定该比特加载对应关系。
可替代地，作为另一实施例，针对第二种情况，在110中接收该接收端发送的指示消息，该指示消息指示该比特加载对应关系；
根据该指示消息确定该比特加载对应关系。
上文中，结合图1和图2从发送端描述了本发明实施例的传输数据的方法，下面结合图3和图4从接收端描述本发明实施例的传输数据的方法。
图3是根据本发明另一实施例的传输数据的方法示意流程图。如图3所示的方法，可以由接收端执行。
应注意，图3中接收端执行的传输数据的方法，与发送端向对应，接收端执行的步骤可以看出是发送的的逆过程，接收端能够实现的各个过程可以参照发送端实现的各个过程，为避免重复，此处适当省略详细描述。应用于数字用户线路DSL中，图3所示的方法300可以包括：
310，通过K条线路接收发送端发送的K*N个子载波，其中，该K条线路中的每条线路包括N个子载波，K为大于或等于2的正整数，N为正整数；
320，确定比特加载对应关系，该比特加载对应关系包括该K条线路中所有子载波的加载比特的先后顺序以及所有子载波中每个子载波与加载比特个数的对应关系；
330，按照该比特加载对应关系合并该K*N个子载波，获得传输数据。
因此，本发明实施例通过比特加载对应关系合并K条线路中的K*N子载波，获得传输数据。本发明实施例通过比特加载和不同线路子载波之间安排，实现了多条线路的绑定，提高了绑定效率。
进一步地，由于，现有的绑定中每条线路中的数据是码块级别的，码块级别发送方需要切割，接收方要重新排序并合，每条线路的速率不一样等，会导致消耗大量时间，时延大，而本发明实施例中的子载波承载的数据是比特级别的，无需切割，绑定时延可以认为为零，因此，本发明实施例无需等待时延，进而提高了绑定效率。
应理解，本发明实施例中的K条线路可以是实际的K对双绞线，也可以是实际A对双绞线和幻影(Phantom)模式产生的B条线路，其中，K＝A+B，本发明实施例并不对此做限定。
应理解，该比特加载对应关系的具体形式可以是一个表格，也可以是一个矩阵，还可以是一组数字等，只要能够表示K条线路中所有子载波的加载比特的先后顺序以及所有子载波中每个子载波与加载比特个数的对应关系即可，本发明实施例并不限于此。
可选地，作为另一实施例，在330中，根据该K条线路中的所有的子载波的加载比特的先后顺序，合并所有子载波中每个子载波的加载比特，获得传输数据。
举例来说，如图4所示，接收端在进行译码时，K条线路中每条线路都对应有自己的：模拟前端(AFE)、时域处理模块(例如可以进行去循环扩展CE处理)、FFT模块和频域均衡FEQ处理模块；且这K条线路共用一些物理媒质子层PMD模块、物理媒质相关汇聚子层PMS-TC模块和传送协议相关汇聚子层TPS-TC模块；其中，这些PMD模块可以包括Trellis/LDPC模块，比特加载模块和星座映射模块，以及星座归一化模块和串扰处理模块(Vector)。其中，各个模块用于进行相对应的处理，具体的处理过程如图4所示。
具体而言，发送端可以按照如图2所示的过程进行发送子载波，然后，接收端需要把K个不同的线路比特流合并成一个数据流，以恢复发送方的那个数据流。接收方的进行的译码过程如图4所示，这K条线路通过自己AFE把各自线路的信号采集和转成时域数据信号，各自的时域处理模块对时域数据信号进行处理(例如去掉CE等)，然后送到各自的FFT模块变为频域信号，FFT的输出经过各自FEQ处理。完成FEQ处理后送到串扰处理模块，进行串扰处理；完成串扰处理后；进行symbol decoder模块；(symbol decoder模块，串扰处理模式是K条线路公共的)；symbol decoder模块根据发送方 的比特加载模块处理子载波顺序，把所有子载波的频域信号解映射为比特流。
由于比特加载模块在同一数据流中取比特加载到K个不同的线路上。这就在发送方实现了把一个数据流分配到k个不同的线路中去，即实现了发送方K个不同的线路的绑定。
应注意，图4的例子仅仅是为了帮助本领域技术人员理解本发明实施例，而非要将本发明实施例限于所例示的具体数值或具体场景。本领域技术人员根据所给出的图4的例子，显然可以进行各种等价的修改或变化，这样的修改或变化也落入本发明实施例的范围内。换句话说，本发明实施并不对具体的译码过程做具体的限定，可以按照现有的译码方法和译码过程对本发明实施例中的K*N个子载波进行译码，本发明实施例并不限于此。
由于发送方比特加载模块对子载波加载比特的顺序和接收方译码模块把所有子载波频域信号转为比特流的顺序必须严格一致。所以系统在初始化时应该发送方和接收方同步比特加载矩阵，当然同步方式可以发送方发送给接收方，也可以接收方通过反向通道发送给发送方。
换句话说，本发明实施例中，第一种情况，可以是发送端首先确定比特加载对应关系，然后，发送端将该比特加载对应关系发送给接收端，以进行收发双方的同步。
第二种情况，也可以是接收端首先确定比特加载对应关系，然后，接收端通过反向通道将该比特加载对应关系发送给发送端，以进行收发双方的同步。
相应地，作为另一实施例，针对第一种情况，在320中，接收该发送端发送的指示消息；该指示消息指示该比特加载对应关系，根据该指示消息确定该比特加载对应关系。
可替代地，作为另一实施例，针对第二种情况，在320中，按照预存储的规则确定该比特加载对应关系。
进一步地，作为另一实施例，该方法还可以包括：
向该发送端发送指示消息，该指示消息指示该比特加载对应关系，以便该发送端根据该指示消息确定该比特加载对应关系。
上文中结合图1至图4详细描述了本发明实施例的传输数据的方法，下面将结合图5至图8详细描述本发明实施例的传输数据的设备。
图5是根据本发明一个实施例的发送端的示意框图。应理解，图5所示的发送端500能够实现图1至图4方法实施例中涉及发送端的各个过程，发送端500中的各个模块的操作和/或功能，分别为了实现图1至图4中的方法实施例中的相应流程，具体可参见上述方法实施例中的描述，为避免重复，此处适当省略详述描述。
图5所示的发送端500包括：确定单元510、加载单元520和第一发送单元530。
具体地，确定单元510用于确定比特加载对应关系，该比特加载对应关系包括K条线路中所有子载波的加载比特的先后顺序以及所有子载波中每个子载波与加载比特个数的对应关系，其中，该K条线路中的每条线路包括N个子载波，K为大于或等于2的正整数，N为正整数；加载单元520用于按照该比特加载对应关系将待传输数据的比特分别加载到K条线路中的K*N个子载波中；第一发送单元530用于向接收端发送加载比特后的该K*N个子载波。
因此，本发明实施例通过比特加载对应关系将待传输数据的比特分别加载到K条线路中的K*N个子载波；并向接收端发送加载比特后的该K*N个子载波。本发明实施例通过比特加载和不同线路子载波之间安排，实现了多条线路的绑定，提高了绑定效率。
进一步地，由于，现有的绑定中每条线路中的数据是码块级别的，码块级别发送方需要切割，接收方要重新排序并合，每条线路的速率不一样等，会导致消耗大量时间，时延大，而本发明实施例中的子载波承载的数据是比特级别的，无需切割，绑定时延可以认为为零，因此，本发明实施例无需等待时延，进而提高了绑定效率。
可选地，作为另一实施例，该加载单元520具体用于根据该K条线路中的所有的子载波的加载比特的先后顺序，依次按照所有子载波中每个子载波的加载比特个数将待传输数据的比特分别加载到K条线路中的K*N个子载波中。
可选地，作为另一实施例，该确定单元510具体用于按照预存储的规则确定该比特加载对应关系。
可选地，作为另一实施例，该发送端500还包括：第二发送单元。
具体地，第二发送单元用于向该接收端发送指示消息，该指示消息指示 该比特加载对应关系，以便该接收端根据该指示消息确定该比特加载对应关系。
可替代地，作为另一实施例，该确定单元510具体用于接收该接收端发送的指示消息，该指示消息指示该比特加载对应关系，并根据该指示消息确定该比特加载对应关系。
图6是根据本发明一个实施例的接收端的示意框图。应理解，图6所示的接收端600能够实现图1至图4方法实施例中涉及接收端的各个过程，接收端600中的各个模块的操作和/或功能，分别为了实现图1至图4中的方法实施例中的相应流程，具体可参见上述方法实施例中的描述，为避免重复，此处适当省略详述描述。
图6所示的接收端600包括接收单元610、确定单元620和合并单元630。
具体地，接收单元610用于通过K条线路接收发送端发送的K*N个子载波，其中，该K条线路中的每条线路包括N个子载波，K为大于或等于2的正整数，N为正整数；
确定单元620用于确定比特加载对应关系，该比特加载对应关系包括该K条线路中所有子载波的加载比特的先后顺序以及所有子载波中每个子载波与加载比特个数的对应关系；
合并单元630用于按照该比特加载对应关系合并该K*N个子载波，获得传输数据。
因此，本发明实施例通过比特加载对应关系合并K条线路中的K*N子载波，获得传输数据。本发明实施例通过比特加载和不同线路子载波之间安排，实现了多条线路的绑定，提高了绑定效率。
进一步地，由于，现有的绑定中每条线路中的数据是码块级别的，码块级别发送方需要切割，接收方要重新排序并合，每条线路的速率不一样等，会导致消耗大量时间，时延大，而本发明实施例中的子载波承载的数据是比特级别的，无需切割，绑定时延可以认为为零，因此，本发明实施例无需等待时延，进而提高了绑定效率。
可选地，作为另一实施例，该合并单元630具体用于根据该K条线路中的所有的子载波的加载比特的先后顺序，合并所有子载波中每个子载波的加载比特，获得传输数据。
可选地，作为另一实施例，该确定单元620具体用于按照预存储的规则 确定该比特加载对应关系。
进一步地，作为另一实施例，该接收端600还包括：发送单元。
具体地，发送单元用于在接收单元通过K条线路接收发送端发送的K*N个子载波之前，向该发送端发送指示消息，该指示消息指示该比特加载对应关系，以便该发送端根据该指示消息确定该比特加载对应关系。
可替代地，作为另一实施例，该确定单元620具体用于接收该发送端发送的指示消息，该指示消息指示该比特加载对应关系；并根据该指示消息确定该比特加载对应关系。
图7是根据本发明另一实施例的发送端的示意框图。应理解，图7所示的发送端700能够实现图1至图4方法实施例中涉及发送端的各个过程，发送端700的具体功能可参见上述方法实施例中的描述，为避免重复，此处适当省略详述描述。
图7所示的发送端700包括：处理器710、存储器720、总线系统730和收发器740。其中，处理器710、存储器720和收发器740通过总线系统730相连，该存储器720用于存储指令，该处理器710用于执行该存储器720存储的指令确定比特加载对应关系，该比特加载对应关系包括K条线路中所有子载波的加载比特的先后顺序以及所有子载波中每个子载波与加载比特个数的对应关系，其中，该K条线路中的每条线路包括N个子载波，K为大于或等于2的正整数，N为正整数；并按照该比特加载对应关系将待传输数据的比特分别加载到K条线路中的K*N个子载波中；收发器740用于向接收端发送加载比特后的该K*N个子载波。
因此，本发明实施例通过比特加载对应关系将待传输数据的比特分别加载到K条线路中的K*N个子载波；并向接收端发送加载比特后的该K*N个子载波。本发明实施例通过比特加载和不同线路子载波之间安排，实现了多条线路的绑定，提高了绑定效率。
进一步地，由于，现有的绑定中每条线路中的数据是码块级别的，码块级别发送方需要切割，接收方要重新排序并合，每条线路的速率不一样等，会导致消耗大量时间，时延大，而本发明实施例中的子载波承载的数据是比特级别的，无需切割，绑定时延可以认为为零，因此，本发明实施例无需等待时延，进而提高了绑定效率。
上述本发明实施例揭示的方法可以应用于处理器710中，或者由处理器 710实现。处理器710可能是一种集成电路芯片，具有信号的处理能力。在实现过程中，上述方法的各步骤可以通过处理器710中的硬件的集成逻辑电路或者软件形式的指令完成。上述的处理器710可以是通用处理器、数字信号处理器(Digital Signal Processor，DSP)、专用集成电路(Application Specific Integrated Circuit，ASIC)、现成可编程门阵列(Field Programmable Gate Array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件。可以实现或者执行本发明实施例中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。结合本发明实施例所公开的方法的步骤可以直接体现为硬件译码处理器执行完成，或者用译码处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存取存储器(Random Access Memory，RAM)、闪存、只读存储器(Read-Only Memory，ROM)、可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器720，处理器710读取存储器720中的信息，结合其硬件完成上述方法的步骤，该总线系统730除包括数据总线之外，还可以包括电源总线、控制总线和状态信号总线等。但是为了清楚说明起见，在图中将各种总线都标为总线系统730。
可选地，作为另一实施例，处理器710根据该K条线路中的所有的子载波的加载比特的先后顺序，依次按照所有子载波中每个子载波的加载比特个数将待传输数据的比特分别加载到K条线路中的K*N个子载波中。
可选地，作为另一实施例，处理器710按照预存储的规则确定该比特加载对应关系。
可选地，作为另一实施例，收发器740还用于向该接收端发送指示消息，该指示消息指示该比特加载对应关系，以便该接收端根据该指示消息确定该比特加载对应关系。
可替代地，作为另一实施例，处理器710接收该接收端发送的指示消息，该指示消息指示该比特加载对应关系，并根据该指示消息确定该比特加载对应关系。
图8是根据本发明另一实施例的接收端的示意框图。应理解，图8所示的接收端800能够实现图1至图4方法实施例中涉及接收端的各个过程，接收端800中的各个模块的操作和/或功能，分别为了实现图1至图4中的方法实施例中的相应流程，具体可参见上述方法实施例中的描述，为避免重复， 此处适当省略详述描述。
图8所示的接收端800包括：处理器810、存储器820、总线系统830和收发器840。其中，处理器810、存储器820和收发器840通过总线系统830相连，该存储器820用于存储指令，收发器840通过K条线路接收发送端发送的K*N个子载波，其中，该K条线路中的每条线路包括N个子载波，K为大于或等于2的正整数，N为正整数；该处理器810用于执行该存储器820存储的指令确定比特加载对应关系，该比特加载对应关系包括该K条线路中所有子载波的加载比特的先后顺序以及所有子载波中每个子载波与加载比特个数的对应关系；并按照该比特加载对应关系合并该K*N个子载波，获得传输数据。
因此，本发明实施例通过比特加载对应关系合并K条线路中的K*N子载波，获得传输数据。本发明实施例通过比特加载和不同线路子载波之间安排，实现了多条线路的绑定，提高了绑定效率。
进一步地，由于，现有的绑定中每条线路中的数据是码块级别的，码块级别发送方需要切割，接收方要重新排序并合，每条线路的速率不一样等，会导致消耗大量时间，时延大，而本发明实施例中的子载波承载的数据是比特级别的，无需切割，绑定时延可以认为为零，因此，本发明实施例无需等待时延，进而提高了绑定效率。
上述本发明实施例揭示的方法可以应用于处理器810中，或者由处理器810实现。处理器810可能是一种集成电路芯片，具有信号的处理能力。在实现过程中，上述方法的各步骤可以通过处理器810中的硬件的集成逻辑电路或者软件形式的指令完成。上述的处理器810可以是通用处理器、数字信号处理器(Digital Signal Processor，DSP)、专用集成电路(Application Specific Integrated Circuit，ASIC)、现成可编程门阵列(Field Programmable Gate Array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件。可以实现或者执行本发明实施例中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。结合本发明实施例所公开的方法的步骤可以直接体现为硬件译码处理器执行完成，或者用译码处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存取存储器(Random Access Memory，RAM)、闪存、只读存储器(Read-Only Memory，ROM)、可编程只读存储器或者电可擦写可编程存储 器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器820，处理器810读取存储器820中的信息，结合其硬件完成上述方法的步骤，该总线系统830除包括数据总线之外，还可以包括电源总线、控制总线和状态信号总线等。但是为了清楚说明起见，在图中将各种总线都标为总线系统830。
可选地，作为另一实施例，处理器810根据该K条线路中的所有的子载波的加载比特的先后顺序，合并所有子载波中每个子载波的加载比特，获得传输数据。
可选地，作为另一实施例，处理器810按照预存储的规则确定该比特加载对应关系。
进一步地，作为另一实施例，收发器840还用于在接收单元通过K条线路接收发送端发送的K*N个子载波之前，向该发送端发送指示消息，该指示消息指示该比特加载对应关系，以便该发送端根据该指示消息确定该比特加载对应关系。
可替代地，作为另一实施例，处理器810用于接收该发送端发送的指示消息，该指示消息指示该比特加载对应关系；并根据该指示消息确定该比特加载对应关系。
应理解，说明书通篇中提到的“一个实施例”或“一实施例”意味着与实施例有关的特定特征、结构或特性包括在本发明的至少一个实施例中。因此，在整个说明书各处出现的“在一个实施例中”或“在一实施例中”未必一定指相同的实施例。此外，这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。应理解，在本发明的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本发明实施例的实施过程构成任何限定。
另外，本文中术语“系统”和“网络”在本文中常被可互换使用。本文中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系。
应理解，在本发明实施例中，“与A相应的B”表示B与A相关联，根据A可以确定B。但还应理解，根据A确定B并不意味着仅仅根据A确定B，还可以根据A和/或其它信息确定B。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、计算机软件或者二者的结合来实现，为了清楚地说明硬件和软件的可互换性，在上述说明中已经按照功能一般性地描述了各示例的组成及步骤。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明的范围。
所属领域的技术人员可以清楚地了解到，为了描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口、装置或单元的间接耦合或通信连接，也可以是电的，机械的或其它的形式连接。
作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本发明实施例方案的目的。
另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以是两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
通过以上的实施方式的描述，所属领域的技术人员可以清楚地了解到本发明可以用硬件实现，或固件实现，或它们的组合方式来实现。当使用软件实现时，可以将上述功能存储在计算机可读介质中或作为计算机可读介质上的一个或多个指令或代码进行传输。计算机可读介质包括计算机存储介质和通信介质，其中通信介质包括便于从一个地方向另一个地方传送计算机程序的任何介质。存储介质可以是计算机能够存取的任何可用介质。以此为例但 不限于：计算机可读介质可以包括RAM、ROM、EEPROM、CD-ROM或其他光盘存储、磁盘存储介质或者其他磁存储设备、或者能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其他介质。此外。任何连接可以适当的成为计算机可读介质。例如，如果软件是使用同轴电缆、光纤光缆、双绞线、数字用户线(DSL)或者诸如红外线、无线电和微波之类的无线技术从网站、服务器或者其他远程源传输的，那么同轴电缆、光纤光缆、双绞线、DSL或者诸如红外线、无线和微波之类的无线技术包括在所属介质的定影中。如本发明所使用的，盘(Disk)和碟(disc)包括压缩光碟(CD)、激光碟、光碟、数字通用光碟(DVD)、软盘和蓝光光碟，其中盘通常磁性的复制数据，而碟则用激光来光学的复制数据。上面的组合也应当包括在计算机可读介质的保护范围之内。
总之，以上所述仅为本发明技术方案的较佳实施例而已，并非用于限定本发明的保护范围。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (20)

  1. 一种传输数据的方法，其特征在于，应用于数字用户线路DSL中，所述方法包括：
    确定比特加载对应关系，所述比特加载对应关系包括K条线路中所有子载波的加载比特的先后顺序以及所有子载波中每个子载波与加载比特个数的对应关系，其中，所述K条线路中的每条线路包括N个子载波，K为大于或等于2的正整数，N为正整数；
    按照所述比特加载对应关系将待传输数据的比特分别加载到K条线路中的K*N个子载波中；
    向接收端发送加载比特后的所述K*N个子载波。
  2. 根据权利要求1所述的方法，其特征在于，
    所述按照所述比特加载对应关系将待传输数据的比特分别加载到K条线路中的K*N个子载波中，包括：
    根据所述K条线路中的所有的子载波的加载比特的先后顺序，依次按照所有子载波中每个子载波的加载比特个数将待传输数据的比特分别加载到K条线路中的K*N个子载波中。
  3. 根据权利要求1或2所述的方法，其特征在于，所述确定比特加载对应关系，包括：
    按照预存储的规则确定所述比特加载对应关系。
  4. 根据权利要求3所述的方法，其特征在于，所述方法还包括：
    向所述接收端发送指示消息，所述指示消息指示所述比特加载对应关系，以便所述接收端根据所述指示消息确定所述比特加载对应关系。
  5. 根据权利要求1或2所述的方法，其特征在于，所述确定比特加载对应关系，包括：
    接收所述接收端发送的指示消息，所述指示消息指示所述比特加载对应关系；
    根据所述指示消息确定所述比特加载对应关系。
  6. 一种传输数据的方法，其特征在于，应用于数字用户线路DSL中，所述方法包括：
    通过K条线路接收发送端发送的K*N个子载波，其中，所述K条线路中的每条线路包括N个子载波，K为大于或等于2的正整数，N为正整数；
    确定比特加载对应关系，所述比特加载对应关系包括所述K条线路中所有子载波的加载比特的先后顺序以及所有子载波中每个子载波与加载比特个数的对应关系；
    按照所述比特加载对应关系合并所述K*N个子载波，获得传输数据。
  7. 根据权利要求6所述的方法，其特征在于，
    所述按照所述比特加载对应关系合并所述K*N个子载波，获得传输数据，包括：
    根据所述K条线路中的所有的子载波的加载比特的先后顺序，合并所有子载波中每个子载波的加载比特，获得传输数据。
  8. 根据权利要求6或7所述的方法，其特征在于，所述确定比特加载对应关系，包括：
    按照预存储的规则确定所述比特加载对应关系。
  9. 根据权利要求8所述的方法，其特征在于，在通过K条线路接收发送端发送的K*N个子载波之前，所述方法还包括：
    向所述发送端发送指示消息，所述指示消息指示所述比特加载对应关系，以便所述发送端根据所述指示消息确定所述比特加载对应关系。
  10. 根据权利要求6或7所述的方法，其特征在于，所述确定比特加载对应关系，包括：
    接收所述发送端发送的指示消息，所述指示消息指示所述比特加载对应关系；
    根据所述指示消息确定所述比特加载对应关系。
  11. 一种发送端，其特征在于，应用于数字用户线路DSL中，包括：
    确定单元，用于确定比特加载对应关系，所述比特加载对应关系包括K条线路中所有子载波的加载比特的先后顺序以及所有子载波中每个子载波与加载比特个数的对应关系，其中，所述K条线路中的每条线路包括N个子载波，K为大于或等于2的正整数，N为正整数；
    加载单元，用于按照所述比特加载对应关系将待传输数据的比特分别加载到K条线路中的K*N个子载波中；
    第一发送单元，用于向接收端发送加载比特后的所述K*N个子载波。
  12. 根据权利要求11所述的发送端，其特征在于，
    所述加载单元具体用于根据所述K条线路中的所有的子载波的加载比 特的先后顺序，依次按照所有子载波中每个子载波的加载比特个数将待传输数据的比特分别加载到K条线路中的K*N个子载波中。
  13. 根据权利要求11或12所述的发送端，其特征在于，
    所述确定单元具体用于按照预存储的规则确定所述比特加载对应关系。
  14. 根据权利要求13所述的发送端，其特征在于，所述发送端还包括：
    第二发送单元，用于向所述接收端发送指示消息，所述指示消息指示所述比特加载对应关系，以便所述接收端根据所述指示消息确定所述比特加载对应关系。
  15. 根据权利要求11或12所述的发送端，其特征在于，
    所述确定单元具体用于接收所述接收端发送的指示消息，所述指示消息指示所述比特加载对应关系，并根据所述指示消息确定所述比特加载对应关系。
  16. 一种接收端，其特征在于，应用于数字用户线路DSL中，包括：
    接收单元，用于通过K条线路接收发送端发送的K*N个子载波，其中，所述K条线路中的每条线路包括N个子载波，K为大于或等于2的正整数，N为正整数；
    确定单元，用于确定比特加载对应关系，所述比特加载对应关系包括所述K条线路中所有子载波的加载比特的先后顺序以及所有子载波中每个子载波与加载比特个数的对应关系；
    合并单元，用于按照所述比特加载对应关系合并所述K*N个子载波，获得传输数据。
  17. 根据权利要求16所述的接收端，其特征在于，
    所述合并单元具体用于根据所述K条线路中的所有的子载波的加载比特的先后顺序，合并所有子载波中每个子载波的加载比特，获得传输数据。
  18. 根据权利要求16或17所述的接收端，其特征在于，
    所述确定单元具体用于按照预存储的规则确定所述比特加载对应关系。
  19. 根据权利要求18所述的接收端，其特征在于，所述接收端还包括：
    发送单元，用于在接收单元通过K条线路接收发送端发送的K*N个子载波之前，向所述发送端发送指示消息，所述指示消息指示所述比特加载对应关系，以便所述发送端根据所述指示消息确定所述比特加载对应关系。
  20. 根据权利要求16或17所述的接收端，其特征在于，
    所述确定单元具体用于接收所述发送端发送的指示消息，所述指示消息指示所述比特加载对应关系；并根据所述指示消息确定所述比特加载对应关系。
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