WO2017070861A1

WO2017070861A1 - Interrupt response method, apparatus and base station

Info

Publication number: WO2017070861A1
Application number: PCT/CN2015/093041
Authority: WO
Inventors: 袁张慧
Original assignee: 华为技术有限公司
Priority date: 2015-10-28
Filing date: 2015-10-28
Publication date: 2017-05-04
Also published as: CN107003899B; CN107003899A

Abstract

An embodiment of the present invention discloses an interrupt response method, an apparatus, and a base station. The method can be applied to a base station whose CPU is provided with an MMU and at least two registers, each of the registers containing an interrupt number and a process number. The method comprises: interrupting a target process running under a user mode when receiving an interrupt request carrying the interrupt number, and storing context information of the target process; acquiring the process number of the target process; judging whether there is a target register in which the process number of the target process and the interrupt number are stored among the at least two registers; if there is a register in which the process number of the target process and the interrupt number are stored, then executing an interrupt handler corresponding to the interrupt number under the user mode; and when the execution of the interrupt handler is complete, continuing running the target process according to the stored context information of the target process. By implementing the embodiment of the present invention, the running efficiency of the process can be improved.

Description

Interrupt response method, device and base station

Technical field

The embodiments of the present invention relate to the field of communications technologies, and in particular, to an interrupt response method, apparatus, and base station.

Background technique

When the central processing unit (CPU) includes a memory management unit (MMU), the working state of the operating system may include a kernel state and a user state, and the kernel state is a mode in which the operating system kernel runs, and runs on The process of this mode can access system memory, peripherals, etc. without restriction; the user state refers to the non-privileged state, and the process running in this state is limited by hardware, and some privileged operations cannot be performed.

When the operating system runs a process, if an external emergency occurs, the operating system will be suspended to process the emergency. After the processing, the suspended process will continue. This process is called interrupt. Since the interrupt needs to be switched from the user mode to the kernel state, when there is a plurality of interrupts when running a certain process, the operating system needs to frequently switch between the user state and the kernel state, which reduces the running efficiency of the process.

Summary of the invention

The embodiment of the invention discloses an interrupt response method, device and base station, which are used for improving the running efficiency of a process.

A first aspect of the embodiment of the present invention discloses a base station, including a memory and a central processing unit CPU, wherein the CPU is provided with a memory management unit MMU, and the CPU is further provided with at least two registers, each of which is stored in the register. There is an interrupt number and a process number, where:

The memory is used to store processes and programs;

The CPU is connected to the memory through a memory bus, and the CPU is used to:

When receiving an interrupt request carrying an interrupt number, interrupting a target process running in a user state, and storing context information of the target process;

Obtaining the process ID of the target process;

Determining whether a register exists in the at least two registers, where the process number of the target process and the interrupt number are stored;

If there is a register storing the process ID of the target process and the interrupt number, executing an interrupt processing program corresponding to the interrupt number in the user state;

When the interrupt handler is executed, the target process is continued to be run according to the stored context information of the target process.

With reference to the first aspect of the embodiments of the present invention, in a first possible implementation manner of the first aspect of the embodiments, the CPU is further configured to:

If there is no register storing the process number of the target process and the interrupt number, the user mode is switched to the kernel mode;

Executing, in the kernel state, an interrupt processing program corresponding to the interrupt number;

When the interrupt handler is executed, the kernel mode is switched to the user mode;

The target process continues to run in the user state according to the stored context information of the target process.

With reference to the first possible implementation manner of the first aspect of the embodiments of the present invention, in a second possible implementation manner of the first aspect of the embodiments, the CPU further includes a transmission backup buffer, where the transmission A matching table of virtual addresses to physical addresses is stored in the backing buffer;

The manner in which the CPU executes the interrupt processing program corresponding to the interrupt number in the user state is specifically:

Performing, in the user state, an interrupt processing program corresponding to the interrupt number according to a matching table corresponding to a user state stored in the transmission backing buffer;

After the CPU is switched from the user mode to the kernel mode, the CPU is further configured to:

Refreshing the matching table corresponding to the user state stored in the transmission backing buffer to a matching table corresponding to the kernel state;

The manner in which the CPU executes the interrupt processing program corresponding to the interrupt number in the kernel state is specifically:

Performing, in the kernel state, an interrupt processing program corresponding to the interrupt number according to a matching table corresponding to a kernel state stored in the transport backup buffer;

After the CPU is switched from the kernel mode to the user mode, the CPU is further configured to:

The matching table corresponding to the kernel state stored in the transmission backing buffer is refreshed to a matching table corresponding to the user state.

A second aspect of the embodiments of the present invention discloses a terminal response apparatus, where the apparatus is disposed in a base station, where a central processing unit CPU of the base station is provided with a memory management unit MMU, and at least two registers are further disposed in the CPU. Each of the registers stores an interrupt number and a process number, and the device includes:

An interrupt unit, configured to interrupt a target process running in a user state when receiving an interrupt request carrying an interrupt number;

a storage unit, configured to store context information of a target process interrupted by the interrupt unit;

An obtaining unit, configured to acquire a process ID of a target process interrupted by the interrupt unit;

a determining unit, configured to determine whether a register exists in the at least two registers, and a process number of the target process acquired by the acquiring unit and the interrupt number are stored;

a first execution unit, configured to: when the judgment result of the determining unit is that the process register and the interrupt number of the target process are stored in the register, execute the interrupt processing program corresponding to the interrupt number in the user state;

a first running unit, configured to continue to run the target process of the interrupt unit interrupt according to the context information of the target process stored by the storage unit when the interrupt processing program executed by the first execution unit is executed.

With reference to the second aspect of the embodiments of the present invention, in a first possible implementation manner of the second aspect of the embodiment, the device further includes:

a switching unit, configured to switch from the user state to a kernel state when the judgment result of the determining unit is that the process number of the target process and the interrupt number are stored in the non-existing register;

a second execution unit, configured to execute an interrupt processing program corresponding to the interrupt number in a kernel state of the switching unit switching;

The switching unit is further configured to: when the interrupt processing program executed by the second execution unit is executed, switch from the kernel state to the user state;

a second running unit, configured to continue to run the target process of the interrupt unit interrupt according to the context information of the target process stored by the storage unit in the user state.

With reference to the first possible implementation manner of the second aspect of the embodiment of the present invention, in a second possible implementation manner of the second aspect of the embodiment, the CPU further includes a transmission backup buffer, where the transmission A matching table of virtual addresses to physical addresses is stored in the backing buffer;

The first execution unit is configured to execute, in the user state, an interrupt processing program corresponding to the interrupt number according to a matching table corresponding to a user state stored in the transmission backup buffer;

The device also includes:

a refreshing unit, configured to refresh the matching table corresponding to the user state stored in the transmission backing buffer to a matching table corresponding to the kernel state after the switching unit is to be switched from the user state to the kernel state;

The second execution unit is configured to execute, in the kernel state, an interrupt processing program corresponding to the interrupt number according to a matching table corresponding to a kernel state stored in the transport backup buffer;

The refreshing unit is further configured to: after the switching unit switches the kernel state to the user state, refresh a matching table corresponding to a kernel state stored in the transmission backing buffer to a matching table corresponding to a user state. .

A third aspect of the embodiments of the present invention discloses an interrupt response method, which is applied to a base station of a central processing unit CPU in which a memory management unit MMU is disposed, and the CPU further includes at least two registers, each of the registers. There is an interrupt number and a process number stored in the method, and the method includes:

Obtaining the process ID of the target process;

With reference to the third aspect of the embodiments of the present invention, in a first possible implementation manner of the third aspect of the embodiments, the method further includes:

If there is no register storing the process number of the target process and the interrupt number, the Switch to the kernel mode;

With reference to the first possible implementation manner of the third aspect of the embodiments of the present invention, in a second possible implementation manner of the third aspect of the embodiments, the CPU further includes a transmission backup buffer, where the transmission A matching table of virtual addresses to physical addresses is stored in the backing buffer;

The interrupt processing program corresponding to the execution of the interrupt number in the user state includes:

After the user mode is switched to the kernel mode, the method further includes:

The interrupt processing program corresponding to executing the interrupt number in the kernel state includes:

After the switching from the kernel mode to the user mode, the method further includes:

In the embodiment of the present invention, when there is a process number and an interrupt number in which the running process is stored in the register, the interrupt response will be performed in the user state, and the user state is not required to be switched to the kernel state. Therefore, the running efficiency of the process can be improved.

DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings to be used in the embodiments will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without paying for creative labor.

1 is a structural diagram of a base station according to an embodiment of the present invention;

2 is a structural diagram of an interrupt response apparatus according to an embodiment of the present invention;

3 is a flowchart of an interrupt response method according to an embodiment of the present invention;

FIG. 4 is a flowchart of another interrupt response method disclosed in an embodiment of the present invention.

detailed description

The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.

The embodiment of the invention discloses an interrupt response method, device and base station, which are used for improving the running efficiency of a process. The details are described below separately.

For a better understanding of the embodiments of the present invention, the application scenarios of the embodiments of the present invention are described below. In the embodiment of the present invention, a central processing unit (CPU) of the base station is provided with a memory management unit (MMU), and the working states of the base station operating system include a user state and a kernel state. In addition, the CPU is further provided with at least two registers, each of which stores an interrupt number and a process number. When a process corresponding to the process number stored in a register is run in the user mode, if an interrupt request is received, And the interrupt number carried by the interrupt request is the interrupt number stored in this register, and the base station operating system can respond to the interrupt request directly in the user state. In addition, the CPU is further provided with a Translation Lookaside Buffer (TLB). The TLB stores a matching table of virtual addresses to physical addresses. When the base station operating system works in the user state, the TLB stores the user state corresponding to The matching table of the virtual address to the physical address. When the base station operating system works in the kernel state, the TLB stores the matching table of the virtual address to the physical address corresponding to the kernel state. Therefore, the operating system performs between the kernel state and the user state. When switching, the TLB needs to be refreshed to refresh the matching table stored in the TLB to the matching table corresponding to the working state.

Please refer to FIG. 1. FIG. 1 is a structural diagram of a base station according to an embodiment of the present invention. The base station is the base station introduced above. As shown in FIG. 1, the base station 100 can include:

Memory 101 for storing processes and programs;

The CPU 102 is connected to the memory 101 via a memory bus 103, and the CPU 102 is configured to:

When receiving the interrupt request carrying the interrupt number, interrupting the target process running in the user state, and storing the context information of the target process;

Get the process ID of the target process;

Determining whether there is a register in the at least two registers, wherein the process number of the target process and the interrupt number carried by the interrupt request are stored;

If there is a register storing the process number of the target process and the interrupt number carried by the interrupt request, the interrupt processing program corresponding to the interrupt number carried in the interrupt request is executed in the user state;

When the interrupt handler finishes executing, the target process continues to run based on the context information of the stored target process.

As a possible implementation manner, the CPU 102 is further configured to:

If there is no register to store the process number of the target process and the interrupt number carried by the interrupt request, the user mode is switched to the kernel mode;

Executing an interrupt handler corresponding to the interrupt number carried in the interrupt request in the kernel state;

When the interrupt handler finishes executing, it will be switched from kernel mode to user mode;

The user process continues to run the target process according to the context information of the stored target process.

As a possible implementation manner, the manner in which the CPU 102 executes the interrupt processing program corresponding to the interrupt number carried in the interrupt request by the CPU 102 is specifically:

And executing, in the user state, an interrupt processing program corresponding to the interrupt number carried by the interrupt request according to the matching table corresponding to the user state stored in the transmission backup buffer;

After the CPU 102 is switched from the user mode to the kernel mode, the CPU 102 is further configured to:

The manner in which the CPU 102 executes the interrupt handler corresponding to the interrupt number carried in the interrupt request in the kernel state is specifically:

Performing, in the kernel state, an interrupt processing program corresponding to the interrupt number carried in the interrupt request according to the matching table corresponding to the kernel state stored in the transmission backing buffer;

After the CPU 102 is switched from the kernel mode to the user mode, the CPU 102 is further configured to:

The matching table corresponding to the kernel state stored in the transmission backing buffer is refreshed to the matching table corresponding to the user state.

In the base station described in FIG. 1, when there is a process number and an interrupt number in which the running process is stored in the register, the interrupt response will be performed in the user mode, and the user state is not required to be switched to the kernel state, thereby improving the operating efficiency of the process. .

Please refer to FIG. 2. FIG. 2 is an interrupt response apparatus according to an embodiment of the present invention. The interrupt response device is disposed in the base station described above. As shown in FIG. 2, the interrupt response apparatus 200 can include:

The interrupting unit 201 is configured to interrupt the target process running in the user state when receiving the interrupt request carrying the interrupt number;

The storage unit 202 is configured to store context information of the target process interrupted by the interrupt unit 201.

The obtaining unit 203 is configured to acquire a process ID of the target process interrupted by the interrupt unit 201.

The determining unit 204 is configured to determine whether the register is stored in the at least two registers, and the process ID of the target process acquired by the obtaining unit 203 and the interrupt number carried by the interrupt request are stored;

The first execution unit 205 is configured to: when the judgment result of the determining unit 204 is that the process ID of the target process and the interrupt number carried by the interrupt request are stored in the register, the interrupt processing program corresponding to the interrupt number carried in the interrupt request is executed in the user state;

The first running unit 206 is configured to continue to run the target process interrupted by the interrupting unit 201 according to the context information of the target process stored by the storage unit 202 when the interrupt processing program executed by the first executing unit 205 is executed.

As a possible implementation, the interrupt response apparatus 200 may further include:

The switching unit 207 is configured to switch from the user mode to the kernel mode when the judgment result of the determining unit 204 is that the process number of the target process and the interrupt number carried by the interrupt request are stored in the non-existing register;

The second execution unit 208 is configured to execute, in the kernel mode switched by the switching unit 207, an interrupt processing program corresponding to the interrupt number carried by the interrupt request;

The switching unit 207 is further configured to switch from the kernel mode to the user state when the interrupt processing program executed by the second execution unit 208 is executed;

The second running unit 209 is configured to continue to run the target process interrupted by the interrupting unit 201 according to the context information of the target process stored by the storage unit 202 in the user state.

Specifically, after the switching unit 207 is switched from the kernel mode to the user state, the second running unit 209 is triggered to continue to run the interrupt ticket according to the context information of the target process stored in the user state according to the storage unit 202. The target process interrupted by meta 201.

As a possible implementation manner, the first execution unit 205 is specifically configured to execute, in the user state, an interrupt processing program corresponding to the interrupt number carried by the interrupt request according to the matching table corresponding to the user state stored in the transmission backup buffer;

The interrupt response device 200 can also include:

The refreshing unit 210 is configured to refresh the matching table corresponding to the user state stored in the transmission backing buffer to the matching table corresponding to the kernel state after the switching unit 207 switches from the user state to the kernel state;

The second execution unit 208 is specifically configured to execute, in the kernel state, an interrupt processing program corresponding to the interrupt number carried by the interrupt request according to the matching table corresponding to the kernel state stored in the transmission backup buffer;

The refreshing unit 210 is further configured to refresh the matching table corresponding to the kernel state stored in the transmission backing buffer to the matching table corresponding to the user state after the switching unit 207 switches the kernel state to the user state.

In the interrupt response apparatus described in FIG. 2, when there is a process number and an interrupt number in which the register stores the running process, the interrupt response will be performed in the user mode, and it is not necessary to switch from the user state to the kernel state, thereby improving the process. operating efficiency.

Please refer to FIG. 3. FIG. 3 is a flowchart of an interrupt response method according to an embodiment of the present invention. The interrupt response method is applicable to the base station described above. As shown in FIG. 3, the interrupt response method may include the following steps.

S301. When receiving the interrupt request carrying the interrupt number, interrupt the target process running in the user state, and store the context information of the target process.

In this embodiment, in the process of running the target process in the user state, when receiving the interrupt request carrying the interrupt number, the target process needs to be interrupted, and the context information of the target process is stored, so that the target process needs to continue to be run later. It is possible to continue running the portion of the target process that is not running from the interrupted location of the target process. The context information of the target process may include interrupt location information of the target process, part of the running information, and part of the information that is not running.

S302. Obtain a process ID of the target process.

In this embodiment, when an interrupt request carrying an interrupt number is received, the process ID of the target process is obtained. The step S301 and the step S302 may be performed in series or in parallel, which is not limited in this embodiment.

S303. Determine whether a register has a process number of the target process and an interrupt number carried by the interrupt request in the at least two registers. If yes, execute step S304. If not, execute step S306.

In this embodiment, after the process number of the target process is obtained, the process ID of the target process and the interrupt number carried by the interrupt request are compared with the process number and the interrupt number stored in each register.

S304. Execute an interrupt processing program corresponding to the interrupt number in the user mode.

In this embodiment, when the process number stored in one register is the same as the process ID of the target process, and the interrupt number stored in the register is the same as the interrupt number carried in the interrupt request, it indicates that the register is stored in at least two registers. The process ID of the target process and the interrupt number carried by the interrupt request will execute the interrupt handler corresponding to the interrupt number carried in the interrupt request in the user mode.

S305. When the interrupt handler is executed, continue to run the target process according to the context information of the stored target process.

In this embodiment, when it is detected that the interrupt handler corresponding to the interrupt number carried by the interrupt request is executed in the user state, the user state continues to run the target process from the interrupted position of the target process according to the stored context information of the target process. The part that runs.

S306. The user mode is switched to the kernel mode, and the interrupt handler corresponding to the interrupt number carried in the interrupt request is executed in the kernel state.

In this embodiment, when there is no register in at least two registers, the process number of the target process and the interrupt number carried by the interrupt request are simultaneously stored, indicating that the process number and the interrupt request of the target process are not stored in the at least two registers. The interrupt number carried will not be able to directly respond to the interrupt in the user mode. Therefore, the user mode is switched to the kernel mode, and the interrupt handler corresponding to the interrupt number carried in the interrupt request is executed in the kernel mode.

S307. When the interrupt handler is executed, the kernel state is switched to the user state, and the user process continues to run the target process according to the context information of the stored target process.

In this embodiment, since the target process needs to be run in the user mode, when it is detected that the interrupt handler corresponding to the interrupt number carried by the interrupt request is executed in the kernel state, the kernel state is switched to the user state, and in the user mode. The non-running portion of the target process continues to run from the interrupted location of the target process based on the context information of the stored target process.

In the interrupt response method described in FIG. 3, when there is a process number and an interrupt number in which the register stores the running process, the interrupt response will be performed in the user mode, and it is not necessary to switch from the user state to the kernel state. Can improve the efficiency of the process.

Please refer to FIG. 4. FIG. 4 is a flowchart of another interrupt response method according to an embodiment of the present invention. The interrupt response method is applicable to the base station described above. As shown in FIG. 4, the interrupt response method may include the following steps.

S401. When receiving the interrupt request carrying the interrupt number, interrupt the target process running in the user state, and store the context information of the target process.

S402. Obtain a process ID of the target process.

In this embodiment, when an interrupt request carrying an interrupt number is received, the process ID of the target process is obtained. The step S401 and the step S402 may be performed in series or in parallel, which is not limited in this embodiment.

S403. Determine whether a process number of the target process and the interrupt number are stored in the at least two registers. If yes, execute step S404. If not, execute step S406.

S404: Perform an interrupt processing program corresponding to the interrupt number carried in the interrupt request according to the matching table corresponding to the user state stored in the TLB in the user state.

In this embodiment, when the process number stored in one register is the same as the process ID of the target process, and the interrupt number stored in the register is the same as the interrupt number carried in the interrupt request, it indicates that the register is stored in at least two registers. The process ID of the target process and the interrupt number carried in the interrupt request will execute the interrupt handler corresponding to the interrupt number carried in the interrupt request according to the matching table corresponding to the user mode stored in the TLB.

S405. When the interrupt handler is executed, continue to run the target process according to the context information of the stored target process.

S406. The user state is switched to the kernel state, and the matching table corresponding to the user state stored in the TLB is refreshed to a matching table corresponding to the kernel state.

In this embodiment, when there is no register in at least two registers, the process number of the target process and the interrupt number carried by the interrupt request are simultaneously stored, indicating that the process number and the interrupt request of the target process are not stored in the at least two registers. The interrupt number carried will not be able to directly respond to the interrupt in the user mode. Therefore, the user mode is switched to the kernel mode, and the matching table corresponding to the user mode stored in the TLB is refreshed to the matching table corresponding to the kernel state.

S407. The interrupt processing program corresponding to the interrupt number carried in the interrupt request is executed in the kernel state according to the matching table corresponding to the kernel state stored in the TLB.

S408. When the interrupt processing program is executed, the kernel state is switched to the user state, and the matching table corresponding to the kernel state stored in the TLB is refreshed to the matching table corresponding to the user state.

In this embodiment, since the target process needs to be run in the user mode, when it is detected that the interrupt handler corresponding to the interrupt number carried by the interrupt request is executed in the kernel state, the kernel state is switched to the user state, and the TLB is The matching table corresponding to the stored kernel state is refreshed to the matching table corresponding to the user state.

S409. The user process continues to run the target process according to the context information of the stored target process.

In this embodiment, the user mode continues to run the non-running part of the target process from the interrupted location of the target process according to the context information of the stored target process.

In the interrupt response method described in FIG. 4, when there is a process number and an interrupt number in which the register stores the running process, the interrupt response will be performed in the user state, and it is not necessary to switch from the user state to the kernel state, thereby improving the process. operating efficiency.

In one embodiment, an embodiment of the present invention further discloses a computer storage medium storing a computer program. When the computer program in the computer storage medium is read into a computer, the computer can cause the computer to complete the disclosure of the embodiment of the present invention. All steps of the data transfer method.

It should be noted that, for the foregoing various method embodiments, for the sake of simple description, they are all expressed as a series of action combinations, but those skilled in the art should know that the present invention is not described. The order of the actions is limited, as some steps may be performed in other orders or simultaneously in accordance with the present invention. In addition, those skilled in the art should also understand that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present invention.

A person skilled in the art may understand that all or part of the various steps of the foregoing embodiments may be performed by a program to instruct related hardware. The program may be stored in a computer readable storage medium, and the storage medium may include: Flash disk, Read-Only Memory (ROM), Random Access Memory (RAM), disk or optical disk.

The interrupt response method, device and base station provided by the embodiments of the present invention are described in detail. The principles and embodiments of the present invention are described in the following. The description of the above embodiments is only for helping to understand the present invention. The method and its core idea; at the same time, those skilled in the art, according to the idea of the present invention, there will be changes in the specific implementation and application scope. In summary, the content of the specification should not be understood as Limitations of the invention.

Claims

A base station, comprising: a memory and a central processing unit CPU, wherein the CPU is provided with a memory management unit MMU, wherein the CPU is further provided with at least two registers, and each of the registers stores an interrupt number And a process number where:

The memory is used to store processes and programs;

The CPU is connected to the memory through a memory bus, and the CPU is used to:

When receiving an interrupt request carrying an interrupt number, interrupting a target process running in a user state, and storing context information of the target process;

Obtaining the process ID of the target process;

Determining whether a register exists in the at least two registers, where the process number of the target process and the interrupt number are stored;

If there is a register storing the process ID of the target process and the interrupt number, executing an interrupt processing program corresponding to the interrupt number in the user state;

When the interrupt handler is executed, the target process is continued to be run according to the stored context information of the target process.
The base station according to claim 1, wherein the CPU is further configured to:

If there is no register storing the process number of the target process and the interrupt number, the user mode is switched to the kernel mode;

Executing, in the kernel state, an interrupt processing program corresponding to the interrupt number;

When the interrupt handler is executed, the kernel mode is switched to the user mode;

The target process continues to run in the user state according to the stored context information of the target process.
The base station according to claim 2, wherein the CPU further includes a transmission backup buffer, wherein the transmission backup buffer stores a matching table of a virtual address to a physical address;

The manner in which the CPU executes the interrupt processing program corresponding to the interrupt number in the user state is specifically:

Performing, in the user state, a matching table corresponding to a user state stored in the transmission backup buffer Interrupting the interrupt handler corresponding to the interrupt number;

After the CPU is switched from the user mode to the kernel mode, the CPU is further configured to:

Refreshing the matching table corresponding to the user state stored in the transmission backing buffer to a matching table corresponding to the kernel state;

The manner in which the CPU executes the interrupt processing program corresponding to the interrupt number in the kernel state is specifically:

Performing, in the kernel state, an interrupt processing program corresponding to the interrupt number according to a matching table corresponding to a kernel state stored in the transport backup buffer;

After the CPU is switched from the kernel mode to the user mode, the CPU is further configured to:

The matching table corresponding to the kernel state stored in the transmission backing buffer is refreshed to a matching table corresponding to the user state.
A terminal response device, the device is disposed in a base station, and the central processing unit CPU of the base station is provided with a memory management unit MMU, wherein the CPU is further provided with at least two registers, each of the The register stores an interrupt number and a process number, and the device includes:

An interrupt unit, configured to interrupt a target process running in a user state when receiving an interrupt request carrying an interrupt number;

a storage unit, configured to store context information of a target process interrupted by the interrupt unit;

An obtaining unit, configured to acquire a process ID of a target process interrupted by the interrupt unit;

a determining unit, configured to determine whether a register exists in the at least two registers, and a process number of the target process acquired by the acquiring unit and the interrupt number are stored;

a first execution unit, configured to: when the judgment result of the determining unit is that the process register and the interrupt number of the target process are stored in the register, execute the interrupt processing program corresponding to the interrupt number in the user state;

a first running unit, configured to continue to run the target process of the interrupt unit interrupt according to the context information of the target process stored by the storage unit when the interrupt processing program executed by the first execution unit is executed.
The device according to claim 4, wherein the device further comprises:

a switching unit, configured to switch from the user state to a kernel state when the judgment result of the determining unit is that the process number of the target process and the interrupt number are stored in the non-existing register;

a second execution unit, configured to execute an interrupt processing program corresponding to the interrupt number in a kernel state of the switching unit switching;

The switching unit is further configured to: when the interrupt processing program executed by the second execution unit is executed, switch from the kernel state to the user state;

a second running unit, configured to continue to run the target process of the interrupt unit interrupt according to the context information of the target process stored by the storage unit in the user state.
The apparatus according to claim 5, wherein the CPU further comprises a transmission backup buffer, wherein the transmission backup buffer stores a matching table of a virtual address to a physical address;

The first execution unit is configured to execute, in the user state, an interrupt processing program corresponding to the interrupt number according to a matching table corresponding to a user state stored in the transmission backup buffer;

The device also includes:

a refreshing unit, configured to refresh the matching table corresponding to the user state stored in the transmission backing buffer to a matching table corresponding to the kernel state after the switching unit is to be switched from the user state to the kernel state;

The second execution unit is configured to execute, in the kernel state, an interrupt processing program corresponding to the interrupt number according to a matching table corresponding to a kernel state stored in the transport backup buffer;

The refreshing unit is further configured to: after the switching unit switches the kernel state to the user state, refresh a matching table corresponding to a kernel state stored in the transmission backing buffer to a matching table corresponding to a user state. .
An interrupt response method, the method being applied to a base station provided with a memory management unit MMU in a CPU of a central processing unit, wherein at least two registers are further disposed in the CPU, and one of each of the registers is stored The interrupt number and a process number, the method includes:

When receiving an interrupt request carrying an interrupt number, interrupting a target process running in a user state, and storing context information of the target process;

Obtaining the process ID of the target process;

Determining whether there is a process in the at least two registers that stores the target process Number and the interrupt number;

If there is a register storing the process ID of the target process and the interrupt number, executing an interrupt processing program corresponding to the interrupt number in the user state;

When the interrupt handler is executed, the target process is continued to be run according to the stored context information of the target process.
The method of claim 7, wherein the method further comprises:

If there is no register storing the process number of the target process and the interrupt number, the user mode is switched to the kernel mode;

Executing, in the kernel state, an interrupt processing program corresponding to the interrupt number;

When the interrupt handler is executed, the kernel mode is switched to the user mode;

The target process continues to run in the user state according to the stored context information of the target process.
The method according to claim 8, wherein the CPU further comprises a transmission backup buffer, wherein the transmission backup buffer stores a matching table of virtual addresses to physical addresses;

The interrupt processing program corresponding to the execution of the interrupt number in the user state includes:

Performing, in the user state, an interrupt processing program corresponding to the interrupt number according to a matching table corresponding to a user state stored in the transmission backing buffer;

After the user mode is switched to the kernel mode, the method further includes:

Refreshing the matching table corresponding to the user state stored in the transmission backing buffer to a matching table corresponding to the kernel state;

The interrupt processing program corresponding to executing the interrupt number in the kernel state includes:

Performing, in the kernel state, an interrupt processing program corresponding to the interrupt number according to a matching table corresponding to a kernel state stored in the transport backup buffer;

After the switching from the kernel mode to the user mode, the method further includes:

The matching table corresponding to the kernel state stored in the transmission backing buffer is refreshed to a matching table corresponding to the user state.