JP2015197802A - Information processing device, information processing method and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve throughput without deteriorating real time performance in an environment adopting a multi-core and dual kernel system.SOLUTION: An information processing device having a plurality of processing execution means has control means for cooperating processing by the plurality of processing execution means. The control means includes detection means for detecting a processing request issued from second processing execution means for executing non-priority processing to first processing execution means during the execution of priority processing, determination means for determining whether processing of the processing request is avoidable in the case that the detection means detects the processing request, and execution means for executing avoidance correspondence processing to the processing request in the case that the determination means determines to be avoidable.

Description

  The present invention relates to an information processing apparatus, an information processing method, and a program.

For the general-purpose OS, there is a dual kernel method as a method for improving real-time performance without losing existing functions. The dual kernel method is a method that improves the real-time performance of the system by adding a subsystem with higher operating priority than the original kernel in the kernel and operating tasks that require real-time performance on the subsystem. That is. In the following description, the subsystem side is referred to as a real-time domain, and the existing kernel side is referred to as a non-real-time domain. In order to control in accordance with this operation priority, software independent of the kernel (hereinafter referred to as hypervisor) is placed between the kernel and hardware to control the behavior of the real-time domain and non-real-time domain. ing.
For the non-real time domain, the real time domain is transparent, and the non-real time domain does not need to be aware of the existence of the real time domain. That is, the real-time domain operates with priority over the non-real-time domain. When a task on the real-time domain wakes up, it is preempted regardless of what task is operating on the non-real-time domain, and starts the operation of the real-time domain task.

Further, the domain and the CPU are independent of each other, and any CPU can operate in any domain and switch between domains. In a multi-core environment, while a certain CPU operates in the real-time domain, other CPUs can operate in the non-real-time domain. Therefore, it is possible to improve the throughput of the entire system by utilizing multi-core while maintaining the real-time property.
Patent Document 1 discloses a technique for improving throughput in an environment employing a multi-core and dual kernel method. In this technology, when the CPU 1 operating in the domain A having a high priority and the CPU 2 operating in the domain B having a low priority issue a process for requesting a response to the CPU 1, the CPU 1 changes from the domain A to the domain B. Transition. Then, after the requested processing is performed by the CPU 1 and a response is returned to the CPU 2, the throughput of the entire system is improved by returning to the domain A and restarting the suspended processing.

JP 2010-250817 A

A general-purpose OS that operates in a multi-core environment includes processing that requires synchronization among a plurality of CPUs. An example of processing that requires synchronization among a plurality of CPUs is the synchronization of a translation lookaside buffer (hereinafter referred to as TLB).
In a dual kernel environment in which a real-time OS is used for the real-time domain and a general-purpose OS is used for the non-real-time domain, it is assumed that the CPU operating in the non-real-time domain requests some kind of response to the CPU operating in the real-time domain. Here, when the CPU operating in the non-real-time domain issues a process that continues to wait until a response is returned, the response is not returned until the process in the real-time domain is completed, and the process continues to wait for a response. Therefore, there arises a problem that the throughput of the entire system is lowered.
The technique disclosed in Patent Document 1 reduces the real-time performance instead of improving the throughput with respect to this problem.
An object of the present invention is to improve throughput without degrading real-time performance in an environment employing a multi-core and dual kernel system.

  Therefore, the present invention is an information processing apparatus having a plurality of process execution means, and has a control means for linking processes by the plurality of process execution means, wherein the control means is a first executing priority process. A detection means for detecting a processing request issued from a second processing execution means for executing non-priority processing on the processing execution means, and processing of the processing request when the detection means detects the processing request Determining means for determining whether or not the problem can be avoided, and execution means for executing an avoidance handling process for the process request when the determination means determines that avoidance is possible.

  According to the present invention, it is possible to improve throughput without degrading real-time performance in an environment employing a multi-core and dual kernel method.

It is a figure which shows an example of the hardware constitutions of information processing apparatus. It is a figure which shows an example of a function structure of information processing apparatus. It is a figure which shows an example of the page table regarding TLBSshotdown. It is a sequence diagram which shows an example of a process of TLBSshotdown. It is a sequence diagram which shows an example of the process of TLBSrootdown at the time of applying the existing technique. It is a sequence diagram which shows an example of the process of TLBSshotdown at the time of applying the technique proposed by embodiment. It is a figure which shows an example of a domain switching process management table. It is a flowchart which shows an example of object process detection processing. It is a figure which shows an example of the data structure of an avoidance means management table.

Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.
<Embodiment 1>
FIG. 1 is a diagram illustrating an example of a hardware configuration of an information processing apparatus 200 according to the present embodiment. CPUs (Central Processing Units) 201 and 204 control the entire information processing apparatus 200. The CPUs 201 and 204 are examples of processing execution means in a multi-core environment. MMUs (Memory Management Units) 202 and 205 convert virtual addresses into physical addresses. TLBs (Translation Lookaside Buffers) 203 and 206 cache a correspondence table between virtual addresses and physical addresses used in the MMU. There is one TLB for each CPU, and in a multi-core environment, there is a case that must be synchronized in order to maintain data consistency. A ROM (Read Only Memory) 207 is a non-volatile recording medium capable of recording data and programs, such as a hard disk drive (hereinafter referred to as HDD). A RAM (Random Access Memory) 208 is a memory that temporarily stores programs and data, and is also referred to as a system memory. The address bus 209 is a bus for exchanging addresses. The data bus 210 is a bus for exchanging data.

  When the CPUs 201 and 204 execute programs stored in the ROM 207 and the like, the functional configuration of the information processing apparatus 200 and the processing of the flowchart described below are realized. The functional configuration of the information processing apparatus 200 includes an operating system (hereinafter referred to as OS) function, a kernel function, a hypervisor function, and the like. In FIG. 1, the information processing apparatus 200 according to the present embodiment is configured to have two CPUs, but may be configured to include three or more CPUs.

  FIG. 2 is a diagram illustrating an example of a functional configuration of the information processing apparatus 200 according to the present embodiment. More specifically, FIG. 2 is a diagram illustrating an example of a functional configuration of the hypervisor 100 of the information processing apparatus 200 in the present embodiment. In the present embodiment, a dual kernel method is assumed in which a subsystem having a higher operation priority than the original kernel is added to the kernel, and a task requiring real-time performance is operated on the subsystem. The hypervisor 100 is arranged as an independent function between the kernel and hardware, and controls the subsystem side (real-time domain) and the existing kernel side (non-real-time domain) according to the operation priority. Here, real-time domain processing is an example of priority processing that requires real-time performance. On the other hand, the non-real-time domain process is an example of a non-priority process that does not require real-time performance. The processing executed by the hypervisor 100 is an example of control processing that links real-time domain processing and non-real-time domain processing.

Hereinafter, a more specific functional configuration of the hypervisor 100 will be described.
The CPU-specific domain state management table 101 is a table that holds information indicating whether all CPUs included in the information processing apparatus 200 are currently operating in a real-time domain or a non-real-time domain. The CPU-specific domain state management table 101 holds data for the number of CPUs. The retained data indicates whether the target CPU is operating in the real time domain or non-real time domain. The state of the domain is exclusive, and there is no state that is operating in both domains or that it is not operating in either domain.
The avoidance means management table 102 is a table that holds information related to avoidance means for a process determined as an avoidance target. The information processing apparatus 200 holds the avoidance means management table 102 for each process. In the avoidance means management table 102, information related to avoidance means for processing is described in association with each processing information. A more detailed description of the avoidance means management table 102 will be described later with reference to FIG.

The target process detection unit 103 detects that a CPU operating in the non-real-time domain has requested processing for a CPU operating in the real-time domain (processing is being executed).
The avoidance determination unit 104 determines whether or not the process detected by the target process detection unit 103 can be avoided.
The domain switching detection unit 105 detects switching between a real-time domain and a non-real-time domain.
The domain switching processing management table 106 holds processing information of processing executed when domain switching is detected by the domain switching detection unit 105. A more detailed description of the domain switching process management table 106 will be described later with reference to FIG.
In this embodiment, the per-CPU domain state management table 101, the avoidance means management table 102, and the domain switching process management table 106 are stored in the ROM 207 and HDD of the information processing apparatus 200. However, the present invention is not limited to this. There is no need. For example, these tables may be stored in an external device that can communicate with the information processing apparatus 200 via a network.
The above is the basic configuration of the hypervisor 100 of the information processing apparatus 200 in the present embodiment. Although the details of the data used by the information processing apparatus 200 are not described in detail in the description of FIG. 2, the processing procedure and the like of the present embodiment will be described using more specific data in the following description.

Hereinafter, the existing techniques necessary for understanding the present embodiment will be described with reference to FIGS. 3 to 5. Then, details such as the advantages of the present embodiment over the existing technology will be described with reference to FIGS.
First, with reference to FIGS. 3 and 4, TLBSshotdown, which is a processing example in which the present embodiment is useful, will be described.
FIG. 3 is a diagram illustrating an example of a page table related to TLBSshot for explaining an outline of TLBSbootdown. TLBshotdown is a process for maintaining the consistency of a page table that holds the correspondence between virtual addresses and physical addresses in a multi-core environment. In the environment of FIG. 3, there are CPUs 201 and 204 and TLBs 203 and 206 corresponding to the respective CPUs. The TLBs 203 and 206 cache a part of the page table 301 that exists for each process. Here, it is assumed that the page table entry in the kernel space is rewritten. Since the kernel space page table is common to all processes, the CPUs 201 and 204 refer to the same kernel space page table entry, and the TLBs 203 and 206 hold the common page table entry 302. And
Assume that the CPU 201 rewrites the page table entry 302 existing on the page table 301 without synchronizing, and the CPU 204 accesses an address described in the page table entry 302. In this case, since the page table entry 302 before rewriting is cached in the TLB 206, even if the same address is specified between the CPU 201 and the CPU 204, another page is specified, and the page table is consistent between the CPUs. Sex is lost. The processing for maintaining this consistency is TLBSshotdown.

Next, the flow of TLBSshotdown processing will be described with reference to FIG. FIG. 4 is an example of a sequence diagram illustrating an example of an outline of the TLBSshotdown process. When the CPU 201 rewrites the page table entry, the CPU 201 sends a page table entry change start notification 401 to the CPU 204 that is executing a process for holding the page table entry. When there are a plurality of CPUs executing the process, the CPU 201 sends a page table entry change start notification 401 to all other CPUs (hereinafter referred to as all CPUs) except for itself. The CPU 201 continues to wait until the page table entry change approval notification 402 is returned from all the CPUs (here, the CPU 204) that have notified the page table entry change start notification 401.
Upon receiving the notification, the CPU 204 returns a page table entry change approval notification 402 to the CPU 201 and continues to wait until receiving a page table entry change completion notification 405. The CPU 201 performs a page table entry change process 403 and a TLB invalidation process 404 of itself (CPU 201) after responses are returned from all the CPUs (here, the CPU 204) holding the page table entry to be rewritten. Then, the CPU 201 sends a page table entry change completion notification 405 to all the waiting CPUs (here, the CPU 204). All the CPUs (here, the CPU 204) that have received the page table entry change completion notification 405 perform a TLB invalidation process 406. TLBSshotdown is completed by executing these series of processes.

Next, the flow of processing when TLBSshotdown occurs in the existing multi-core dual kernel method will be described with reference to FIG. FIG. 5 is an example of a sequence diagram illustrating an example of a TLBS bootdown process when an existing technology is applied. Assume that the CPU 201 operates in the real-time domain 501 and the CPU 204 operates in the non-real-time domain 502 in a multi-core environment where the CPU 201 and the CPU 204 operate.
When the CPU 204 rewrites the page table entry in the kernel space, the page table entry change start notification 504 is sent to all the CPUs (here, the CPU 201) other than the CPU that performs the rewriting process. A page table entry change start notification 506 is sent from the CPU 204 to the CPU 201 by the transfer notification 505 via the hypervisor 503, but the CPU 201 is operating in the real-time domain 501. Therefore, the handler process (interrupt process) corresponding to the page table entry change start notification 506, which is the process on the non-real time domain 502, is delayed by the hypervisor 503 until the process on the real time domain 501 is completed. During this time, the CPU 204 continues to wait in a busy loop until a response to the notification is returned, so the system throughput decreases.

When the CPU 201 ends the processing on the real-time domain 501 and starts the processing on the non-real-time domain 502, the handler processing corresponding to the page table entry change start notification 506 is executed. Then, the CPU 201 returns a page table entry change approval notification 507 to the CPU 204. As a result, the notification transfer 508 via the hypervisor 503 returns the page table change approval notification 509 to the non-real time domain 502 of the CPU 204, and the CPU 204 resumes processing.
The CPU 204 performs a page table entry change process 510 and a TLB invalidation process 511, and sends a page table entry change completion notification 512 to the CPU 201 via the hypervisor 503. When the CPU 201 receives the page table entry change completion notification 514 from the CPU 204 via the notification transfer 513, the CPU 201 executes the TLB invalidation processing 515 and completes the TLBSshotdown processing.
As described above, in the existing technology, when a certain CPU is operating in the real-time domain and another CPU issues a TLBSshotdown instruction, the throughput decreases.

Next, in the multi-core dual kernel method to which the technique proposed in the present embodiment is applied, a processing flow when TLBSshotdown occurs will be described with reference to FIG. FIG. 6 is an example of a sequence diagram illustrating an example of TLBSshotdown processing when the technique proposed in the present embodiment is applied. As in the case of FIG. 5, it is assumed that the CPU 201 operates in the real-time domain 601 and the CPU 204 operates in the non-real-time domain 602 in a multi-core environment where the CPU 201 and the CPU 204 operate.
In the proposed technique, the CPU 201 executes the TLB invalidation process 604 when switching from the non-real time domain 602 to the real time domain 601. As a result, the non-real time domain page table is not cached in the TLB while the CPU 201 operates in the real time domain 601.

When the CPU 204 rewrites the page table entry in the kernel space, it tries to send a page table entry change start notification 605 to all the CPUs (here, the CPU 201) other than the CPU that performs the rewriting process. Here, in the proposed technique, when the hypervisor 603 detects that a CPU operating in the non-real-time domain 602 needs to wait until a response is received, another CPU executes a CPU execution domain confirmation process 606. To do. When the CPU execution domain confirmation processing 606 confirms that the execution domain of the communication destination CPU is a real-time domain, the hypervisor 603 performs a determination processing 607 as to whether or not processing of the processing request can be avoided. When it is determined in the determination process 607 that avoidance is possible, the hypervisor 603 returns a page table entry change approval notification 608 to the non-real time domain 602.
Then, the CPU 204 executes a page table entry change process 609 and a TLB invalidation process 610, which are TLBSshotdown processes, as in the existing technique of FIG. Thereafter, in the case of the existing technology, the CPU 204 attempts to notify the CPU 201 of the page table entry change completion notification 611 via the hypervisor 603. However, in the proposed technique, the page table entry change completion notification 611 is ignored, and the CPU 201 is not notified.
Through the above processing, the throughput can be improved without degrading the real-time performance.

Hereinafter, a mechanism for realizing the processing described with reference to FIG. 6 will be described with reference to FIGS.
First, a technique for executing the TLB invalidation process 604 at the time of real-time domain switching will be described with reference to FIG. The domain switching detection unit 105 and the domain switching processing management table 106 in FIG. 7 are the same as described in FIG. The domain switching detection unit 105 detects that the processing of the CPU has switched to a real time domain or a non-real time domain. The domain switching detection unit 105 executes the process indicated by the processing information for each switching destination domain registered in the domain switching process management table 106 every time a domain switch occurs. In this example applied to the TLBShutdown, it is registered in advance in the domain switching process management table 106 so that the TLB invalidation process 701 is executed when switching to the real-time domain.

Next, details of the target process detection process including the CPU execution domain confirmation process 606 and the determination process 607 will be described with reference to FIG. FIG. 8 is a flowchart illustrating an example of target process detection processing including CPU execution domain confirmation processing 606 and determination processing 607.
In S800, the domain switching detection unit 105 confirms (processing determination) whether the communication destination CPU is operating in a real-time domain or a non-real-time domain. When the communication destination CPU is operating in the non-real-time domain, the domain switching detection unit 105 continues the detected process without avoiding the detected process (S803). On the other hand, if the communication destination CPU is operating in the real-time domain, the domain switching detection unit 105 advances the process to S801.
In step S <b> 801, the avoidance determination unit 104 determines whether the processing request detected by the target process detection unit 103 can be avoided. The avoidance determination unit 104 determines whether or not avoidance is possible by the process indicated by the avoidance confirmation process information for the detected process registered in the avoidance means management table 102. Details of the processing of S801 will be described later with reference to FIG. If the avoidance determination unit 104 determines that avoidance is possible, the process proceeds to step S802.
In step S802, the target process detection unit 103 discards the detected process request. Further, avoidance handling processing described later with reference to FIG. 9 is executed. On the other hand, if the avoidance determination unit 104 determines that avoidance is not possible, the process proceeds to step S803. The processing in S803 is as described above.
With the above processing, it is possible to reduce the time that the CPU operating in the non-real time domain unnecessarily waits for the CPU operating in the real time domain, and to improve the system throughput.

FIG. 9 is a diagram illustrating an example of the data structure of the avoidance means management table 102. The avoidance means management table 102 includes four pieces of information: detection target information 901, avoidance confirmation process information 902, avoidance handling process information 903, and valid / invalid flag 904. The avoidance means management table 102 is an example of management information.
The detection target information 901 is information for collating with the processing information of the processing request processing detected by the target processing detection unit 103. When a process corresponding to the information indicated by the detection target information 901 is detected and the valid / invalid flag 904 is valid, the process indicated by the avoidance confirmation process information 902 (avoidance confirmation process), the avoidance response process information 903 Is executed (avoidance handling process).
The avoidance confirmation processing information 902 varies depending on the detection target. When the page table entry change start notification is detected, the avoidance determination unit 104 determines whether the page table entry to be rewritten belongs to which group can be avoided. More specifically, the avoidance determination unit 104 determines that it can be avoided in the case of a page table entry in the user space or kernel space of the non-real-time domain, and cannot be avoided in other cases. Is determined. That is, the avoidance determination unit 104 determines whether or not the avoidance is possible depending on whether or not the page table entry satisfies a predetermined condition. When the avoidance determination unit 104 determines that avoidance is possible by the process indicated by the avoidance confirmation process information 902, the process indicated by the avoidance handling process information 903 is executed instead of the normal process (process of the detected process request). More specifically, as an avoidance handling process corresponding to the page table entry rewriting process, the hypervisor 603 returns a page table entry change approval notification to the processing request source CPU 204. Then, the hypervisor 603 validates the valid / invalid flag 906 of the page table entry change completion notification.

When a page table entry change approval notification is returned to the CPU 204 as a result of the process indicated by the avoidance handling process information 903, the CPU 204 performs a page table entry change process 609 and a TLB invalidation process 610. Then, the CPU 204 sends a page table entry change completion notification 611 to the hypervisor 603.
Here, the page table entry change completion notification valid / invalid flag 906 in the avoidance means management table 102 is validated by the previous page table entry change start notice. Therefore, as this process, the CPU 204 executes a page table entry change completion notification invalidation process 905 that is a process registered in the avoidance means management table 102.
As a result, the CPU 204 can continue the next process without waiting for the process of the CPU 201 operating in the real-time domain to end.

<Other embodiments>
The present invention can also be realized by executing the following processing. That is, software (program) that realizes the functions of the above-described embodiments is supplied to a system or apparatus via a network or various storage media, and a computer (or CPU, MPU, etc.) of the system or apparatus reads the program. It is a process to be executed.

  As described above, according to each of the above-described embodiments, it is possible to improve throughput without degrading real-time performance in an environment employing a multi-core and dual kernel method.

  The preferred embodiment of the present invention has been described in detail above, but the present embodiment is not limited to the specific embodiment, and various modifications can be made within the scope of the gist of the present invention described in the claims.・ Change is possible.

Claims (11)

An information processing apparatus having a plurality of processing execution means,
Control means for coordinating processes by the plurality of process execution means,
The control means includes
Detecting means for detecting a processing request issued from a second processing execution means for executing non-priority processing with respect to the first processing execution means executing the priority processing;
Determination means for determining whether or not processing of the processing request is avoidable when the processing request is detected by the detection means;
An execution unit that executes an avoidance handling process for the processing request when the determination unit determines that avoidance is possible;
An information processing apparatus.   The determination means refers to management information associated with avoidance confirmation processing information for each processing information based on the processing information of the processing request processing, and avoidance confirmation associated with the processing information of the processing request processing The information processing apparatus according to claim 1, wherein it is determined whether or not the processing request process can be avoided according to a result of the avoidance confirmation process indicated by the process information. The management information is associated with avoidance confirmation process information and avoidance handling process information for each process information,
3. The information processing according to claim 2, wherein the execution unit executes the avoidance handling process indicated by the avoidance handling process information associated with the process information of the process of the process request when the determination unit determines that avoidance is possible. apparatus.   The information processing apparatus according to any one of claims 1 to 3, wherein the control unit further includes a continuation unit that continues the processing of the processing request when the determination unit determines that avoidance is not possible. The control means includes a process determination means for determining whether the first process execution means is executing a priority process or a non-priority process when the detection request is detected by the detection means. In addition,
The determination unit determines whether or not processing of the processing request is avoidable when the processing determination unit determines that the first processing execution unit is executing priority processing. 5. The information processing apparatus according to any one of items 4 to 4.   6. The information processing according to claim 1, wherein the detection unit detects the processing request related to the interrupt processing issued from the second processing execution unit to the first processing execution unit. 7. apparatus. The control means further comprises a switching detection means for detecting whether the process execution means executes priority processing or non-priority processing,
The information processing apparatus according to claim 1, wherein the process execution unit executes a process according to the switching detected by the switching detection unit.   The information processing apparatus according to claim 1, wherein the process execution unit executes a process that requires synchronization with another process execution unit. The process execution means is a CPU,
The information processing apparatus according to claim 1, wherein the control unit is a hypervisor that coordinates processing of a plurality of CPUs. An information processing method executed by an information processing apparatus having a plurality of processing execution means,
Including a control step of coordinating processes by the plurality of process execution means,
The control step includes
A detection step of detecting a processing request issued from a second processing execution means for executing non-priority processing with respect to the first processing execution means executing the priority processing;
A determination step of determining whether or not processing of the processing request is avoidable when the processing request is detected by the detection step;
If it is determined that avoidance is possible in the determination step, an execution step of executing avoidance handling processing for the processing request;
An information processing method including: In a computer having a plurality of processing execution means,
Executing a control step for coordinating processes by the plurality of process execution means;
The control step includes
A detection step of detecting a processing request issued from a second processing execution means for executing non-priority processing with respect to the first processing execution means executing the priority processing;
A determination step of determining whether or not processing of the processing request is avoidable when the processing request is detected by the detection step;
If it is determined that avoidance is possible in the determination step, an execution step of executing avoidance handling processing for the processing request;
Including programs.

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