WO2017054412A1 - 阵列基板及其制作方法、显示装置 - Google Patents

阵列基板及其制作方法、显示装置 Download PDF

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Publication number
WO2017054412A1
WO2017054412A1 PCT/CN2016/075398 CN2016075398W WO2017054412A1 WO 2017054412 A1 WO2017054412 A1 WO 2017054412A1 CN 2016075398 W CN2016075398 W CN 2016075398W WO 2017054412 A1 WO2017054412 A1 WO 2017054412A1
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Prior art keywords
edge
array substrate
data lines
parallel
display area
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PCT/CN2016/075398
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English (en)
French (fr)
Inventor
李文波
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京东方科技集团股份有限公司
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Priority to US15/326,002 priority Critical patent/US20170261825A1/en
Publication of WO2017054412A1 publication Critical patent/WO2017054412A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/56—Substrates having a particular shape, e.g. non-rectangular
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections

Definitions

  • the present invention relates to the field of display, and in particular, to an array substrate, a manufacturing method thereof, and a display device.
  • Liquid crystal display panels such as thin film transistor (TFT) TFTs have the advantages of small size, low power consumption, no radiation, low manufacturing cost, etc.
  • TFT thin film transistor
  • the display screen shape of the conventional liquid crystal display panel is generally rectangular, which is applied to the wearable display device.
  • the display screen shape of the liquid crystal display panel is generally determined by the display area (A/A area) of the array substrate, wherein the display area of the array substrate is provided with a plurality of intersecting gate lines and data lines, passing through the gate lines and the data lines. Dividing a plurality of sub-pixel units to realize the display function of the entire liquid crystal display panel.
  • the gate lines and the data lines on the array substrate are both The vertical cross setting mode.
  • the liquid crystal display panel of the non-rectangular display screen as shown in FIG.
  • the edge area of the display area 2 is made. It is impossible to realize full-pixel display (pixels cannot be divided at the position of the shadow area 10'), and it is easy to cause the produced liquid crystal display panel to have a zigzag pattern at the edge.
  • the technical problem to be solved by the present invention is to provide an array substrate, a manufacturing method thereof, and a display device capable of at least reducing the occurrence of a zigzag pattern at the edge of the formed non-rectangular display screen.
  • the technical solution of the present invention provides an array substrate including a display area, wherein the display area is provided with a plurality of gate lines and a plurality of data lines, and the gate lines are disposed to intersect with the data lines to thereby
  • the display area is divided into a plurality of sub-pixel units, the display
  • the display area includes a first edge and a second edge disposed adjacent to each other, a third edge opposite the first edge, and a fourth edge opposite the second edge, the gate line and the first edge, the third The edge of the data line is consistent with the second edge and the fourth edge, wherein the first edge is non-perpendicular to the second edge or at least one of the plurality of gate lines is non-linear.
  • a continuous set of gate lines starting from a gate line of the first edge is parallel to the first edge, and a continuous set of data lines from the data line closest to the second edge of the plurality of data lines and the first The two edges are parallel.
  • the gate lines other than the set of gate lines of the plurality of gate lines are parallel to the third edge.
  • the data lines other than the one of the plurality of data lines are parallel to the fourth edge.
  • the third edge is disposed parallel to the first edge, and/or the fourth edge is disposed in parallel with the second edge.
  • the set of gate lines includes all of the plurality of gate lines, and/or the set of data lines includes all of the plurality of data lines.
  • the non-linear shape is any one of the following: a curve, a polygonal line.
  • the present invention also provides a display device including the above array substrate.
  • the present invention further provides a method for fabricating an array substrate, the array substrate comprising a display area, wherein the display area is provided with a plurality of gate lines and a plurality of data lines, the gate lines intersecting the data lines Providing dividing the display area into a plurality of sub-pixel units, the display area including a first edge and a second edge disposed adjacent to each other, a third edge opposite to the first edge, and a fourth edge opposite to the second edge
  • the gate line is aligned with the first edge and the third edge.
  • the data line is aligned with the second edge and the fourth edge.
  • the first edge of the array substrate is non-perpendicular to the second edge. Or at least one of them is non-linear, and the plurality of gate lines and the plurality of data lines are set in the display area in the following manner:
  • the setting the plurality of gate lines and the plurality of data lines in the display area further includes:
  • Another set of gate lines is formed in the region of the display area adjacent to the third edge, which is parallel to the third edge.
  • the setting the plurality of gate lines and the plurality of data lines in the display area further includes:
  • Another set of data lines is formed in the area of the display area adjacent to the fourth edge, which is parallel to the second edge.
  • the third edge is disposed parallel to the first edge, and/or the fourth edge is disposed in parallel with the second edge.
  • the set of gate lines includes all of the plurality of gate lines, and/or the set of data lines includes all of the plurality of data lines
  • the non-linear shape is any one of the following: a curve, a polygonal line.
  • the array substrate provided by the embodiment of the present invention has a non-rectangular display area on the display substrate.
  • full-pixel fabrication can be realized at the edge of the display area.
  • Full pixel display can be achieved at the edges, avoiding the appearance of zigzag patterns at the edges of the formed non-rectangular display screen.
  • FIG. 1 is a schematic view of an array substrate in the prior art
  • FIG. 2 is a schematic diagram of a first array substrate provided by an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a second array substrate provided by an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a third array substrate provided by an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a fourth array substrate provided by an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of a fifth array substrate provided by an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of a sixth array substrate provided by an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of a shape of a display area of an array substrate according to an embodiment of the present invention.
  • Figure 9 is a schematic view showing the arrangement of gate lines and data lines on the display area shown in Figure 8.
  • FIG. 10 is a flow chart of fabricating an array substrate according to an embodiment of the present invention.
  • An embodiment of the present invention provides an array substrate 1 including a display area 2 on which a plurality of gate lines and a plurality of data lines are disposed, the gate lines are disposed to intersect with the data lines to divide the display area 2 a plurality of sub-pixel units, the display area 2 includes a first edge and a second edge disposed adjacent to each other, a third edge opposite to the first edge and a fourth edge opposite to the second edge, the gate line is aligned with the first edge and the third edge, and the data line is aligned with the second edge and the fourth edge, wherein the first edge and the first edge
  • the two edges are non-perpendicular or at least one of which is non-linear, and the plurality of gate lines are parallel to the first edge from a gate line closest to the gate line of the first edge, and the plurality of data lines are A continuous set of data lines starting from the data line closest to the second edge is parallel to the second edge.
  • the array substrate 1 provided by the embodiment of the present invention has a display area 2 on the display substrate 2 which is non-rectangular, and can be realized at the edge of the display area 2 by routing the gate lines and the data lines therein along the edges of the display area 2.
  • Pixel fabrication which in turn enables full-pixel display at the edges, avoids the appearance of jagged patterns at the edges of the formed non-rectangular display screen, improving the display quality of the surrounding area.
  • the display area of the array substrate is non-rectangular, and the first edge and the second edge may be linear, and the two are not perpendicularly arranged, and may be non-linear, for example, may be curved (such as an arc) ) or a broken line.
  • FIG. 2 is a schematic diagram of an array substrate according to an embodiment of the present invention.
  • the display area 2 on the array substrate 1 is non-rectangular, and includes a first edge 11 and a second edge 12 disposed adjacent to each other. a third edge 13 opposite the first edge 11 and a fourth edge 14 opposite the second edge 12, the first edge 11, the second edge 12, the third edge 13, and the fourth edge 14 are curved,
  • the display area 2 is provided with a plurality of gate lines and a plurality of data lines.
  • the gate lines of the display area 2 are divided into two groups, one of which is a plurality of mutually parallel gate lines 21 on the upper side of the dotted line 50 near the first edge 11, and the other is the lower side of the dotted line 50 on the lower side of the third edge 13
  • a plurality of mutually parallel gate lines 22 are curved and disposed in parallel with the first edge, and the gate lines 22 are curved and disposed in parallel with the third edge 13.
  • the data lines on the display area 2 are also divided into two groups, one of which is a plurality of mutually parallel data lines 31 disposed on the left side of the dotted line 40 near the second edge 12, and the other group is the right side of the dotted line 40.
  • the plurality of mutually parallel data lines 32 are disposed on the four edges 14.
  • the data lines 31 are curved and disposed in parallel with the second edge 12.
  • the data lines 32 are curved and disposed in parallel with the fourth edge 14.
  • the gate lines and the data lines of the array substrate 1 may be divided into two groups as shown in FIG. 2, but also all the gate lines on the array substrate 1 may be omitted. All are arranged in parallel with one of the edges of the display area 2, and all the data lines are arranged in parallel with the adjacent other edge. For example, for the shape of the display area 2 shown in FIG. 2, all the gate lines below the broken line 50 can be the same. The data line disposed on the right side of the dashed line 40 is also disposed in parallel with the second edge adjacent to the first edge.
  • a set of gate lines parallel to the first edge may be A plurality of gate lines on the array substrate 1 may also be all gate lines, and a group of data lines parallel to the second edge may be arrayed on a portion of the data lines on the substrate 1 or may be all data lines.
  • FIG. 3 is a second embodiment provided by the embodiment of the present invention.
  • a schematic view of the array substrate 1 , the display region 2 on the array substrate is non-rectangular, comprising a first edge 11 and a second edge 12 disposed adjacent to each other, and a third edge 13 disposed opposite to and parallel to the first edge 11
  • the fourth edge 14 opposite to the second edge 12 are all curved.
  • the display area 2 is provided with a plurality of gate lines 20 and a plurality of data lines, wherein the gate lines on the display area 2 are both disposed in parallel with the first edge 11, and the data lines on the display area 2 are divided into two groups, wherein A plurality of data lines 31 disposed on the left side of the dotted line 40 near the second edge 12 are disposed in parallel with the second edge 11 , and the other group is a plurality of data lines 32 disposed on the right side of the dotted line 40 adjacent to the fourth edge 14 . It is arranged parallel to the fourth edge 14.
  • the present embodiment can reduce the number of larger or smaller cells in the divided sub-pixel units, and further improve the display quality.
  • FIG. 4 is a schematic diagram of a third array substrate provided by an embodiment of the present invention.
  • the array substrate 1 is substantially the same as the array substrate 1 of FIG. 3, except that the first edge is oppositely and parallelly disposed. Both the 11 and the third edge 13 are linear.
  • FIG. 5 is a schematic diagram of a fourth array substrate provided by an embodiment of the present invention.
  • the display area 2 on the array substrate 1 is non-rectangular, and includes a first edge 11 and a second edge disposed adjacent to each other. 12.
  • a third edge 13 disposed opposite and parallel to the first edge 11 and a fourth edge 14 disposed opposite to and parallel to the second edge, wherein the first edge 11 and the third edge 13 are linear, and second Both the edge 12 and the fourth edge 14 are curved.
  • all the gate lines 20 may be routed according to the first edge 11, and are disposed in parallel with the first edge 11 and the third edge 13, and all the data lines 30 may follow the second edge 12 The routing is performed in parallel with both the second edge 12 and the fourth edge 14.
  • the present embodiment can divide the sub-pixel units of uniform size at each position, thereby further improving the display quality.
  • FIG. 6 is a schematic diagram of a fifth array substrate provided by an embodiment of the present invention.
  • the array substrate 1 is substantially the same as the array substrate 1 of FIG. 5, except that the first edge is oppositely and in parallel. Both the 11 and the third edge 13 are curved.
  • FIG. 7 is a schematic diagram of a sixth array substrate according to an embodiment of the present invention.
  • the display area 2 on the array substrate 1 includes adjacent and non-vertical first edges 11 and second edges 12, and first a third edge 13 opposite and parallel to the edge 11 and a fourth edge 14 disposed opposite and parallel to the second edge, wherein the first edge 11, the second edge 12, the third edge 13, and the fourth edge 14 are It is linear, thereby forming a display area 2 of a parallelogram shape.
  • all the gate lines 20 are arranged in parallel with the first edge 11 and the third edge 13, and all the data lines 30 are arranged in parallel with the second edge 12 and the fourth edge 14, that is, the gate lines
  • the data lines 30 are also arranged non-vertically, so that sub-pixel units of uniform size are divided at various positions of the display area 2.
  • a segmentation design method may be adopted, and the display area is divided into a plurality of areas with relatively regular shapes, and the gate lines and the data lines are sequentially tracked according to the edge shape of the partition, for example,
  • the shape of the display area 2 shown in Fig. 8 can be divided into three parallelogram areas along the position indicated by the broken line, and then the gate lines and the data lines are placed thereon.
  • first and second edges 11 and 12 are also substantially constituted by adjacent first and second edges 11 and 12, and a third edge 13 which is opposite and parallel to the first edge and a fourth edge 14 which is opposite and parallel to the second edge,
  • the presence of the fold lines 11 and 13 does not affect the application of the spirit of the present invention, and the arrangement of the grid lines and data lines suitable for use in Figures 5-7 is equally well applicable to the display area 2 of Figure 8 without the need for a segmentation step.
  • the gate line and the data line may be disposed in the display area 2 shown in FIG. 8 as shown in FIG. 9 .
  • the gate lines of the array substrate 1 are routed according to the first edge 11 and the third edge 13 .
  • the first edge 11 and the second edge 13 are both in a line shape, and the first edge 11 includes three straight portions, which are a straight portion 111, a straight portion 112, and a straight portion 113, and a third
  • the edge 13 also includes three corresponding straight portions, which are a straight portion 131 parallel to the straight portion 111, a straight portion 132 parallel to the straight portion 112, and a straight portion 133 parallel to the straight portion 113, and the gate line 20 is formed in the same manner.
  • the data lines of the array substrate 1 are routed in a second edge 12 and a fourth edge 14 which are parallel to each other and are linear, to form corresponding data lines 30.
  • the array substrate provided by the invention ensures that the formed pixel structure is matched to the corresponding display screen structure to the greatest extent by routing the gate lines and the data lines in accordance with the edges of the display area, thereby ensuring the display quality of the peripheral area.
  • Embodiments of the present invention also provide a display device including the above array substrate.
  • the display device provided by the embodiment of the present invention may be any product or component having a display function, such as a notebook computer display screen, a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone, a tablet computer, and the like.
  • the display device can also be a wearable display device.
  • FIG. 10 illustrates a method of fabricating an array substrate according to an embodiment of the present invention.
  • the array substrate 1 includes a display area 2 on which a plurality of gate lines and a plurality of data lines are disposed.
  • the data line cross setting divides the display area 2 into a plurality of sub-pixel units, the display area 2 including first and second edges disposed adjacent to each other, a third edge opposite to the first edge, and the second a fourth edge opposite to the edge, the gate line is aligned with the first edge and the third edge, and the data line is aligned with the second edge and the fourth edge, wherein the first edge of the array substrate 1 Non-perpendicular to the second edge or at least one of which is non-linear, the plurality of gate lines and the plurality of data lines are disposed in the display area 2 in the following manner:
  • step 902 Forming a region adjacent to the first edge in the display region 2 to form a set of gate lines parallel to the first edge, and forming a group parallel to the second edge in the region of the display region 2 adjacent to the second edge Data line (step 902).
  • the setting the plurality of gate lines and the plurality of data lines in the display area 2 further includes:
  • Another set of gate lines is formed in the region of the display region 2 adjacent to the third edge, which is parallel to the third edge (step 904).
  • the setting the plurality of gate lines and the plurality of data lines in the display area 2 further includes:
  • the third edge is arranged parallel to the first edge, and/or the fourth edge is arranged parallel to the second edge.
  • the set of gate lines includes all of the plurality of gate lines, and/or the set of data lines includes all of the plurality of data lines.
  • the non-linear shape is any one of the following: a curve, a fold line.

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Abstract

一种阵列基板及其制作方法、显示装置，该阵列基板（1）包括显示区域（2），该显示区域（2）上设置有多条栅线（21、22）和多条数据线（31、32），该栅线（21、22）与该数据线（31、32）交叉设置将该显示区域（2）划分为多个子像素单元，该显示区域（2）包括呈相邻设置的第一边缘（11）和第二边缘（12），与该第一边缘（11）相对的第三边缘（13）和与该第二边缘（12）相对的第四边缘（14），该栅线（21、22）与该第一边缘（11）、该第三边缘（13）走向一致，该数据线（31、32）与该第二边缘（12）、该第四边缘（14）走向一致，该第一边缘（11）与该第二边缘（12）非垂直或者其中至少一者为非直线状，该多条栅线（21、22）中靠近该第一边缘（11）设置的一组栅线（21）与该第一边缘（11）平行，该多条数据线（31、32）中靠近该第二边缘（12）设置的一组数据线（31）与该第二边缘（12）平行。该阵列基板（1）能够避免在所形成的非矩形显示屏幕的边缘处出现锯齿状图案。

Description

阵列基板及其制作方法、显示装置 技术领域
本发明涉及显示领域，尤其涉及一种阵列基板及其制作方法、显示装置。
背景技术
液晶显示面板(例如薄膜场效应晶体管液晶显示器TFT(Thin Film Transistor)-LCD)具有体积小、功耗低、无辐射、制造成本低等优点，随着科技的发展和人们生活水平的提高，人们不再局限于仅关注液晶显示面板的显示性能，还对液晶显示面板的其它方面提出了诸多的需求，例如，传统的液晶显示面板的显示屏幕形状通常为矩形状，为应用在穿戴显示设备上并满足用户的个性化需求，目前出现了其他显示屏幕形状的液晶显示面板。
液晶显示面板的显示屏幕形状通常由其阵列基板的显示区域(A/A区)决定，其中，阵列基板的显示区域上设置有多条相互交叉的栅线和数据线，通过栅线和数据线划分出多个子像素单元从而能够实现整个液晶显示面板的显示功能，目前，不管是矩形显示屏幕的液晶显示面板，还是非矩形显示屏幕的液晶显示面板，其阵列基板上的栅线和数据线均采用垂直交叉的设置方式，然而，对于非矩形显示屏幕的液晶显示面板，如图1所示，由于栅线20’和数据线30’采用相互垂直的设置方法，使得在显示区域2的边缘区域处不能实现全像素显示(在阴影区10’的位置上不能划分出像素)，容易造成所制作的液晶显示面板在边缘处出现锯齿状图案。
发明内容
本发明要解决的技术问题是：提供一种阵列基板及其制作方法、显示装置，能够至少减少在所形成的非矩形显示屏幕的边缘处出现锯齿状图案。
为解决上述技术问题，本发明的技术方案提供了一种阵列基板，包括显示区域，该显示区域上设置有多条栅线和多条数据线，该栅线与该数据线交叉设置从而将该显示区域划分为多个子像素单元，该显 示区域包括呈相邻设置的第一边缘和第二边缘，与该第一边缘相对的第三边缘和与该第二边缘相对的第四边缘，该栅线与该第一边缘、该第三边缘走向一致，该数据线与该第二边缘、该第四边缘走向一致，其中，该第一边缘与该第二边缘非垂直或者其中至少一者为非直线状，该多条栅线从最靠近该第一边缘的栅线开始的连续的一组栅线与该第一边缘平行，该多条数据线中从最靠近该第二边缘的数据线开始的连续的一组数据线与该第二边缘平行。
优选地，该多条栅线中该一组栅线以外的栅线与该第三边缘平行。
优选地，该多条数据线中该一组数据线以外的数据线与该第四边缘平行。
优选地，该第三边缘与该第一边缘平行设置，和/或该第四边缘与该第二边缘平行设置。
优选地，该一组栅线包括所有的该多条栅线，和/或该一组数据线包括所有的该多条数据线。
优选地，该非直线状为以下的任意一种：曲线、折线。
为解决上述技术问题，本发明还提供了一种显示装置，包括上述的阵列基板。
为解决上述技术问题，本发明还提供了一种阵列基板的制作方法，该阵列基板包括显示区域，该显示区域上设置有多条栅线和多条数据线，该栅线与该数据线交叉设置将该显示区域划分为多个子像素单元，该显示区域包括呈相邻设置的第一边缘和第二边缘，与该第一边缘相对的第三边缘和与该第二边缘相对的第四边缘，该栅线与该第一边缘、该第三边缘走向一致，该数据线与该第二边缘、该第四边缘走向一致，其中，该阵列基板的该第一边缘与该第二边缘非垂直或者其中至少一者为非直线状，在该显示区域以以下方式设置该多条栅线和该多条数据线：
在该显示区域中靠近该第一边缘的区域形成与该第一边缘平行的一组栅线，在该显示区域中靠近该第二边缘的区域中形成与该第二边缘平行的一组数据线，其中。
优选地，在该显示区域设置该多条栅线和该多条数据线还包括：
在该显示区域靠近该第三边缘的区域中形成另一组栅线，其与该第三边缘平行。
优选地，在该显示区域设置该多条栅线和该多条数据线还包括：
在该显示区域靠近该第四边缘的区域中形成另一组数据线，其与该第二边缘平行。
优选地，该第三边缘与该第一边缘平行设置，和/或该第四边缘与该第二边缘平行设置。
优选地，该一组栅线包括所有的该多条栅线，和/或该一组数据线包括所有的该多条数据线
优选地，该非直线状为以下的任意一种：曲线、折线。
本发明实施方式提供的阵列基板，其上的显示区域为非矩形状，通过将其中的栅线和数据线按照显示区域的边缘走线，从而能够在显示区域的边缘处实现全像素制作，进而可以在边缘处实现全像素显示，能够避免在所形成的非矩形显示屏幕的边缘处出现锯齿状图案。
附图说明
图1是现有技术中的阵列基板的示意图；
图2是本发明实施方式提供的第一种阵列基板的示意图；
图3是本发明实施方式提供的第二种阵列基板的示意图；
图4是本发明实施方式提供的第三种阵列基板的示意图；
图5是本发明实施方式提供的第四种阵列基板的示意图；
图6是本发明实施方式提供的第五种阵列基板的示意图；
图7是本发明实施方式提供的第六种阵列基板的示意图；
图8是本发明实施方式提供的阵列基板显示区域形状的示意图；
图9是在图8所示的显示区域上设置栅线和数据线的示意图；
图10是本发明实施方式提供的阵列基板的制作流程图。
具体实施方式
下面结合附图和实施例，对本发明的具体实施方式作进一步详细描述。以下实施例用于说明本发明，但不用来限制本发明的范围。
本发明实施方式提供了一种阵列基板1，包括显示区域2，该显示区域2上设置有多条栅线和多条数据线，该栅线与该数据线交叉设置从而将该显示区域2划分为多个子像素单元，该显示区域2包括呈相邻设置的第一边缘和第二边缘，与该第一边缘相对的第三边缘和与该 第二边缘相对的第四边缘，该栅线与该第一边缘、该第三边缘走向一致，该数据线与该第二边缘、该第四边缘走向一致，其中，该第一边缘与该第二边缘非垂直或者其中至少一者为非直线状，该多条栅线从最靠近该第一边缘的栅线开始的连续的一组栅线与该第一边缘平行，该多条数据线中从最靠近该第二边缘的数据线开始的连续的一组数据线与该第二边缘平行。
本发明实施方式提供的阵列基板1，其上的显示区域2为非矩形状，通过将其中的栅线和数据线按照显示区域2的边缘走线，从而能够在显示区域2的边缘处实现全像素制作，进而可以在边缘处实现全像素显示，能够避免在所形成的非矩形显示屏幕的边缘处出现锯齿状图案，提高周边区域的显示质量。
本发明中，阵列基板的显示区域为非矩形状，其第一边缘、第二边缘可以为直线状，且两者非垂直设置，也可以为非直线状，例如，可以为曲线(如弧线)或者折线。
参见图2，图2是本发明实施方式提供的一种阵列基板的示意图，该阵列基板1上的显示区域2为非矩形状，其包括呈相邻设置的第一边缘11和第二边缘12、与第一边缘11相对的第三边缘13、以及与第二边缘12相对的第四边缘14，第一边缘11、第二边缘12、第三边缘13以及第四边缘14均为曲线状，该显示区域2上设置有多条栅线和多条数据线。
其中，显示区域2的栅线被分为两组，其中一组为虚线50上侧靠近第一边缘11的多条相互平行的栅线21，另一组为虚线50下侧靠近第三边缘13的多条相互平行的栅线22，栅线21为曲线状并与第一边缘平行设置，栅线22为曲线状并与第三边缘13平行设置。
其中，显示区域2上的数据线也被分为两组，其中一组为虚线40左侧靠近第二边缘12设置的多条相互平行的数据线31，另一组为虚线40右侧靠近第四边缘14设置的多条相互平行的数据线32，数据线31为曲线状并与第二边缘12平行设置，数据线32为曲线状并与第四边缘14平行设置。
如图2所示，通过将栅线和数据线按照显示区域2的边缘设置，从而能够在显示区域2的边缘处实现全像素制作，进而能够避免所制作的液晶显示面板在边缘处出现锯齿状图案。
其中，对于本发明实施方式提供的阵列基板，不仅可以如图2所示将阵列基板1的栅线和数据线分别划分为两组，也可以不进行分组，将阵列基板1上的所有栅线均与显示区域2的其中一个边缘平行设置，将所有的数据线与相邻的另一边缘平行设置，例如，对于图2所示的显示区域2形状，可以将虚线50下方的所有栅线同样设置为与第一边缘11平行，将虚线40右侧的所有数据线同样设置为与第一边缘相邻的第二边缘平行，即本发明中，与第一边缘平行的一组栅线可以为阵列基板1上部分数量的栅线，也可以为全部栅线，与第二边缘平行的一组数据线可以阵列基板1上部分数量的数据线，也可以为全部数据线。
优选地，为了减少栅线和数据线所划分出的子像素单元之间的大小差异，显示区域2相对的两边缘可以平行设置，参见图3，图3是本发明实施方式提供的第二种阵列基板1的示意图，该阵列基板上的显示区域2为非矩形状，其包括呈相邻设置的第一边缘11和第二边缘12、与第一边缘11相对且平行设置的第三边缘13、以及与第二边缘12相对的第四边缘14，第一边缘11、第二边缘12、第三边缘13以及第四边缘14均为曲线状。
该显示区域2上设置有多条栅线20和多条数据线，其中，显示区域2上的栅线均与第一边缘11平行设置，显示区域2上的数据线被分为两组，其中一组为虚线40左侧靠近第二边缘12设置的多条数据线31，其与第二边缘11平行设置，另一组为虚线40右侧靠近第四边缘14设置的多条数据线32，其与第四边缘14平行设置。
相比图2中的结构，本实施方式可以减少所划分出的子像素单元中较大或者较小单元的数量，进一步地提高显示质量。
参见图4，图4是本发明实施方式提供的第三种阵列基板的示意图，该阵列基板1与图3中的阵列基板1基本相同，其不同之处在于，相对且平行设置的第一边缘11和第三边缘13均为直线状。
参见图5，图5是本发明实施方式提供的第四种阵列基板的示意图，该阵列基板1上的显示区域2为非矩形状，其包括呈相邻设置的第一边缘11和第二边缘12、与第一边缘11相对且平行设置的第三边缘13、以及与第二边缘相对且平行设置的第四边缘14，其中，第一边缘11以及第三边缘13均为直线状，第二边缘12以及第四边缘14均为曲线状。
在阵列基板1的显示区域2中，所有的栅线20可以按照第一边缘11进行走线，与第一边缘11和第三边缘13均平行设置，所有的数据线30可以按照第二边缘12进行走线，与第二边缘12和第四边缘14均平行设置。
如图5所示，相比图4中的结构，本实施方式在各个位置上均能够划分出大小均匀的子像素单元，从而能够进一步地提高显示质量。
参见图6，图6是本发明实施方式提供的第五种阵列基板的示意图，该阵列基板1与图5中的阵列基板1基本相同，其不同之处在于，相对且平行设置的第一边缘11和第三边缘13均为曲线状。
参见图7，图7是本发明实施方式提供的第六种阵列基板的示意图，该阵列基板1上的显示区域2包括相邻且非垂直的第一边缘11和第二边缘12、与第一边缘11相对且平行设置的第三边缘13、以及与第二边缘相对且平行设置的第四边缘14，其中，第一边缘11、第二边缘12、第三边缘13以及第四边缘14均为直线状，从而形成平行四边形状的显示区域2。
在所形成的显示区域2中，所有的栅线20同第一边缘11和第三边缘13均平行设置，所有的数据线30同第二边缘12和第四边缘14均平行设置，即栅线20和数据线30同样非垂直设置，从而在显示区域2的各个位置上划分出了大小一致的子像素单元。
此外，对于其他不规则形状的显示区域，可以采用分割设计方式，将显示区域划分为形状较为规则的多个区域，再将栅线、数据线按照分区的边缘形状进行实时走线，例如对于图8所示的显示区域2形状，可以沿虚线所示的位置将其分割为三个平行四边形区域，而后再在其上设置栅线和数据线。当然，由于图8实质上也是由相邻的第一边缘11和第二边缘12，以及与第一边缘相对且平行的第三边缘13和与第二边缘相对且平行的第四边缘14构成，折线11和13的存在并不影响对本发明精神的应用，适用于图5-7的栅线和数据线的设置方式同样很好地适用于图8的显示区域2而无需分割步骤。
例如，可以如图9所述在图8所示的显示区域2设置栅线和数据线，具体地，使阵列基板1的栅线按照第一边缘11、第三边缘13进行走线，其中，第一边缘11和第二边缘13均为折线状，第一边缘11包括三个直线部，分别为直线部111、直线部112以及直线部113，第三 边缘13同样包括对应的三个直线部，分别为与直线部111平行的直线部131、与直线部112平行的直线部132以及与直线部113平行的直线部133，所形成的栅线20同样为与第一边缘11、第二边缘13一致的折线状；
使阵列基板1的数据线按照相互平行且均为直线状的第二边缘12和第四边缘14进行走线，形成相应的数据线30。
本发明提供的阵列基板，通过将其中的栅线和数据线按照显示区域的边缘走线，使形成的像素结构最大程度匹配对应的显示屏结构，从而保证周边区域的显示质量。
本发明实施方式还提供了一种显示装置，包括上述的阵列基板。其中，本发明实施方式提供的显示装置可以是笔记本电脑显示屏、液晶显示器、液晶电视、数码相框、手机、平板电脑等任何具有显示功能的产品或部件。例如，该显示装置还可以为穿戴显示设备。
图10示出了根据本发明实施方式提供的一种阵列基板的制作方法，该阵列基板1包括显示区域2，该显示区域2上设置有多条栅线和多条数据线，该栅线与该数据线交叉设置将该显示区域2划分为多个子像素单元，该显示区域2包括呈相邻设置的第一边缘和第二边缘，与该第一边缘相对的第三边缘和与该第二边缘相对的第四边缘，该栅线与该第一边缘、该第三边缘走向一致，该数据线与该第二边缘、该第四边缘走向一致，其中，该阵列基板1的该第一边缘与该第二边缘非垂直或者其中至少一者为非直线状，在该显示区域2以以下方式设置该多条栅线和该多条数据线：
在该显示区域2中靠近该第一边缘的区域形成与该第一边缘平行的一组栅线，在该显示区域2中靠近该第二边缘的区域中形成与该第二边缘平行的一组数据线(步骤902)。
根据一个实施例，在该显示区域2设置该多条栅线和该多条数据线还包括：
在该显示区域2靠近该第三边缘的区域中形成另一组栅线，其与该第三边缘平行(步骤904)。
根据一个实施例，在该显示区域2设置该多条栅线和该多条数据线还包括：
在该显示区域2靠近该第四边缘的区域中形成另一组数据线，其 与该第二边缘平行(步骤906)。
根据一个实施例，该第三边缘与该第一边缘平行设置，和/或该第四边缘与该第二边缘平行设置。
根据一个实施例，该一组栅线包括所有的该多条栅线，和/或该一组数据线包括所有的该多条数据线。
根据一个实施例，该非直线状为以下的任意一种：曲线、折线。
以上实施方式仅用于说明本发明，而并非对本发明的限制，有关技术领域的普通技术人员，在不脱离本发明的精神和范围的情况下，还可以做出各种变化和变型，因此所有等同的技术方案也属于本发明的范畴，本发明的专利保护范围应由权利要求限定。

Claims (13)

  1. 一种阵列基板，包括显示区域，所述显示区域上设置有多条栅线和多条数据线，所述栅线与所述数据线交叉设置从而将所述显示区域划分为多个子像素单元，所述显示区域包括呈相邻设置的第一边缘和第二边缘，与所述第一边缘相对的第三边缘和与所述第二边缘相对的第四边缘，所述栅线与所述第一边缘、所述第三边缘走向一致，所述数据线与所述第二边缘、所述第四边缘走向一致，其特征在于，所述第一边缘与所述第二边缘非垂直或者其中至少一者为非直线状，所述多条栅线中从最靠近所述第一边缘的栅线开始的连续的一组栅线与所述第一边缘平行，所述多条数据线中从最靠近所述第二边缘的数据线开始的连续的一组数据线与所述第二边缘平行。
  2. 根据权利要求1所述的阵列基板，其特征在于，所述多条栅线中所述一组栅线以外的栅线与所述第三边缘平行。
  3. 根据权利要求1所述的阵列基板，其特征在于，所述多条数据线中所述一组数据线以外的数据线与所述第四边缘平行。
  4. 根据权利要求1所述的阵列基板，其特征在于，所述第三边缘与所述第一边缘平行设置，和/或所述第四边缘与所述第二边缘平行设置。
  5. 根据权利要求1所述的阵列基板，其特征在于，所述一组栅线包括所有的所述多条栅线，和/或所述一组数据线包括所有的所述多条数据线。
  6. 根据权利要求1-5任一所述的阵列基板，其特征在于，所述非直线状为以下的任意一种：曲线、折线。
  7. 一种显示装置，其特征在于，包括如权利要求1-6任一所述的阵列基板。
  8. 一种阵列基板的制作方法，所述阵列基板包括显示区域，所述显示区域上设置有多条栅线和多条数据线，所述栅线与所述数据线交叉设置将所述显示区域划分为多个子像素单元，所述显示区域包括呈相邻设置的第一边缘和第二边缘，与所述第一边缘相对的第三边缘和与所述第二边缘相对的第四边缘，所述栅线与所述第一边缘、所述第三边缘走向一致，所述数据线与所述第二边缘、所述第四边缘走向一 致，其特征在于，所述阵列基板的所述第一边缘与所述第二边缘非垂直或者其中至少一者为非直线状，在所述显示区域以以下方式设置所述多条栅线和所述多条数据线：
    在所述显示区域中靠近所述第一边缘的区域形成与所述第一边缘平行的一组栅线，在所述显示区域中靠近所述第二边缘的区域中形成与所述第二边缘平行的一组数据线。
  9. 根据权利要求8所述的阵列基板的制作方法，其特征在于，在所述显示区域设置所述多条栅线和所述多条数据线还包括：
    在所述显示区域靠近所述第三边缘的区域中形成另一组栅线，其与所述第三边缘平行。
  10. 根据权利要求8所述的阵列基板的制作方法，其特征在于，在所述显示区域设置所述多条栅线和所述多条数据线还包括：
    在所述显示区域靠近所述第四边缘的区域中形成另一组数据线，其与所述第二边缘平行。
  11. 根据权利要求8所述的阵列基板的制作方法，其特征在于，所述第三边缘与所述第一边缘平行设置，和/或所述第四边缘与所述第二边缘平行设置。
  12. 根据权利要求8所述的阵列基板的制作方法，其特征在于，所述一组栅线包括所有的所述多条栅线，和/或所述一组数据线包括所有的所述多条数据线。
  13. 根据权利要求8-12任一所述的阵列基板的制作方法，其特征在于，所述非直线状为以下的任意一种：曲线、折线。
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