WO2017044124A1 - Procédé de commutation d'espaces d'adresses virtuels - Google Patents

Procédé de commutation d'espaces d'adresses virtuels Download PDF

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Publication number
WO2017044124A1
WO2017044124A1 PCT/US2015/049726 US2015049726W WO2017044124A1 WO 2017044124 A1 WO2017044124 A1 WO 2017044124A1 US 2015049726 W US2015049726 W US 2015049726W WO 2017044124 A1 WO2017044124 A1 WO 2017044124A1
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WO
WIPO (PCT)
Prior art keywords
virtual address
address space
vas
processor
instructions
Prior art date
Application number
PCT/US2015/049726
Other languages
English (en)
Inventor
Izzat EL HAJJ
Alexander M. MERRITT
Gerd ZELLWEGER
Dejan S. Milojicic
Original Assignee
Hewlett Packard Enterprise Development Lp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Enterprise Development Lp filed Critical Hewlett Packard Enterprise Development Lp
Priority to PCT/US2015/049726 priority Critical patent/WO2017044124A1/fr
Publication of WO2017044124A1 publication Critical patent/WO2017044124A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory

Definitions

  • VAS virtual address space
  • each process is provided a virtual address space (VAS) that spans the entire address space addressable by the architecture of the processor (e.g. a 32 bit processor has a 4 Gigabyte address space), although not all of that address space may be directly accessible by the process due to other constraints.
  • VAS virtual address space
  • certain address ranges within the VAS may be reserved for system functions (e.g. kernel space).
  • the virtual memory system may not implement the maximum address space supported by the processor (e.g. the virtual memory system may only support 30 address bits, limiting the VAS to 1 Gigabyte).
  • the address space for each process is virtual because the computing system may not actually include enough physical memory for every processes' address space to be loaded into physical memory at the same time.
  • the virtual memory system hides the fact that each processes' address space may not actually be loaded into the physical memory of the computing system by transparently swapping pages of each processes' address space between physical memory and some other storage (e.g. a swap file on disk).
  • FIG. 1 is an example of a device that may utilize the process virtual address space switch techniques described herein.
  • FIG. 2 depicts an example of switching a virtual address space according to the techniques described herein.
  • FIG. 3 is an example of a high level flow diagram for switching virtual address spaces, according to techniques described herein.
  • FIG. 4 is another example of a high level flow diagram for switching virtual address spaces, according to techniques described herein.
  • FIG. 5 is an example of a high level flow diagram of a process switching virtual address spaces according to techniques described herein.
  • FIG. 6 is another example of a high level flow diagram of a process switching virtual address spaces according to techniques described herein.
  • computing devices employing a virtual memory system may allow a process to include a VAS that exceeds the amount of physical memory in the device.
  • VAS virtual memory
  • systems are currently being developed with large amounts of physical memory, in some case, the amount of physical memory may exceed that which is available in the VAS.
  • a system supporting a 32 bit VAS defines the maximum address range as 4 Gigabytes. Physical memory exceeding 4 Gigabytes would not be addressable at any given moment in time by a process running on a computing device with such a VAS, regardless of how much physical memory was actually installed in the device.
  • a VAS may be created, stored, and deleted in the same way as any other first class entity, such as a file.
  • a process may include data (e.g. a pointer) indicating the process's current VAS. The data may then be changed to indicate a different VAS. Because the process is now associated with a different VAS, the effective address space has doubled. If additional address space is needed, additional virtual address spaces may be created.
  • a first and second process may each have a VAS.
  • the first process ma switch to the second process's VAS (or at ieast portions of the VAS) and thus will have access to the second processes VAS without requiring the complexity that accompanies memory segments shared between processes.
  • one process could simply switch to the other process's VAS, thus eliminating conflicts that may arise when mapping physical memory into two separate virtual address spaces.
  • VAS may also exist that is not currently associated with any process.
  • each VAS is a first class entity that may exist independently of a process
  • new mechanisms for accessing data resident in system memory may become available.
  • a VAS may be created to contain a dataset that is not associated with any process. When a process needs access to that dataset, the process may switch to the VAS associated with the dataset. Once the process no longer needs to access the data set, it may switch back to its original VAS.
  • FIG. 1 is an example of a device that may utilize the process virtual address space switch techniques described herein.
  • System 100 may include a device 1 10.
  • the device 1 10 may include a processor 120, a physical memory 130, and a non-transitory processor readable medium 140.
  • the device 1 10 may be a computing device, such as a server computer, a desktop computer, a laptop, a tablet, a smartphone. or any other suitable device.
  • the techniques described herein are not limited to any particular device and are usable in any device that includes a virtual memory system.
  • the device 1 10 may include a processor 120.
  • the processor may be of any type, such as a central processing unit (CPU), graphics processing unit (GPU), and application specific integrated circuit (ASIC), or any other suitable type of circuitry or device.
  • CPU central processing unit
  • GPU graphics processing unit
  • ASIC application specific integrated circuit
  • the techniques described herein are not limited to any particular type of processor, but rather are applicable to any processor thai may be utilized in a device that implements a virtual memory system,
  • the device 1 10 may also include a physical memory 130.
  • the physical memory may include dynamic random access memory (DRAM), static random access memory (SRAM), non-volatile random access memory
  • NVRAM such as rnemristor or phase change memory
  • the memory may be used to store processor executable instructions and data.
  • the techniques described herein are suitable for use with any type of memory that may be utilized by the processor 120.
  • the device 1 10 may also include a non-transitory processor readable medium 140.
  • the medium may contain thereon a set of instructions, which when executed by the processor 120, may cause the processor to implement the techniques described herein.
  • the medium may include virtual memory system instructions 142.
  • a virtual memory system may be used to abstract the physical memory of a device 1 10 from processes running on that device. Each process is provided an address space sized according to the constraints of the virtual memory system. Each process utilizes this address space and need not be aware of the actual physical memory 130 that is included in the device.
  • the medium 140 may also include virtual address space switch instructions 144.
  • the virtual address space switch instructions may allow the processor to switch a process's VAS from a first VAS to a second VAS, thus effectively increasing the amount of memory the process may access beyond the range defined by a single VAS.
  • the virtual address space switch instructions are described in more detail below and in conjunction with FIGS. 3 and 4.
  • a process 150 may be executing on device 1 10.
  • a process may be instructions and data that are executable b a processor to complete a task.
  • a database program running on the device 1 10 may be comprised of one or more processes.
  • a process runs under the control of an operating system and may have process state information. Included amongst the process state information may be data that defines the VAS of the process.
  • an operating system is any control software, including hypervisors and other supervisory software.
  • a process refers to anything that exists within a virtual address space, including virtual machines.
  • a process 150 may initially be associated with a first VAS 180-1 .
  • a VAS is used by the virtual memory system to make it appear to the process that the full address space of the device 1 10 is available to the process, even though the device may not be equipped with enough physical memory for the process's entire VAS to be loaded into physical memory.
  • a process may desire to access a different VAS.
  • the process may need more memory than is available in the VAS. in other cases, the process may wish to access data that is contained in the VAS of a different process. Regardless of the reason, the process may wish to switch from the first VAS 160-1 to a second VAS 180-2.
  • the techniques provided herein provide instructions executable by the processor to cause a process to switch from a first VAS 160-1 to a second VAS 160-2.
  • each process running on device 1 10 may include process state information 210.
  • the process state information may include the contents of registers contained within the processor, in a multiprocessing system, multiple processes may run on the same processor. When a particular process is not actively running, processor state information, such as the processor register contents may be saved.
  • the process state information may include a program counter (PC) which may indicate the current instruction being executed within the process.
  • PC program counter
  • Another piece of process state may include a pointer to the page table root for the process (PT ROOT PTR).
  • PT ROOT PTR pointer to the page table root for the process
  • a system including a virtual memory system may include a VAS with a defined range. As mentioned above, the range may be from 0 to the maximum supported by the virtual memory system. As shown in FIG. 2, VAS 220 has an address range from 0- AX. It should be understood that the particular value of MAX is unimportant. The VAS may be broken down into smaller units called pages. For example, one common page size is 4 Kilobytes. Thus, a 4 Gigabyte VAS address space may be divided into slightly more than 1 million pages.
  • Each page of the VAS may be represented by a page table entry, and those combinations of the page table entries for the entire VAS may be referred to as a page table structure.
  • FIG. 2 depicts a high level view of a page table structure 222-1 .
  • the page table structure is depicted as containing a root node 223-1 , intermediate nodes 224-1 , and leaf nodes 225-1 .
  • the leaf nodes may include the actual page table entries. It should be understood that the particular format of the page table structure is unimportant, but rather that the page table structure may have a root node from which all page table entries descend.
  • Each page table entry may include at least two pieces of information.
  • the first piece of information may be if the page is currently mapped to physical memory.
  • a virtual memory system hides the fact that all of a process's VAS may not be contained in physical memory from the process. If the page is not in physical memory, the page may be stored in some other storage area (e.g. disk).
  • the second piece of information may be the address in physical memory storing the page (assuming the first piece of information indicates the page is stored in physical memory), it should be understood that because the physical memory may not necessarily be as large as the VAS, the virtual ⁇
  • a process may wish to execute instructions or access data located at a specific virtual address.
  • the virtual memory system may receive the virtual address and access the page table structure pointed to by the process state information (e.g. the PT ROOT PTR).
  • the virtual memory system may traverse the structure to find the page table entry associated with the memory page containing the virtual address of interest. If the page is currently loaded into physical memory, the virtual memory system may return the address within the physical memory where the page is stored and the process may access the page in the physical memory. If the page is not currently in physical memory, a page fault occurs and control may be handed to the operating system.
  • the operating system may then load the page from storage (e.g. disk) into the physical memory (this process may involve clearing space for the page in the physical memory be selecting a page to evict from physical memory and store to disk). Once the page has been loaded into physical memory, the process can access the address.
  • the VAS may be defined by the page fable structure.
  • the page table structure was strictly associated with a process.
  • the structure is no longer tied to a given process, and the corollary is true as well; the process is no longer tied to a given page table structure.
  • the pointer to the page table root structure in the process state information 210 may be switched from the initial VAS to the new VAS.
  • the processor may include data associated with the first VAS in registers or in various levels of on processor caches. This data may need to be flushed to memory before switching from one VAS to another.
  • a process may wish to switch from a first VAS 220-1 to a second VAS 220-2.
  • the process may first prepare for the switch by flushing processor registers and caches to the memory, as needed, to ensure that data associated with the first VAS is not inadvertently stored in the second VAS should a flush occur after the switch of the VAS.
  • the processor may then update the page table root pointer of the process state information to point from the page table root 223-1 to page table root 223-2.
  • the VAS of the process then switches from VAS 220-1 to VAS 220-2. Because the each VAS is independent, the process has effectively increased the total size of its virtual address space. Furthermore, because the VAS spaces can exist independent of a process, the process gains access to the data stored in the VAS prior to the process switching to that VAS.
  • the previous example has been described in terms of switching the page table root pointer, it should be understood that this is not the only possible implementation.
  • the contents of the page table structure e.g. 222-1
  • the contents of the page table structure 222-1 may first be stored elsewhere (e.g. to disk, or in the address space of a different process, such as the operating system kernel).
  • the contents of the page table structure 222-1 may then be overwritten with the contents of a different page table structure, thus effectively changing the page table structure 222-1 without changing the page table root pointer.
  • page fables may not be used at ail.
  • Such systems may use segment registers and offset computations to define virtual address spaces.
  • the techniques for switching virtual address spaces are suitable for use regardless of the type of virtual memory system.
  • a VAS is treated as a first class entity and can be associated and / or disassociated with a process.
  • virtual address spaces are independent entities, this does not mean that portions of the VAS cannot be shared or duplicated between virtual address spaces.
  • a VAS may contain several portions that are effectively defined by the process.
  • the BSS, data, and text portions of a process generally define the instructions and variables that are executed by the processor and are the functional code portions of the process
  • a portion of the VAS may be set aside for the kernel portion of the operating system (e.g. allowing the process to make system calls).
  • additional portion of the VAS may be set aside for the stack.
  • the stack is a data structure used by the process to store temporary variables and return pointers, among other data.
  • the VAS may also include portions such as the heap, from which the process may allocate new memory within the virtual address space.
  • the VAS may also include memory mapped portions.
  • the portions of the VAS that are to be shared may simply be copied, in their entirety, from one VAS to the other.
  • the references to the portions may be duplicated.
  • the page table entries denoted by the reference characters A, B, and C represent the kernel, stack, and BSS, data, and text page table entries.
  • page table structure 222-1 , 222-2 those page table entries (A,B and C) can simply be duplicated in each page. Because the page table entries are associated with memory (either in physical memory or in storage), the second VAS 220-2 contains the same kernel, stack, and BSS, data, and text portions, without having to actually copy those portions.
  • the operating system or processor may provide an API or a new processor instruction to ensure the switch from the first VAS to the second VAS is safe.
  • the process may invoke a system call to inform the operating system to inform the operating system of the switch in VAS.
  • the operating system may then alter process state information in order to accurately track the VAS that is currently active for the process, in another example implementation, the processor may provide a special instruction to execute the switch.
  • the processor may be provided an identifier associated with the second VAS, and the processor would perform the switch in the page table roof pointer automatically, after state information is provided by the operating system.
  • FIG. 3 is an example of a high level flow diagram for switching virtual address spaces, according to techniques described herein.
  • the example flow diagram of FIG. 3 may be implemented as instructions contained on a non- transitory medium, such as instructions 144.
  • a request may be received from a process to switch from a first virtual address space to a second virtual address space.
  • the switch may be requested because the process needs access to more memory than can be addressed in a single VAS, or it may be for other reasons, such as a desire to access data contained in a VAS that is different than the one currently associated with the process.
  • the process state information may be modified to reflect the change from the first virtual address space to the second virtual address space.
  • the switch may be implemented by changing the page table root pointer for the process from a page table associated with the first virtual address space to a page table associated with the second virtual address space. Other implementations are described in further detail below, with respect to FIG. 4.
  • FIG. 4 is another example of a high level flow diagram for switching virtual address spaces, according to techniques described herein.
  • the example flow diagram of FIG. 4 may be implemented as instructions contained on a non-transitory medium, such as instructions 144.
  • a request to create the second virtual address space may be received.
  • a VAS is now a first class entity and may be created independently of a process.
  • the second virtual address space may be created.
  • creating a VAS may include creating a new page table structure to associate with the new VAS.
  • creation of a new VAS may include creating the contents of a page table structure.
  • access permissions for the first and second virtual address spaces may be defined.
  • read and write permissions for a virtual address may be defined and a given process's ability to access the VAS may depend on those permissions.
  • a given process's ability to access the VAS may depend on those permissions.
  • a VAS may be desired that a VAS is only writeabie by one process at a time.
  • a VAS may only be able to be deleted when no other process is using the VAS.
  • a request may be received from a process to switch from a first virtual address space to a second virtual address space, in block 425, the defined access permissions for the first and second virtual address space may be enforced. For example, if a given VAS should not be accessed by a given process based on the permission defined in block 415, the request to switch the process into the prohibited VAS may be denied in order to enforce the permissions.
  • the duplication may be an actual copy of the address spaces from one space to another or it may be a copy of the page table entries associated with that portion of the address space. Regardless of implementation, the duplication of the address space may allow the process to continue executing without interruption.
  • Blocks 435-460 represent possible actions performed when switching from one virtual address space to another. Not all blocks need be executed by ail implementations and the depiction is intended to be an example. Other possible implementations may execute different blocks. What should be understood is that the process switches from a first VAS to a second VAS.
  • the process state information may be modified to reflect the change from the first virtual address space to the second virtual address space.
  • the process moves to block 440.
  • the contents of a page table Instance associated with the process may be stored to a data store.
  • the contents may be associated with the first virtual address space
  • the contents of the page table instance may be replaced with contents associated with the second virtual address space.
  • a page table instance may be data structure corresponding to the page table structure described with respect to FIG. 2.
  • the process in block 450, may be disassociated from a first page table instance corresponding to the first virtual address space. In block 455, the process may be associated with a second page table instance corresponding to the second virtual address space.
  • a processor instruction may be executed to switch from the first to the second virtual address spaces.
  • the instruction may be a part of the processor instruction set.
  • the instruction may result from the process making a system call.
  • the switch from one VAS to the other may include flushing processor caches and updating process state information.
  • the second virtual address space may be maintained after the process has terminated.
  • a VAS is now a first class entity, meaning that it may exist separate from any process. Thus, a VAS may continue to exist even if it is no longer associated with a process.
  • a request to delete the second VAS may be received. Again, because the VAS is a first class entity, it may be deleted just as any other first class entity may be deleted, in block 475, the second virtual address space may be deleted. For example, deletion may include deletion of the page table instance associated with the second VAS.
  • FIG. 5 is an example of a high level flow diagram of a process switching virtual address spaces according to techniques described herein, in block 510, a process executing on a processor may identify a desire to switch from a first virtual address space to a second virtual address space. As mentioned above, the process may determine the desire to switch to a different VAS in order to access memory beyond that which is available in a single VAS or the process may wish to access data contained in a different VAS.
  • the process may identify the desire to switch virtual address spaces.
  • an identifier for the second virtual address space may be obtained.
  • an identifier associated with the second VAS may be used to particuiariy identify the address space to which the process will switch.
  • a process may request, from an operating system running on the processor, a switch from the first virtual address space to the second virtual address space.
  • the process may simply identify the VAS to switch to (e.g. using the identifier) and then request the operating system to switch the process form the first VAS to the second VAS.
  • the particular details of the switching process may be transparent to the process itself.
  • FIG. 6 is another example of a high level flow diagram of a process switching virtual address spaces according to techniques described herein, in block 805, creation of the second virtual address space may be requested.
  • a VAS is now treated as a first class entity, and as such, can be created independent of any process.
  • the techniques described provide for the ability to request creation of a new VAS.
  • an identifier associated with the created second virtual address space may be received.
  • a VAS may be identified through the identifier.
  • the identifier may be created as part of the creation of a VAS.
  • the identifier may then be sent to the process that requested creation of the second VAS, such that process is able to identify the created second VAS.
  • a process executing on a processor may identify a desire to switch from a first virtual address space to a second virtual address space.
  • the desire may stem from a desire to access memory beyond that which is accessible in a single VAS or it may stem from a desire to access data that is stored in a different VAS.
  • an identifier for the second VAS may be obtained.
  • the identifier may be the identifier that was received in block 810 in the case that the VAS has been newly created.
  • the identifier may be associated with a VAS that was previously created. Regardless of when created the identifier may identify the VAS to which the process will switch.
  • the process may request from an operating system running on the processor a switch from the first virtual address space to the second virtual address space.
  • the process may request deletion of the second virtual address space.
  • the VAS is treated as a first class entity meaning that it can be created independently of a process.
  • a VAS can be deleted independent of a process being destroyed.
  • deletion of the VAS may be requested, thus freeing up any resources being used to maintain the VAS to be deleted.
  • resources may include page table structures or storage space used to store the data contained in page fable structures.

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  • Software Systems (AREA)
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  • Memory System Of A Hierarchy Structure (AREA)

Abstract

L'invention concerne des techniques permettant à un processus de commuter des espaces d'adresses virtuels. Dans un aspect, une demande de commutation d'un premier espace d'adresse virtuel vers un second espace d'adresse virtuel peut être reçue d'un processus. Des informations d'état de processus peuvent être modifiées afin de refléter le passage du premier espace d'adresse virtuel au second espace d'adresse virtuel.
PCT/US2015/049726 2015-09-11 2015-09-11 Procédé de commutation d'espaces d'adresses virtuels WO2017044124A1 (fr)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10754792B2 (en) 2016-01-29 2020-08-25 Hewlett Packard Enterprise Development Lp Persistent virtual address spaces
US11086660B2 (en) 2016-03-09 2021-08-10 Hewlett Packard Enterprise Development Lp Server virtual address space

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US20050216695A1 (en) * 2004-03-26 2005-09-29 Jean-Pierre Bono Memory extension for a data processor to provide both common and separate physical memory areas for virtual memory spaces
US20050273570A1 (en) * 2004-06-03 2005-12-08 Desouter Marc A Virtual space manager for computer having a physical address extension feature
WO2011048606A2 (fr) * 2009-09-25 2011-04-28 Kamlesh Gandhi Description
US20120066469A1 (en) * 2009-02-11 2012-03-15 Infinidat Ltd. Virtualized storage system and method of operating thereof
US20130232316A1 (en) * 2004-07-30 2013-09-05 Jason W. Brandt Maintaining processor resources during architectural evens

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050216695A1 (en) * 2004-03-26 2005-09-29 Jean-Pierre Bono Memory extension for a data processor to provide both common and separate physical memory areas for virtual memory spaces
US20050273570A1 (en) * 2004-06-03 2005-12-08 Desouter Marc A Virtual space manager for computer having a physical address extension feature
US20130232316A1 (en) * 2004-07-30 2013-09-05 Jason W. Brandt Maintaining processor resources during architectural evens
US20120066469A1 (en) * 2009-02-11 2012-03-15 Infinidat Ltd. Virtualized storage system and method of operating thereof
WO2011048606A2 (fr) * 2009-09-25 2011-04-28 Kamlesh Gandhi Description

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10754792B2 (en) 2016-01-29 2020-08-25 Hewlett Packard Enterprise Development Lp Persistent virtual address spaces
US11086660B2 (en) 2016-03-09 2021-08-10 Hewlett Packard Enterprise Development Lp Server virtual address space

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