WO2017042486A1

WO2017042486A1 - Method for manufacturing an electronic junction device and associated device

Info

Publication number: WO2017042486A1
Application number: PCT/FR2016/052228
Authority: WO
Inventors: Olivier PLANTEVIN; Alice DEFRESNE; Pere Roca I Cabarrocas
Original assignee: Ecole Polytechnique; Universite Paris-Sud 11; Centre National De La Recherche Scientifique
Priority date: 2015-09-07
Filing date: 2016-09-07
Publication date: 2017-03-16
Also published as: FR3040822B1; FR3040822A1; EP3347921A1

Abstract

The invention concerns a method for manufacturing an electronic junction device, the electronic junction device (3) comprising a thin-layer surface passivation structure (10, 20) on a surface (1, 2) of a crystalline silicon substrate (4), the surface passivation structure (10, 20) having a determined thickness and comprising at least one thin layer (11, 12, 21, 22) of an amorphous or microcrystalline hydrogenated silicon. According to the invention, the manufacturing method comprises the following steps: a) ion irradiation of the surface passivation structure (10, 20) with an ion beam (30), avoiding the generation of defects in the crystalline substrate during said irradiation; and b) following said ion irradiation step a), thermal annealing of the substrate (4) and of the surface passivation structure (10, 20) at a temperature included in a range extending from 175°C to 530°C, thermal annealing step b) being carried out in the ambient air, under vacuum or in a gaseous atmosphere, and the duration of thermal annealing step b) being of between a few minutes and a few hours. An electronic junction device obtained according to said method is also described.

Description

METHOD FOR MANUFACTURING A JUNCTION DEVICE

ELECTRONIC AND ASSOCIATED DEVICE

TECHNICAL FIELD TO WHICH THE INVENTION RELATES The present invention relates generally to the field of the manufacture of electronic junction devices on a crystalline substrate, used in particular in photovoltaic cells or in microelectronic devices.

It relates more particularly to the manufacture of microelectronic devices or solar cells with heterojunction on crystalline silicon substrate, hereinafter also designated by the formula c-Si.

It concerns in particular the surface passivation of crystalline silicon, and the improvement of the temperature resistance of a crystalline silicon-based electronic device comprising a surface passivation structure.

BACKGROUND

Crystalline silicon, in particular mono- or polycrystalline silicon, is the most widely used material for the fabrication of microelectronic integrated circuits, optoelectronic devices or high efficiency solar cells.

The surface passivation of crystalline silicon is intended to reduce the density of surface defects.

A.G. Aberle "Surface passivation of crystalline silicon solar cells: A review", Prog. Photovolt. : Res. Appl., 2000, 8, pages 473-487, various surface passivation methods applied for the production of crystalline silicon solar cells.

A first passivation method consists of forming a thermal oxide layer at the surface of the c-Si. The thermal oxide provides excellent surface passivation but requires a high temperature of about 1000 ° C. Other low temperature (<500 ° C) passivation methods have been developed. In particular, an effective method of surface passivation is to deposit by plasma (PECVD for Plasma Enhanced Chemical Vapor Deposition) at a temperature of about 200 ° C a stack of two layers of hydrogenated amorphous silicon (or a-Si: H) formed of a first layer of intrinsic hydrogenated amorphous silicon (a-Si: H (i)) and a second layer of hydrogenated amorphous silicon doped n-type or p-type. This method provides an intrinsic thin layer heterojunction with a conversion efficiency of greater than 20% as described in US 6,380,479.

The deposition parameters of the hydrogenated amorphous silicon (a-Si: H) by the PECVD technique have been optimized to obtain a good passivation. It was first shown that it was necessary to avoid an epitaxial relationship between the deposited layer and the crystalline substrate (H. Fujiwara and M. Kondo, "Impact of epitaxial growth at the heterointerface of a-Si: H / c-Si solar cells, Appl., Phys., Lett., 90, 013503, 2007; UK Das et al., Surface passivation and heterojunction cells on Si (100) and (11) wafers using DC and RF plasma deposited Si: H Thin Films ", Appl Phys Lett, 92, 63504, 2008).

Another study then showed that an epitaxy of the intrinsic amorphous layer did not always interfere with passivation if the junction was abrupt. However, it is necessary to avoid depositing a mixed crystal / amorphous phase with a random interface (J. Damon-Lacoste and P. Roca i Cabarrocas, "Toward a better physical understanding of a-Si: H / c-Si heterojunction solar cells", J. Appl Phys 105, 63712, 2009). Amorphous deposition conditions close to those for micro-crystalline deposition make it possible to obtain optimal passivation (A. Descoeudres et al., "The silane depletion fraction as an indicator for the amorphous / crystalline silicon interface passivation quality", Appl Phys Lett, 97, 183505, 2010).

Oxygen can also be introduced into the hydrogenated amorphous silicon layer to avoid epitaxy (Fujiwara et al., Application of hydrogenated amorphous silicon oxide layers to c-Si heterojunction solar cells, Appl. 91, 133508, 2007). Hydrogen plasma treatment of amorphous silicon layers during film deposition or a posteriori may also allow an improvement in passivation.

On the other hand, the realization of the contact electrodes is carried out after the surface passivation of the crystalline silicon. The production of such a contact electrode is based on a deposition of a metal layer, for example by screen printing, possibly preceded by a deposit of a transparent conductive layer, for example a layer of an indium oxide and a tin (ITO, for Indium Tin Oxide) or a layer of zinc oxide (ZnO). This step is generally performed at a temperature of at least 200 to 400 ° C, or followed by an annealing step at comparable temperatures, to reduce the resistivity of the deposited metal and / or transparent conductive layer (s) and to reduce corresponding contact resistances.

However, surface passivation is impaired when the electronic splicing device is subjected to a temperature above 200 ° C, which is a current limitation. This deterioration is particularly marked when this passivation is obtained by means of a thin-layer structure comprising a doped hydrogenated amorphous silicon layer deposited on an intrinsic hydrogenated amorphous silicon layer covering the crystalline silicon substrate.

Thus the publication J.W.A. Schuttauf et al., "Improving the performance of amorphous and crystalline silicon heterojunction solar cells by surface passivation monitoring", J. Non-Cryst. Solids 358, pp. 2245-2248, 2012, shows that a thermal post-treatment leads to a degradation of the passivation of a passivated crystalline silicon substrate by an intrinsic amorphous silicon thin film passivation structure. This degradation of the passivation appears from annealing temperatures between 255 ° C and 300 ° C for a passivation structure consisting of a single layer of intrinsic hydrogenated amorphous silicon (i) or a stack consisting of a layer of doped hydrogenated amorphous silicon (n) deposited on an intrinsic hydrogenated amorphous silicon layer (i) on a doped crystalline silicon substrate (n). The degradation of the passivation occurs at an annealing temperature of 150 ° C. in the case of a heterojunction comprising a doped hydrogenated amorphous silicon layer (p) deposited on an intrinsic hydrogenated amorphous silicon layer (i) on a crystalline silicon substrate. doped (n). The authors of this publication attribute this degradation to the breakdown of silicon-hydrogen bonds in the intrinsic amorphous silicon layer and to the hydrogen diffusion from the intrinsic layer to the doped layer, the diffusion of hydrogen being known to be more important. in a p-doped amorphous silicon layer in an n-doped amorphous silicon layer.

In addition, ion implantation is used to implant doping ions, such as for example boron or phosphorus ions, under the surface of a crystalline silicon substrate. However, the thermal diffusion of dopants is the standard doping technique used in the photovoltaic field.

Argon ion implantation has been used to create defects, either by atomic displacement or by creating gaps, at low concentration below the surface or at different interfaces in a heterojunction solar cell in order to improve understanding of the mechanisms of degradation of a solar cell (Defresne et al., "Interface defects in a-Si: H / c-Si heterojunction solar cells", Nucl., Instr Meth., B, 2015, http: / /dx.doi.orq/10.1 016 / i.nimb.2015.04.009). According to this publication, the implantation of argon ions having an energy of 1 keV or 10 keV generates localized defects in the doped amorphous silicon layer (n or p) and / or extending in the intrinsic amorphous silicon layer. .

The defect profile, that is to say here the manner in which the defect concentration varies as a function of the distance to the irradiated surface, is determined by the implantation energy of these ions. For some values of this implantation energy, these defects are generated in the amorphous layers without reaching the interface between the hydrogenated amorphous silicon (a-Si: H) and the crystalline silicon (c-Si). The implantation of argon ions with an energy of 17 keV generates defects that extend into the doped and intrinsic amorphous silicon layers up to the α-Si: H / c-Si interface. The authors observed a degradation of the passivation interface not only for an energy of 17 keV and a fluence of 10 ¹⁰ ions / cm ² , but also for an energy of 10 keV and a fluence of 10 ¹⁴ ions / cm ² , this degradation being attributed to the generation of faults in the vicinity of this interface. The ion implantation of argon ions is therefore considered to be very harmful to the passivation of the α-Si: H / c-Si interface.

OBJECT OF THE INVENTION

It is desirable to provide a low temperature surface passivation method for manufacturing a heterojunction device having both good surface passivation properties of the crystalline silicon substrate and a good temperature stability of this passivation for a higher temperature. at 200 ° C.

In order to overcome the aforementioned drawback of the state of the art, the present invention proposes a method of manufacturing an electronic junction device, the electronic junction device comprising a surface passivation structure in a thin layer on a surface. a silicon substrate crystalline, in particular mono- or polycrystalline, the surface passivation structure having a determined thickness and comprising at least one thin layer of an amorphous or microcrystalline hydrogenated silicon.

More particularly, it is proposed according to the invention a manufacturing method as mentioned above comprising the following steps:

a) ion irradiation of the surface passivation structure by an ion beam having an energy in a range of 100 eV to 50 keV and a fluence in a range of 10 ^{10 to} 10 ²⁰ ions / cm ² , energy and fluence of said ion beam being adapted according to the thickness of the surface passivation structure so as to generate a defect profile having a determined concentration and limited in depth to said surface passivation structure and / or at the interface between the crystalline substrate and said surface passivation structure, while avoiding generating defects in the crystalline substrate; and

b) following step a) ion irradiation, thermal annealing of the crystalline substrate and the surface passivation structure, at a temperature ranging from 175 ° C to 530 ° C, step b ) of thermal annealing being carried out in ambient air, under vacuum or in a gaseous atmosphere, and the duration of the thermal annealing step b) being between a few minutes and a few hours.

Surprisingly, this method makes it possible to increase the robustness, in the face of subsequent heat treatments, of the surface passivation of the crystalline silicon by a thin film passivation structure comprising an amorphous or microcrystalline hydrogenated silicon layer. The passivation properties can be maintained after a thermal annealing step at a temperature up to 400 ° C and for a thermal annealing time of about 30 minutes.

The process can be carried out in situ in the deposition reactor of the thin film passivation structure.

Even more surprisingly, this method also makes it possible to improve the performance of said passivation structure: the electronic junction device may have a lifetime of the minority carriers after irradiation and thermal annealing greater than for an electronic junction device analogue without ion irradiation or thermal annealing or with only thermal annealing without ion irradiation.

Other nonlimiting and advantageous features of the manufacturing method according to the invention, taken individually or in any technically possible combination, are as follows:

the ion beam is formed of ions of a noble gas, preferably chosen from argon, neon, krypton, and xenon. A combined effect of creating defects comparable to that obtained with a rare gas ion beam can also be obtained with a silicon ion beam;

the ion beam is formed of ions of a non-doping chemical element for the passivation structure in a thin layer and adapted to modify the gap of said at least one thin layer of an amorphous or microcrystalline hydrogenated silicon when implanted in this layer, this chemical element being preferably selected from germanium, carbon, nitrogen, and oxygen;

the ion beam is formed of ions of a doping chemical element for the passivation structure in a thin layer, this chemical element being preferably chosen from boron, phosphorus, arsenic and gallium;

the ionic irradiation step a) comprises ion implantation by a beam scanning ion implanter, ion implantation by ion gun, or exposure to an ion bombardment plasma, or ion implantation. plasma immersion ions;

step a) of ionic irradiation is carried out at a temperature of less than or equal to 400 ° C .;

said at least one thin layer of an amorphous or microcrystalline hydrogenated silicon comprises a thin layer of an intrinsic amorphous or microcrystalline hydrogenated silicon, a thin layer of an amorphous hydrogenated or microcrystalline silicon doped with -n or -p type, thin layer of a hydrogenated silicon nitride, a hydrogenated silicon oxide, a hydrogenated amorphous silicon-carbon alloy, a hydrogenated silicon-germanium alloy, a hydrogenated microcrystalline silicon and / or an alloy hydrogenated microcrystalline silicon or any one of a plurality of such thin layers;

the thermal annealing step b) is carried out in the presence of a mixture of gaseous dihydrogen and at least one neutral gas, or in ambient air;

the duration of the thermal annealing step b) is between 5 minutes and 1 hour; the thermal annealing step b) comprises several thermal annealing cycles.

According to a particular and advantageous aspect, the method of manufacturing an electronic junction device further comprises, after step a), an additional step of forming a contact electrode on the surface passivation structure at a temperature greater than or equal to about 150 ° C. This additional step can be performed before or after step b) of thermal annealing.

When this additional step is carried out after the thermal annealing step b), the formation of this electrode can be carried out at elevated temperature, for example between 200 ° C. and 600 ° C., and this in order to deteriorate the surface passivation of the substrate of the substrate. crystalline silicon, thanks to steps a) and b) above.

Advantageously, the additional step of forming a contact electrode is performed before step b) of thermal annealing. The contact resistance of this electrode and the resistivity of the material which composes it are then reduced during the thermal annealing step b), without damaging the surface passivation of the crystalline silicon.

The invention also provides an electronic junction device obtained according to the method of the present disclosure comprising:

a) a crystalline silicon substrate;

b) a thin film surface passivation structure comprising at least one thin layer of an amorphous or microcrystalline hydrogenated silicon on a surface of the crystalline silicon substrate; the electronic joining device being thermally annealed, in a temperature range of 175 ° C to 530 ° C, after ionic irradiation of the surface passivation structure at an energy in the range of 100 eV to 50 keV and at a temperature of fluence in a range between 10 ¹⁰ and 10 ²⁰ ions / cm ^2, the energy and fluence are adapted according to a thickness and a doping said surface passivation structure, the electronic device having a junction lifetime of the minority carriers after irradiation and increasing thermal annealing as a function of the annealing temperature in a range of annealing temperature ranging from 200 ° C to 300 ° C or 350 ° C.

This electronic junction device has a service life of minority carriers larger than for a similar electronic junction device without ion irradiation.

DETAILED DESCRIPTION OF AN EXEMPLARY EMBODIMENT The following description with reference to the accompanying drawings, given by way of non-limiting examples, will make it clear what the invention consists of and how it can be implemented.

In the accompanying drawings:

- Figure 1 shows schematically a sectional view of a device for electronic junction having two passivated surfaces and subjected to surface irradiation;

FIG. 2 diagrammatically represents an exemplary embodiment of exposure of a sample to an irradiation beam emitted by an ionic implanter;

FIG. 3 represents defect concentration profile curves normalized by the fluence of the ion beam as a function of the depth for different energies of the ion beam;

FIG. 4 represents photoconductance measurements as a function of the density of carriers injected for the same sample respectively before irradiation (disks), after irradiation (diamonds), and after thermal annealing (triangles);

FIG. 5 represents measurements of the effective lifetime of minority carriers as a function of the thermal annealing temperature for various crystalline silicon devices irradiated with an argon ion beam having an energy of 10 keV and a fluence of 10 ¹⁴ ions / cm ² ;

FIG. 6 represents measurements of the effective lifetime of minority carriers as a function of the thermal annealing temperature for various crystalline silicon devices irradiated by an argon ion beam having an energy of 17 keV and a fluence of 10 ¹² ions / cm ² ;

FIG. 7 shows measurements of the effective lifetime of minority carriers as a function of the thermal annealing temperature for various devices based on crystalline silicon irradiated by an argon ion beam having an energy of 30 keV and a fluence of 10 ¹² ions / cm ² .

Process

FIG. 1 shows a sectional view of a device for electronic junction comprising a crystalline silicon substrate 4 having a first surface 1 and a second surface 2. For example, the substrate 4 is an n-doped monocrystalline silicon substrate, previously cleaned in a hydrofluoric acid bath diluted to 5%.

The first surface 1 comprises a first passivation structure

10 in a thin layer comprising here a stack of an intrinsic amorphous hydrogenated silicon layer 1 1 in thickness and a doped amorphous siliconized silicon layer 12 of thickness ei ₂ having n-type or p-doping.

The second surface 2 comprises a second thin film passivation structure 20 comprising here a stack of an intrinsic amorphous hydrogenated silicon layer 21 of thickness e ₂ A and of a doped amorphous hydrogenated silicon layer 22 of thickness e _22. having n-type or p-type doping.

In an exemplary embodiment, the substrate 4 has a thickness e of 280 micrometers, the intrinsic amorphous silicon layer 1 1, respectively 21, a thickness of, respectively e ₂ i of 20 nanometers, the doped amorphous silicon layer 12 a thickness ei ₂ of 25 nanometers and the doped amorphous silicon layer 22 having a thickness e ₂₂ of 25 nanometers.

Advantageously, the layers of intrinsic amorphous silicon 1 1, 21 and doped amorphous silicon 12, 22 are deposited by PECVD. Optionally, the passivation structure 10, respectively 20, comprises a thin layer of silicon carbon having a thickness of about 2 nm at the interface between the crystalline silicon substrate 4 and the silicon layer 1 1, respectively 21 intrinsic amorphous. This thin carbon-based silicon layer makes it possible to avoid epitaxial growth during the deposition of the intrinsic amorphous silicon layer 1 1, respectively 21, on the crystalline silicon substrate 4. During the PECVD deposition steps, the crystalline silicon substrate 4 is maintained at a temperature of about 200 ° C.

The method then has two main steps. In the first step, we irradiate with an ion beam 30 the first passivation structure 10 deposited on the crystalline silicon substrate 4. The ions used are preferably ions of a noble gas, chosen, for example, from argon, helium, krypton, or xenon, or possibly silicon ions.

The ions used can also be ions of a non-chemical element dopant for the passivation structure in a thin layer, and adapted to modify the gap of the amorphous or microcrystalline hydrogenated silicon thin layer once implanted in this layer, for example germanium, carbon, nitrogen, or oxygen.

In a variant, the ion beam is formed of ions of a doping chemical element for the thin film passivation structure, this chemical element being preferably chosen from boron, phosphorus, arsenic and gallium.

In one embodiment, the first step implements an ion implanter to implant ions of one or more of the aforementioned chemical elements. The ion implanter controls the energy range and fluence range of the implanted ions.

In another embodiment, the first step implements an ion gun, having a diameter greater than the sample, which therefore does not require beam scanning.

In another embodiment, the first step implements a plasma treatment of one or more of the aforementioned chemical elements, in energy and fluence ranges of argon ions equivalent to those used in an ion implanter. . The plasma may be chosen from a pulsed microwave plasma or a radio frequency plasma. Plasma treatment can have excellent uniformity over a surface that can be very large, up to 5 m ² .

In another embodiment, the first step implements a plasma immersion ion beam system (IBS). Such an IBS system is generally used for implantation doping, but can here be used for implantation of non-doping ions.

The first step is generally carried out at room temperature, and in any case below 400 ° C.

In the second step, following the step of irradiation with argon or other ions, thermal annealing of the substrate and thin film passivation structures is carried out at a temperature T between about 175 ° C. and 530 ° C. (ie between about 450 to 800 Kelvin), and preferably between 250 and 350 ° C or 400 ° C. The second step is carried out nettenœnt below the recrystallization temperature of the amorphous thin film passivation structure. In the case of amorphous silicon, the recrystallization temperature is about 600 ° C.

The thermal annealing is carried out for example under a gaseous mixture of nitrogen (N ₂ ) diluted to 10% in dihydrogen (H ₂ ). This thermal annealing can also be carried out in ambient air, or under vacuum. The duration of the thermal annealing is generally between 30 and 360 minutes. Thermal annealing can be applied in several cycles.

A surprising effect of this combination of ion irradiation and thermal annealing is to improve or recover passivation at least as good as the starting point (before irradiation with argon ions) for an annealing temperature. of the order of 300 ° C.

This method makes it possible to maintain a good surface passivation of the crystalline silicon for temperatures up to 400 ° C. for annealing times of 30 minutes.

Thus, a solar cell precursor whose crystalline silicon substrate has a robust surface passivation vis-à-vis subsequent heat treatment.

After the second thermal annealing step, a solar cell precursor, for example of the HiT type, is manufactured by depositing, on each of the two thin film passivation structures 10, 20 of this solar cell precursor, a layer of an oxide transparent conductor. The conductive transparent oxide is preferably selected from zinc oxide or indium tin oxide (ITO). For example, a layer of ITO having a thickness of 80 nanometers is sputtered onto each thin-film passivation structure 10, 20 by sputtering. Then, the rear face of the device is metallized by depositing a uniform layer of silver. about 1 micrometer thick on one of the ITO layers. A contact grid is deposited on the front face of the device, by depositing contact strips on the other layer of ITO. The electrical contacts are thus formed at a temperature of 200 to 600 ° C. for a time of between 5 minutes and 1 hour. This gives an operational solar cell.

For the purposes of evaluating the proposed device performance method, different precursors of solar cells are produced: a solar cell precursor based on a passivated crystalline silicon substrate with a thin film passivation structure, without irradiation or annealing treatment. thermal; another solar cell precursor based on a passivated crystalline silicon substrate in an analogous manner, with irradiation treatment and without thermal annealing; yet another solar cell precursor based on an analogously passivated crystalline silicon substrate, with irradiation treatment and with thermal annealing.

Device

FIG. 2 shows a first embodiment of the irradiation step based on the implementation of an ionic implanter 5. For the different experiments illustrated in FIGS. 4-6, an implanter was used IRMA available at CSNSM (J. Chaumont, F. Lalu, M. Salome, AM Lamoise, and H. Bernas, Nuclear Inst, Meth Phys Res 189, 193 (1981)). The ion implanter 5 comprises an ion source 15, an extraction electrode 16, a sorting magnet 17, an ion focusing triplet 18 and deflection plates 19 for scanning the ion beam 30 on a surface sample 3 following two transverse directions.

The ion implantation allows a precise control on the one hand of the energy E of the ions and on the other hand of the fluence of irradiation F.

The ions are accelerated to an energy E adapted to the thickness of the passivation structure 10 in thin layer (s) of amorphous silicon. The diameter of the ion beam is of the order of a few millimeters. The surface of the substrate is for example about 5 × 5 cm ² . The ion beam 30 is scanned over the entire outer surface of the thin film passivation structure 10 to produce a laterally uniform irradiation of the passivation structure.

In the examples detailed below, the energy E of the argon ions is between 1 keV and 30 keV so as to obtain a fault profile located mainly in the thin film passivation structure. As detailed in the present disclosure, the useful range of energy E depends on the thickness of the thin film passivation structure 10.

The SRIM software makes it possible to simulate the concentration profile of the lacunar defects induced by irradiation as a function of the energy and the fluence of the ions.

FIG. 3 represents fluence normalized lacunae defect profile simulations as a function of the depth P measured from the surface of the layer 12 exposed to the ion beam 30. FIG. vertices the limit of the layer 12 of thickness ei ₂ , corresponding to a depth P between 0 and about 20 nm, and the limit of the layer 1 1 of thickness in, corresponding to a depth P of between about 20 nm and 45 nm, and the interface between the thin film passivation structure and the crystalline silicon substrate 4 corresponding to a depth P greater than about 45 nm. Specifically, Figure 3 illustrates different gap profiles simulated for an energy E respectively of 1 keV (dashed line curve), 5 keV (dashed line curve spaced by two points), 10 keV (dashed curve), 17 keV (dashed line curve spaced by one point) and 30 keV (dashed line curve). The fluence F used is respectively 7 × 10 ¹³ ions / cm ² at 1 keV, 10 ¹⁵ ions / cm ² at 5 keV, 10 ¹⁴ ions / cm ² at 10 keV, 10 ¹² ions / cm ² at 17 keV and 30 keV.

Ion implantation generates a lacunar defect profile located mainly in the thin film passivation structure with a maximum located, according to the energy E, in the doped hydrogenated amorphous silicon layer 12 or in the intrinsic hydrogenated amorphous silicon layer. 1 1. The lacunar defect profile extends into the crystalline silicon substrate 4 in the case of irradiations at an energy of 10 to 30 keV, more and more depending on the energy E of the ions.

By way of illustrative example, the irradiation at an energy E of 10 keV and a fluence F of 10 ¹⁴ ions / cm ² results in a defect profile having a maximum at a depth P of 17 nm of the outer surface of the doped hydrogenated amorphous silicon layer 12. This irradiation produces the displacement of one atom out of five and the implantation of atoms of argon in atomic proportion of the order of 1/1000, that is to say that of the order of 1 argon atom is implanted per 1000 silicon atoms.

In addition, irradiation at an energy E of between 10 keV and 30 keV also causes the introduction of defects in a very small proportion (1/10000 to 17 keV and 10 ¹² ions / cm ² for example) at the interface between the crystalline silicon substrate and amorphous thin film passivation structure.

In this energy range, the lacunary defects induced by irradiation of the crystalline silicon substrate lead in the first place to a degradation of the lifetimes of the minority carriers due to the formation of recombination centers for the charge carriers. On the contrary, for an energy E less than or equal to 5 keV, it is observed that the thin layer passivation structure of hydrogenated amorphous silicon is affected without impacting the crystalline silicon substrate 4. The irradiation at 1 keV or 5 keV does not occur. therefore results in no significant decline in the life of the minority holders.

For an energy of 1 keV, the photoconductance of a photovoltaic cell precursor was measured as a function of the fluence, for a fluence F respectively of 10 ¹⁰ ions / cm ² , 10 ¹¹ ions / cm ² , 10 ¹² ions / cm ² , 10 ¹³ ions / cm ² and 7.10 ¹³ ions / cm ² . The lacunary defect profile remains limited to the doped amorphous silicon layer 12 with a maximum of defects at a depth P of approximately 10 nm, without degrading the interface between the crystalline silicon substrate 4 and the thin film passivation structure. amorphous 10. After irradiation of an electron-junction device with argon ions having an energy E of 1 keV, an average decrease of about 15% in the photoconductance of a solar cell precursor formed from this device is observed. with irradiated electronic junction. However, a photoluminescence measurement shows that the effect of irradiation at 1 keV is negligible compared to the natural aging of the solar cell precursor.

The spectral photoluminescence of a solar cell precursor formed from a substrate and surface passivation structures as described in connection with FIG. 1 were measured. The solar cell precursor has a pinin structure, the substrate being n-doped, passivated on its two opposite faces by an intrinsic thin layer (i) on which a p-doped layer has been deposited on one side and on the other side a n-doped layer. More precisely, the spectral photoluminescence of a solar cell precursor formed respectively from a passivated substrate without irradiation or annealing, a passivated substrate with irradiation, here on its two faces, without thermal annealing and finally from a passivated substrate with irradiation, again on both sides, and thermally annealed at 300 ° C under the atmosphere of dihydrogen (H ₂ ). The energy of the ion beam is 5 keV and the fluence is 10 ¹⁵ ions / cm ² . The thermal annealing is carried out at 300 ° C. for 30 minutes in a gaseous mixture of nitrogen and dihydrogen. The spectral photoluminescence of a solar cell with irradiation without thermal annealing is about 30% lower compared to the spectral photoluminescence of a solar cell without irradiation or annealing. thermal. Nevertheless, the spectral photoluminescence of a solar cell precursor with irradiation and with thermal annealing is superior to the spectral photoluminescence of the solar cell with irradiation without thermal annealing. The spectral photoluminescence of the solar cell precursor with irradiation and without thermal annealing is only about 10% lower than that of the solar cell without irradiation or thermal annealing. With an ion energy of 5 keV and a fluence of 10 ¹⁵ ions / cm ² , the ions are implanted in the amorphous passivation structure and not in the crystalline substrate. This implantation makes the amorphous passivation structure more robust with respect to thermal annealing.

FIG. 4 represents photoconductance measurements of a solar cell formed respectively from a passivated substrate without irradiation or annealing (ECLO curve), from a passivated substrate with irradiation without thermal annealing (ECL1 curve) and finally from a passivated substrate with irradiation and thermal annealing (ECL2 curve). The energy of the ion beam is 5 keV and the fluence is 10 ¹⁵ ions / cm ² . The thermal annealing is carried out at 300 ° C. More precisely, FIG. 4 represents measurements of the effective lifetime of the excess carriers (ECL for Effective Carrier Lifetime) as a function of the density of the excess charge carriers. By comparing the ECLO and ECL1 curves, a decrease in photoconductance after irradiation is observed. On the other hand, by comparing the ECL2 and ECLO curves, a higher photoconductance is observed after irradiation then thermal annealing (ECL2) than that of the unirradiated cell and without thermal annealing (ECLO). This increase in the lifespan of the charge carriers is probably due to a decrease in surface recombinations. We thus obtain a better quality of the passivation.

On the other hand, the lifetime of the minority carriers of a sample is measured after irradiation with argon ions of 5 keV and a fluence of 10 ¹⁵ cm ^-2 and an annealing of 30 min at 300 ° C. For a sample having an initial lifetime before irradiation of 2.64 ms, a lifetime of 2.38 ms after irradiation is measured, surprisingly, after a 30 min annealing at 300 ° C., this same sample shows an increased lifetime at This result indicates that the low-energy irradiation process with argon ions followed by annealing of the thin layer of amorphous silicon makes it possible to improve both the passivation of the crystalline silicon and its resistance. temperature in a temperature range of technological interest. the improvement of the lifetime is obtained under conditions (5 keV and a fluence of 10 ¹⁵ cm- ² ) where the implanted ions do not reach the amorphous-crystal interface.

On the contrary, if the radiation-induced damage affects the crystalline silicon too much beyond the amorphous-crystal interface, as is the case after irradiation at 30 keV, for a surface passivation structure having a thickness of about 45 nanometers, the thermal annealing at a moderate temperature (between about 200 and 400 ° C) does not allow to recover a lifetime longer than the lifetime before irradiation, probably because of the defects generated by this irradiation in crystalline silicon. In this case, one obtains a life comparable to that which one would have with an annealing alone, without irradiation. There is no benefit from the point of view of temperature robustness.

For a crystalline silicon substrate electronic junction structure having an amorphous or microcrystalline hydrogenated thin film surface passivation structure having a thickness of 45 nm, an ion energy range of about 5 keV to 17 keV is deduced therefrom. a fluence range of ions between 10 ¹² ions. cm ^"2 at high energy (17 keV) and 10 ¹⁵ cm ^{" 2} at low energy (5 keV). These irradiation conditions make it possible to obtain an optimum lifetime for thermal annealing at a temperature of about 300 ° C. In addition, these irradiation conditions make it possible to maintain a high service life up to an annealing temperature of about 380 ° C.

More generally, the energy range of the ions must be adapted to locate the profile of radiation defects in the amorphous or microcrystalline hydrogenated thin layer passivation structure. The ion energy range then ranges from 100 eV to 50 keV and preferably from a few 100 eV to about 20 keV, depending on the thickness of the hydrogenated thin layer passivation structure. The range of fluence to be used to have a significant effect is between 10 ¹⁰ and 10 ²⁰ ions / cm ² and preferably between 10 ¹⁰ ions / cm ² and 10 ¹⁷ ions / cm ^2.

Figures 5 to 7 show life-time measurement curves versus annealing temperature for different operating conditions of energy and fluence. Each of FIGS. 5 to 7 represents life measurement curves as a function of the annealing temperature for different stacks of surface passivation structures under identical operating conditions of irradiation and annealing, as compared to a non-irradiated sample. The irradiation is carried out at 25 ° C. before annealing.

In FIGS. 5 to 7, the curves marked by a triangle correspond to a ni / c-Si / in type cell architecture, that is to say a crystalline silicon substrate comprising identical surface passivation structures on its two faces comprising a n-doped hydrogenated amorphous silicon layer of 25 nm and an intrinsic amorphous hydrogenated silicon layer of 20 nm at the interface between the substrate and the n-doped layer, the two surface passivation structures being irradiated.

The curves marked by a square correspond to an i / c-Si / in type cell architecture, that is to say a crystalline silicon substrate comprising a first surface passivation structure consisting of a hydrogenated silicon layer. intrinsically amorphous at 45 nm and, on the other side, a second surface passivation structure comprising a 25 nm n-doped amorphous hydrogenated silicon layer and an intrinsic amorphous hydrogenated silicon layer of 20 nm at the interface between the substrate and the n-doped layer, the two surface passivation structures being irradiated.

The curves marked by a disk correspond to a pi / c-Si / in type cell architecture, that is to say a crystalline silicon substrate comprising a first surface passivation structure composed of a hydrogenated silicon layer. p-doped amorphous membrane of 25 nm and an intrinsic amorphous hydrogenated silicon layer of 20 nm at the interface between the substrate and the p-doped layer and, on the other side, a second surface passivation structure comprising a hydrogenated silicon layer 25 nm doped amorphous layer and an intrinsic amorphous hydrogenated silicon layer of 20 nm at the interface between the substrate and the n-doped layer, the two surface passivation structures being irradiated.

Finally, the curves marked by a diamond correspond to a cell architecture of pi / c-Si / in type, not exposed to an ion beam.

In FIG. 5, the irradiation conditions are as follows: implantation of argon ions at an energy of 10 keV and a fluence of 10 ¹⁴ ions / cm ² . The argon ions are mainly implanted in the surface passivation structure in amorphous thin layer and in the minority at the interface between the intrinsic layer and the crystalline substrate and in the crystalline silicon (FIG. 3). The annealing of each sample is carried out for 30 minutes in the presence of a controlled gaseous mixture of dihydrogen diluted to 10% in dinitrogen. For ECL lifetime measurements, the density of minority carriers injected is 10 ¹⁵ cm ^-3 .

In FIGS. 5 to 7, it can be observed that the non-irradiated sample (diamonds) has a decrease in the ECL lifetime which goes from approximately 1.2 ms before annealing to 0.7 ms after annealing at 350 ° C. It is noted that J.W.A. Schuttauf et al., Mentioned above, shows even more drastic lifetimes from 1 millisecond to 50 microseconds after a series of anneals up to 300 ° C under a nitrogen atmosphere.

In FIGS. 5 to 7, irradiation at 25.degree. C., before annealing, produces a decrease in lifetime for all the irradiated samples. In these figures, the non-irradiated samples are represented by solid symbols (disk, square, triangle, rhombus) and, respectively, the samples after irradiation are represented by empty symbols (disk, square, triangle). The lifetime ECL for example passes from about 3.6 ms to about 0.4 ms for the sample ni / c-Si / in in FIG. 5. After irradiation with an energy greater than or equal to about 10 keV, complementary measurements of photoconductance indicate a significant decrease in the lifetime of minority carriers in crystalline silicon.

However, it can be seen in FIGS. 5 and 6 that the post-irradiation annealing makes it possible, under certain annealing conditions, to increase the lifetime of the minority carriers and thus to recover an excellent passivation for which the lifetime of the minority carriers is greater than 3 milliseconds.

FIG. 5 shows, for a given type of irradiated sample and under determined irradiation conditions, a progressive increase in the lifetime of the minority carriers (ECL) from an annealing temperature of about 200 ° C to a temperature of about 300 ° C and then gradually decreases between 300 ° C and 400 ° C. By comparison, the lifetime of a non-irradiated sample decreases continuously from an annealing temperature above 200 ° C.

For the irradiated samples of Figure 5, however, a good shelf life up to 400 ° C, indicating that irradiation can delay the degradation mechanisms of the interface between the crystalline substrate and the amorphous thin-film passivation structure. Pre-treatment with ion irradiation ensures that cell precursors have better temperature stability. We also note that in some cases (samples pi / c-Si / in and i / c-SI / in of Figure 5), the post-irradiation annealing allows to obtain durations of life greater than the starting point of approximately 1 ms, which corresponds to a surprising improvement in the passivation of an electronic junction device. In particular, there is an unexpected improvement in the lifetime for the pi / c-Si / in sample comprising a p-doped amorphous silicon layer, whereas it is known that such a p-doped layer is more sensitive to annealing an n-doped or intrinsic doped amorphous silicon layer.

An interpretation of the physical phenomena implemented is that the irradiation of an amorphous or microcrystalline hydrogenated layer modifies the microscopic structure of this layer while forming defects that trap hydrogen. Thus, the annealing at a moderate temperature makes it possible to reactivate the passivation without exodiffusion of the hydrogen, forming a passivation layer that is stable with respect to the temperature.

In FIG. 6, the irradiation conditions are as follows: implantation of argon ions at an energy of 17 keV and a fluence of 10 ¹² ions / cm ² . The argon ions are mainly implanted in the hydrogenated amorphous thin film surface passivation structure while extending significantly at the interface between the crystalline substrate and the hydrogenated amorphous thin film surface passivation structure ( see Figure 3). These conditions therefore produce some defects in the crystalline substrate. The thermal annealing of each sample is carried out for 30 minutes in the presence of a controlled gaseous mixture of dihydrogen diluted to 10% in dinitrogen. For ECL lifetime measurements, the density of minority carriers injected is 10 ¹⁵ cm ^-3 .

FIG. 6 shows a significant drop in life span from 4-5 ms to less than 0.2 ms when irradiated with argon ions at an energy of 17 keV and a fluence of 10 ¹² cm ^-2. This irradiation corresponds to the introduction into the crystalline silicon substrate of a concentration of lacunary defects similar to the concentration of defects induced under the conditions of the figure 5.

In FIG. 6, for the three types of irradiated samples, there is a gradual increase in the lifetime of the minority carriers (ECL) from an annealing temperature of about 200 ° C. to a temperature of from about 300 ° C to 350 ° C and then a progressive decrease between 350 ° C and 400 ° C.

For the irradiated samples of FIG. 6, a good shelf life of up to 400 ° C. is also preserved, which indicates that the irradiation makes it possible to delay the mechanisms of degradation of the interface between the crystalline substrate and the structure of the substrate. passivation in amorphous thin layer. The pretreatment by ion irradiation ensures the precursors of cells a better temperature resistance. Note also that for the ni / c-Si / in sample of FIG. 6, the post-irradiation annealing at a temperature of between 275 ° C. and 350 ° C. makes it possible to obtain a service life greater than Starting from about 1.5 ms, which corresponds to a surprising improvement in the passivation of the electronic junction device. For the i / c-Si / in samples of FIG. 6, the post-irradiation annealing at a temperature of between 300 ° C. and 350 ° C. makes it possible to obtain a service life of about 3 ms which is of the same order of magnitude. magnitude than the life before irradiation of about 4 ms. On the other hand, in the case of the pi / c-Si / in sample, the recovery of the lifetime is less important in FIG. 6 for an ion irradiation energy of 17 keV and a fluence of 10 ¹² ions / cm ² as in Figure 5, for an ionic irradiation energy of 10 keV and a fluence of 10 ¹⁴ ions / cm ² .

In FIG. 7, the irradiation conditions are the following: implantation of argon ions at an energy of 30 keV and a fluence of 10 ¹² ions / cm ² . Argon ions are implanted at high energy not only in the hydrogenated amorphous thin film surface passivation structure but extend to a depth P of 80-100 nm in the crystalline substrate (see FIG. 3). These irradiation conditions produce a high concentration of defects in the crystalline substrate of the samples considered. Thermal annealing and ECL life measurements are performed in a similar manner as for Figures 5 and 6.

FIG. 7 shows a drastic decrease in the lifetime of the minority carriers which goes from 1 -5.5 ms to less than 0.05 ms during irradiation with argon ions at an energy of 30 keV and a fluence of 10 ¹² cm ^"2 .

In FIG. 7, for the three types of irradiated samples, there is a limited increase in the lifetime of the minority carriers (ECL) from an annealing temperature of 300 ° C. to 350 ° C. However, the service life after annealing remains lower than the lifetime of the non-irradiated sample even after annealing for a sample of ni / c-Si / in. The life of the i / c-Si / in and pi / c-Si / in samples annealed at a temperature of 320-350 ° C is only slightly greater than the service life of the non-irradiated sample annealed at the same temperature. In FIG. 7, contrary to FIG. 5 or 6, no improvement in the service life is observed up to an annealing temperature of 250 ° C.

For a surface passivation structure having a thickness of 45 nanometers, an irradiation at 30 keV seems to produce damage that affects the crystalline silicon to a thickness too great beyond the amorphous-crystal interface, so that the annealing to a moderate temperature (from 300 to 400 ° C) does not make it possible to recover a lifetime comparable to the lifetime before irradiation, contrary to an irradiation with 10keV or 17keV. With irradiation at 30 keV and 10 ¹² ions / cm ² , degradation of passivation is generally due to damage to crystalline silicon that can not be rectified by annealing at 400 ° C.

From these measurements, it is deduced that there is an operational domain that not only allows an increase in the lifetime of the minority carriers, compared with the same sample before irradiation, but a stabilization of the passivation at a relatively high annealing temperature, d. about 200 to 400 ° C. Depending on the thickness and the doping of the hydrogenated thin layer passivation structure, it appears that determined ionic irradiation and thermal annealing conditions make it possible to increase the lifetime of the minority carriers.

To determine the range of ion fluxes as a function of energy, the rate of photoconductance loss induced by irradiation at a given energy is measured, for example, as a function of the flow of ions.

For an energy of 10 keV, an irradiation-induced photoconductance loss rate of about 90% is measured for an ion flux of 10 ¹⁴ ions / cm ² , of about 25% for a 10-ion ion flux. ¹² ions / cm ² and about 0% for an ion flux of 10 ¹⁰ ions / cm ² . For an energy of 17 keV, a radiation-induced photoconductance loss rate of about 98% is measured for an ion flux of 10 ¹² to 10 ¹³ ions / cm ² , of about 90% for a flux of ions of 10 ¹¹ ions / cm ² and about 50% for an ion flux of 10 ¹⁰ ions / cm ² .

The method of the present disclosure applies to a surface passivation structure comprising a layer or stack of layers of hydrogenated, doped or undoped amorphous silicon. This method also applies to a surface passivation structure comprising a layer of a hydrogenated silicon nitride, a hydrogenated amorphous silicon-carbon alloy, a hydrogenated silicon oxide, a hydrogenated silicon-germanium alloy or a layer of a hydrogenated microcrystalline silicon. The surface passivation structure comprises a layer or a stack of one or more of these layers of doped or undoped amorphous or microcrystalline hydrogenated silicon.

The stabilization of the passivation at a temperature higher than the deposition temperature of the amorphous or microcrystalline hydrogenated thin layer passivation structure is advantageously compatible with metallization steps, for example by deposition of zinc oxide, at a higher temperature. (about 400 ° C) to form better electrical contact areas. The method of the present disclosure further allows, as described above, to improve the performance of this passivation structure. Indeed, the electronic junction device may have a lifetime of minority carriers after irradiation and thermal annealing greater than for a similar electronic junction device without ion irradiation or thermal annealing.

The method thus makes it possible to increase the efficiency and the thermal stability of an electronic junction device and in particular of a solar cell formed from a crystalline silicon substrate passivated by an amorphous hydrogenated thin layer passivation structure. or microcrystalline, especially a HiT type cell.

The method also applies to the manufacture of electronic junction devices having applications in microelectronics or optoelectronics, such as detectors.

Claims

1. A method of manufacturing an electronic junction device, the electronic junction device (3) comprising a surface passivation structure (10, 20) in a thin layer on a surface (1, 2) of a substrate (4) of crystalline silicon, the surface passivation structure (10, 20) having a determined thickness and comprising at least one thin layer (1 1, 12, 21, 22) of an amorphous or microcrystalline hydrogenated silicon,

characterized in that the manufacturing method comprises the following steps:

a) ion irradiating the surface passivation structure (10, 20) with an ion beam (30) having an energy in the range of 100 eV to 50 keV and a fluence in a range of 10 ^{10 to} 10 ²⁰ ions / cm ² , the energy and fluence of said ion beam (30) being adapted as a function of the thickness of the surface passivation structure (10, 20) to generate a defect profile having a determined concentration and limited in depth to said surface passivation structure (10, 20) and / or at the interface between said substrate (4) and said surface passivation structure (10, 20) and while avoiding generating defects in the crystalline substrate (4); and

b) following step a) of ion irradiation, thermal annealing of the substrate

(4) and the surface passivation structure (1 0, 20) at a temperature in the range of 175 ° C to 530 ° C, the thermal annealing step b) being carried out in the air ambient, vacuum or gas atmosphere, and the duration of step b) of thermal annealing being between a few minutes and a few hours.

The method of manufacturing an electronic junction device according to claim 1, wherein the ion beam (30) is formed of ions of a noble gas.

The method of manufacturing an electronic junction device according to claim 1, wherein the ion beam (30) is formed of ions of a non-doping chemical element for the surface passivation structure (10, 20) in a thin layer and adapted to modify the gap of said at least one thin layer (1 1, 12, 21, 22) of an amorphous or microcrystalline hydrogenated silicon when implanted in this layer.

The method of manufacturing an electronic junction device according to claim 1, wherein the ion beam (30) is formed of ions of a doping chemical element for the surface passivation structure (10, 20). in thin layer.

5. A method of manufacturing an electronic junction device according to one of claims 1 to 4, wherein the ion irradiation step a) comprises an implantation of ions by a beam scanning ion implanter (5). , or ion implantation by ion gun, or exposure to ion bombardment plasma, or ion implantation by plasma immersion.

6. A method of manufacturing an electronic junction device according to one of claims 1 to 5, wherein the step a) ion irradiation is carried out at a temperature less than or equal to 400 ° C.

7. A method of manufacturing an electronic junction device according to one of claims 1 to 6, wherein said at least one thin layer (1 1,

12, 21, 22) of an amorphous or microcrystalline hydrogenated silicon comprises a thin layer of an intrinsic amorphous or microcrystalline hydrogenated silicon, a thin layer of an amorphous hydrogenated or microcrystalline silicon doped with n or p type, a thin layer of a hydrogenated silicon nitride, a hydrogenated silicon oxide, a hydrogenated amorphous silicon-carbon alloy, a hydrogenated silicon-germanium alloy, a hydrogenated microcrystalline silicon and / or a microcrystalline silicon alloy hydrogenated or any one of a plurality of such thin layers.

8. A method of manufacturing an electronic junction device according to one of claims 1 to 7, wherein the step b) thermal annealing is performed in the presence of a mixture of gaseous hydrogen and at least one gas neutral.

9. A method of manufacturing an electronic junction device according to one of claims 1 to 8, wherein the duration of the thermal annealing step b) is between 5 minutes and 1 hour.

10. A method of manufacturing an electronic junction device according to one of claims 1 to 9, wherein the thermal annealing step b) comprises several thermal annealing cycles.

1 1. Method of manufacturing an electronic junction device according to one of claims 1 to 10, further comprising, after step a), an additional step of forming a contact electrode on the surface passivation structure (10, 20) at a temperature greater than or equal to about 150 ° C.

An electronic junction device (3) comprising:

a) a substrate (4) of crystalline silicon;

b) a thin film surface passivation structure (10, 20) comprising at least one thin layer (1 1, 12, 21, 22) of an amorphous or microcrystalline hydrogenated silicon on a surface of the crystalline silicon substrate; the electronic jointing device (3) being thermally annealed, in a temperature range of 175 ° C to 530 ° C, after ion irradiation of the surface passivation structure (10, 20) at an energy in a range between 100 eV and 50 keV and at a fluence in a range of 10 ^{10 to} 10 ²⁰ ions / cm ² , the energy and the fluence being adjusted according to a thickness and a doping of said surface passivation structure (10, 20), the electronic junction device (3) having a minority carrier life after irradiation and increasing thermal annealing as a function of the annealing temperature in an annealing temperature range from 200 ° C up to at 300 ° C or 350 ° C.