WO2017041815A1

WO2017041815A1 - Parallel re-sampler

Info

Publication number: WO2017041815A1
Application number: PCT/EP2015/070346
Authority: WO
Inventors: Yaron Ben-Arie; Oded Redlich; Doron Ezri; Shimi Shilo; Xin Xue; Chaoke DONG; Junping Zhang
Original assignee: Huawei Technologies Co., Ltd.
Priority date: 2015-09-07
Filing date: 2015-09-07
Publication date: 2017-03-16
Also published as: CN107852166A; CN107852166B; WO2017041815A9

Abstract

A device for signal re-sampling and, in particular wireless signal re-sampling, comprising: 1) A signal processing unit adapted to: (a) Receive a plurality of time interleaved input signals. (b) Generate a plurality of filtered signals by filtering in parallel the interleaved input signals. The filtering is performed in a time-interleaved manner. (c) Integrate the plurality of filtered signals into a plurality of signal streams.

Description

Title: PARALLEL RE-SAMPLER BACKGROUND

The present invention, in some embodiments thereof, relates to parallel resampling and, more specifically, but not exclusively, to parallel re-sampling for communication protocols.

Communication between remote nodes presents several challenges and as transmission frequencies increase to provide higher bandwidth these challenges become more difficult to deal with. One of the major obstacles is maintaining a common frequency for sampling the data of the transmitter at the receiver node since they each operate using a different clock source. Where timing shifts between the two separate clock frequencies may reach hundreds of PPM (Parts Per Million).

In order to ensure the integrity of the transferred data it is crucial to apply resampling of the transmitted and/or the received data to adapt the data received and decoded at the receiving node (receiver) to the data encoded and transmitted by the transmitting node (transmitter). Re- sampling is applied to compensate for frequency shift and /or signal compression which may be induced due to the different clock frequencies of the two nodes (receiver and transmitter).

Re- sampling of the transferred data is performed in various techniques. However as communication frequencies increase, re- sampling requires faster and deeper mechanisms, hardware and/or software to verify data integrity. This forces the use of faster hardware which implies higher complexity, higher cost and/or higher power consumption. SUMMARY

An object of the invention is to improve signal re-sampling. This object is solved by the subject matter of the independent claims. The dependent claims provide further embodiments, in particular in connection with the description and the figures.

According to an aspect of some embodiments of the present invention there is provided a system for signal re-sampling, in particular wireless signal re-sampling, comprising of a signal processing unit adapted to receive a plurality of time interleaved input signals, generate a plurality of filtered signals by filtering in parallel in a time interleaved manner the interleaved input signals and integrate the plurality of filtered signals into a plurality of signal streams.

The signal processing unit is adapted to group together a subset of the plurality of filtered signals by summing up the plurality of filtered signals into a plurality of groups. Each one of the plurality of groups comprises a plurality of filtered signal members each originated from a different interleaved input signal of the plurality of time interleaved input signals.

The signal processing unit comprises a plurality of re-sampling components each comprising a plurality of filters each having one of a plurality of time interleaved filtering coefficients.

The plurality of time interleaved filtering coefficients is a derivative of the total number of the plurality of time interleaved input signals.

Each one of the plurality of filters receives in parallel one of the plurality of time interleaved input signals to output separately one of the plurality of filtered signals.

The signal processing unit comprises a plurality of summing components which are wired in parallel to one another. Each one of the plurality of summing components is wired to sum up a plurality of members of one of the plurality of groups, where each of the plurality of members originated from a different re-sampling component of the plurality of re-sampling components. _j^^lity of re-sampling components is implemented in a silicon integrated circuit (IC) of at least 40 Nanometers.

The plurality of re- sampling components is adapted to change a sampling period of the output signal.

The plurality of re- sampling components comprises four or more re- sampling components, the plurality of filters comprises four or more filters, and the plurality of summing components comprises four or more summing components.

Each of the plurality of filters is a digital filter.

The signal processing unit comprises a plurality of first in first out (FIFO) components each wired to adapt a rate of one of the plurality of signal streams.

Each of the plurality of time interleaved input signals having a bandwidth of at least 1.4 Megahertz (MHz).

According to an aspect of some embodiments of the present invention there is provided a method for adapting a sampling period, by receiving a plurality of time interleaved input signals, generating a plurality of filtered signals by filtering in parallel each one of the plurality of time interleaved input signals using a plurality of time interleaved filtering coefficients and summing up a plurality of groups of the plurality of filtered signals into a plurality of signal streams.

Each group of the plurality of groups comprises a plurality of filtered signal members each originated from a different interleaved input signal of the plurality of time interleaved input signals.

Unless otherwise defined, all technical and/or scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the invention pertains. Although methods and materials similar or equivalent to those described herein can be used in the practice or testing of embodiments of the invention, exemplary methods and/or materials are described below. In case of conflict, the patent specification, including definitions, will control. In addition, the materials, methods, and examples are illustrative only and are not intended to be necessarily limiting. JRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

Some embodiments of the invention are herein described, by way of example only, with reference to the accompanying drawings. With specific reference now to the drawings in detail, it is stressed that the particulars shown are by way of example and for purposes of illustrative discussion of embodiments of the invention. In this regard, the description taken with the drawings makes apparent to those skilled in the art how embodiments of the invention may be practiced.

In the drawings:

FIG. 1 is a schematic illustration of two nodes which communicate with each other while using parallel re- sampling components such as integrated circuits (ICs), according to some embodiments of the present invention;

FIG. 2 is a schematic illustration of exemplary components and the connectivity thereof in an exemplary system, according to some embodiments of the present invention;

FIG. 3 is a flowchart of an exemplary process of re-sampling a signal in a parallel manner using filters having interleaved timing coefficients, according to some embodiments of the present invention; and

FIG. 4 is a schematic illustration of an exemplary system implementation for parallel re-sampling, according to some embodiments of the present invention.

DETAILED DESCRIPTION

The present invention, in some embodiments thereof, relates to parallel re- sampling and, more specifically, but not exclusively, to parallel re-sampling for communication protocols.

As discussed before, re- sampling data at the transmitter and/or the receiver is essential to maintain data integrity during communication sessions between remote nodes each operating using different clock sources.

A parallel re-sampling system is implemented through hardware and/or software is utilized through multiple re-sampling components such as circuits operating in parallel (wherein the term circuit may refer to hardware and/or software module(s)). Each of the re-sampling components receives a plurality of time _iiiJr,„. stream samples, optionally at a rate of no lower than 1.4MHz. The interleaved input samples are processed through digital filters integrated in the resampling components. The digital filters process the input signals to compensate for signal frequency shift and/or signal compression. Processing the interleaved input samples is performed in parallel within the plurality of re-sampling components each processing one of the interleaved input samples using a corresponding timing coefficient to produce a plurality of intermediate output samples. A plurality of groups is created, whose members are a subset of the plurality of intermediate output samples correlating to the interleaved input samples. Each of the plurality of groups is then integrated together in an integration module, i.e. summing all relevant intermediate output samples to create the output stream samples.

Arrays of first in first out (FIFO) elements may be used at the input to the resampling components' filters as well as at the output of the integrations modules. The FIFOs adapt the rate of the input samples which are processed and/or used for temporarily storing the output stream samples in order to construct the output stream in the correct order and rate (timing) based on the clock frequency as generated from local source, i.e. compensate for over or under sampling, transfer rate gaps and/or to verify proper initialization and/or closure of the output stream.

Optionally, each of the output signal samples is constructed from a plurality of corresponding input samples each processed using an appropriate timing coefficient. The plurality of timing coefficients is also interleaved and includes frequency shift and/or signal compression values. The multiplication result is divided by the number of re- sampling components so to assign the proper weight to each input sample in the corresponding output stream sample. The plurality of timing coefficients may be updated in real time (e.g. on the fly) to adjust to the estimated signal frequency shift and/or signal compression ratio.

A control module is controlling in real time the FIFOs' outputs as well as selecting the timing coefficients to be applied to the filters in the re- sampling components.

By employing multiple re-sampling components, multiple time interleaved input samples may be processed in parallel allowing for lower sampling rate since each of the re- sampling components is not sampling consecutive input samples. The number of re-sampling components, n, may be any power of 2, for example, 2, 4, 8, _^Ui^er of re-sampling components is obviously the same as the number of interleaved input samples which are processed in parallel. Each of the results of the re-sampling components, i.e. input sample processed with its respective timing coefficient is divided by 1/2 ^Λη to assign it with a proper weight during integration to create the final output signal samples.

For example, in case 4 re- sampling components are implemented, each resampling component will process every 4th input sample thus reducing the sampling frequency to a 1/4 of the sampling frequency as required by a traditional re-sampling system. The result of the processed input sample in this example will be divided by 4.

Reducing the sampling frequency has a major impact on the hardware used for performing the re-sampling. Reducing the sampling frequency allows the use of less complex and/or slower hardware which is necessarily cheaper and/or consumes less power, for example an integrated circuit (IC) produced using a 40 Nanometers process. For example a 16Gsps re-sampling unit may be utilized through 256 parallel re-sampling components each operating at ~67Msps (16Gsps/256).

Before explaining at least one embodiment of the invention in detail, it is to be understood that the invention is not necessarily limited in its application to the details of construction and the arrangement of the components and/or methods set forth in the following description and/or illustrated in the drawings and/or the Examples. The invention is capable of other embodiments or of being practiced or carried out in various ways.

The present invention may be a system, a method, and/or a computer program product. The computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present invention.

The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing.

Computer readable program instructions described herein can be downloaded to respective computing/processing devices from a computer readable storage external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and/or a wireless network.

The computer readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) may execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present invention.

Aspects of the present invention are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer readable program instructions.

The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by _^ardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions.

Reference is now made to FIG. 1 which is a schematic illustration of two nodes which communicate with each other while using parallel re- sampling components such as integrated circuits (ICs), according to some embodiments of the present invention. Each of the two nodes 110 and 120 comprises a transmitter 130 and a receiver 140. The two nodes 110 and 120 communicate with one another through a physical medium 150, such as air. Due to the frequency difference which may result from the difference in clock sources of the nodes 110 and 120, re-sampling of the signals is performed to compensate for the digital data sampling in both the nodes 110 and 120. As further explained below, re-sampling may be performed on both the transmit path and the receive path by the re- sampling components at the node 110 and/or at the node 120. In the example 100 re-sampling is performed by the node 120 using two re-sampling components 101 integrated in the node 120. The re-sampling components 101 may be implemented through hardware, software and/or a combination of hardware and software. Data received by the node 120 is re-sampled using the re- sampling component 101 prior to being driven to the receiver 140 of the node 120. Data from the transmitter 130 of the node 120 is re-sampled using a second re-sampling component 101 prior to being transmitted to the receiver 140 of the node 110. As result the effects of timing differences between the two nodes 110 and 120 are compensated such that the data received at both receivers 140 maintains its integrity as if the two nodes 110 and 120 operate using the same clock frequency and/or source.

Reference is now also made to FIG. 2 which is a schematic illustration of exemplary components for parallel re-sampling and the connectivity thereof in an exemplary system, according to some embodiments of the present invention. The exemplary system 200 employs 4 re-sampling components each containing four filter elements, for instance sub circuits. The system 200 may employ any number of resampling components as long as the overall number is a power of 2. The first re- sampling component includes filters 240, 241, 242 and 243, the second includes filters 250, 251, 252 and 253, the third includes filters 260, 261, 262 and 263 and the fourth includes filters 270, 271, 272 and 273. Each of the four re-sampling components processes a subset of the incoming input samples where the subset . ^h input sample while every subset of four input samples are interleaved to be processed by the four re-sampling components in parallel. The first input samples subset is INPUT_SAMPLE_0 210 which includes input samples 0, 4, 8, 12, etc. The second input samples subset is INPUT_SAMPLE_1 211 which includes input samples 1, 5, 9, 13, etc. The third input samples subset is INPUT_SAMPLE_2 212 which includes input samples 2, 6, 10, 14, etc. The fourth input samples subset is INPUT_SAMPLE_3 213 which includes input samples 3, 7, 11, 15, etc. The input sample of subset 210, for example input sample 0 is driven into the filters 240, 241, 242 and 243 of the first re-sampling component. The same is done for the other subsets 211, 212 and 213 which are driven to the corresponding filters of the second, third and fourth re-sampling components. The input samples are then multiplied by interleaved timing coefficients to compensate for the input signal frequency shift and/or compression. The timing coefficients are interleaved in the sense that each of the filters 240-243, 250-253, 260-263 and 270-273 may use a different timing coefficient depending on the nature of the input sample it processes. INPUT_SAMPLE_0 210 is processed in parallel in the filters 240, 241, 242 and 243 at the same time INPUT_SAMPLE_1 211 is processed in parallel in the filters 250, 251, 252 and 253, INPUT_SAMPLE_2 212 is processed in parallel in the filters 260, 261, 262 and 263 and INPUT_SAMPLE_3 213 is processed in parallel in the filters 270, 271, 272 and 273. Each of the filters 240-243, 250-253, 260-263 and 270-273 uses an appropriate timing coefficient which may be manipulated in real time (on the fly) for processing the input sample. The results of the filters 240-243, 250-253, 260- 263 and 270-273 are divided by 4 to assign them with the appropriate weight in intermediate output samples. After processing is complete four groups 220, 221, 222, and 223 are created, each group includes a plurality of members which are the intermediate output samples of the four respective filters from the four re-sampling components. Group 220 includes the intermediate output samples coming out of filters 240, 250, 260 and 270, group 221 includes the intermediate output samples coming out of filters 241, 251, 261 and 271, group 222 includes the intermediate output samples coming out of filters 242, 252, 262 and 272 and group 223 includes the intermediate output samples coming out of filters 243, 253, 263 and 273. The four intermediate output signals of the each of the groups 220, 221, 222 and 223 are summed together in an integration module. Group 220 is integrated through 280, group 221 is integrated through integration module 281, group 222 is integrated through integration module 282 and group 223 is integrated through integration module 283. Integration of the intermediate output samples of each of the groups 220, 221, 222 and 223 produces the respective output stream samples OUTPUT_SAMPLE_0 230, OUTPUT_SAMPLE_l 231, OUTPUT_SAMPLE_2 232 and OUTPUT_SAMPLE_3 233. The output stream is then constructed from the four output samples streams, OUTPUT_SAMPLE_0 230, OUTPUT_SAMPLE_l 231, OUTPUT_SAMPLE_2 232 and OUTPUT_SAMPLE_3 233 in the proper order.

Reference is now made to FIG. 3 which is a flowchart of an exemplary process of re-sampling a signal in a parallel manner using filters having interleaved timing coefficients, according to some embodiments of the present invention. An exemplary process 300 which is performed in a system for example, system 200, describes the process of re-sampling an input stream in a parallel manner. The process 300 may be performed in a system other than system 200 which may include a different number of re-sampling components, where the number of re-sampling components should be a power of 2.

As shown at 301, input samples from an input stream are driven in an interleaved fashion into a plurality of filters such as filters 240-243, 250-253, 260-263 and 270-273 integrated in a plurality of re-sampling components.

As shown at 302, each of the plurality of filters such as the filters FILTER_0_0 240, FILTER_0_1 241, FILTER_0_2 242 and FILTER_0_3 243 processes its respective interleaved input sample such as the input samples INPUT_SAMPLE_0 210, INPUT_SAMPLE_1 211, INPUT_SAMPLE_2 212 and INPUT_SAMPLE_3 213 using an appropriate interleaved timing coefficient. The interleaved timing coefficients represent the timing difference between the two clock frequencies of the receiver such as receiver 140 and the transmitter such as the transmitter 130. Each of the 240-243 may use a different interleaved timing coefficient according to the input sample it is processing. The timing coefficients are selected from a storage media according to difference in timing between the clock frequencies of the two nodes communicating with one another.

As shown at 303, a plurality of groups, such as the groups 220-223 is created where each group includes members which are the intermediate output samples respective filters 24-243 from the corresponding four input samples

210-213. The groups are then driven into a plurality of integration modules, such as the integration modules 280, 281, 282 and 283.

As shown at 304, the intermediate output signals of each of the groups 220- 223 are summed up in one of the plurality of integration modules such as the integration modules 280, 281, 282 and/or 283. Summing up may be performed using a sum component which adds together the values of the four intermediate output samples.

As shown at 305, the plurality of output samples driven out of the integration modules 280 - 283, such as OUTPUT_SAMPLE_0 230, OUTPUT_SAMPLE_l 231, OUTPUT_SAMPLE_2 232 and/or OUTPUT_SAMPLE_3 233, are properly ordered in time to match the order in which the input samples INPUT_SAMPLE_0, INPUT_SAMPLE_1, INPUT_SAMPLE_2 and INPUT_SAMPLE_3 were received in order to produce the output stream.

Reference is now made to FIG. 4 which is a schematic illustration of an exemplary system implementation for parallel re-sampling, according to some embodiments of the present invention. An exemplary system 400 may be used to implement the conceptual system 200 for example. The system 400 employs four resampling components 410, 411, 412 and 413, however re-sampling may be performed using any number of re- sampling components as long as the number of re- sampling components is a power of 2. Each of the four re-sampling components 410, 411, 412 and 413 contains four 16 samples filters such as the filters 240-243, 250-253, 260-263 and 270-273 respectively. Each of the filters 240-243, 250-253, 260-263 and 270-273 is preceded with a FIFO 440, 441, 442 and 443 used to temporarily store the incoming input samples subsets, INPUT_SAMPLE_0 210, INPUT_SAMPLE_1 211, INPUT_SAMPLE_2 212 and INPUT_SAMPLE_3 213 in order to adapt the transfer rate and synchronize their insertion into their respective filter 240-243, 250-253, 260- 263 and 270-273. A set of input FIFOs identical to the set of FIFOs 440- 443 is duplicated in each of the re-sampling components 410, 411, 412 and 413 As described for the system 200, each of the filters 240-240-243, 250-253, 260-263 and 270-273 process its respective input sample using a specific appropriate timing coefficients selected from a plurality of timing coefficients stored in a dedicated RAM available for each of the filters 240-243, 250-253, 260-263 and 270-273. Groups of _^ut signals OUT_00 - OUT_30, OUT_01 - OUT_31, OUT_02 -

OUT_32 and OUT_30 - OUT_33 are created from the plurality of filters 240-243, 250-253, 260-263 and 270-273 respectively, such as groups 220, 221, 222 and 223. The intermediate output samples of each of the groups 220, 221, 222 and 223 are summed together in a plurality of integration modules such as the integration modules 280, 281, 282 and 283 to produce the output samples OUT_0 410, OUT_l 411, OUT_2 412 and OUT_3 413 which are driven into a second set of output FIFOs 450, 451, 452 and 453 at the output of each of the integration modules 280, 281, 282 and 283. The FIFOs 450, 451, 452 and 453 are used to store the output stream samples OUT_0 410, OUT_l 411, OUT_2 412 and OUT_3 413 in order to properly drive out output stream samples, such as OUTPUT_SAMPLE_0 230, OUTPUT_SAMPLE_l 231, OUTPUT_SAMPLE_2 232 and OUTPUT_SAMPLE_3 233 that construct the final output stream in the correct order and rate (timing) based on the local clock frequency, i.e. compensate for over or under sampling and/or to verify proper initialization and/or closure of the output stream.

The system includes an exemplary control module 401 for supervising the operation of the plurality of the re-sampling components 410-413, the FIFOs 440-443 and the timing coefficients RAM 240-243. The control module 401 controls the resampling process and is responsible for all sequencing, synchronization and streams constructions. The control unit 401 generates a plurality of control signals going into the components of each of the re-sampling components 410, 411, 412 and 413.

The control signals include:

- Control signals RI_00 - RI_33 487 out of which RI_00, RI_01, RI_02 and RI_03 control the input FIFOs, for example FIFOs 440, 441, 442 and 443.

- Control signals CTRL_00 - CTRL_33 488 which control the timing coefficient RAM of each of the filters 240-243, 250-253, 260-263 and 270-273 in order to select the appropriate coefficient for the filter processing operation.

- Control signals WO_0 - WO_3 486 which control the output FIFOs 450, 451, 452 and 453.

The control module 401 receives a clock signal CLK 482, a reset signal RST

484 and the value y 480 representing the difference between the clock frequency of the two nodes communicating with one another, for example nodes 110 and 120. The clock signal CLK 482 is the primary clock source for the entire system 400 and serves _{^ ^} or all operations that take place in the system 400. The reset signal

RST 484 is used to reset the system 400 and initialize it to its initial state. The clocks' frequencies difference value y 480 is required to identify the actual timing difference between the system 400 and the remote system which system 400 communicates with in order to set the timing coefficients value for the filters 240-243.

The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

It is expected that during the life of a patent maturing from this application many relevant re- sampling systems and/or methods and/or algorithms will be developed and the scope of the term re- sampling is intended to include all such new technologies a priori.

As used herein the term "about" refers to ± 10 %.

The terms "comprises", "comprising", "includes", "including", "having" and their conjugates mean "including but not limited to". This term encompasses the terms "consisting of" and "consisting essentially of".

The phrase "consisting essentially of" means that the composition or method may include additional ingredients and/or steps, but only if the additional ingredients and/or steps do not materially alter the basic and novel characteristics of the claimed composition or method.

As used herein, the singular form "a", "an" and "the" include plural references unless the context clearly dictates otherwise. For example, the term "a compound" or "at least one compound" may include a plurality of compounds, including mixtures thereof.

The word "exemplary" is used herein to mean "serving as an example, instance or illustration". Any embodiment described as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments and/or to exclude the incorporation of features from other embodiments. "optionally" is used herein to mean "is provided in some embodiments and not provided in other embodiments". Any particular embodiment of the invention may include a plurality of "optional" features unless such features conflict.

Throughout this application, various embodiments of this invention may be presented in a range format. It should be understood that the description in range format is merely for convenience and brevity and should not be construed as an inflexible limitation on the scope of the invention. Accordingly, the description of a range should be considered to have specifically disclosed all the possible subranges as well as individual numerical values within that range. For example, description of a range such as from 1 to 6 should be considered to have specifically disclosed subranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6 etc., as well as individual numbers within that range, for example, 1, 2, 3, 4, 5, and 6. This applies regardless of the breadth of the range.

Whenever a numerical range is indicated herein, it is meant to include any cited numeral (fractional or integral) within the indicated range. The phrases "ranging/ranges between" a first indicate number and a second indicate number and "ranging/ranges from" a first indicate number "to" a second indicate number are used herein interchangeably and are meant to include the first and second indicated numbers and all the fractional and integral numerals therebetween.

It is appreciated that certain features of the invention, which are, for clarity, described in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features of the invention, which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable subcombination or as suitable in any other described embodiment of the invention. Certain features described in the context of various embodiments are not to be considered essential features of those embodiments, unless the embodiment is inoperative without those elements.

All publications, patents and patent applications mentioned in this specification are herein incorporated in their entirety by reference into the specification, to the same extent as if each individual publication, patent or patent application was specifically and individually indicated to be incorporated herein by reference. In addition, citation or identification of any reference in this application _^ ~_iitJlJ-ued as an admission that such reference is available as prior art to the present invention. To the extent that section headings are used, they should not be construed as necessarily limiting.

Claims

1. A system for signal re-sampling and, in particular wireless signal re-sampling, comprising:

a signal processing unit adapted to:

- receive a plurality of time interleaved input signals;

- generate a plurality of filtered signals by filtering in parallel said interleaved input signals, wherein said filtering is performed in a time-interleaved manner; and

- integrate said plurality of filtered signals into a plurality of signal streams.

2. The system of claim 1, wherein said signal processing unit is adapted to group together a subset of said plurality of filtered signals by summing up said plurality of filtered signals into a plurality of groups; wherein each one of said plurality of groups comprises a plurality of filtered signal members each originated from a different interleaved input signal of said plurality of time interleaved input signals.

3. The system of any one of claims 1-2, wherein said signal processing unit comprises a plurality of re-sampling components each comprising a plurality of filters each having one of a plurality of time interleaved filtering coefficients.

4. The system of any one of claims 2-3, wherein each one of said plurality of time interleaved filtering coefficients is a derivative of the total number of said plurality of time interleaved input signals.

5. The system of any one of claim 3-4, wherein each one of said plurality of filters receives in parallel one of said plurality of time interleaved input signals to output separately one of said plurality of filtered signals.

6. The system of any one of claims 2-5, wherein said signal processing unit comprises a plurality of summing components which are wired in parallel to one another, each one of said plurality of summing components is wired to sum up a plurality of members of one of said plurality of groups, each of said plurality of members originated from a different re-sampling component of said plurality of resampling component.

7. The system of any one of claims 3-6, wherein said plurality of re-sampling components is implemented in a silicon integrated circuit (IC) of at least 40

Nanometers.

8. The system of any one of claims 3-7, wherein each one of said plurality of resampling components is adapted to change a sampling period of said output signal.

9. The system of any one of claims 3-8, wherein said plurality of re-sampling components comprises at least four re-sampling components, said plurality of filters comprises at least four filters, and said plurality of summing components comprises at least four summing components.

The system of any one of claims 3-9, wherein each one of said plurality of is a digital filter.

11. The system of any one of the preceding claims, wherein said signal processing unit comprises a plurality of first in first out (FIFO) components each wired to adapt a rate of one of said plurality of signal streams.

12. The system of any one of the preceding claims, wherein each of said plurality of time interleaved input signals having a bandwidth of at least 1.4 Megahertz (MHz).

13. A method of adapting a sampling period, comprising:

receiving a plurality of time interleaved input signals;

generating a plurality of filtered signals by filtering in parallel each one of said plurality of time interleaved input signals using a plurality of time interleaved filtering coefficients; and

summing up a plurality of groups of said plurality of filtered signals into a plurality of signal streams;

wherein each group of said plurality of groups comprises a plurality of filtered signal members each originated from a different interleaved input signal of said plurality of time interleaved input signals.