WO2017031723A1 - 基片集成同轴波导互连阵列结构 - Google Patents

基片集成同轴波导互连阵列结构 Download PDF

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Publication number
WO2017031723A1
WO2017031723A1 PCT/CN2015/088164 CN2015088164W WO2017031723A1 WO 2017031723 A1 WO2017031723 A1 WO 2017031723A1 CN 2015088164 W CN2015088164 W CN 2015088164W WO 2017031723 A1 WO2017031723 A1 WO 2017031723A1
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conductor layer
outer conductor
layer
coaxial waveguide
integrated coaxial
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French (fr)
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李晓春
邵妍
王宁
袁斌
毛军发
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Shanghai Jiao Tong University
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Shanghai Jiao Tong University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P3/00—Waveguides; Transmission lines of the waveguide type
    • H01P3/02—Waveguides; Transmission lines of the waveguide type with two longitudinal conductors
    • H01P3/06—Coaxial lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P3/00—Waveguides; Transmission lines of the waveguide type
    • H01P3/02—Waveguides; Transmission lines of the waveguide type with two longitudinal conductors
    • H01P3/08—Microstrips; Strip lines
    • H01P3/081—Microstriplines
    • H01P3/082—Multilayer dielectric

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  • the present invention relates to the field of high speed data transmission interconnections at the board level/package level/chip level, and in particular to a substrate integrated coaxial waveguide interconnect array structure.
  • the traditional interconnection adopts a structure such as a microstrip line/strip line/coplanar waveguide, and realizes interconnection and intercommunication of signals based on a quasi-TEM mode or a TEM mode, and is suitable for baseband signal transmission at a rate below gigabit.
  • a substrate-integrated waveguide interconnect based on a rectangular waveguide is currently under study.
  • the interconnect structure is an electronic bandgap structure composed of upper and lower conductor plates and a via array.
  • the channel exhibits high-pass and wide-band characteristics, but due to the TE10 mode,
  • the baseband signal cannot be directly transmitted, and the baseband signal must be moved to the transmission bandwidth of the rectangular waveguide interconnect by modulation and demodulation, which increases the complexity of the system, and the channel bandwidth is also limited by the bandwidth of the modem component.
  • the single-channel substrate integrated coaxial waveguide is used as a discrete device, and its closed circuit structure has the advantages of small signal loss, low signal delay, weak crosstalk, strong anti-electromagnetic interference capability, and is suitable for TEM mode.
  • the baseband signal is transmitted, but the single-channel substrate-integrated coaxial waveguide interconnect has a limited transmission rate.
  • the invention adopts an open microstrip line/strip line/coplanar waveguide structure for the traditional interconnect line, and has the problems of low speed, high loss and weak anti-electromagnetic interference capability, and single-channel substrate integrated coaxial waveguide interconnect transmission.
  • the rate is limited, providing a substrate-integrated coaxial waveguide interconnect array structure for integrating a coaxial waveguide interconnect array onto a substrate, the structure passing through the outer metal layer and the metallized via, the inner metal layer, and the dielectric layer
  • the outer conductors, the inner conductors, and the dielectric between the inner and outer conductors respectively constituting the substrate-integrated coaxial waveguide interconnect array respectively realize an interconnect array of multi-channel parallel transmission.
  • the substrate integrated coaxial waveguide interconnection array structure proposed by the invention not only has the advantages of small signal loss, low signal delay, weak crosstalk, strong anti-electromagnetic interference capability, but also can transmit multi-channel signals in parallel, thereby further expanding the bandwidth. Increase the data transfer rate.
  • the present invention has been achieved by the following technical solutions.
  • a substrate-integrated coaxial waveguide interconnect array structure adopts a quasi-closed structure, and the physical structure of the substrate integrated coaxial waveguide interconnect array structure includes: at least one single-channel structure from the top to the bottom, the single-channel structure includes a first outer conductor layer, a first dielectric layer, an inner conductor layer, a second dielectric layer, a second outer conductor layer, and a metallized via array; wherein:
  • the inner conductor layer is disposed between the first outer conductor layer and the second outer conductor layer; the first dielectric layer is disposed between the first outer conductor layer and the inner conductor layer, and the second dielectric layer is disposed inside Between the conductor layer and the second outer conductor layer;
  • the single-channel structure is longitudinally disposed with a metallized via array.
  • the first outer conductor layer, the second outer conductor layer and the metalized via array together form an outer conductor of a single channel structure; the plurality of single channel structures form an array in both horizontal and vertical directions, sharing the outer conductor, and the composition
  • the substrate integrated coaxial waveguide interconnect array structure of the invention is not limited to, but not limited to, but not limited to, but not limited to, but not limited to, but not limited to, but not limited to, but not limited to the first outer conductor layer, the second outer conductor layer and the metalized via array together form an outer conductor of a single channel structure; the plurality of single channel structures form an array in both horizontal and vertical directions, sharing the outer conductor, and the composition
  • the substrate integrated coaxial waveguide interconnect array structure of the invention are provided.
  • the two adjacent single-channel structures in the vertical direction share the same outer conductor layer, that is, the second outer conductor layer of the upper single-channel structure is the first outer conductor layer of the next single-channel structure.
  • the metallized via array is two columns, and the two rows of metalized via arrays are equally spaced along the length direction of the physical structure; the two adjacent single channel structures in the horizontal direction share the same row of metallized via arrays.
  • each row of metallized via arrays includes a plurality of metallized vias disposed at equal intervals between adjacent two metallized vias.
  • the through hole diameter of each metallized via hole is d
  • the spacing between adjacent two metallized via holes is s
  • the width between adjacent two rows of metallized via hole arrays is a
  • the number of metallized vias in each column of metallized via arrays depends on the length of the physical structure.
  • the first outer conductor layer, the inner conductor layer and the second outer conductor layer have a thickness t; Both the mass layer and the second dielectric layer have a thickness of h; the physical structure has a length of l.
  • the inner conductor layer comprises at least one discretely disposed metal monomer located between two adjacent rows of metallized via arrays in the width direction of the physical structure.
  • the metal monomer has a width b and a width b is smaller than a width of the outer conductor layer.
  • the first outer conductor layer and the second outer conductor layer each adopt a metal layer.
  • the substrate integrated coaxial waveguide interconnect array structure transmits signals in a TEM (Transverse Electromagnetic Mode) mode, and is capable of simultaneously transmitting multi-channel signals in parallel.
  • TEM Transverse Electromagnetic Mode
  • the substrate provided by the invention integrates a coaxial waveguide interconnect array structure, comprising a shared outer conductor, a plurality of independent inner conductors, a medium disposed between the outer conductor and the inner conductor; and an integrated coaxial with 2 rows ⁇ 2 columns of substrates
  • the physical structure of the substrate integrated coaxial waveguide interconnect array structure is divided into nine layers from top to bottom, and the first layer is the metal layer L1 (the first layer of the first layer single channel structure) Conductor layer), the second layer is the dielectric layer L2 (the first dielectric layer of the first layer single-channel structure), the third layer is the metal layer L3 (the inner conductor layer of the first layer single-channel structure), and the fourth layer is the medium Layer L4 (the second dielectric layer of the first layer single-channel structure), the fifth layer is the metal layer L5 (as the second outer conductor layer of the first layer single-channel structure, and the first layer of the single-channel structure of the second layer)
  • the integrated waveguide waveguide interconnect array structure can be analogized to a n-row by m-column substrate integrated coaxial waveguide interconnect array structure by using 2 rows x 2 columns of substrates, where n is the number of rows, m is the number of columns, and the array There are a total of n rows ⁇ m columns.
  • the substrate integrated coaxial waveguide interconnect array structure provided by the invention is a quasi-closed structure, and the signal is transmitted in the TEM mode, and the signals are transmitted in parallel by multiple channels. It can be used as a board level/package level/chip level interconnect circuit, and the present invention has a low frequency bandwidth and low delay crosstalk compared to a conventional open structure microstrip/stripline/coplanar waveguide interconnect.
  • the advantage of good electromagnetic compatibility is suitable for high-speed data parallel transmission above gigabit, and has scalability in horizontal and vertical directions.
  • the present invention has the following beneficial effects:
  • the substrate integrated coaxial waveguide interconnect array provided by the present invention is a quasi-closed structure, and transmits signals by using a TEM mode, and adopts a quasi-TEM mode with an open interconnect structure such as a conventional microstrip line/strip line/coplanar waveguide. Compared with the transmission signal, it has the advantages of high transmission rate, low delay crosstalk and strong anti-electromagnetic interference capability;
  • the present invention uses a TE10 mode to transmit signals.
  • the substrate integrated coaxial waveguide interconnect array structure does not require a modem device, and has low loss, high speed, simple system, and low cost. advantage;
  • the invention has the advantages of being suitable for multi-channel parallel high-speed transmission;
  • the substrate integrated coaxial waveguide interconnect array provided by the present invention is suitable for high speed data transmission at the board level/package level/chip level.
  • FIG. 1 is a schematic diagram of a single channel structure of a substrate integrated coaxial waveguide interconnect array structure provided by the present invention.
  • FIG. 2 is a schematic view showing the structure of a substrate-integrated coaxial waveguide interconnect array of 2 rows ⁇ 2 columns.
  • FIG. 3 is a schematic structural view of a substrate-integrated coaxial waveguide interconnect array of n rows ⁇ m columns.
  • Figure 4 is an S21 parameter for one channel in a substrate-integrated coaxial waveguide interconnect array.
  • Figure 5 is an S11 parameter for one channel in a substrate-integrated coaxial waveguide interconnect array.
  • 10, 11, 12, 13 are respectively four independent metal monomers of the inner conductor layer, respectively recorded as a first metal monomer, a second metal monomer, a third metal monomer, and a fourth metal monomer;
  • a substrate integrated coaxial waveguide interconnection array structure suitable for circuit board level, package level and chip level is provided.
  • the substrate integrated coaxial waveguide interconnect array structure adopts a quasi-closed structure, and the physical structure of the substrate integrated coaxial waveguide interconnect array structure includes: at least one single channel structure, the single The channel structure comprises: a first outer conductor layer, a first dielectric layer, an inner conductor layer, a second dielectric layer, a second outer conductor layer and two columns of metallized via arrays (metallized via arrays); wherein:
  • the inner conductor layer is disposed between the first outer conductor layer and the second outer conductor layer; the first dielectric layer is disposed between the first outer conductor layer and the inner conductor layer, and the second dielectric layer is disposed inside Between the conductor layer and the second outer conductor layer;
  • the single-channel structure is longitudinally disposed with a metallized via array.
  • first outer conductor layer, the second outer conductor layer and the two rows of metallized via arrays together form an outer conductor of a single channel structure.
  • the plurality of single-channel structures form an array in both horizontal and vertical directions, sharing an outer conductor, and constituting the substrate-integrated coaxial waveguide interconnect array structure of the present invention.
  • the two adjacent single-channel structures in the vertical direction share the same outer conductor layer, that is, the second outer conductor layer of the upper single-channel structure is the first outer conductor layer of the next single-channel structure.
  • the metallized via array is two columns, and the two rows of metalized via arrays are arranged at equal intervals along the length direction of the physical structure. Two single-channel structures adjacent in the horizontal direction share the same row of metallized via arrays.
  • each column of metallized via arrays includes a plurality of metallized vias, and adjacent two metallized vias are equally spaced apart.
  • the through hole diameter of each of the metallized through holes is d
  • the spacing between adjacent two metallized through holes is s
  • the width between adjacent two rows of metallized through hole arrays is a
  • the number of metallized vias in each column of metallized via arrays depends on the length of the physical structure.
  • first outer conductor layer, the inner conductor layer and the second outer conductor layer have a thickness t; the first dielectric layer and the second dielectric layer have a thickness h; the physical structure has a length of l.
  • the inner conductor layer includes at least one discretely disposed metal monomer, the metal monomer being The width direction of the physical structure is between the adjacent two rows of metallized via arrays.
  • the metal monomer has a width b and a width b is smaller than a width of the outer conductor layer.
  • first outer conductor layer and the second outer conductor layer each adopt a metal layer.
  • the substrate integrated coaxial waveguide interconnect array structure transmits signals in a TEM (Transverse Electromagnetic Mode) mode, and is capable of simultaneously transmitting multi-channel signals in parallel.
  • TEM Transverse Electromagnetic Mode
  • a five-layer metal layer and three columns of metallized via holes are used to form an outer conductor and an inner conductor of the array substrate integrated coaxial waveguide, and four dielectric layers are used to form the inner and outer conductors.
  • the dielectric fill enables a substrate-integrated coaxial waveguide interconnect array suitable for high-speed data transfer.
  • the utility model comprises a shared outer conductor, a plurality of independent inner conductors, a medium disposed between the outer conductor and the inner conductor, and the number of channels can be expanded in the lateral direction and the longitudinal direction; the substrate is integrated with the coaxial waveguide interconnection array, and the physical structure thereof is from above
  • the lower layer is divided into nine layers, the first layer is the metal layer L1, the second layer is the dielectric layer L2, the third layer is the metal layer L3, the fourth layer is the dielectric layer L4, and the fifth layer is the metal layer L5, the sixth layer
  • the dielectric layer L6, the seventh layer is the metal layer L7, the eighth layer is the dielectric layer L8, and the ninth layer is the metal layer L9;
  • a metallized via array is disposed between the metal layer L1 and the metal layer L9, the metallized via array extends through the first to ninth layers, and the coaxial waveguide interconnect array is integrated along the substrate a metalized through hole in which the length direction of the structure (physical structure) is arranged in three columns;
  • a metal layer L1, a metal layer L5, a metal layer L9, and a metalized via array constitute the outer conductor
  • the metal layer L3 and the metal layer L7 constitute the inner conductor
  • the dielectric layer L2, the dielectric layer L4, the dielectric layer L6, and the dielectric layer L8 constitute a medium filled between the outer conductor and the inner conductor.
  • the thicknesses of the metal layer L1, the metal layer L3, the metal layer L5, the metal layer L7, and the metal layer L9 are all t
  • the thicknesses of the dielectric layer L2, the dielectric layer L4, the dielectric layer L6, and the dielectric layer L8 are all h
  • the length of the array substrate integrated coaxial waveguide interconnect structure is l.
  • the metal layer width b of the metal layer L3 and the metal layer L7 is smaller than the widths of the metal layer L1, the metal layer L5, and the metal layer L9, and the metal layer L3 and the metal layer L7 are integrated with the coaxial waveguides on the array substrate.
  • the width direction of the connecting structure is between adjacent two rows of metallized through holes.
  • the diameter of the metallized via in the metallized via array is d, and adjacent metallization vias are equally spaced between each other, the pitch is s, and the width between the two rows of metallized via arrays is a.
  • the substrate integrated coaxial waveguide interconnect array structure transmits signals by using a TEM mode
  • the substrate integrated coaxial waveguide interconnect array structure adopts a multi-channel parallel transmission structure, and can simultaneously transmit multi-channel signals.
  • FIG. 1 is a schematic diagram of a single-channel structure of a substrate-integrated coaxial waveguide interconnect array structure provided by the present invention, comprising an outer conductor, an inner conductor, and a medium between the inner and outer conductors, comprising three metal layers and two dielectric layers. .
  • the structure is expanded in the lateral and longitudinal directions to form an array of substrate integrated coaxial waveguide interconnect structures provided by the present invention.
  • FIG. 2 is a schematic diagram of the substrate integrated coaxial waveguide interconnect array structure provided by the present invention when the number of rows and the number of columns are two, including the outer conductor, the inner conductor, and the medium between the inner and outer conductors, and the substrate is integrated coaxially.
  • the physical structure of the waveguide interconnect array consists of five metal layers and four dielectric layers.
  • the substrate integrated coaxial waveguide interconnect array transmits signals in a TEM mode.
  • the substrate integrated coaxial waveguide interconnect array structure provided in FIG. 2 can be expanded into n rows ⁇ m columns channels, where n and m are any positive integers, n represents the number of rows of the array, and m represents the number of columns of the array, as shown in the figure. 3 is shown.
  • the physical structure of the substrate integrated coaxial waveguide interconnect array is divided into nine layers from top to bottom, the first layer is the metal layer L1, the second layer is the dielectric layer L2, and the third layer is the metal layer L3, the fourth layer For the dielectric layer L4, the fifth layer is the metal layer L5, the sixth layer is the dielectric layer L6, the seventh layer is the metal layer L7, the eighth layer is the dielectric layer L8, the ninth layer is the metal layer L9, and the fifth layer is the metal layer L9.
  • the thickness is t, the thickness of both dielectric layers is h, and the length of the waveguide interconnect (physical structure) is l.
  • the outer conductor is composed of a metallized via array formed by a metal layer L1, a metal layer L5, a metal layer L9, and a three-row metallized via array between the metal layer L1 and the metal layer L9.
  • the metallized via has a diameter d and a pitch of s, and the width between adjacent two rows of metallized via arrays is a.
  • the inner conductor is a metal layer L3 and a metal layer L7, and the metal monomer constituting the metal layer L3 and the metal layer L7 has a width b.
  • the medium is composed of a dielectric layer L2, a dielectric layer L4, a dielectric layer L6, and a dielectric layer L8, and forms a dielectric filling between the inner conductor and the outer conductor.
  • the characteristic impedance Z 0 of the substrate-integrated coaxial waveguide interconnect array is typically designed to be 50 ohms, which is calculated as:
  • ⁇ r represents the relative dielectric constant of the medium.
  • the frequency range of the substrate-integrated coaxial waveguide interconnect array is the cutoff frequency f TE10 from DC to TE10 mode, which is calculated as:
  • the substrate integrated coaxial waveguide interconnect array structure designed in this embodiment has the advantages of low frequency bandwidth, low loss, low delay crosstalk, strong anti-electromagnetic interference capability, and easy expansion of the channel, and is suitable for circuit board level/ Multi-channel parallel high-speed data transfer at the package level/chip level.

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Abstract

一种基片集成同轴波导互连阵列结构，包括至少一个单通道结构，内导体层设置于第一外导体层和第二外导体层之间；第一介质层设置于第一外导体层和内导体层之间，第二介质层设置于内导体层和第二外导体层之间。第一外导体层、第二外导体层、金属化通孔阵列组成外导体，多个单通道结构在水平、垂直方向形成阵列，共享外导体。垂直方向相邻单通道结构共用同一层外导体层。水平方向相邻单通道结构共用同一列金属化通孔阵列。一种用作电路板级/封装级/芯片级的互连电路，具有频带宽、时延串扰低、电磁兼容性能好的优点，适合于吉比特以上的高速数据多通道并行传输，并且在横向和纵向具有可扩展性。

Description

基片集成同轴波导互连阵列结构 技术领域
本发明涉及电路板级/封装级/芯片级的高速数据传输互连技术领域，具体地，涉及一种基片集成同轴波导互连阵列结构。
背景技术
随着社会的发展与进步，对太比特数据传输速率的需求正变得愈发迫切。应对太比特数据传输速率的需求，高速电互连技术成为系统得以实现的关键。传统互连采用微带线/带状线/共面波导等结构，基于准TEM模式或者TEM模式实现信号的互连互通，适合速率在吉比特以下的基带信号传输。但其开放式的物理结构在高频条件下显示出高损耗的缺点，并且损耗随频率的上升而急剧增加，严重制约信号传输的距离和速率；当传输速率超过吉比特时，还将引起严重的串扰、时延、畸变、码间干扰等信号完整性及电磁干扰问题。虽然串行链路技术的引入可降低电互连线间的串扰，但同时也降低了信号的传输密度；均衡和预加重技术虽然补偿了传统电互连在高频时的损耗，扩展了带宽，但仍无法避免电磁干扰(EMI)问题，同时还增加了额外的电路开销，导致成本的大幅上升。总之，传统电互连技术已经无法满足新一代数据传输的需求，迫切需要发展适合更高传输速率的新型电互连技术。目前正在研究基于矩形波导的基片集成波导互连，该互连结构是由上下导体板和通孔阵列构成的电子带隙结构，其信道呈现高通、宽频带特性，但是由于采用TE10模式，因此无法直接传输基带信号，必须经过调制解调将基带信号搬移到矩形波导互连的传输带宽中，增加了系统的复杂性，并且其信道带宽还受到调制解调器件带宽的限制。
而单通道的基片集成同轴波导作为分立器件，其封闭式的电路结构具有信号损耗小、信号时延低、串扰弱、抗电磁干扰能力强的优点，并且由于其采用TEM模式，因此适合传输基带信号，但是单通道的基片集成同轴波导互连传输速率有限。
发明内容
本发明针对传统互连线采用开放式的微带线/带状线/共面波导结构面临速率低、损耗高、抗电磁干扰能力弱的问题，而单通道基片集成同轴波导互连传输速率有限，提供了一种将同轴波导互连阵列集成到基片上的基片集成同轴波导互连阵列结构，该结构通过外层金属层和金属化通孔、内层金属层、介质层分别构成基片集成同轴波导互连阵列的外导体、内导体以及内外导体间的介质填充，实现了多通道并行传输的互连阵列。本发明提出的基片集成同轴波导互连阵列结构，不仅具有信号损耗小、信号时延低、串扰弱、抗电磁干扰能力强的优点，还可以并行传输多通道信号，从而进一步拓展了带宽、增大了数据传输速率。
为实现上述目的，本发明是通过以下技术方案实现的。
一种基片集成同轴波导互连阵列结构，采用准封闭式结构，基片集成同轴波导互连阵列结构的物理结构自上而下包括：至少一个单通道结构，所述单通道结构包括：第一外导体层、第一介质层、内导体层、第二介质层、第二外导体层以及金属化通孔阵列；其中：
所述内导体层设置于第一外导体层和第二外导体层之间；所述第一介质层设置于第一外导体层和内导体层之间，所述第二介质层设置于内导体层和第二外导体层之间；
所述单通道结构纵向贯穿设置有金属化通孔阵列。
优选地，第一外导体层、第二外导体层以及金属化通孔阵列共同组成单通道结构的外导体；多个单通道结构在水平和垂直两个方向形成阵列，共享外导体，组成本发明所述的基片集成同轴波导互连阵列结构。
优选地，垂直方向两个相邻单通道结构共用同一层外导体层，即，上一层单通道结构的第二外导体层为下一层单通道结构的第一外导体层。
优选地，所述金属化通孔阵列为两列，两列金属化通孔阵列沿物理结构的长度方向等间距排列；水平方向相邻两个单通道结构共用同一列金属化通孔阵列。
优选地，每一列金属化通孔阵列均包括若干个金属化通孔，相邻两个金属化通孔之间等间距设置。
优选地，每一个金属化通孔的通孔直径均为d，相邻两个金属化通孔之间的间距为s，相邻两列金属化通孔阵列之间的宽度为a；
每一列金属化通孔阵列的金属化通孔个数取决于物理结构的长度。
优选地，所述第一外导体层、内导体层和第二外导体层的厚度均为t；第一介 质层和第二介质层的厚度均为h；所述物理结构的长度为l。
优选地，所述内导体层包括至少一个离散设置的金属单体，所述金属单体在物理结构的宽度方向上位于相邻两列金属化通孔阵列之间。
优选地，所述金属单体的宽度为b，且宽度b小于外导体层的宽度。
优选地，所述第一外导体层和第二外导体层均采用金属层。
优选地，所述基片集成同轴波导互连阵列结构采用TEM(横电磁模)模式传输信号，且能够同时并行传输多通道信号。
本发明提供的基片集成同轴波导互连阵列结构，包括共享的外导体、多个独立的内导体，外导体与内导体之间设置有介质；以2行×2列基片集成同轴波导互连阵列结构为例，所述基片集成同轴波导互连阵列结构的物理结构自上而下分为九层，第一层为金属层L1(第一层单通道结构的第一外导体层)，第二层为介质层L2(第一层单通道结构的第一介质层)，第三层为金属层L3(第一层单通道结构的内导体层)，第四层为介质层L4(第一层单通道结构的第二介质层)，第五层为金属层L5(既作为第一层单通道结构的第二外导体层，又作为第二层单通道结构的第一外导体层)，第六层为介质层L6(第二层单通道结构的第一介质层)，第七层为金属层L7(第二层单通道结构的内导体层)，第八层为介质层L8(第二层单通道结构的第二介质层)，第九层为金属层L9(第二层单通道结构的第二外导体层)。通过2行×2列的基片集成同轴波导互连阵列结构，可以类推到n行×m列的基片集成同轴波导互连阵列结构，其中n为行数，m为列数，阵列共有n行×m列个通道。本发明提供的基片集成同轴波导互连阵列结构为准封闭式结构，采用TEM模式传输信号，信号由多通道并行传输。其可以用作电路板级/封装级/芯片级的互连电路，与传统开放结构的微带线/带状线/共面波导互连相比，本发明具有频带宽、时延串扰低、电磁兼容性能好的优点，适合于吉比特以上的高速数据并行传输，并且在横向和纵向具有可扩展性。
与现有技术相比，本发明具有如下的有益效果：
1、本发明提供的基片集成同轴波导互连阵列为准封闭式结构，采用TEM模式传输信号，与传统微带线/带状线/共面波导等开放式互连结构采用准TEM模式传输信号相比，具有传输速率高、时延串扰低、抗电磁干扰能力强的优点；
2、本发明与矩形基片集成波导采用TE10模式传输信号相比，基片集成同轴波导互连阵列结构不需要调制解调器件，具有损耗小、速率高、系统简单、成本低的 优点；
3、本发明与单通道基片集成同轴波导相比，具有适于多通道并行高速传输的优点；
4、本发明提供的基片集成同轴波导互连阵列适合用于电路板级/封装级/芯片级的高速数据传输。
附图说明
通过阅读参照以下附图对非限制性实施例所作的详细描述，本发明的其它特征、目的和优点将会变得更明显：
图1为本发明所提供的基片集成同轴波导互连阵列结构的一个单通道结构示意图。
图2为2行×2列的基片集成同轴波导互连阵列的结构示意图。
图3为n行×m列的基片集成同轴波导互连阵列的结构示意图。
图4为基片集成同轴波导互连阵列中一个通道的S21参数。
图5为基片集成同轴波导互连阵列中一个通道的S11参数。
图中：
1 为金属层L1；
2 为介质层L2；
3 为金属层L3；
4 为介质层L4；
5 为金属层L5；
6 为介质层L6；
7 为金属层L7；
8 为介质层L8；
9 为金属层L9；
10、11、12、13 分别为内导体层的四个独立的金属单体，分别记为第一金属单体、第二金属单体、第三金属单体、第四金属单体；
14 为共享的外导体层。
具体实施方式
下面对本发明的实施例作详细说明：本实施例在以本发明技术方案为前提下进行实施，给出了详细的实施方式和具体的操作过程。应当指出的是，对本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。
实施例
本实施例为了实现阵列同轴波导电路板级/封装级/芯片级的基片集成化，提供了一种适用于电路板级、封装级及芯片级的基片集成同轴波导互连阵列结构。
本实施例提供的基片集成同轴波导互连阵列结构，采用准封闭式结构，基片集成同轴波导互连阵列结构的物理结构自上而下包括：至少一个单通道结构，所述单通道结构包括：第一外导体层、第一介质层、内导体层、第二介质层、第二外导体层以及两列金属化通孔阵列(金属化通孔阵列)；其中：
所述内导体层设置于第一外导体层和第二外导体层之间；所述第一介质层设置于第一外导体层和内导体层之间，所述第二介质层设置于内导体层和第二外导体层之间；
所述单通道结构纵向贯穿设置有金属化通孔阵列。
进一步地，第一外导体层、第二外导体层以及两列金属化通孔阵列共同组成单通道结构的外导体。多个单通道结构在水平、垂直两方向形成阵列，共享外导体，组成本发明所述的基片集成同轴波导互连阵列结构。
进一步地，垂直方向相邻两个单通道结构共用同一层外导体层，即，上一层单通道结构的第二外导体层为下一层单通道结构的第一外导体层。
进一步地，所述金属化通孔阵列为两列，两列金属化通孔阵列沿物理结构的长度方向等间距排列。水平方向相邻两个单通道结构共用同一列金属化通孔阵列。
进一步地，每一列金属化通孔阵列均包括若干个金属化通孔，相邻两个金属化通孔之间等间距设置。
进一步地，每一个金属化通孔的通孔直径均为d，相邻两个金属化通孔之间的间距为s，相邻两列金属化通孔阵列之间的宽度为a；
每一列金属化通孔阵列的金属化通孔个数取决于物理结构的长度。
进一步地，所述第一外导体层、内导体层和第二外导体层的厚度均为t；第一介质层和第二介质层的厚度均为h；所述物理结构的长度为l。
进一步地，所述内导体层包括至少一个离散设置的金属单体，所述金属单体在 物理结构的宽度方向上位于相邻两列金属化通孔阵列之间。
进一步地，所述金属单体的宽度为b，且宽度b小于外导体层的宽度。
进一步地，所述第一外导体层和第二外导体层均采用金属层。
进一步地，所述基片集成同轴波导互连阵列结构采用TEM(横电磁模)模式传输信号，且能够同时并行传输多通道信号。
下面以2行x2列互连阵列为例，采用五层金属层、三列金属化通孔构成阵列基片集成同轴波导的外导体、内导体，采用四层介质层构成内、外导体间的介质填充，实现了适合高速数据传输的基片集成同轴波导互连阵列。
具体为：
包括共享的外导体、多个独立的内导体，外导体与内导体之间设置有介质，可以在横向和纵向拓展通道数；所述基片集成同轴波导互连阵列，其物理结构自上而下分为九层，第一层为金属层L1，第二层为介质层L2，第三层为金属层L3，第四层为介质层L4，第五层为金属层L5，第六层为介质层L6，第七层为金属层L7，第八层为介质层L8，第九层为金属层L9；
在金属层L1与金属层L9之间设置有金属化通孔阵列，所述金属化通孔阵列贯穿所述第一层至第九层，且由沿所述基片集成同轴波导互连阵列结构(物理结构)的长度方向呈三列排列的金属化通孔构成；
其中：
金属层L1、金属层L5、金属层L9、金属化通孔阵列构成所述外导体；
金属层L3、金属层L7构成所述内导体；
介质层L2、介质层L4、介质层L6、介质层L8构成填充于外导体与内导体之间的介质。
进一步地，金属层L1、金属层L3、金属层L5、金属层L7和金属层L9的厚度均为t，介质层L2、介质层L4、介质层L6、介质层L8的厚度均为h，所述阵列基片集成同轴波导互连结构的长度为l。
进一步地，金属层L3、金属层L7的金属单体宽度b小于金属层L1、金属层L5以及金属层L9的宽度，且金属层L3、金属层L7在所述阵列基片集成同轴波导互连结构的宽度方向上位于相邻两列金属化通孔之间。
进一步地，金属化通孔阵列中的金属化通孔的直径为d，且相邻金属化通孔之间等间距排列，间距为s，两列金属化通孔阵列之间的宽度为a。
进一步地，所述基片集成同轴波导互连阵列结构采用TEM模式传输信号，且所述基片集成同轴波导互连阵列结构采用多通道并行传输结构，可同时传输多通道信号。
下面结合附图对本实施例进一步描述。
图1为本发明所提供的基片集成同轴波导互连阵列结构的一个单通道结构示意图，包括外导体、内导体以及内外导体之间的介质，由三层金属层和二层介质层组成。该结构在横向和纵向扩充，即可形成本发明所提供的基片集成同轴波导互连结构阵列。
图2为本发明所提供的基片集成同轴波导互连阵列结构当行数和列数都为2的时候的示意图，包括外导体、内导体以及内外导体之间的介质，基片集成同轴波导互连阵列的物理结构由五层金属层和四层介质层组成。所述基片集成同轴波导互连阵列采用TEM模式传输信号。
图2所提供的基片集成同轴波导互连阵列结构可扩充为n行×m列通道，其中n、m为任意正整数，n表示阵列的行数，m表示阵列的列数，如图3所示。
以图2所示的2行x2列互连阵列为例：
所述基片集成同轴波导互连阵列的物理结构自上而下分为九层，第一层为金属层L1，第二层为介质层L2，第三层为金属层L3，第四层为介质层L4，第五层为金属层L5，第六层为介质层L6，第七层为金属层L7，第八层为介质层L8，第九层为金属层L9，五层金属层的厚度均为t，两层介质层的厚度均为h，波导互连(物理结构)的长度为l。
所述外导体由金属层L1、金属层L5、金属层L9以及金属层L1到金属层L9间的三列金属化通孔阵列所形成的金属化通孔阵列组成。金属化通孔的直径为d，间距为s，相邻两列金属化通孔阵列间的宽度为a。
所述内导体为金属层L3、金属层L7，构成金属层L3和金属层L7的金属单体的宽度为b。
所述介质由介质层L2、介质层L4、介质层L6、介质层L8组成，形成内导体与外导体之间的介质填充。
基片集成同轴波导互连阵列的特性阻抗Z0通常设计为50欧姆，其计算公式为：
Figure PCTCN2015088164-appb-000001
其中，εr表示介质的相对介电常数。
基片集成同轴波导互连阵列的频带范围是从直流到TE10模式的截止频率fTE10，其计算公式为：
Figure PCTCN2015088164-appb-000002
其中，c表示真空中的光速。
以电路板级的2行x2列基片集成同轴波导互连阵列为例，采用Rogers RT/duroid5880材料(介电常数2.2，介质损耗角正切0.0009)，外导体宽度a＝2mm，内导体宽度b＝0.37mm；金属层厚度t＝0.018mm，介质层厚度h＝0.254mm，通孔直径d＝0.4mm，通孔间距s＝0.6mm，波导长度l＝30mm。阵列中单通道的插入损耗S21参数、回波损耗S11参数分别如图4、图5所示，其中图4、图5中的横轴表示频率(Frequency(GHz))，纵轴表示分贝(dB)。
综上，本实施例所设计的基片集成同轴波导互连阵列结构，具有频带宽、损耗小、时延串扰低、抗电磁干扰能力强、便于拓展通道的优点，适合于电路板级/封装级/芯片级的多通道并行高速数据传输。
以上对本发明的具体实施例进行了描述。需要理解的是，本发明并不局限于上述特定实施方式，本领域技术人员可以在权利要求的范围内做出各种变形或修改，这并不影响本发明的实质内容。

Claims (10)

  1. 一种基片集成同轴波导互连阵列结构，其特征在于，采用准封闭式结构，基片集成同轴波导互连阵列结构的物理结构包括：至少一个单通道结构，所述单通道结构包括：第一外导体层、第一介质层、内导体层、第二介质层、第二外导体层以及金属化通孔阵列；其中：
    所述内导体层设置于第一外导体层和第二外导体层之间；所述第一介质层设置于第一外导体层和内导体层之间，所述第二介质层设置于内导体层和第二外导体层之间；所述单通道结构纵向贯穿设置有金属化通孔阵列；
    所述第一外导体层、第二外导体层以及金属化通孔阵列共同组成单通道结构的外导体；多个单通道结构在水平和垂直两个方向形成阵列，共享外导体。
  2. 根据权利要求1所述的基片集成同轴波导互连阵列结构，其特征在于，垂直方向相邻两个单通道结构共用同一层外导体层，即，上一层单通道结构的第二外导体层为下一层单通道结构的第一外导体层。
  3. 根据权利要求1所述的基片集成同轴波导互连阵列结构，其特征在于，所述金属化通孔阵列为两列，两列金属化通孔阵列沿物理结构的长度方向等间距排列；水平方向相邻两个单通道结构共用同一列金属化通孔阵列。
  4. 根据权利要求3所述的基片集成同轴波导互连阵列结构，其特征在于，每一列金属化通孔阵列均包括若干个金属化通孔，相邻两个金属化通孔之间等间距设置。
  5. 根据权利要求4所述的基片集成同轴波导互连阵列结构，其特征在于，每一个金属化通孔的通孔直径均为d，相邻两个金属化通孔之间的间距为s，相邻两列金属化通孔阵列之间的宽度为a；
    每一列金属化通孔阵列的金属化通孔个数取决于物理结构的长度。
  6. 根据权利要求1所述的基片集成同轴波导互连阵列结构，其特征在于，所述第一外导体层、内导体层和第二外导体层的厚度均为t；第一介质层和第二介质层的厚度均为h；所述物理结构的长度为l。
  7. 根据权利要求3所述的基片集成同轴波导互连阵列结构，其特征在于，所述内导体层包括至少一个离散设置的金属单体，所述金属单体在物理结构的宽度方向上位于相邻两列金属化通孔阵列之间。
  8. 根据权利要求7所述的基片集成同轴波导互连阵列结构，其特征在于，所述金属单体的宽度为b，且宽度b小于外导体层的宽度。
  9. 根据权利要求1所述的基片集成同轴波导互连阵列结构，其特征在于，所述第一外导体层和第二外导体层均采用金属层。
  10. 根据权利要求1所述的基片集成同轴波导互连阵列结构，其特征在于，所述基片集成同轴波导互连阵列结构采用TEM模式传输信号，且能够同时并行传输多通道信号。
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