WO2017030267A1 - Planar liquid crystal-gate-field effect transistor comprising dipole control layer and super-sensitivity tactile sensor using same - Google Patents

Planar liquid crystal-gate-field effect transistor comprising dipole control layer and super-sensitivity tactile sensor using same Download PDF

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Publication number
WO2017030267A1
WO2017030267A1 PCT/KR2016/003923 KR2016003923W WO2017030267A1 WO 2017030267 A1 WO2017030267 A1 WO 2017030267A1 KR 2016003923 W KR2016003923 W KR 2016003923W WO 2017030267 A1 WO2017030267 A1 WO 2017030267A1
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liquid crystal
layer
gate
channel layer
substrate
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PCT/KR2016/003923
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French (fr)
Korean (ko)
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김영규
김화정
서주역
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경북대학교산학협력단
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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01LMEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
    • G01L1/00Measuring force or stress, in general
    • G01L1/12Measuring force or stress, in general by measuring variations in the magnetic properties of materials resulting from the application of stress
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/1368Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the present invention relates to a planar liquid crystal-gate-field effect transistor including a dipole control layer and a supersensitive tactile sensor using the same. More particularly, a polymer having a low dielectric constant is incorporated into a structure of a conventional liquid crystal-gate-field effect transistor. By significantly reducing the leakage of drain current through the channel layer at a gate voltage of zero, thereby providing a transistor and a dipole control layer that can simultaneously provide the function of a tactile sensor with significantly improved sensing sensitivity. It relates to a gate-field effect transistor and a supersensitive tactile sensor using the same.
  • the planar liquid crystal-gate-field effect transistor 1 ′ includes a substrate 10 ′, a gate electrode 20 ′ formed on the substrate 10 ′ at a predetermined interval, A source layer 30 'and a channel layer 50' electrically connecting the source electrode 30 'and the drain electrode 40' on the substrate 10 'and the channel layer ( 50 ') and the gate electrode 20' are formed to have a structure including a liquid crystal layer 60 'which functions as a gate insulating layer and a sensing function.
  • the conventional planar liquid crystal-gate-field effect transistor 1 'as described above has a drain current value through the channel layer 50' in a state where a voltage is applied to the gate electrode, and a voltage is applied to the gate electrode 20 '.
  • a voltage is applied to the gate electrode 20 '.
  • the physical stimulus is applied to the liquid crystal layer 60 'from the outside and the charge density of the channel layer 50' is increased due to the orientation change of the liquid crystal molecules M 'of the liquid crystal layer 60'.
  • It has a function as a sensor for detecting a physical stimulus applied to the liquid crystal layer 60 'from the outside by using a change amount of the drain current value through the channel layer 50'.
  • the above-described conventional planar liquid crystal-gate-field effect transistor 1 ' has a gate electrode (as shown in FIG. 2) due to the structure in which the liquid crystal layer 60' is in direct contact with the channel layer 50 '.
  • the liquid crystal molecules M 'of the liquid crystal layer 60' induce a charge generation in the channel layer 50 'even when no voltage is applied to the channel layer 50', thereby generating charges in the channel layer 50 '. Leakage of drain current occurs through layer 50 '.
  • the present invention has been made to solve the above problems, and an object of the present invention is to incorporate a low dielectric constant polymer material into the structure of an existing liquid crystal-gate-field effect transistor to provide a channel layer at a '0' gate voltage.
  • a liquid crystal-gate-field effect transistor including a dipole control layer which significantly reduces leakage of drain current through the same, and a tactile sensor using the same.
  • a gate electrode formed on the substrate and the substrate and a source electrode formed to be spaced apart from the gate electrode on the substrate and spaced apart from the source electrode on the substrate A drain layer formed on the drain electrode and the substrate to cover the source electrode and the drain electrode, and a channel layer electrically connecting the source electrode and the drain electrode, and connecting the gate electrode and the channel layer on the substrate. And a dipole control layer interposed between the liquid crystal layer and the channel layer to minimize charge generation in the channel layer by the liquid crystal layer.
  • a gate-field effect transistor is provided.
  • the dipole control layer may be a polymer material having a lower dielectric constant than the channel layer.
  • the dipole control layer is characterized in that it comprises poly methyl methacrylate (PMMA).
  • the channel layer may be any one of an organic semiconductor layer, an inorganic semiconductor layer, and an organic-inorganic mixed semiconductor layer.
  • liquid crystal layer may include liquid crystal molecules whose molecular orientation changes according to the voltage of the gate electrode.
  • liquid crystal layer is characterized in that it comprises nematic liquid crystal molecules.
  • the liquid crystal layer is characterized in that it has a function as a gate insulating layer for insulating between the channel layer and the gate electrode.
  • a protective wall formed on the channel layer and the gate electrode to surround at least a portion of the channel layer and the gate electrode, characterized in that the liquid crystal layer is formed inside the protective wall.
  • the protective wall is characterized in that it comprises a silicon film.
  • the apparatus may further include a protective layer covering the upper side opening of the protective wall.
  • the protective layer is characterized in that it comprises a stretched polypropylene film.
  • a tactile sensor using a liquid crystal-gate-field effect transistor comprising a dipole control layer of the substrate.
  • the transistor by incorporating a low dielectric constant polymer material into the structure of the conventional liquid crystal-gate-field effect transistor to significantly reduce the leakage of the drain current through the channel layer in the '0' gate voltage state, the transistor It is possible to simultaneously provide the function of the tactile sensor with significantly improved sensing and sensing sensitivity.
  • FIG. 1 schematically shows a conventional planar liquid crystal-gate-field effect transistor.
  • FIG. 2 illustrates a state in which charge generation of a channel layer is induced by liquid crystal molecules of a liquid crystal layer of a conventional planar liquid crystal-gate-field effect transistor.
  • FIG. 3 is a schematic diagram of a planar liquid crystal-gate-field effect transistor including a dipole control layer in accordance with an embodiment of the present invention.
  • 4A, 4B and 4C are schematic diagrams for explaining the operation of a planar liquid crystal-gate-field effect transistor including a dipole control layer according to an embodiment of the present invention.
  • FIG. 5 is a graph illustrating a change in drain current according to drain voltage according to the drain voltage of a planar liquid crystal-gate-field effect transistor including a dipole control layer according to an embodiment of the present invention for each gate voltage.
  • FIG. 6 is a graph showing changes in drain currents when a flow of nitrogen gas having different intensities is applied to a planar liquid crystal-gate-field effect transistor including a dipole control layer according to an embodiment of the present invention. to be.
  • FIG. 3 is a schematic diagram of a planar liquid crystal-gate-field effect transistor including a dipole control layer in accordance with an embodiment of the present invention.
  • a planar liquid crystal-gate-field effect transistor 1 including a dipole control layer includes a substrate 10, a gate electrode 20, a source electrode 30, and a drain electrode. 40, a channel layer 50, a liquid crystal layer 60, a dipole control layer 70, a protective wall 80, and a protective layer 90.
  • the substrate 10 may be a silicon substrate, a glass substrate, or a plastic substrate.
  • the gate electrode 20 is formed on the substrate 10, and for example, a conductive material such as gold (Au), silver (Ag), copper (Cu), nickel (Ni), aluminum (Al), a polymer, or sulfide It may be formed of a transparent electrode such as tungsten.
  • a conductive material such as gold (Au), silver (Ag), copper (Cu), nickel (Ni), aluminum (Al), a polymer, or sulfide It may be formed of a transparent electrode such as tungsten.
  • the source electrode 30 is formed on the substrate 10 so as to be spaced apart from the gate electrode 20, and for example, gold (Au), silver (Ag), copper (Cu), nickel (Ni), and aluminum (Al). , A conductive material such as a polymer, or a transparent electrode such as tungsten sulfide.
  • the drain electrode 40 is formed on the substrate 10 on the opposite side of the gate electrode 20 spaced apart from the source electrode 30, for example, gold (Au), silver (Ag), copper (Cu), and nickel. It may be formed of a conductive material such as (Ni), aluminum (Al), a polymer, or a transparent electrode such as tungsten sulfide.
  • the channel layer 50 is formed to cover the source electrode 30 and the drain electrode 40 on the substrate 10, and serves to electrically connect the source electrode 30 and the drain electrode 40.
  • the channel layer 50 may be any one of an organic semiconductor layer, an inorganic semiconductor layer, or an organic-inorganic mixed semiconductor layer. If the channel layer 50 is formed of an organic semiconductor layer that is well bent and flexible, it may be implemented as a flexible transistor.
  • the organic semiconductor layer may be, for example, poly-3-hexylthiophene (P3HT), pentacene, tetracene, tetratracene, anthracene, naphthalene, rubrene (rubrene), coronene (coronene), perylene (perylene), phthalocyanine (phthalocyanine) or derivatives thereof, and may be formed of one or more materials of conjugated polymer derivatives including thiophene.
  • P3HT poly-3-hexylthiophene
  • pentacene tetracene
  • tetratracene anthracene
  • naphthalene rubrene
  • coronene coronene
  • perylene perylene
  • phthalocyanine phthalocyanine
  • the liquid crystal layer 60 is formed on the substrate 10 to connect the gate electrode 20 and the channel layer 50, and functions as a gate insulating layer that insulates the gate electrode 20 from the channel layer 50. It also functions as a sensing function for sensing external physical stimuli.
  • the liquid crystal layer 60 includes liquid crystal molecules in the form of dipoles whose molecular orientation changes according to the voltage of the gate electrode 20, and the liquid crystal molecules are nematic liquid crystal molecules having a constant directionality. It may be formed as 4-cyano-4'pentylbiphenyl (4-cyano-4'pentylbiphenyl).
  • the dipole control layer 70 is a polymer material having a lower dielectric constant than the channel layer 50 and is interposed between the channel layer 50 and the liquid crystal layer 60 to prevent the channel layer from directly contacting the liquid crystal layer.
  • a '0' gate voltage state a state in which the voltage is not stable
  • the charge is induced in the channel layer 50 by the liquid crystal molecules of the liquid crystal layer 60 to minimize the generation of the charge in the channel layer 50. It acts as a poly methyl methacrylate (Poly methyl methacrylate, PMMA) can be formed.
  • the dipole control layer 70 as described above minimizes the generation of electric charge in the channel layer 50 by the liquid crystal molecules of the liquid crystal layer 60 in the '0' gate voltage state, and through the drain electrode in the '0' gate voltage state. By minimizing the occurrence of leakage current, it serves to stabilize the base drain current value of the '0' gate voltage state.
  • a voltage is applied to the gate electrode 20 to electrically polarize the dipole control layer 70, thereby stabilizing the drain current value in the state where charge is generated in the channel layer 50.
  • a physical stimulus is applied to the liquid crystal layer 60 to change the orientation of the liquid crystal molecules of the liquid crystal layer 60, the liquid crystal layer from the outside through an increase in the drain current value generated due to an increase in the charge density generated in the channel layer 50. Sensing sensitivity for sensing the physical stimulus applied to 60 is greatly improved.
  • the sensing sensitivity for sensing the physical stimulus applied to the liquid crystal layer 60 from the outside through the dipole control layer 70 is greatly improved, so that even a small vertical gas flow having a very low intensity can be sensed. It can be used as a super sensitive tactile sensor.
  • the passivation wall 80 is formed on the channel layer 50 and the gate electrode 20 to surround at least a portion of the channel layer 50 and the gate electrode 20 to accommodate the liquid crystal layer 60 therein. 60 is prevented from leaking to the outside, serves to adjust the thickness of the liquid crystal layer 60, a known silicon film may be used.
  • the protective layer 90 is installed to cover the upper side opening of the protective wall 80 to prevent the liquid crystal layer 60 from leaking to the outside and to provide a flat touch area for allowing the user to touch the liquid crystal layer 60.
  • oriented polypropylene film (OPP) can be used.
  • 4A, 4B and 4C are schematic diagrams for explaining the operation of a planar liquid crystal-gate-field effect transistor including a dipole control layer according to an embodiment of the present invention.
  • the planar liquid crystal-gate-field effect transistor 1 including the dipole control layer has liquid crystal molecules M of the liquid crystal layer 60 in the '0' gate voltage state. ) Have a structure that is randomly oriented.
  • the liquid crystal molecules M of the liquid crystal layer 60 are guided to the channel layer 50 through the dipole control layer 70 which prevents the channel layer 50 from directly contacting the liquid crystal layer 60.
  • the charge is minimized to minimize charge generation in the channel layer 50, thereby stabilizing the base drain current value at the '0' gate voltage state.
  • the liquid crystal molecules of the liquid crystal layer 60 are aligned in a structure in which the liquid crystal molecules of the liquid crystal layer 60 are constantly oriented in the direction of the source electrode 30 and the drain electrode 40.
  • the dipole control layer 70 is electrically polarized by the voltage applied to the gate electrode 20, charge is induced in the channel layer 50 to generate charge in the channel layer.
  • the base drain current value in the '0' gate voltage state is stabilized, so that the drain current value in the state where the voltage is applied to the gate electrode 20 is also stabilized.
  • the bipolar control layer is changed as the alignment structure of the liquid crystal molecules M of the liquid crystal layer 60 is changed. 70 is more electrically polarized.
  • channel layer 50 is more electrically polarized, more charge is induced in the channel layer 50, thereby increasing the charge density in the channel layer 50, thereby increasing the drain current value.
  • the present invention senses the physical stimulus applied to the liquid crystal layer from the outside by using an increase in the drain current value according to the increase in the charge density induced in the channel layer 50.
  • the drain current value in the voltage applied state is stabilized, and thus, due to the physical stimulus acting on the liquid crystal layer from the outside.
  • Sensing sensitivity is greatly improved by accurately measuring the increase in the generated drain current value, and thus it can be used as an ultra-sensitive tactile sensor that can sense even a small vertical gas flow having a very low intensity.
  • FIG. 5 is a graph illustrating a change in drain current according to drain voltage according to the drain voltage of a planar liquid crystal-gate-field effect transistor including a dipole control layer according to an embodiment of the present invention for each gate voltage.
  • the drain current I D increases rapidly as the drain voltage V D increases. As the gate voltage V G increases, the drain current I D increases.
  • FIG. 6 is a graph illustrating a change in drain current when a flow of nitrogen gas having different intensities is applied to a planar liquid crystal-gate-field effect transistor including a dipole control layer according to an embodiment of the present invention.
  • the experiment was performed for each nitrogen gas having an intensity corresponding to 0.5sccm, 1.0sccm, 2.0sccm, 4.0sccm, where unit sccm is the unit of flow rate Standard Cubic centimeter per minutes (cm 3 / min ).
  • the planar liquid crystal-gate-field effect transistor 1 including the dipole control layer according to an embodiment of the present invention has a 20s band in which vertical flow of nitrogen gas having different intensities acts on the liquid crystal layer. It can be seen that the peak value of the drain current value I D occurs at.
  • the present invention can be seen that the sensing sensitivity is high irrespective of the strength of the gas acting on the liquid crystal layer, and due to this high sensing sensitivity can be used as an ultra-sensitive tactile sensor that can sense even a small vertical gas flow with a very low intensity It can be seen that.

Abstract

The present invention relates to a liquid crystal-gate-field effect transistor comprising a dipole control layer and a tactile sensor using the same, and comprises: a substrate; a gate electrode formed on the substrate; a source electrode formed on the substrate to be spaced from the gate electrode; a drain electrode formed on the substrate to be spaced from the source electrode; a channel layer formed on the substrate so as to cover the source electrode and the drain electrode, the channel layer electrically connecting the source electrode and the drain electrode; a liquid crystal layer formed on the substrate so as to connect the gate electrode and the channel layer; and a dipole control layer interposed between the liquid crystal layer and the channel layer so as to minimize induction of generation of electric charges in the channel layer by the liquid crystal layer. The present invention, as described above, combines a conventional liquid crystal-gate-field effect transistor structure with a polymer material having a low permittivity such that leakage of drain current through the channel layer, in zero gate voltage state, is substantially reduced, thereby both providing the function of a transistor and providing the function of a tactile sensor having a substantially improved sensing sensitivity.

Description

쌍극자 제어층을 포함한 평면 액정-게이트-전계효과 트랜지스터 및 이를 이용한 초감도 촉각센서Planar Liquid Crystal-Gate-Field Effect Transistor with Dipole Control Layer and Supersensitive Tactile Sensor Using the Same
본 발명은 쌍극자 제어층을 포함한 평면 액정-게이트-전계효과 트랜지스터 및 이를 이용한 초감도 촉각센서에 관한 것으로서, 보다 상세하게는 기존의 액정-게이트-전계효과 트랜지스터의 구조에 유전율이 낮은 고분자 물질을 접목하여 '0'게이트 전압상태에서 채널층을 통한 드레인 전류의 누설을 현저하게 감소시킴으로써, 트랜지스터의 기능과 센싱 감도가 현저하게 향상된 촉각센서의 기능을 동시에 제공할 수 있는 쌍극자 제어층을 포함한 평면 액정-게이트-전계효과 트랜지스터 및 이를 이용한 초감도 촉각센서에 관한 것이다.The present invention relates to a planar liquid crystal-gate-field effect transistor including a dipole control layer and a supersensitive tactile sensor using the same. More particularly, a polymer having a low dielectric constant is incorporated into a structure of a conventional liquid crystal-gate-field effect transistor. By significantly reducing the leakage of drain current through the channel layer at a gate voltage of zero, thereby providing a transistor and a dipole control layer that can simultaneously provide the function of a tactile sensor with significantly improved sensing sensitivity. It relates to a gate-field effect transistor and a supersensitive tactile sensor using the same.
일반적으로 평면 액정-게이트-전계효과 트랜지스터(1')는 도 1에 도시된 바와 같이, 기판(10')과, 기판(10') 상에 일정 간격 이격되게 형성되는 게이트 전극(20'), 소스 전극(30') 및 드레인 전극(40')과, 기판(10') 상에 소스 전극(30')과 드레인 전극(40')을 전기적으로 연결하는 채널층(50'), 채널층(50')과 게이트 전극(20')을 연결하도록 형성되어 게이트 절연층의 기능과 센싱 기능을 겸하는 액정층(60')을 포함하는 구조로 형성된다.In general, as shown in FIG. 1, the planar liquid crystal-gate-field effect transistor 1 ′ includes a substrate 10 ′, a gate electrode 20 ′ formed on the substrate 10 ′ at a predetermined interval, A source layer 30 'and a channel layer 50' electrically connecting the source electrode 30 'and the drain electrode 40' on the substrate 10 'and the channel layer ( 50 ') and the gate electrode 20' are formed to have a structure including a liquid crystal layer 60 'which functions as a gate insulating layer and a sensing function.
위와 같은 종래의 평면 액정-게이트-전계효과 트랜지스터(1')는 게이트 전극에 전압이 인가된 상태에서의 채널층(50')을 통한 드레인 전류값과, 게이트 전극(20')에 전압이 인가된 상태에서 외부로부터 액정층(60')에 물리적인 자극이 인가되어 액정층(60')의 액정분자(M')의 배향변화로 인해 채널층(50')의 전하밀도가 증가된 상태에서 채널층(50')을 통한 드레인 전류값의 변화량을 이용하여 외부로부터 액정층(60')에 인가되는 물리적인 자극을 감지하는 센서로서의 기능을 가진다.The conventional planar liquid crystal-gate-field effect transistor 1 'as described above has a drain current value through the channel layer 50' in a state where a voltage is applied to the gate electrode, and a voltage is applied to the gate electrode 20 '. In the state in which the physical stimulus is applied to the liquid crystal layer 60 'from the outside and the charge density of the channel layer 50' is increased due to the orientation change of the liquid crystal molecules M 'of the liquid crystal layer 60'. It has a function as a sensor for detecting a physical stimulus applied to the liquid crystal layer 60 'from the outside by using a change amount of the drain current value through the channel layer 50'.
그러나, 전술한 종래의 평면 액정-게이트-전계효과 트랜지스터(1')는 액정층(60')이 채널층(50')에 직접 접촉되는 구조로 인해 도 2에 도시된 바와 같이, 게이트 전극(20')에 전압이 인가되지 않은 상태에서도 액정층(60')의 액정분자(M')가 채널층(50')의 전하 생성을 유도하여 채널층(50')에 전하가 생성됨으로 인해 채널층(50')을 통해 드레인 전류의 누설이 발생하게 된다.However, the above-described conventional planar liquid crystal-gate-field effect transistor 1 'has a gate electrode (as shown in FIG. 2) due to the structure in which the liquid crystal layer 60' is in direct contact with the channel layer 50 '. The liquid crystal molecules M 'of the liquid crystal layer 60' induce a charge generation in the channel layer 50 'even when no voltage is applied to the channel layer 50', thereby generating charges in the channel layer 50 '. Leakage of drain current occurs through layer 50 '.
이로 인해 게이트 전극(20')에 전압이 인가되지 않은 상태의 베이스 드레인 전류값이 안정화되지 않아 액정층(60')에 인가되는 외부의 물리적인 자극을 드레인 전류값의 변화량을 이용하여 감지하는 경우, 이를 센싱하는 감도가 저하되는 문제점이 발생하게 된다.As a result, when the base drain current value in a state where no voltage is applied to the gate electrode 20 'is not stabilized, an external physical stimulus applied to the liquid crystal layer 60' is sensed using a change amount of the drain current value. In this case, there is a problem in that the sensitivity for sensing this is reduced.
본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로서, 본 발명의 목적은 기존의 액정-게이트-전계효과 트랜지스터의 구조에 유전율이 낮은 고분자 물질을 접목하여 '0'게이트 전압 상태에서 채널층을 통한 드레인 전류의 누설을 현저하게 감소시킨 쌍극자 제어층을 포함한 액정-게이트-전계효과 트랜지스터 및 이를 이용한 촉각센서를 제공함에 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to incorporate a low dielectric constant polymer material into the structure of an existing liquid crystal-gate-field effect transistor to provide a channel layer at a '0' gate voltage. Disclosed is a liquid crystal-gate-field effect transistor including a dipole control layer which significantly reduces leakage of drain current through the same, and a tactile sensor using the same.
상기 목적을 달성하기 위한 본 발명의 일측면에 따르면, 기판 및 상기 기판 상에 형성되는 게이트 전극 및 상기 기판 상에 상기 게이트 전극과 이격되게 형성되는 소스 전극 및 상기 기판 상에 상기 소스 전극과 이격되게 형성되는 드레인 전극 및 상기 기판 상에 상기 소스 전극 및 상기 드레인 전극을 덮도록 형성되고, 상기 소스 전극과 상기 드레인 전극을 전기적으로 연결하는 채널층 및 상기 기판 상에 상기 게이트 전극과 상기 채널층을 연결하도록 형성되는 액정층 및 상기 액정층과 상기 채널층 간에 개재되어 상기 액정층에 의해 상기 채널층에 전하 생성이 유도되는 것을 최소화하는 쌍극자 제어층을 포함하는 것을 특징으로 하는 쌍극자 제어층을 포함한 평면 액정-게이트-전계효과 트랜지스터가 제공된다.According to an aspect of the present invention for achieving the above object, a gate electrode formed on the substrate and the substrate and a source electrode formed to be spaced apart from the gate electrode on the substrate and spaced apart from the source electrode on the substrate A drain layer formed on the drain electrode and the substrate to cover the source electrode and the drain electrode, and a channel layer electrically connecting the source electrode and the drain electrode, and connecting the gate electrode and the channel layer on the substrate. And a dipole control layer interposed between the liquid crystal layer and the channel layer to minimize charge generation in the channel layer by the liquid crystal layer. A gate-field effect transistor is provided.
또한, 상기 쌍극자 제어층은 상기 채널층보다 유전율이 낮은 고분자 물질인 것을 특징으로 한다.The dipole control layer may be a polymer material having a lower dielectric constant than the channel layer.
또한, 상기 쌍극자 제어층은 폴리 메틸 메타크릴레이트(PMMA)를 포함하는 것을 특징으로 한다.In addition, the dipole control layer is characterized in that it comprises poly methyl methacrylate (PMMA).
또한, 상기 채널층은 유기 반도체층, 무기 반도체층 또는 유무기 혼합 반도체층 중 어느 하나인 것을 특징으로 한다.The channel layer may be any one of an organic semiconductor layer, an inorganic semiconductor layer, and an organic-inorganic mixed semiconductor layer.
또한, 상기 액정층은 상기 게이트 전극의 전압에 따라 분자 배향이 변화되는 액정 분자들을 포함하는 것을 특징으로 한다.In addition, the liquid crystal layer may include liquid crystal molecules whose molecular orientation changes according to the voltage of the gate electrode.
또한, 상기 액정층은 네마틱 액정 분자들을 포함하는 것을 특징으로 한다.In addition, the liquid crystal layer is characterized in that it comprises nematic liquid crystal molecules.
또한, 상기 액정층은 상기 채널층과 상기 게이트 전극 간을 절연하는 게이트 절연층으로서의 기능을 갖는 것을 특징으로 한다.The liquid crystal layer is characterized in that it has a function as a gate insulating layer for insulating between the channel layer and the gate electrode.
또한, 상기 채널층 및 상기 게이트 전극 상에 상기 채널층과 상기 게이트 전극의 적어도 일부를 둘러싸도록 형성되는 보호벽을 포함하고, 상기 액정층은 상기 보호벽의 내측에 형성되는 것을 특징으로 한다.In addition, a protective wall formed on the channel layer and the gate electrode to surround at least a portion of the channel layer and the gate electrode, characterized in that the liquid crystal layer is formed inside the protective wall.
또한, 상기 보호벽은 실리콘 필름을 포함하는 것을 특징으로 한다.In addition, the protective wall is characterized in that it comprises a silicon film.
또한, 상기 보호벽의 상부 측 개방부를 덮는 보호층을 더 포함하는 것을 특징으로 한다.The apparatus may further include a protective layer covering the upper side opening of the protective wall.
또한, 상기 보호층은 연신 폴리프로필렌 필름을 포함하는 것을 특징으로 한다.In addition, the protective layer is characterized in that it comprises a stretched polypropylene film.
상기 목적을 달성하기 위한 본 발명의 다른 측면에 따르면, 상기 기재의 쌍극자 제어층을 포함한 액정-게이트-전계효과 트랜지스터를 이용한 촉각센서가 제공된다.According to another aspect of the present invention for achieving the above object, there is provided a tactile sensor using a liquid crystal-gate-field effect transistor comprising a dipole control layer of the substrate.
상기와 같은 본 발명에 의하면, 기존의 액정-게이트-전계효과 트랜지스터의 구조에 유전율이 낮은 고분자 물질을 접목하여 '0'게이트 전압 상태에서 채널층을 통한 드레인 전류의 누설을 현저하게 감소시킴으로써, 트랜지스터의 기능과 센싱 감도가 현저하게 향상된 촉각센서의 기능을 동시에 제공할 수 있게 된다.According to the present invention as described above, by incorporating a low dielectric constant polymer material into the structure of the conventional liquid crystal-gate-field effect transistor to significantly reduce the leakage of the drain current through the channel layer in the '0' gate voltage state, the transistor It is possible to simultaneously provide the function of the tactile sensor with significantly improved sensing and sensing sensitivity.
도 1은 종래 평면 액정-게이트-전계효과 트랜지스터를 개략적으로 도시한 것이다.1 schematically shows a conventional planar liquid crystal-gate-field effect transistor.
도 2는 종래 평면 액정-게이트-전계효과 트랜지스터의 액정층의 액정분자에 의해 채널층의 전하 생성이 유도되는 상태를 도시한 것이다.2 illustrates a state in which charge generation of a channel layer is induced by liquid crystal molecules of a liquid crystal layer of a conventional planar liquid crystal-gate-field effect transistor.
도 3은 본 발명의 일실시예에 따른 쌍극자 제어층을 포함한 평면 액정-게이트-전계효과 트랜지스터의 개략도이다.3 is a schematic diagram of a planar liquid crystal-gate-field effect transistor including a dipole control layer in accordance with an embodiment of the present invention.
도 4a, 도 4b 및 4c는 본 발명의 일실시예에 따른 쌍극자 제어층을 포함한 평면 액정-게이트-전계효과 트랜지스터의 동작을 설명하기 위한 개략도이다.4A, 4B and 4C are schematic diagrams for explaining the operation of a planar liquid crystal-gate-field effect transistor including a dipole control layer according to an embodiment of the present invention.
도 5는 본 발명의 일실시예에 따른 쌍극자 제어층을 포함한 평면 액정-게이트-전계효과 트랜지스터의 드레인 전압에 따른 드레인 전압에 따른 드레인 전류의 변화를 게이트 전압별로 보여주는 그래프이다.FIG. 5 is a graph illustrating a change in drain current according to drain voltage according to the drain voltage of a planar liquid crystal-gate-field effect transistor including a dipole control layer according to an embodiment of the present invention for each gate voltage.
도 6은 본 발명의 일실시예에 따른 쌍극자 제어층을 포함한 평면 액정-게이트-전계효과 트랜지스터에 강도(intensity)가 다른 각각의 질소 기체의 흐름이 작용할 때 각각의 드레인 전류의 변화를 도시한 그래프이다.FIG. 6 is a graph showing changes in drain currents when a flow of nitrogen gas having different intensities is applied to a planar liquid crystal-gate-field effect transistor including a dipole control layer according to an embodiment of the present invention. to be.
이하에서는 도면을 참조하여 본 발명을 보다 상세하게 설명한다. 도면들 중 동일한 구성요소들은 가능한 어느 곳에서든지 동일한 부호들로 나타내고 있음에 유의해야 한다. 또한 발명의 요지를 불필요하게 흐릴 수 있는 공지기능 및 구성에 대한 상세한 설명은 생략한다.Hereinafter, with reference to the drawings will be described the present invention in more detail. It should be noted that like elements in the figures are denoted by the same numerals wherever possible. In addition, detailed descriptions of well-known functions and configurations that may unnecessarily obscure the subject matter of the present invention will be omitted.
도 3은 본 발명의 일실시예에 따른 쌍극자 제어층을 포함한 평면 액정-게이트-전계효과 트랜지스터의 개략도이다.3 is a schematic diagram of a planar liquid crystal-gate-field effect transistor including a dipole control layer in accordance with an embodiment of the present invention.
도 3을 참조하면, 본 발명의 일실시예에 따른 쌍극자 제어층을 포함한 평면 액정-게이트-전계효과 트랜지스터(1)는 기판(10), 게이트 전극(20), 소스 전극(30), 드레인 전극(40), 채널층(50), 액정층(60), 쌍극자 제어층(70), 보호벽(80) 및 보호층(90)을 포함한다.Referring to FIG. 3, a planar liquid crystal-gate-field effect transistor 1 including a dipole control layer according to an embodiment of the present invention includes a substrate 10, a gate electrode 20, a source electrode 30, and a drain electrode. 40, a channel layer 50, a liquid crystal layer 60, a dipole control layer 70, a protective wall 80, and a protective layer 90.
기판(10)은 실리콘(silicon) 기판, 유리 기판 또는 플라스틱 기판이 사용될 수 있다.The substrate 10 may be a silicon substrate, a glass substrate, or a plastic substrate.
게이트 전극(20)은 기판(10) 상에 형성되고, 예시적으로 금(Au), 은(Ag), 구리(Cu), 니켈(Ni), 알루미늄(Al), 폴리머 등의 도전성 물질 또는 황화 텅스텐과 같은 투명 전극 등으로 형성될 수 있다.The gate electrode 20 is formed on the substrate 10, and for example, a conductive material such as gold (Au), silver (Ag), copper (Cu), nickel (Ni), aluminum (Al), a polymer, or sulfide It may be formed of a transparent electrode such as tungsten.
소스 전극(30)은 기판(10) 상에 게이트 전극(20)과 이격되게 형성되고, 예시적으로 금(Au), 은(Ag), 구리(Cu), 니켈(Ni), 알루미늄(Al), 폴리머 등의 도전성 물질 또는 황화 텅스텐과 같은 투명 전극 등으로 형성될 수 있다.The source electrode 30 is formed on the substrate 10 so as to be spaced apart from the gate electrode 20, and for example, gold (Au), silver (Ag), copper (Cu), nickel (Ni), and aluminum (Al). , A conductive material such as a polymer, or a transparent electrode such as tungsten sulfide.
드레인 전극(40)은 기판(10) 상에 소스 전극(30)과 이격된 게이트 전극(20)의 반대측에 형성되고, 예시적으로 금(Au), 은(Ag), 구리(Cu), 니켈(Ni), 알루미늄(Al), 폴리머 등의 도전성 물질 또는 황화 텅스텐과 같은 투명 전극 등으로 형성될 수 있다.The drain electrode 40 is formed on the substrate 10 on the opposite side of the gate electrode 20 spaced apart from the source electrode 30, for example, gold (Au), silver (Ag), copper (Cu), and nickel. It may be formed of a conductive material such as (Ni), aluminum (Al), a polymer, or a transparent electrode such as tungsten sulfide.
채널층(50)은 기판(10) 상에 소스 전극(30) 및 드레인 전극(40)을 덮도록 형성되고, 소스 전극(30)과 드레인 전극(40)을 전기적으로 연결하는 역할을 한다.The channel layer 50 is formed to cover the source electrode 30 and the drain electrode 40 on the substrate 10, and serves to electrically connect the source electrode 30 and the drain electrode 40.
이러한 채널층(50)은 유기 반도체층, 무기 반도체층 또는 유무기 혼합 반도체층 중 어느 하나가 사용될 수 있으며, 잘 구부러지고 유연성을 갖는 유기 반도체층으로 형성하게 되면 유연 트랜지스터로 구현할 수 있다.The channel layer 50 may be any one of an organic semiconductor layer, an inorganic semiconductor layer, or an organic-inorganic mixed semiconductor layer. If the channel layer 50 is formed of an organic semiconductor layer that is well bent and flexible, it may be implemented as a flexible transistor.
여기서, 유기 반도체층은 예시적으로 폴리-3-헥실티오핀(poly-3-hexylthiophene, P3HT), 펜타센(pentacene), 테트라센(tetracene), 안트라센(anthracene), 나프탈렌(naphthalene), 루브렌(rubrene), 코로넨(coronene), 페릴렌(perylene), 프탈로시아닌(phthalocyanine) 혹은 이들의 유도체, 티오펜(thiophene)을 포함하는 공액계 고분자 유도체 중 하나 이상의 물질로 형성될 수 있다.The organic semiconductor layer may be, for example, poly-3-hexylthiophene (P3HT), pentacene, tetracene, tetratracene, anthracene, naphthalene, rubrene (rubrene), coronene (coronene), perylene (perylene), phthalocyanine (phthalocyanine) or derivatives thereof, and may be formed of one or more materials of conjugated polymer derivatives including thiophene.
액정층(60)은 기판(10) 상에 게이트 전극(20)과 채널층(50)을 연결하도록 형성되고, 게이트 전극(20)과 채널층(50) 간을 절연하는 게이트 절연층으로서의 기능과 외부의 물리적인 자극을 센싱하는 센싱 기능을 겸한다.The liquid crystal layer 60 is formed on the substrate 10 to connect the gate electrode 20 and the channel layer 50, and functions as a gate insulating layer that insulates the gate electrode 20 from the channel layer 50. It also functions as a sensing function for sensing external physical stimuli.
이러한 액정층(60)은 게이트 전극(20)의 전압에 따라 분자 배향이 변화되는 쌍극자 형태의 액정분자들을 포함하고, 이러한 액정분자들은 일정한 방향성을 가지는 네마틱 액정분자인 것을 특징으로 하며, 예시적으로 4-시아노-4'펜틸바이페닐(4-cyano-4'pentylbiphenyl) 로 형성될 수 있다.The liquid crystal layer 60 includes liquid crystal molecules in the form of dipoles whose molecular orientation changes according to the voltage of the gate electrode 20, and the liquid crystal molecules are nematic liquid crystal molecules having a constant directionality. It may be formed as 4-cyano-4'pentylbiphenyl (4-cyano-4'pentylbiphenyl).
쌍극자 제어층(70)은 채널층(50)보다 유전율이 낮은 고분자 물질로서 채널층(50)과 액정층(60) 간에 개재되어 채널층이 액정층에 직접적으로 접촉되는 것을 방지함으로써, 게이트 전극에 전압이 안가되지 않는 상태(이하, '0' 게이트 전압 상태)에서 액정층(60)의 액정분자에 의해 채널층(50)에 전하가 유도되어 채널층(50)에 전하가 생성되는 것을 최소화하는 역할을 하며, 폴리 메틸 메타크릴레이트(Poly methyl methacrylate, PMMA)로 형성될 수 있다.The dipole control layer 70 is a polymer material having a lower dielectric constant than the channel layer 50 and is interposed between the channel layer 50 and the liquid crystal layer 60 to prevent the channel layer from directly contacting the liquid crystal layer. In a state in which the voltage is not stable (hereinafter, referred to as a '0' gate voltage state), the charge is induced in the channel layer 50 by the liquid crystal molecules of the liquid crystal layer 60 to minimize the generation of the charge in the channel layer 50. It acts as a poly methyl methacrylate (Poly methyl methacrylate, PMMA) can be formed.
위와 같은 쌍극자 제어층(70)은 '0' 게이트 전압 상태에서 액정층(60)의 액정분자에 의해 채널층(50)에 전하가 생성되는 것을 최소화하여 '0' 게이트 전압 상태에서 드레인 전극을 통해 누설전류가 발생되는 것을 최소화함으로써, '0' 게이트 전압 상태의 베이스 드레인 전류값을 안정화시키는 역할을 한다.The dipole control layer 70 as described above minimizes the generation of electric charge in the channel layer 50 by the liquid crystal molecules of the liquid crystal layer 60 in the '0' gate voltage state, and through the drain electrode in the '0' gate voltage state. By minimizing the occurrence of leakage current, it serves to stabilize the base drain current value of the '0' gate voltage state.
이로 인해 게이트 전극(20)에 전압이 인가되어 쌍극자 제어층(70)이 전기적으로 분극됨에 따라 채널층(50)에 전하가 생성된 상태의 드레인 전류값이 안정화되고, 이에 따라 외부로부터 액정층(60)에 물리적인 자극이 인가되어 액정층(60)의 액정분자의 배향이 변화됨에 따라 채널층(50)에 생성되는 전하 밀도의 증가로 인해 발생되는 드레인 전류값의 증가분을 통해 외부로부터 액정층(60)에 인가되는 물리적인 자극을 센싱하는 센싱 감도가 크게 향상된다.As a result, a voltage is applied to the gate electrode 20 to electrically polarize the dipole control layer 70, thereby stabilizing the drain current value in the state where charge is generated in the channel layer 50. As a physical stimulus is applied to the liquid crystal layer 60 to change the orientation of the liquid crystal molecules of the liquid crystal layer 60, the liquid crystal layer from the outside through an increase in the drain current value generated due to an increase in the charge density generated in the channel layer 50. Sensing sensitivity for sensing the physical stimulus applied to 60 is greatly improved.
위와 같이, 본 발명은 쌍극자 제어층(70)을 통해 외부로부터 액정층(60)에 인가되는 물리적인 자극을 센싱하는 센싱 감도가 크게 향상됨에 따라 강도가 매우 낮은 미세한 수직 기체흐름 까지도 센싱할 수 있는 초감도 촉각센서로 사용할 수 있게 된다.As described above, according to the present invention, the sensing sensitivity for sensing the physical stimulus applied to the liquid crystal layer 60 from the outside through the dipole control layer 70 is greatly improved, so that even a small vertical gas flow having a very low intensity can be sensed. It can be used as a super sensitive tactile sensor.
보호벽(80)은 내측에 액정층(60)이 수용되도록 채널층(50) 및 게이트 전극(20) 상에 채널층(50)과 게이트 전극(20)의 적어도 일부를 둘러싸도록 형성되어 액정층(60)이 외부로 누출되는 것을 방지하고, 액정층(60)의 두께를 조절하는 역할을 하며, 공지의 실리콘 필름이 사용될 수 있다.The passivation wall 80 is formed on the channel layer 50 and the gate electrode 20 to surround at least a portion of the channel layer 50 and the gate electrode 20 to accommodate the liquid crystal layer 60 therein. 60 is prevented from leaking to the outside, serves to adjust the thickness of the liquid crystal layer 60, a known silicon film may be used.
보호층(90)은 보호벽(80)의 상부 측 개방부를 덮도록 설치되어 액정층(60)이 외부로 누출되는 것을 방지함과 아울러 사용자가 액정층(60)을 터치할 수 있는 평탄한 터치 영역을 제공하며, 연신 폴리프로필렌 필름(oriented polypropylene, OPP)가 사용될 수 있다.The protective layer 90 is installed to cover the upper side opening of the protective wall 80 to prevent the liquid crystal layer 60 from leaking to the outside and to provide a flat touch area for allowing the user to touch the liquid crystal layer 60. And oriented polypropylene film (OPP) can be used.
도 4a, 도 4b 및 도 4c는 본 발명의 일실시예에 따른 쌍극자 제어층을 포함한 평면 액정-게이트-전계효과 트랜지스터의 동작을 설명하기 위한 개략도이다.4A, 4B and 4C are schematic diagrams for explaining the operation of a planar liquid crystal-gate-field effect transistor including a dipole control layer according to an embodiment of the present invention.
본 발명의 일실시예에 따른 쌍극자 제어층을 포함한 평면 액정-게이트-전계효과 트랜지스터(1)는 도 4a에 도시된 바와 같이, '0'게이트 전압 상태에서는 액정층(60)의 액정분자(M)들이 무작위작으로 배향되는 구조를 가진다.As shown in FIG. 4A, the planar liquid crystal-gate-field effect transistor 1 including the dipole control layer according to an exemplary embodiment of the present invention has liquid crystal molecules M of the liquid crystal layer 60 in the '0' gate voltage state. ) Have a structure that is randomly oriented.
그리고, 채널층(50)과 액정층(60)이 직접적으로 접촉되는 것을 방지하는 쌍극자 제어층(70)을 통해 액정층(60)의 액정분자(M)에 의해 채널층(50)에 유도되는 전하가 최소화되어 채널층(50)의 전하 생성이 최소화되며, 이에 따라 '0'게이트 전압 상태에서의 베이스 드레인 전류값이 안정화된다.The liquid crystal molecules M of the liquid crystal layer 60 are guided to the channel layer 50 through the dipole control layer 70 which prevents the channel layer 50 from directly contacting the liquid crystal layer 60. The charge is minimized to minimize charge generation in the channel layer 50, thereby stabilizing the base drain current value at the '0' gate voltage state.
도 4b에 도시된 바와 같이, 게이트 전극(20)에 전압이 인가된 상태에서는 액정층(60)의 액정분자들이 소스 전극(30) 및 드레인 전극(40) 방향으로 일정하게 배향되는 구조로 정렬되며, 게이트 전극(20)에 인가되는 전압에 의해 쌍극자 제어층(70)이 전기적으로 분극됨에 따라 채널층(50) 내부에 전하가 유도되어 채널층 내부에 전하가 생성된다.As shown in FIG. 4B, when a voltage is applied to the gate electrode 20, the liquid crystal molecules of the liquid crystal layer 60 are aligned in a structure in which the liquid crystal molecules of the liquid crystal layer 60 are constantly oriented in the direction of the source electrode 30 and the drain electrode 40. As the dipole control layer 70 is electrically polarized by the voltage applied to the gate electrode 20, charge is induced in the channel layer 50 to generate charge in the channel layer.
본 발명은 앞서 설명된 바와 같이, '0'게이트 전압 상태에서의 베이스 드레인 전류값이 안정화됨으로써, 게이트 전극(20)에 전압이 인가된 상태에서의 드레인 전류값도 안정화되게 된다.As described above, the base drain current value in the '0' gate voltage state is stabilized, so that the drain current value in the state where the voltage is applied to the gate electrode 20 is also stabilized.
도 4c에 도시된 바와 같이, 도 4b의 상태에서 외부로부터 액정층(60)에 물리적인 자극이 인가되면, 액정층(60)의 액정분자(M)들의 배향 구조가 변화됨에 따라 쌍극제 제어층(70)이 전기적으로 보다 많이 분극된다.As shown in FIG. 4C, when a physical stimulus is applied to the liquid crystal layer 60 from the outside in the state of FIG. 4B, the bipolar control layer is changed as the alignment structure of the liquid crystal molecules M of the liquid crystal layer 60 is changed. 70 is more electrically polarized.
그리고, 채널층(50)이 전기적으로 보다 많이 분극됨에 따라 채널층(50) 내부에 더 많은 전하가 유도되어 채널층(50) 내부의 전하 밀도가 증가하며, 이로 인해 드레인 전류값이 증가하게 된다.In addition, as the channel layer 50 is more electrically polarized, more charge is induced in the channel layer 50, thereby increasing the charge density in the channel layer 50, thereby increasing the drain current value. .
이 때, 본 발명은 채널층(50) 내부에 유도되는 전하 밀도의 증가에 따른 드레인 전류값의 증가분을 이용하여 외부로부터 액정층에 인가되는 물리적인 자극을 센싱하게 된다.At this time, the present invention senses the physical stimulus applied to the liquid crystal layer from the outside by using an increase in the drain current value according to the increase in the charge density induced in the channel layer 50.
상기와 같은 본 발명은 '0'게이트 전압 상태에서의 베이스 드레인 전류값이 안정화됨에 따라 전압이 인가된 상태에서의 드레인 전류값이 안정화되고, 이에 따라 외부로부터 액정층에 작용하는 물리적인 자극으로 인해 발생되는 드레인 전류값의 증가분을 정확하게 측정할 수 있어 센싱 감도가 크게 향상되며, 이로 인해 강도가 매우 낮은 미세한 수직 기체흐름 까지도 센싱할 수 있는 초감도 촉각센서로 사용할 수 있게 된다.As described above, according to the present invention, as the base drain current value in the '0' gate voltage state is stabilized, the drain current value in the voltage applied state is stabilized, and thus, due to the physical stimulus acting on the liquid crystal layer from the outside. Sensing sensitivity is greatly improved by accurately measuring the increase in the generated drain current value, and thus it can be used as an ultra-sensitive tactile sensor that can sense even a small vertical gas flow having a very low intensity.
도 5는 본 발명의 일실시예에 따른 쌍극자 제어층을 포함한 평면 액정-게이트-전계효과 트랜지스터의 드레인 전압에 따른 드레인 전압에 따른 드레인 전류의 변화를 게이트 전압별로 보여주는 그래프이다.FIG. 5 is a graph illustrating a change in drain current according to drain voltage according to the drain voltage of a planar liquid crystal-gate-field effect transistor including a dipole control layer according to an embodiment of the present invention for each gate voltage.
본 발명의 일실시예에 따른 쌍극자 제어층을 포함한 평면 액정-게이트-전계효과 트랜지스터는 도 5에 도시된 바와 같이, 드레인 전압(VD)이 증가함에 따라 드레인 전류(ID)가 급격하게 증가하고, 게이트 전압(VG)이 증가함에 따라 드레인 전류(ID)가 증가하는 트랜지스터의 특성을 갖는 것을 알 수 있다.In the planar liquid crystal-gate-field effect transistor including the dipole control layer according to an exemplary embodiment of the present invention, as shown in FIG. 5, the drain current I D increases rapidly as the drain voltage V D increases. As the gate voltage V G increases, the drain current I D increases.
도 6은 본 발명의 일실시예에 따른 쌍극자 제어층을 포함한 평면 액정-게이트-전계효과 트랜지스터에 강도(intensity)가 다른 각각의 질소 기체의 흐름이 작용할때 드레인 전류의 변화를 도시한 그래프이다.FIG. 6 is a graph illustrating a change in drain current when a flow of nitrogen gas having different intensities is applied to a planar liquid crystal-gate-field effect transistor including a dipole control layer according to an embodiment of the present invention.
본 실시예에서는 0.5sccm, 1.0sccm, 2.0sccm, 4.0sccm에 해당하는 강도를 가지는 각각의 질소 기체에 대해 실험을 실시하였으며, 여기서 단위 sccm은 유량의 단위로 Standard Cubic centimeter per minutes(cm3/min)을 의미한다.In this embodiment, the experiment was performed for each nitrogen gas having an intensity corresponding to 0.5sccm, 1.0sccm, 2.0sccm, 4.0sccm, where unit sccm is the unit of flow rate Standard Cubic centimeter per minutes (cm 3 / min ).
본 발명의 일실시예에 따른 쌍극자 제어층을 포함한 평면 액정-게이트-전계효과 트랜지스터(1)는 도 6에 도시된 바와 같이, 각각 강도가 다른 질소 기체의 수직 흐름이 액정층에 작용하는 20s 대에서 드레인 전류값(ID)의 피크치가 발생되는 것을 알 수 있다.As shown in FIG. 6, the planar liquid crystal-gate-field effect transistor 1 including the dipole control layer according to an embodiment of the present invention has a 20s band in which vertical flow of nitrogen gas having different intensities acts on the liquid crystal layer. It can be seen that the peak value of the drain current value I D occurs at.
이에 따라, 본 발명은 액정층에 작용하는 기체의 강도에 관계없이 센싱 감도가 높은 것을 알수 있으며, 이러한 높은 센싱 감도로 인해 강도가 매우 낮은 미세한 수직 기체흐름 까지도 센싱할 수 있는 초감도 촉각센서로 사용할 수 있음을 알수 있다.Accordingly, the present invention can be seen that the sensing sensitivity is high irrespective of the strength of the gas acting on the liquid crystal layer, and due to this high sensing sensitivity can be used as an ultra-sensitive tactile sensor that can sense even a small vertical gas flow with a very low intensity It can be seen that.
비록 본 발명이 상기 바람직한 실시 예들과 관련하여 설명되어졌지만, 발명의 요지와 범위로부터 벗어남이 없이 다양한 수정이나 변형을 하는 것이 가능하다. 따라서, 첨부된 특허 청구범위는 본 발명의 요지에 속하는 이러한 수정이나 변형을 포함할 것이다.Although the present invention has been described in connection with the above preferred embodiments, it is possible to make various modifications or variations without departing from the spirit and scope of the invention. Accordingly, the appended claims will cover such modifications and variations as fall within the spirit of the invention.

Claims (12)

  1. 기판과;A substrate;
    상기 기판 상에 형성되는 게이트 전극과;A gate electrode formed on the substrate;
    상기 기판 상에 상기 게이트 전극과 이격되게 형성되는 소스 전극과;A source electrode formed spaced apart from the gate electrode on the substrate;
    상기 기판 상에 상기 소스 전극과 이격되게 형성되는 드레인 전극과;A drain electrode formed on the substrate to be spaced apart from the source electrode;
    상기 기판 상에 상기 소스 전극 및 상기 드레인 전극을 덮도록 형성되고, 상기 소스 전극과 상기 드레인 전극을 전기적으로 연결하는 채널층과;A channel layer formed on the substrate to cover the source electrode and the drain electrode, the channel layer electrically connecting the source electrode and the drain electrode;
    상기 기판 상에 상기 게이트 전극과 상기 채널층을 연결하도록 형성되는 액정층과;A liquid crystal layer formed to connect the gate electrode and the channel layer on the substrate;
    상기 액정층과 상기 채널층 간에 개재되어 상기 액정층에 의해 상기 채널층에 전하 생성이 유도되는 것을 최소화하는 쌍극자 제어층을 포함하는 것을 특징으로 하는 쌍극자 제어층을 포함한 평면 액정-게이트-전계효과 트랜지스터.A planar liquid crystal-gate-field effect transistor comprising a dipole control layer interposed between the liquid crystal layer and the channel layer to minimize the generation of charge generation in the channel layer by the liquid crystal layer. .
  2. 제 1 항에 있어서,The method of claim 1,
    상기 쌍극자 제어층은 상기 채널층보다 유전율이 낮은 고분자 물질인 것을 특징으로 하는 쌍극자 제어층을 포함한 평면 액정-게이트-전계효과 트랜지스터.And the dipole control layer is a polymer material having a lower dielectric constant than the channel layer.
  3. 제 2 항에 있어서,The method of claim 2,
    상기 쌍극자 제어층은 폴리 메틸 메타크릴레이트(PMMA)를 포함하는 것을 특징으로 하는 쌍극자 제어층을 포함한 평면 액정-게이트-전계효과 트랜지스터.And the dipole control layer comprises poly methyl methacrylate (PMMA).
  4. 제 1 항에 있어서,The method of claim 1,
    상기 채널층은 유기 반도체층, 무기 반도체층 또는 유무기 혼합 반도체층 중 어느 하나인 것을 특징으로 하는 쌍극자 제어층을 포함한 평면 액정-게이트-전계효과 트랜지스터.And the channel layer is any one of an organic semiconductor layer, an inorganic semiconductor layer, and an organic-inorganic mixed semiconductor layer.
  5. 제 1 항에 있어서,The method of claim 1,
    상기 액정층은 상기 게이트 전극의 전압에 따라 분자 배향이 변화되는 액정 분자들을 포함하는 것을 특징으로 하는 쌍극자 제어층을 포함한 평면 액정-게이트-전계효과 트랜지스터.And the liquid crystal layer includes liquid crystal molecules whose molecular orientation changes according to the voltage of the gate electrode.
  6. 제 1 항에 있어서,The method of claim 1,
    상기 액정층은 네마틱 액정 분자들을 포함하는 것을 특징으로 하는 쌍극자 제어층을 포함한 평면 액정-게이트-전계효과 트랜지스터.And a liquid crystal layer comprising nematic liquid crystal molecules. 2. The planar liquid crystal-gate-field effect transistor comprising a dipole control layer.
  7. 제 1 항에 있어서,The method of claim 1,
    상기 액정층은 상기 채널층과 상기 게이트 전극 간을 절연하는 게이트 절연층으로서의 기능을 갖는 쌍극자 제어층을 포함한 평면 액정-게이트-전계효과 트랜지스터.And the liquid crystal layer includes a dipole control layer having a function as a gate insulating layer for insulating between the channel layer and the gate electrode.
  8. 제 1 항에 있어서,The method of claim 1,
    상기 채널층 및 상기 게이트 전극 상에 상기 채널층과 상기 게이트 전극의 적어도 일부를 둘러싸도록 형성되는 보호벽을 포함하고,A protective wall formed on the channel layer and the gate electrode to surround at least a portion of the channel layer and the gate electrode,
    상기 액정층은 상기 보호벽의 내측에 형성되는 것을 특징으로 하는 쌍극자 제어층을 포함한 평면 액정-게이트-전계효과 트랜지스터.And the liquid crystal layer is formed inside the protective wall.
  9. 제 8 항에 있어서,The method of claim 8,
    상기 보호벽은 실리콘 필름을 포함하는 것을 특징으로 하는 쌍극자 제어층을 포함한 평면 액정-게이트-전계효과 트랜지스터.And the protective wall comprises a silicon film. 20. A planar liquid crystal-gate-field effect transistor comprising a dipole control layer.
  10. 제 8 항에 있어서,The method of claim 8,
    상기 보호벽의 상부 측 개방부를 덮는 보호층을 더 포함하는 것을 특징으로 하는 쌍극자 제어층을 포함한 평면 액정-게이트-전계효과 트랜지스터.And a protective layer covering an upper side opening of the protective wall.
  11. 제 10 항에 있어서,The method of claim 10,
    상기 보호층은 연신 폴리프로필렌 필름을 포함하는 것을 특징으로 하는 쌍극자 제어층을 포함한 평면 액정-게이트-전계효과 트랜지스터.And the protective layer comprises a stretched polypropylene film. 20. A planar liquid crystal-gate-field effect transistor comprising a dipole control layer.
  12. 제 1 항 기재의 쌍극자 제어층을 포함한 평면 액정-게이트-전계효과 트랜지스터를 이용한 촉각센서.A tactile sensor using a planar liquid crystal-gate-field effect transistor comprising the dipole control layer of claim 1.
PCT/KR2016/003923 2015-08-19 2016-04-15 Planar liquid crystal-gate-field effect transistor comprising dipole control layer and super-sensitivity tactile sensor using same WO2017030267A1 (en)

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