WO2017028515A1

WO2017028515A1 - Predistortion coefficient processing method, device and storage medium

Info

Publication number: WO2017028515A1
Application number: PCT/CN2016/074138
Authority: WO
Inventors: 胡安稳; 杨丽宁; 龚晓亮
Original assignee: 深圳市中兴微电子技术有限公司
Priority date: 2015-08-20
Filing date: 2016-02-19
Publication date: 2017-02-23
Also published as: CN106470017A; CN106470017B

Abstract

An embodiment of the present invention discloses a predistortion coefficient processing method configured to reduce overheads, lower manufacturing costs and significantly increase competitiveness of a product. The method comprises: storing an acquired predistortion coefficient in an off-chip buffer; and during table processing of data, copying a corresponding predistortion coefficient of a level number corresponding to transmission of link data from the off-chip buffer to a storage resource of hardware logic. An embodiment of the present invention also discloses a predistortion coefficient processing device.

Description

Predistortion coefficient processing method and device, storage medium

Technical field

The present invention relates to a technique for pre-distortion coefficient over-the-table in the field of wireless communications, and in particular, to a pre-distortion coefficient processing method and apparatus, and a storage medium.

Background technique

In wireless communication systems, linear modulation and multi-carrier modulation schemes are often used to improve spectrum utilization. However, only the output of the RF power amplifier has high linearity, which can improve the output efficiency of the power amplifier and reduce the cost. Because the principle of predistortion processing is simple and easy to implement, it can also track the error caused by the environmental factors such as temperature and humidity of the compensation power amplifier. Therefore, an effective means to improve the linearity is to predistort the input signal of the power amplifier. At present, an adaptive predistortion processing structure widely used is a memory polynomial model.

In the digital predistortion processing device using the memory polynomial model, in order to improve the accuracy of the memory polynomial model and the power amplifier efficiency, the binning is performed according to the real-time power of the transmitted signal, and the data of each gear has corresponding pre-distortion coefficients. Among them, the extraction and training of the predistortion coefficient is performed by a digital signal processor (DSP). At the same time, for extracting the pre-distortion coefficients of the training, the hardware needs corresponding random access memory (RAM) resources to store the pre-distortion coefficients of each gear table. For a digital predistortion processing device with a large number of polynomial orders or a large number of bins, the overhead of storing the storage RAM of the predistortion coefficient table may be large, resulting in high design cost and low product competitiveness.

Summary of the invention

In order to solve the above technical problem, embodiments of the present invention are expected to provide a predistortion coefficient processing method and apparatus, and a storage medium, which can reduce overhead, reduce production cost, and greatly improve products. Competitiveness.

The technical solution of the present invention is implemented as follows:

A predistortion coefficient processing method, the method comprising:

The obtained predistortion coefficient is stored in an off-chip buffer;

When performing data over-the-table processing, copying the pre-distortion coefficient corresponding to the gear position number of the transmit link data from the off-chip buffer to the storage resource of the hardware logic; wherein the data over-table is a pair of data Perform algorithmic operations.

As an implementation manner, the method further includes:

Obtaining a query address of the pre-distortion coefficient;

And performing delay processing, and performing digital pre-distortion table processing on the data corresponding to the pre-distortion coefficient corresponding to the query address according to the query address.

As an implementation manner, the obtaining the query address of the pre-distortion coefficient table includes:

Obtaining a query address of the pre-distortion coefficient according to the transmit link data.

As an implementation manner, when performing the data over-the-table processing, copying the pre-distortion coefficient corresponding to the gear position number of the transmit link data from the off-chip buffer to the storage resource of the hardware logic includes:

Obtain an update interrupt request when performing data over-the-table processing;

And responding to the update interrupt request, copying the predistortion coefficient corresponding to the gear position corresponding to the gear link data from the off-chip buffer to the storage resource of the hardware logic, and forming a pre-distortion coefficient table.

As an implementation manner, the storage resource of the hardware logic is a random access memory RAM;

The RAM includes a first level digital pre-distortion coefficient lookup table and a second level digital pre-distortion coefficient lookup table.

As an implementation manner, the responding to the update interrupt request, the off-chip buffer Pre-distortion coefficients of the data in the same gear position as the gear position corresponding to the transmission link data are copied into the storage resource of the hardware logic, and a pre-distortion coefficient table is formed, including:

And responding to the update interrupt request, copying, in the off-chip buffer, pre-distortion coefficients of data of the same gear position as the corresponding link data of the transmit link data into the first-level digital pre-distortion coefficient lookup table;

When there is a pre-distortion coefficient that needs to be copied into the second level digital pre-distortion coefficient lookup table, a table switch is performed and the pre-distortion coefficients are copied into the second level digital pre-distortion coefficient lookup table.

As an implementation, the off-chip buffer includes a double rate synchronous dynamic random access memory DDR of a digital signal processor DSP.

A predistortion coefficient processing device, the device comprising: a storage unit and a first processing unit; wherein

The storage unit is configured to store the obtained pre-distortion coefficient in an off-chip buffer;

The first processing unit is configured to: when the data is over-processed, copy the pre-distortion coefficient corresponding to the gear link data obtained by the training unit from the off-chip buffer to the hardware logic In the storage resource; wherein the data over-the-table is an algorithm operation on the data.

As an implementation manner, the device further includes: an obtaining unit and a second processing unit, where:

The obtaining unit is configured to acquire a query address of the pre-distortion coefficient;

The second processing unit is configured to perform delay processing, and perform digital pre-distortion table processing on the data corresponding to the pre-distortion coefficient corresponding to the query address according to the query address obtained by the obtaining unit.

As an implementation manner, the acquiring unit is further configured to:

As an implementation manner, the first processing unit includes: an obtaining module and a processing module, where:

The obtaining module is configured to acquire an update interrupt request when performing data over-table processing;

The processing module is configured to: in response to the update interrupt request, copy a pre-distortion coefficient corresponding to the gear link number of the transmit link data from the off-chip buffer to a storage resource of the hardware logic, and form Predistortion coefficient table.

As an implementation manner, the processing module is further configured to:

Responding to the update interrupt request, copying, in the off-chip buffer, pre-distortion coefficients of data of the same gear position as the corresponding link data of the transmit link data to the first-level digital pre-distortion coefficient lookup table, And delay processing;

As an implementation, the off-chip buffer includes a double rate synchronous dynamic random access memory of a digital signal processor DSP.

A predistortion coefficient processing apparatus, the apparatus comprising: a digital signal processor and an off-chip buffer, wherein:

The digital signal processor is configured to store the pre-distortion coefficient in an off-chip buffer;

The off-chip buffer is configured to store a digital pre-distortion coefficient obtained by the digital signal processor;

The digital signal processor is further configured to transmit a link when performing data over-the-table processing The pre-distortion coefficient corresponding to the data corresponding gear number is copied from the off-chip buffer to the storage resource of the hardware logic; wherein the data over-the-table is an algorithm operation on the data.

As an implementation manner, the device further includes: a table controller and a RAM, wherein:

The table controller is configured to obtain a query address of the pre-distortion coefficient according to the transmit link data;

The RAM is configured to store the pre-distortion coefficient obtained by the digital signal processor, and perform data processing on the data corresponding to the pre-distortion coefficient according to the query address obtained by the table controller.

As an implementation manner, the apparatus further includes: a delay processor, wherein:

The delay processor is configured to perform delay processing before performing data over-the-table processing, so that the data at the over-the-table is aligned with the power gear position and the pre-distortion coefficient.

A storage medium having stored therein a computer program configured to perform the pre-distortion coefficient processing method.

The predistortion coefficient processing method and device and the storage medium provided by the embodiment of the present invention first store the obtained predistortion coefficient in an off-chip buffer of the digital signal processor, and then transmit the link data at the current time when the data is over-table. The pre-distortion coefficient of the corresponding power bin is copied to the storage resource of the hardware logic; thus, the storage resource of the hardware logic of the embodiment of the invention only stores the pre-distortion coefficient of a gear at the current time, compared to the prior art. The storage hardware of the hardware logic needs to store the pre-distortion coefficient of all gears, which greatly reduces the storage space, thereby reducing the overhead, reducing the production cost, and greatly improving the competitiveness of the product.

DRAWINGS

1 is a schematic flowchart of a method for processing a predistortion coefficient according to an embodiment of the present invention;

2 is a schematic flowchart of another method for processing pre-distortion coefficients according to an embodiment of the present invention;

FIG. 3 is a schematic flowchart diagram of still another method for processing pre-distortion coefficients according to an embodiment of the present disclosure;

4 is a schematic structural diagram of a predistortion coefficient processing apparatus according to an embodiment of the present invention;

FIG. 5 is a schematic structural diagram of another pre-distortion coefficient processing apparatus according to an embodiment of the present disclosure;

FIG. 6 is a schematic structural diagram of still another pre-distortion coefficient processing apparatus according to an embodiment of the present disclosure;

FIG. 7 is a schematic structural diagram of a predistortion coefficient processing apparatus according to another embodiment of the present invention;

FIG. 8 is a schematic structural diagram of another pre-distortion coefficient processing apparatus according to another embodiment of the present invention; FIG.

FIG. 9 is a schematic structural diagram of still another pre-distortion coefficient processing apparatus according to another embodiment of the present invention; FIG.

FIG. 10 is a schematic structural diagram of an implementation of a pre-distortion coefficient processing apparatus according to an embodiment of the present invention.

detailed description

The technical solutions in the embodiments of the present invention will be clearly and completely described in the following with reference to the accompanying drawings.

An embodiment of the present invention provides a pre-distortion coefficient processing method, which can be applied to a wireless data transmitting device. Referring to FIG. 1, the method includes the following steps:

Step 101: Store the obtained pre-distortion coefficient in an off-chip buffer.

Here, the step may be implemented by the pre-distortion coefficient processing device; the pre-distortion coefficient training may be performed on the valid data having the same gear position as the corresponding gear bit of the transmit link data, and the pre-distortion coefficient of the corresponding valid data is obtained, and The resulting predistortion coefficients are stored in an off-chip buffer.

Step 102: When performing data over-the-table processing, copy the pre-distortion coefficient corresponding to the gear position corresponding to the gear link data from the off-chip buffer to the storage resource of the hardware logic.

This step may be specifically implemented by a pre-distortion coefficient processing device; here, the pre-distortion coefficients copied into the storage resources of the hardware logic may form a pre-distortion coefficient table storage. Among them, the data over-the-table is an algorithm operation on the data, and the data polynomial algorithm can be used to perform the data algorithm. Operation.

The predistortion coefficient processing method provided by the embodiment of the present invention stores the obtained predistortion coefficient in an off-chip buffer of the digital signal processor, and then acquires a pre-distortion of the power bin corresponding to the current time transmission link data by the interrupt request. The coefficient is copied into the storage resource of the hardware logic; thus, the storage resource of the hardware logic of the embodiment of the present invention only stores the pre-distortion coefficient of a gear at the current time, and needs to be stored in the storage resource of the prior art hardware logic. The pre-distortion factor of all gears greatly reduces the storage space, which can reduce the overhead, reduce the production cost, and greatly enhance the competitiveness of the product.

An embodiment of the present invention provides a pre-distortion coefficient processing method. Referring to FIG. 2, the method includes the following steps:

Step 201: The predistortion coefficient processing device stores the obtained predistortion coefficient in an off-chip buffer.

The pre-distortion coefficient in step 201 can be obtained by:

a. The pre-distortion coefficient processing device acquires data of the transmit link data to be processed and the transmit link data through power amplification.

b. The predistortion coefficient processing device classifies the transmit link data to obtain a corresponding gear bit number of the transmit link data.

Specifically, the pre-distortion coefficient processing device may be disposed in the wireless data transmitting device or the wireless data transmitting device itself; the level division of the transmit link data may be the power of the wireless data transmitting device according to the transmit link data, according to the actual The requirements are preset with different power levels, and then the transmit link data is divided into power levels according to a preset power threshold to obtain a corresponding gear number of the transmit link data.

c. The predistortion coefficient processing device acquires valid data in the data of the transmit link data and the transmit link data that has undergone power amplification.

Specifically, according to the obtained transmit link data and the transmit link data, the number of power amplification is performed. The power and the above data are filtered in the position of the entire link, and the data matching the target power and the target position is selected to obtain valid data; wherein the target power and the target position are not uniquely limited herein, and the actual application may be based on Specific application scenarios and requirements to determine.

The step b and the step c can be performed simultaneously, and the specific execution sequence is determined according to an actual implementation process, after the step b of transmitting the link data and the step c obtaining the valid data are not successive in the execution order.

d. The pre-distortion coefficient processing device performs pre-distortion coefficient training on the valid data according to the obtained valid data and the corresponding gear position number of the transmission link data, to obtain a pre-distortion coefficient.

The training of the pre-distortion coefficient may be implemented by a digital signal processor in the wireless data transmitting device; the digital signal processor may preset the valid data in the valid data having the same gear position as the corresponding gear bit of the transmitting link data. The algorithm performs pre-distortion coefficient training, obtains pre-distortion coefficients of the corresponding valid data, and stores the obtained pre-distortion coefficients in the off-chip buffer.

The off-chip buffer includes a double-rate synchronous dynamic random access memory of the DSP, which may be DDR2 or DDR3. In the embodiment of the present invention, the formed pre-distortion coefficient is first stored in the cache space DDR2 or DDR3 of the DSP system itself. The pre-distortion coefficient is stored without occupying additional storage resources.

Step 202: When performing data over-the-table processing, the pre-distortion coefficient processing device copies the pre-distortion coefficient corresponding to the gear position corresponding to the gear link data into the storage resource of the hardware logic.

The pre-distortion coefficients in the storage resources copied to the hardware logic may be stored in a pre-distortion coefficient table.

Step 203: The predistortion coefficient processing device acquires a query address of the predistortion coefficient.

Specifically, obtaining the query address of the pre-distortion coefficient in step 203 can be implemented in the following manner:

Based on the transmit link data, the query address of the predistortion coefficient table is obtained.

Step 204: The pre-distortion coefficient processing device performs delay processing, and checks according to the query address. The data corresponding to the pre-distortion coefficient corresponding to the address is subjected to digital pre-distortion table processing.

Specifically, the pre-distortion coefficient corresponding to the query address may be found in the obtained pre-distortion coefficient table according to the obtained query address, and then the data corresponding to the pre-distortion coefficient is subjected to digital pre-distortion table processing.

It should be noted that the explanation of the same steps in the foregoing embodiments as the above embodiments may be referred to the description in the foregoing embodiments, and details are not described herein again.

The predistortion coefficient processing method provided by the embodiment of the present invention stores the obtained predistortion coefficient in an off-chip buffer of the digital signal processor, and then acquires a pre-distortion of the power bin corresponding to the current time transmission link data by the interrupt request. The coefficient is copied into the storage resource of the hardware logic; thus, the storage resource of the hardware logic of the embodiment of the present invention only stores the pre-distortion coefficient of a gear at the current time, and needs to be stored in the storage resource of the prior art hardware logic. The pre-distortion factor of all gears greatly reduces the storage space, which can reduce the overhead, reduce the production cost, and greatly enhance the competitiveness of the product. Furthermore, the implementation difficulty is reduced, and the upgradeable convenience of the subsequent algorithm is improved.

An embodiment of the present invention provides a pre-distortion coefficient processing method. Referring to FIG. 3, the method includes the following steps:

Step 301: The predistortion coefficient processing device stores the obtained predistortion coefficient in an off-chip buffer.

Wherein, the pre-distortion coefficient in step 301 is stored in a very pre-distortion coefficient can be obtained by:

c. The predistortion coefficient processing device acquires the transmit link data and the transmit link data through the power amplifier Valid data in large data.

d. The predistortion coefficient processing device obtains valid data having the same gear position as the gear position corresponding to the current time transmission link data from the valid data.

Wherein, the obtained valid data is marked with a gear number corresponding to the valid data, so as to subsequently train the pre-distortion coefficient according to the gear number.

e. The pre-distortion coefficient processing device performs pre-distortion coefficient training on the valid data having the same gear position as the gear position number corresponding to the current time transmission link data.

f. If the pre-distortion coefficient of the valid data having the same gear position corresponding to the gear position data of the current time transmission link has been trained, the valid gear data having the same gear position as the corresponding gear position data of the current time transmission link data will be The predistortion coefficients are stored in the off-chip buffer.

g. The pre-distortion coefficient processing device determines whether the pre-distortion coefficient of the valid data having the same gear position as the gear position number corresponding to the transmission link data at the next time is completed.

h. If the pre-distortion coefficient of the valid data having the same gear position corresponding to the gear link data of the next time has been trained, the valid data of the same gear position corresponding to the gear link data of the next time transmission link data The pre-distortion coefficients are stored in the off-chip buffer.

Specifically, the training of the pre-distortion coefficient in the embodiment may be performed by referring to the method in the foregoing embodiment; the data sent by the transmitting link data at each moment is different, and the training of the pre-distortion coefficient may be respectively performed. Valid data in the transmit link data for each moment you make The training of the pre-distortion coefficient, the process of obtaining the valid data in the transmission link data at each moment is the same as the process of obtaining the valid data in the above embodiment; meanwhile, it has the same gear number corresponding to the transmission link data at each moment. The training of the pre-distortion coefficient of the valid data of the gear is also implemented by a preset algorithm. Any algorithm that can implement the pre-distortion coefficient training in the prior art is feasible, and is not limited herein.

Step 302: When performing data over-the-table processing, the pre-distortion coefficient processing device acquires an update interrupt request.

It should be noted that, after step 302 obtains the update interrupt request and step b does not perform power binning on the transmit link data in the execution order, it may be performed simultaneously; while transmitting the link number of the transmit link data, Send an update interrupt request.

Step 303: The pre-distortion coefficient processing device responds to the update interrupt request, and copies the pre-distortion coefficient corresponding to the gear position corresponding to the gear link data from the off-chip buffer to the storage resource of the hardware logic, and forms a pre-distortion coefficient table.

The storage resource of the hardware logic is a RAM, and the RAM includes: a first level digital predistortion coefficient lookup table and a second level digital predistortion coefficient lookup table.

Specifically, in step 303, in response to the update interrupt request, the pre-distortion coefficient of the data in the off-chip buffer corresponding to the gear position corresponding to the transmission link data is copied into the storage resource of the hardware logic, and a pre-distortion coefficient table is formed. This is achieved by the following steps:

Step 303a: The pre-distortion coefficient processing device, in response to the update interrupt request, copies the pre-distortion coefficient of the data in the off-chip buffer that is in the same gear position as the corresponding link bit of the transmit link data into the first-level digital pre-distortion coefficient lookup table.

Step 303b: When there is a pre-distortion coefficient to be copied into the second-level digital pre-distortion coefficient lookup table, the pre-distortion coefficient processing means performs table switching and copies the pre-distortion coefficient into the second-level digital pre-distortion coefficient lookup table.

Where the calculated pre-distortion coefficient is copied from DDR2 or DDR3 to RAM In the middle, the first level digital pre-distortion coefficient lookup table and the second level digital pre-distortion coefficient lookup table are copied into the RAM; specifically, the first pre-distortion coefficient is copied when the first pre-distortion coefficient is copied. The distortion coefficient is copied into the first-level digital pre-distortion coefficient lookup table, and then the delay processing is performed to ensure that there is sufficient time for the table to be switched for the second time when the update interrupt request is obtained for the second pre-distortion coefficient copying. The predistortion coefficients are copied into the second level digital predistortion coefficient lookup table. By analogy, the next predistortion coefficient is copied to the first level digital predistortion coefficient lookup table.

Step 304: The predistortion coefficient processing device acquires a query address of the predistortion coefficient.

Specifically, obtaining the query address of the pre-distortion coefficient in step 304 can be implemented in the following manner:

According to the transmit link data, the query address of the predistortion coefficient is obtained.

The predistortion coefficient table corresponding to the predistortion coefficient to be searched may be firstly found according to the obtained query address of the predistortion coefficient, and then the required predistortion coefficient is found in the predistortion coefficient table.

Step 305: The pre-distortion coefficient processing device performs delay processing, and performs digital pre-distortion processing on the data corresponding to the pre-distortion coefficient corresponding to the query address according to the query address.

Wherein, the pre-distortion coefficient processing method provided in the present invention performs initialization processing before implementation, that is, the pre-distortion coefficient in the off-chip buffer has an initialization, and the update distortion is prevented if the pre-distortion coefficient of a certain gear position is not formed yet. The request requires copying of the pre-distortion coefficient, which affects the normal operation of the entire process.

The rate of matching between the off-chip buffer DDR2/3 and the DSP operation bus needs to be evaluated before implementing the entire operation flow, which reduces the logic resources of the delay unit. The following analysis is carried out through a specific application example: if the DSP uses an Advanced eXtensible Interface (AXI) bus with a clock frequency of 800 Mhz and a bit width of 128 bits, DDR3 is used, DDR3-1600 is used for DDR3, and the DPD memory polynomial order is 11th order. The number of predistortion coefficients is 128. The bit width is 32 bits. In the above structure, the operation cycle of the DSP using the AXI bus copy coefficient is: 11*32*128/128=352cycle, and the other control time operation period does not exceed 400 cycles, which is about 0.5 μs. The time for the DSP to copy data from DDR3 is: 128*32*11/(1600*64*0.3)=0.147μs; where 0.3 is the occupancy of DDR3 in the DSP and 64 is the data bit width of DDR3. Thus, the total time that the DSP completes a copy of the data from DDR3 to the hardware logic is approximately 0.5μs. In this case, the amount of stored data required by the delay unit is 0.5 μs. If the DDR3 or AXI bus is not properly selected, it will result in additional delay unit storage overhead, resulting in an overall cost increase.

An embodiment of the present invention provides a pre-distortion coefficient processing apparatus, which can be applied to a method for processing a pre-distortion coefficient provided by the embodiment corresponding to FIG. 1 to FIG. 3, and the apparatus includes: a storage unit 41 and The first processing unit 42, wherein:

The storage unit 41 is configured to store the obtained predistortion coefficients in an off-chip buffer.

The first processing unit 42 is configured to: when performing the data over-the-table processing, copy the pre-distortion coefficient corresponding to the gear position corresponding to the transmission link data obtained by the storage unit 41 from the off-chip buffer to the storage resource of the hardware logic.

Among them, the data over-the-table is an algorithm operation on the data, and the memory polynomial algorithm can be used to perform the algorithm operation of the data.

The predistortion coefficient processing apparatus provided by the embodiment of the present invention first stores the obtained predistortion coefficient in an off-chip buffer of the digital signal processor, and then acquires an interrupt request to divide the power bin corresponding to the current time transmission link data. The pre-distortion coefficient is copied into the storage resource of the hardware logic; thus, in the storage resource of the hardware logic of the embodiment of the present invention, only the pre-distortion coefficient of one gear position at the current time is stored, compared with the storage resource of the prior art hardware logic. The need to store the pre-distortion coefficients of all gears greatly reduces the storage space, which can reduce overhead, reduce production costs, and greatly enhance the competitiveness of the product.

As an implementation manner, the storage of the pre-distortion coefficient and the pre-distortion number in the storage unit 41 can be implemented in the following manner:

Acquiring the transmit-transmitted transmit link data and the transmit link data through power-amplified data.

The obtained transmit link data is hierarchically divided to obtain a corresponding gear bit number of the transmit link data.

Obtaining valid data in the power-amplified data of the transmit link data and the transmit link data.

The valid data having the same gear number as the gear position corresponding to the current transmission link data is obtained from the valid data.

Pre-distortion coefficient training is performed on the obtained valid data having the same gear number as the gear number corresponding to the current time transmission link data.

If the pre-distortion coefficient of the valid data having the same gear position as the gear position corresponding to the current transmission link data has been trained, the pre-distortion of the valid data having the same gear position as the gear position corresponding to the current time transmission link data is used. The coefficients are stored in the off-chip buffer.

It is judged whether the pre-distortion coefficient of the valid data having the same gear position as the gear position number corresponding to the transmission link data at the next moment is completed.

For valid data having the same gear position as the gear position corresponding to the transmission link data at the next moment The pre-distortion coefficient has been trained to be completed, and the pre-distortion coefficient of the gear position corresponding to the gear position number of the next-time transmission link data is stored in the off-chip buffer.

As an implementation manner, referring to FIG. 5, the apparatus further includes: an obtaining unit 43 and a second processing unit 44, wherein:

The obtaining unit 43 is configured to obtain a query address of the pre-distortion coefficient.

The second processing unit 44 is configured to perform delay processing, and performs digital pre-distortion table processing on the data corresponding to the pre-distortion coefficient corresponding to the query address according to the query address obtained by the obtaining unit 43.

Specifically, the obtaining unit 43 is further configured to obtain a query address of the pre-distortion coefficient according to the transmit link data.

Specifically, referring to FIG. 6, the first processing unit 42 includes: an obtaining module 421 and a processing module 422, where:

The obtaining module 421 is configured to obtain an update interrupt request when performing data over-table processing.

The processing module 422 is configured to: in response to the update interrupt request, copy the pre-distortion coefficient corresponding to the gear position corresponding to the gear link data from the off-chip buffer to the storage resource of the hardware logic, and form a pre-distortion coefficient table.

The storage resource of the hardware logic is a random access memory RAM, and the RAM includes a first level digital predistortion coefficient lookup table and a second level digital predistortion coefficient lookup table.

Specifically, the processing module 422 is further configured to perform the following steps:

In response to the update interrupt request, the pre-distortion coefficient of the data in the off-chip buffer corresponding to the gear position corresponding to the transmission link data is copied to the first-level digital pre-distortion coefficient lookup table, and the delay processing is performed.

Wherein, the off-chip buffer includes a double-rate synchronous dynamic random of the digital signal processor DSP Memory.

It should be noted that the interaction process between the units in this embodiment may refer to the interaction process in the pre-distortion coefficient processing method provided by the embodiment corresponding to FIG. 1 to FIG. 3, and details are not described herein again.

The predistortion coefficient processing apparatus provided by the embodiment of the present invention stores the obtained predistortion coefficient in an off-chip buffer of the digital signal processor, and then acquires a pre-interrupt request for a power bin corresponding to the current time transmission link data. The distortion coefficient is copied into the storage resource of the hardware logic; thus, the storage resource of the hardware logic of the embodiment of the present invention only stores the pre-distortion coefficient of a gear at the current time, which is required in comparison with the storage resources of the prior art hardware logic. The pre-distortion factor for storing all gear positions greatly reduces the storage space, which reduces overhead and reduces production costs, greatly increasing the competitiveness of the product. Furthermore, the implementation difficulty is reduced, and the upgradeable convenience of the subsequent algorithm is improved.

An embodiment of the present invention provides a predistortion coefficient processing apparatus. Referring to FIG. 7, the apparatus includes: a digital signal processor 51 and an off-chip buffer 52, wherein:

The digital signal processor 51 is configured to store the pre-distortion coefficients in an off-chip buffer.

Specifically, the storage of the pre-distortion coefficient and the pre-distortion coefficient can be implemented in the following manner:

The transmit link data and the transmit link data to be processed are subjected to power-amplified data, and valid data is filtered out.

The obtained transmit link data is hierarchically divided to obtain a corresponding gear number of the transmit link data.

Among them, the data of different gear positions correspond to different pre-distortion coefficients.

The off-chip buffer 52 is configured to store digital pre-distortion coefficients obtained by the digital signal processor 51.

The digital signal processor 51 is further configured to: when performing data over-the-table processing, copy the pre-distortion coefficient of the gear position corresponding to the gear position corresponding to the gear link data from the off-chip buffer to the storage resource of the hardware logic to form Predistortion coefficient table.

As an implementation manner, referring to FIG. 8, the apparatus further includes: a table controller 53 and RAM54, where:

The table controller 53 is configured to obtain a query address of the predistortion coefficient based on the transmit link data.

The RAM 54 is configured to store the pre-distortion coefficient obtained by the digital signal processor 51, and performs table processing on the data corresponding to the pre-distortion coefficient based on the inquiry address obtained by the table controller 53.

The RAM 54 includes: a first level digital predistortion coefficient lookup table and a second level digital predistortion coefficient lookup table.

As an implementation manner, referring to FIG. 9, the apparatus further includes: a delay processor 55, wherein:

The delay processor 55 is configured to perform delay processing before performing data over-the-table processing so that the data at the over-the-table is aligned with the power gear and the pre-distortion coefficient.

Specifically, the digital signal processor 51 is further configured to: copy the pre-distortion coefficients of the corresponding gear positions into the storage resources of the hardware logic according to the obtained update interrupt request, to form a pre-distortion coefficient table.

Among them, the predistortion coefficient processing apparatus provided in the present embodiment is applied to the specific structural frame diagram shown in FIG.

The predistortion coefficient processing apparatus provided by the embodiment of the present invention first stores the obtained predistortion coefficient in an off-chip buffer of the digital signal processor, and then acquires a pre-interrupt request for a power bin corresponding to the current time transmission link data. The distortion coefficient is copied into the storage resource of the hardware logic; thus, the storage resource of the hardware logic of the embodiment of the present invention only stores the pre-distortion coefficient of a gear at the current time, which is required in comparison with the storage resources of the prior art hardware logic. The pre-distortion factor for storing all gear positions greatly reduces the storage space, which reduces overhead and reduces production costs, greatly increasing the competitiveness of the product. Furthermore, the implementation difficulty is reduced, and the upgradeable convenience of the subsequent algorithm is improved.

In practical applications, the storage unit 41, the first processing unit 42, the obtaining unit 43, and the second processing unit 44 may each be a central processing unit (Central) located in the wireless data transmitting device. A processing unit (CPU), a microprocessor (Micro Processor Unit, MPU), a digital signal processor (DSP), or a Field Programmable Gate Array (FPGA).

The embodiment of the invention further describes a storage medium in which a computer program is stored, the computer program being configured to perform the predistortion coefficient processing method of the foregoing embodiments.

Those skilled in the art will appreciate that embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention can take the form of a hardware embodiment, a software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.

The present invention has been described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (system), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or FIG. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing device to produce a machine for the execution of instructions for execution by a processor of a computer or other programmable data processing device. Means for implementing the functions specified in one or more of the flow or in a block or blocks of the flow chart.

The computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device. The apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.

These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device. Instructions are provided for implementation The steps of a function specified in a block or blocks of a flow or a flow and/or a block diagram of a flow chart.

The above is only the preferred embodiment of the present invention and is not intended to limit the scope of the present invention.

Industrial applicability

The invention firstly stores the obtained pre-distortion coefficient in the off-chip buffer of the digital signal processor, and then copies the pre-distortion coefficient of the power bin corresponding to the current time-transmitted link data to the storage of the hardware logic when performing the data over-provisioning. In the resource, the storage resource of the hardware logic only stores the pre-distortion coefficient of a gear at the current time, and the pre-distortion coefficient of storing all the gears in the storage resource of the prior art hardware logic greatly reduces the storage. Space, which can reduce overhead, reduce production costs, and greatly enhance the competitiveness of products.

Claims

A predistortion coefficient processing method, the method comprising:

The obtained predistortion coefficient is stored in an off-chip buffer;

When performing data over-the-table processing, copying the pre-distortion coefficient corresponding to the gear position number of the transmit link data from the off-chip buffer to the storage resource of the hardware logic; wherein the data over-table is a pair of data Perform algorithmic operations.
The method of claim 1 wherein the method further comprises:

Obtaining a query address of the pre-distortion coefficient;

And performing delay processing, and performing digital pre-distortion table processing on the data corresponding to the pre-distortion coefficient corresponding to the query address according to the query address.
The method of claim 2, wherein the obtaining the query address of the pre-distortion coefficient table comprises:

Obtaining a query address of the pre-distortion coefficient according to the transmit link data.
The method according to claim 1, wherein when the data over-processing is performed, the pre-distortion coefficient corresponding to the gear number corresponding to the transmission link data is copied from the off-chip buffer to the storage of the hardware logic. Resources include:

Obtain an update interrupt request when performing data over-the-table processing;

And responding to the update interrupt request, copying the predistortion coefficient corresponding to the gear position corresponding to the gear link data from the off-chip buffer to the storage resource of the hardware logic, and forming a pre-distortion coefficient table.
The method according to any one of claims 1 to 4, wherein the storage resource of the hardware logic is a random access memory RAM;

The RAM includes a first level digital pre-distortion coefficient lookup table and a second level digital pre-distortion coefficient lookup table.
The method of claim 5 wherein said responding to said update interrupt request, Copying, in the off-chip buffer, the pre-distortion coefficient of the data of the same gear position as the corresponding gear bit of the transmit link data into the storage resource of the hardware logic, and forming a pre-distortion coefficient table, including:

And responding to the update interrupt request, copying, in the off-chip buffer, pre-distortion coefficients of data of the same gear position as the corresponding link data of the transmit link data into the first-level digital pre-distortion coefficient lookup table;

When there is a pre-distortion coefficient that needs to be copied into the second level digital pre-distortion coefficient lookup table, a table switch is performed and the pre-distortion coefficients are copied into the second level digital pre-distortion coefficient lookup table.
The method of claim 1 wherein said off-chip buffer comprises a double rate synchronous dynamic random access memory DDR of a digital signal processor DSP.
A predistortion coefficient processing device, the device comprising: a storage unit and a first processing unit; wherein

The storage unit is configured to store the obtained pre-distortion coefficient in an off-chip buffer;

The first processing unit is configured to: when the data is over-processed, copy the pre-distortion coefficient corresponding to the gear link data obtained by the training unit from the off-chip buffer to the hardware logic In the storage resource; wherein the data over-the-table is an algorithm operation on the data.
The apparatus of claim 8, wherein the apparatus further comprises: an acquisition unit and a second processing unit, wherein:

The obtaining unit is configured to acquire a query address of the pre-distortion coefficient;

The second processing unit is configured to perform delay processing, and perform digital pre-distortion table processing on the data corresponding to the pre-distortion coefficient corresponding to the query address according to the query address obtained by the obtaining unit.
The apparatus of claim 9, wherein the obtaining unit is further configured to:

Obtaining a query address of the pre-distortion coefficient according to the transmit link data.
The apparatus of claim 8, wherein the first processing unit comprises: an acquisition module and a processing module, wherein:

The obtaining module is configured to acquire an update interrupt request when performing data over-table processing;

The processing module is configured to: in response to the update interrupt request, copy a pre-distortion coefficient corresponding to the gear link number of the transmit link data from the off-chip buffer to a storage resource of the hardware logic, and form Predistortion coefficient table.
The device according to any one of claims 8 to 11, wherein the storage resource of the hardware logic is a random access memory RAM;

The RAM includes a first level digital pre-distortion coefficient lookup table and a second level digital pre-distortion coefficient lookup table.
The apparatus of claim 12 wherein said processing module is further configured to:

Responding to the update interrupt request, copying, in the off-chip buffer, pre-distortion coefficients of data of the same gear position as the corresponding link data of the transmit link data to the first-level digital pre-distortion coefficient lookup table, And delay processing;

When there is a pre-distortion coefficient that needs to be copied into the second level digital pre-distortion coefficient lookup table, a table switch is performed and the pre-distortion coefficients are copied into the second level digital pre-distortion coefficient lookup table.
The apparatus of claim 8 wherein said off-chip buffer comprises a double rate synchronous dynamic random access memory of digital signal processor DSP.
A predistortion coefficient processing apparatus, wherein the apparatus comprises: a digital signal processor and an off-chip buffer, wherein:

The digital signal processor is configured to store the pre-distortion coefficient in an off-chip buffer;

The off-chip buffer is configured to store a digital pre-distortion coefficient obtained by the digital signal processor;

The digital signal processor is further configured to, when performing data over-the-table processing, copy the pre-distortion coefficient corresponding to the gear position corresponding to the gear link data from the off-chip buffer to the storage resource of the hardware logic; The data over-the-table is an algorithmic operation on the data.
The apparatus of claim 15 wherein said apparatus further comprises: a table controller and a RAM, wherein:

The table controller is configured to obtain a query address of the pre-distortion coefficient according to the transmit link data;

The RAM is configured to store the pre-distortion coefficient obtained by the digital signal processor, and perform data processing on the data corresponding to the pre-distortion coefficient according to the query address obtained by the table controller.
The apparatus of claim 16 wherein said apparatus further comprises: a delay processor, wherein:

The delay processor is configured to perform delay processing before performing data over-the-table processing, so that the data at the over-the-table is aligned with the power gear position and the pre-distortion coefficient.
A storage medium storing a computer program configured to perform the predistortion coefficient processing method according to any one of claims 1 to 7.