WO2017027445A1 - Packaging arrangements including a serializing dram interface die - Google Patents

Packaging arrangements including a serializing dram interface die Download PDF

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Publication number
WO2017027445A1
WO2017027445A1 PCT/US2016/045975 US2016045975W WO2017027445A1 WO 2017027445 A1 WO2017027445 A1 WO 2017027445A1 US 2016045975 W US2016045975 W US 2016045975W WO 2017027445 A1 WO2017027445 A1 WO 2017027445A1
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WIPO (PCT)
Prior art keywords
random access
access memory
die
package substrate
serializing
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Ceased
Application number
PCT/US2016/045975
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French (fr)
Inventor
Chenglin Liu
Shiann-Ming Liou
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Marvell World Trade Ltd
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Marvell World Trade Ltd
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Publication of WO2017027445A1 publication Critical patent/WO2017027445A1/en
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H10W72/07554—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/352—Materials of die-attach connectors comprising metals or metalloids, e.g. solders
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/353—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
    • H10W72/354—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics comprising polymers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/547—Dispositions of multiple bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/24—Configurations of stacked chips at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/28—Configurations of stacked chips the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/752—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/753—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between laterally-adjacent chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • Embodiments of the present disclosure relate to semiconductor packaging arrangements, and in particular to packaging arrangements that include a serializing DRAM interface die.
  • Random access memory such as dynamic random access memor
  • DRAM dynamic random access memory
  • the present disclosure provides a packaging arrangement that comprises a package su bstrate.
  • a ra ndom access memory die is coupled to the package substrate and a serializing ra ndom access memory interface die coupled to (i) the package substrate a nd (ii) the ra ndom access memory die.
  • a lso provides a method that comprises providing a package substrate.
  • a ra ndom access memory die is cou pled to the package substrate, and a serializing random access memory interface die is coupled to (i) the package substrate a nd (ii) the ra ndom access memory die.
  • FIG. 1A schematically ill ustrates a packaging arrangement for a ra ndom access memory die and a serializing ra ndom access memory interface die.
  • Fig. IB schematically illustrates another packaging arrangement for a random access memory die and a serializing random access memory interface die.
  • FIG. 1C schematically illustrates another packaging arrangement for two random access memory dies and a serializing random access memory interface die.
  • FIG. 2 is a flow diagram of an example method for making a packaging arrangement for a random access memory die and a serializing random access memory interface die.
  • Fig. 1A schematically illustrates a packaging arrangement 100a that includes a package substrate 102.
  • the packaging arrangement 100a further includes a die 104 configured as a random access memory die.
  • the random access memory die is configured as a dynamic random access memory (DRAM) die.
  • the DRAM die 104 is coupled to the package substrate 102.
  • the DRAM die 104 can be attached to the package substrate 102 via, for example, flip chip attachment, wire bonding, etc. in embodiments where the DRAM die 104 is wire bond attached to the package substrate 102, an adhesive, epoxy, solder, etc., may be used to physically attach the DRAM die 104 to the package substrate 102.
  • DRAM dynamic random access memory
  • the package substrate 102 includes wire bond fingers or pads 106 to allow for wire bond connections.
  • the DRAM die 104 includes wire bond fingers or pads 108 to allow for wire bond connections.
  • Wires 110 provide coupling between the bond fingers 106 and 108, thereby allowing the DRAM die 104 to be coupled to the package substrate 102 to allow for the exchange of signals therebetween.
  • the packaging arrangement 100a further includes a serializing DRAM interface die 112.
  • the serializing DRAM interface die 112 is located on top of the DRAM die 104.
  • the serializing DRAM interface die 112 can be flip chip attached to the DRAM die 104 or wire bond attached to the DRAM die 104.
  • the serializing DRAM interface die 112 may be physically attached to the DRAM die 104 utilizing an adhesive, epoxy, solder, etc.
  • the serializing DRAM interface die 112 includes wire bond fingers or pads 114 to allow for wire bond connections to the package substrate 102 and/or the DRAM die 104.
  • Wires 116 and 118 provide coupling between the bond fingers 114 and 106, 108, respectively, thereby allowing the serializing DRAM interface die 112 to be coupled to the package substrate 102 and/or the DRAM die 104 to allow for the exchange of signals therebetween.
  • the package substrate 102 includes one or more redistribution layers (RDLs) (not illustrated).
  • the RDLs can be utilized to route signals within the package substrate 102 between the DRAM die 104 and the serializing DRAM interface die 112.
  • the wire bonding fingers 106 on the package substrate 102 can be utilized to receive signals from the DRAM die 104 and the serializing DRAM interface die 112 through corresponding wires 110, 116.
  • the signals can be routed through one or more RDLs and provided to other wire bond fingers 106.
  • the signals can then be provided to the DRAM die 104 and the serializing DRAM interface die 112 through corresponding wires 110, 116.
  • the wire bond fingers 106 can also be utilized to provide power and ground signals to the DRAM die 104 and the serializing DRAM interface die 112 through corresponding wires 110, 116. Additionally, wires 118 can be used to directly couple wire bond fingers 108 on the DRAM die 104 with wire bond fingers 114 on the serializing DRAM interface 112 to allow signal exchange directly between the DRAM die 104 and the serializing DRAM interface die 112. Bond pads (not illustrated) may also be included on a surface of the DRAM die 104 to allow for direct coupling via solder to the package substrate 102 for signal exchange therebetween. Likewise, the serializing DRAM interface die 112 may include bond pads (not illustrated) on a surface to allow for direct coupling via solder to the DRAM die 104 for signal exchange therebetween.
  • Fig. IB schematicall illustrates a packaging arrangement 100b wherein the DRAM die 104 and the serializing DRAM interface die 112 are coupled to and located on the package substrate 102 in a side-by-side relationship.
  • the DRAM die 104 can be coupled to the package substrate 102 via flip-chip attachment or wire bond coupling.
  • An adhesive, epoxy, solder, etc. may be used to physically attach the DRAM die 104 to the package substrate 102.
  • the serializing DRAM interface die 112 can be coupled to the package substrate 102 via flip-chip attachment or wire bond coupling.
  • An adhesive, epoxy, solder, etc. may be used to physically attach the serializing DRAM interface die 112 to the package substrate 102.
  • Bond pads (not illustrated) may also be included on a surface of the DRAM die 104 and/or the serializing DRAM interface die 112 to allow for direct coupling via solder to the package substrate 102 for signal exchange therebetween.
  • Fig. 1C schematically illustrates a packaging arrangement 100c that includes a first DRAM die 104a and a second DRAM die 104b. More DRAM dies 104 may be included if desired.
  • the first and second DRAM dies 104a, 104b are stacked on top of one another and the first DRAM die 104a is attached to the package substrate 102. in other embodiments, the first and second DRAM dies 104a, 104b are side by side and both attached to the package substrate 102.
  • the serializing DRAM interface die 112 is located and coupled to the package substrate 102 beside the two stacked DRAM dies 104a, 104b.
  • the serializing DRAM interface die 112 may be located beside one of the DRAM dies 104a, 104b, on top of one of the DRAM dies 104a, 104b, or in between the DRAM dies 104a, 104b.
  • the first DRAM die 104a can be coupled to the package substrate 102 via flip-chip attachment or wire bond coupling.
  • An adhesive, epoxy, solder, etc. may be used to physically attach the first DRAM die 104a to the package substrate 102.
  • the second DRAM die 104b can be coupled to the first die 104a or the package substrate 102 via flip-chip attachment or wire bond coupling.
  • An adhesive, epoxy, solder, etc may be used to physically attach the second DRAM die 104b to the package substrate 102.
  • the serializing DRAM interface die 112 can be coupled to the package substrate 102 via flip-chip attachment or wire bond coupling.
  • An adhesive, epoxy, solder, etc. may be used to physically attach the serializing DRAM interface die 112 to the package substrate 102.
  • Bond pads may also be included on a surface of the DRAM dies 104a, 104b and/or the serializing DRAM interface die 112 to allow for direct coupling via solder to the package substrate 102 for signal exchange therebetween.
  • Wires 116a, 118a can be used to couple bond pads 108a on the first DRAM die 104a to bond pads 106, 114 on the package substrate 102 or the serializing DRAM interface die 112, respectively, while wires 116b, 118b can be used to couple bond pads 108b on the second DRAM die 104b to bond pads 106, 114 on the package substrate 102 or the serializing DRAM interface die 112, respectively.
  • Wires 120 can be used to couple bond pads 108b on the second DRAM die 104b to bond pads 108a on the first DRAM die
  • high speed differential signals may be routed in traditional low cost PCBs and packages.
  • Serializing the DRAM interface by converting many single-ended signals to high speed differential signals in one package with one or more DRAM dies can solve routing issues of the traditional DRAM interface. The signal count is thus significantly reduced and routing resources may be significantly saved.
  • FIG. 2 is a flow diagram of an example method 200 for making a packaging arrangement, e.g., packaging arrangements 100a, 100b and 100c illustrated in Figs. 1A, IB and 1C, respectively, for a random access memory die and a serializing random access memory interface die.
  • a packaging arrangement e.g., packaging arrangements 100a, 100b and 100c illustrated in Figs. 1A, IB and 1C, respectively, for a random access memory die and a serializing random access memory interface die.
  • a package substrate e.g., package substrate 102
  • a random access memory die e.g., DRAM die 104
  • a serializing random access memory interface die e.g., serializing DRAM interface die 112 to (i) the package substrate and (ii) the random access memory die.
  • a packaging arrangement comprising:
  • a serializing random access memory interface die coupled to (i) the package substrate and (ii) the random access memory die.
  • the random access memory die is a first random access memory die
  • the packaging arrangement further comprises a second random access memory die coupled to (i) the package substrate and (ii) the first random
  • Clause 5 The packaging arrangement of clause 4, wherein the second random access memory die is located on the first random access memory die.
  • Clause 7 The packaging arrangement of clause 4, wherein the second random access memor die is directly coupled to the serializing random access memory interface die.
  • Clause 12 The packaging arrangement of clause 1, wherein the serializing random access memory die is wire bonded to (i) the package substrate and (ii) the random access memory die.
  • Clause 15 The method of clause 14, wherein coupling the serializing random access memory interface die to (i) the package substrate and (ii) the random access memory die comprises placing the serializing random access memory interface die on the random access memory die.
  • Clause 16 The method of clause 14, wherein coupling the serializing random access memory interface die to (i) the package substrate and (ii) the random access memory die comprises placing the serializing random access memory interface die on the package substrate beside the random access memory die located on the package substrate.
  • the random access memory die is a first random access memory die; and [0048] the method further comprises coupling a second random access memory die to (i) the package substrate and (ii) the first random access memory die.
  • Clause 18 The method of clause 17, wherein coupling the second random access memory die to (i) the package substrate and (ii) the first random access memory die comprises placing the second random access memory die on the first random access memory die.
  • Clause 23 The method of clause 14, wherein coupling the serializing random access memory interface die to the package substrate comprises wire bonding the serializing random access memory die to (i) the package substrate and (ii) the random access memor die.
  • the description may use the phrases “in an embodiment,” or “in embodiments,” which may each refer to one or more of the same or different embodiments.
  • the phrase “in some embodiments” is used repeatedly. The phrase generally does not refer to the same embodiments; however, it may.
  • the terms “comprising,” “having,” and “including” are synonymous, unless the context dictates otherwise.
  • the phrase “A and/or B” means (A), (B), or (A and B).
  • the phrase “A/B” means (A), (B), or (A and B), similar to the phrase “A and/or B.”
  • the phrase “at least one of A, B and C” means (A), (B), (C), (A and B), (A and C), (B and C) or (A, B and C).
  • the phrase “(A) B” means (B) or (A and B), that is, A is optional.

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Abstract

Embodiments provide a packaging arrangement that comprises a package substrate. A random access memory die is coupled to the package substrate and a serializing random access memory interface die coupled to (i) the package substrate and (ii) the random access memory die.

Description

PACKAGING ARRANGEMENTS INCLUDING A SERIALIZING DRAM INTERFACE DIE
Cross Reference to Related Applications
[0001] This disclosure claims priority to U.S. Patent Application No. 15/228,859, filed August 4, 2016, which claims priority to U.S. Provisional Patent Application
No. 62/204,781, filed on August 13, 2015, which are incorporated herein by reference in their entirety.
Technical Field
[0002] Embodiments of the present disclosure relate to semiconductor packaging arrangements, and in particular to packaging arrangements that include a serializing DRAM interface die.
Background
[0003] Random access memory (such as dynamic random access memor
(DRAM)) interface speeds continue to increase to higher and higher levels. The number of signals to and from the memory are generally high and the data/address signals are single-ended. Thus, the DRAM interface may become the bottleneck of routing of signals at all levels, especially the printed circuit board (PCB) and packaging levels. This generally requires more routing resources such as higher layer counts to route signals, which translates into high costs for PCBs and packaging. Summary
[0004] In various embodiments, the present disclosure provides a packaging arrangement that comprises a package su bstrate. A ra ndom access memory die is coupled to the package substrate and a serializing ra ndom access memory interface die coupled to (i) the package substrate a nd (ii) the ra ndom access memory die.
[0005] I n various embodi ments, the present disclosure a lso provides a method that comprises providing a package substrate. A ra ndom access memory die is cou pled to the package substrate, and a serializing random access memory interface die is coupled to (i) the package substrate a nd (ii) the ra ndom access memory die.
Brief Description of the Drawings
[0006] Embodiments of the present disclosu re will be readily u nderstood by the following detailed description in conju nction with the accompanying d rawings. To facilitate this description, like reference nu merals designate like structu ral elements. Va rious embodiments are ill ustrated by way of example and not by way of limitation i n the figures of the accompanying drawings.
[0007] Fig. 1A schematically ill ustrates a packaging arrangement for a ra ndom access memory die and a serializing ra ndom access memory interface die. [0008] Fig. IB schematically illustrates another packaging arrangement for a random access memory die and a serializing random access memory interface die.
[0009] Fig. 1C schematically illustrates another packaging arrangement for two random access memory dies and a serializing random access memory interface die.
[0010] Fig. 2 is a flow diagram of an example method for making a packaging arrangement for a random access memory die and a serializing random access memory interface die.
[0011] Fig. 1A schematically illustrates a packaging arrangement 100a that includes a package substrate 102. The packaging arrangement 100a further includes a die 104 configured as a random access memory die. In embodiments, the random access memory die is configured as a dynamic random access memory (DRAM) die. The DRAM die 104 is coupled to the package substrate 102. The DRAM die 104 can be attached to the package substrate 102 via, for example, flip chip attachment, wire bonding, etc. in embodiments where the DRAM die 104 is wire bond attached to the package substrate 102, an adhesive, epoxy, solder, etc., may be used to physically attach the DRAM die 104 to the package substrate 102.
[0012] The package substrate 102 includes wire bond fingers or pads 106 to allow for wire bond connections. Likewise, the DRAM die 104 includes wire bond fingers or pads 108 to allow for wire bond connections. Wires 110 provide coupling between the bond fingers 106 and 108, thereby allowing the DRAM die 104 to be coupled to the package substrate 102 to allow for the exchange of signals therebetween.
[0013] The packaging arrangement 100a further includes a serializing DRAM interface die 112. In the embodiment of Fig. 1A, the serializing DRAM interface die 112 is located on top of the DRAM die 104. The serializing DRAM interface die 112 can be flip chip attached to the DRAM die 104 or wire bond attached to the DRAM die 104. The serializing DRAM interface die 112 may be physically attached to the DRAM die 104 utilizing an adhesive, epoxy, solder, etc. The serializing DRAM interface die 112 includes wire bond fingers or pads 114 to allow for wire bond connections to the package substrate 102 and/or the DRAM die 104. Wires 116 and 118 provide coupling between the bond fingers 114 and 106, 108, respectively, thereby allowing the serializing DRAM interface die 112 to be coupled to the package substrate 102 and/or the DRAM die 104 to allow for the exchange of signals therebetween.
[0014] in embodiments, the package substrate 102 includes one or more redistribution layers (RDLs) (not illustrated). The RDLs can be utilized to route signals within the package substrate 102 between the DRAM die 104 and the serializing DRAM interface die 112. Thus, in embodiments, the wire bonding fingers 106 on the package substrate 102 can be utilized to receive signals from the DRAM die 104 and the serializing DRAM interface die 112 through corresponding wires 110, 116. The signals can be routed through one or more RDLs and provided to other wire bond fingers 106. The signals can then be provided to the DRAM die 104 and the serializing DRAM interface die 112 through corresponding wires 110, 116. The wire bond fingers 106 can also be utilized to provide power and ground signals to the DRAM die 104 and the serializing DRAM interface die 112 through corresponding wires 110, 116. Additionally, wires 118 can be used to directly couple wire bond fingers 108 on the DRAM die 104 with wire bond fingers 114 on the serializing DRAM interface 112 to allow signal exchange directly between the DRAM die 104 and the serializing DRAM interface die 112. Bond pads (not illustrated) may also be included on a surface of the DRAM die 104 to allow for direct coupling via solder to the package substrate 102 for signal exchange therebetween. Likewise, the serializing DRAM interface die 112 may include bond pads (not illustrated) on a surface to allow for direct coupling via solder to the DRAM die 104 for signal exchange therebetween.
[0015] Fig. IB schematicall illustrates a packaging arrangement 100b wherein the DRAM die 104 and the serializing DRAM interface die 112 are coupled to and located on the package substrate 102 in a side-by-side relationship. The DRAM die 104 can be coupled to the package substrate 102 via flip-chip attachment or wire bond coupling. An adhesive, epoxy, solder, etc., may be used to physically attach the DRAM die 104 to the package substrate 102. The serializing DRAM interface die 112 can be coupled to the package substrate 102 via flip-chip attachment or wire bond coupling. An adhesive, epoxy, solder, etc., may be used to physically attach the serializing DRAM interface die 112 to the package substrate 102. Bond pads (not illustrated) may also be included on a surface of the DRAM die 104 and/or the serializing DRAM interface die 112 to allow for direct coupling via solder to the package substrate 102 for signal exchange therebetween.
[0016] Fig. 1C schematically illustrates a packaging arrangement 100c that includes a first DRAM die 104a and a second DRAM die 104b. More DRAM dies 104 may be included if desired. In the embodiment of Fig. 1C, the first and second DRAM dies 104a, 104b are stacked on top of one another and the first DRAM die 104a is attached to the package substrate 102. in other embodiments, the first and second DRAM dies 104a, 104b are side by side and both attached to the package substrate 102. The serializing DRAM interface die 112 is located and coupled to the package substrate 102 beside the two stacked DRAM dies 104a, 104b. In embodiments where the first and second DRAM dies 104a, 104b are side by side, the serializing DRAM interface die 112 may be located beside one of the DRAM dies 104a, 104b, on top of one of the DRAM dies 104a, 104b, or in between the DRAM dies 104a, 104b.
[0017] The first DRAM die 104a can be coupled to the package substrate 102 via flip-chip attachment or wire bond coupling. An adhesive, epoxy, solder, etc., may be used to physically attach the first DRAM die 104a to the package substrate 102. The second DRAM die 104b can be coupled to the first die 104a or the package substrate 102 via flip-chip attachment or wire bond coupling. An adhesive, epoxy, solder, etc, may be used to physically attach the second DRAM die 104b to the package substrate 102. The serializing DRAM interface die 112 can be coupled to the package substrate 102 via flip-chip attachment or wire bond coupling. An adhesive, epoxy, solder, etc., may be used to physically attach the serializing DRAM interface die 112 to the package substrate 102. Bond pads (not illustrated) may also be included on a surface of the DRAM dies 104a, 104b and/or the serializing DRAM interface die 112 to allow for direct coupling via solder to the package substrate 102 for signal exchange therebetween. Wires 116a, 118a can be used to couple bond pads 108a on the first DRAM die 104a to bond pads 106, 114 on the package substrate 102 or the serializing DRAM interface die 112, respectively, while wires 116b, 118b can be used to couple bond pads 108b on the second DRAM die 104b to bond pads 106, 114 on the package substrate 102 or the serializing DRAM interface die 112, respectively. Wires 120 can be used to couple bond pads 108b on the second DRAM die 104b to bond pads 108a on the first DRAM die
[0018] Thus, in accordance with various embodiments, high speed differential signals may be routed in traditional low cost PCBs and packages. Serializing the DRAM interface by converting many single-ended signals to high speed differential signals in one package with one or more DRAM dies can solve routing issues of the traditional DRAM interface. The signal count is thus significantly reduced and routing resources may be significantly saved.
[0019] Fig. 2 is a flow diagram of an example method 200 for making a packaging arrangement, e.g., packaging arrangements 100a, 100b and 100c illustrated in Figs. 1A, IB and 1C, respectively, for a random access memory die and a serializing random access memory interface die.
[0020] At 204, a package substrate, e.g., package substrate 102, is provided. At 208, a random access memory die, e.g., DRAM die 104, is coupled to the package substrate. At 212, a serializing random access memory interface die, e.g., serializing DRAM interface die 112, to (i) the package substrate and (ii) the random access memory die.
[0021] Further aspects of the present invention relate to one or more of the following clauses.
[0022] Clause 1. A packaging arrangement comprising:
[0023] a package substrate;
[0024] a random access memory die coupled to the package substrate; and
[0025] a serializing random access memory interface die coupled to (i) the package substrate and (ii) the random access memory die.
[0026] Clause 2. The packaging arrangement of clause 1, wherein the serializing random access memory interface die is located on the random access memory die. [0027] Clause 3. The packaging arrangement of clause 1, wherein the serializing random access memory interface die is located on the package substrate beside the random access memory die located on the package substrate.
[0028] Clause 4. The packaging arrangement of clause 1, wherein:
[0029] the random access memory die is a first random access memory die; and
[0030] the packaging arrangement further comprises a second random access memory die coupled to (i) the package substrate and (ii) the first random
memory die.
[0031] Clause 5. The packaging arrangement of clause 4, wherein the second random access memory die is located on the first random access memory die.
[0032] Clause 6. The packaging arrangement of clause 4, wherein the second random access memory die is located on the package substrate beside the first random access memory die located on the package su bstrate.
[0033] Clause 7. The packaging arrangement of clause 4, wherein the second random access memor die is directly coupled to the serializing random access memory interface die.
[0034] Clause 8. The packaging arrangement of clause 1, wherein the random access memory die is directly coupled to the serializing random access memory interface die. [0035] Clause 9. The packaging arrangement of clause 1, wherein the random access memory die is flip-chip attached to the package substrate.
[0036] Clause 10. The packaging arrangement of clause 1, wherein the random access memory die is wire bonded to (i) the package substrate and (ii) the serializing random access memory interface die.
[0037] Clause 11. The packaging arrangement of clause 1, wherein the serializing random access memory interface die is flip-chip attached to the package substrate.
[0038] Clause 12. The packaging arrangement of clause 1, wherein the serializing random access memory die is wire bonded to (i) the package substrate and (ii) the random access memory die.
[0039] Clause 13. The packaging arrangement of clause 1, wherein the random access memory die is configured as dynamic random access memory.
[0040] Clause 14. A method comprising;
[0041] providing a package substrate;
[0042] coupling a random access memory die to the package substrate; and
[0043] coupling a serializing random access memory interface die to (i) the package substrate and (ii) the random access memory die.
[0044] Clause 15. The method of clause 14, wherein coupling the serializing random access memory interface die to (i) the package substrate and (ii) the random access memory die comprises placing the serializing random access memory interface die on the random access memory die.
[0045] Clause 16. The method of clause 14, wherein coupling the serializing random access memory interface die to (i) the package substrate and (ii) the random access memory die comprises placing the serializing random access memory interface die on the package substrate beside the random access memory die located on the package substrate.
[0046] Clause 17. The method of clause 14, wherein;
[0047] the random access memory die is a first random access memory die; and [0048] the method further comprises coupling a second random access memory die to (i) the package substrate and (ii) the first random access memory die.
[0049] Clause 18. The method of clause 17, wherein coupling the second random access memory die to (i) the package substrate and (ii) the first random access memory die comprises placing the second random access memory die on the first random access memory die.
[0050] Clause 19. The method of clause 17, wherein coupling the second random access memory die to (i) the package substrate and (ii) the first random access memory die comprises placing the second random access memory die on the package substrate beside the first random access memory die located on the package substrate. [0051] Clause 20. The method of clause 14, wherein coupling the random access memory die to the package substrate comprises flip-chip attaching the random access memory die to the package substrate.
[0052] Clause 21. The method of clause 14, wherein coupling the random access memory die to the package substrate comprises wire bonding the random access memory die to (i) the package substrate and (ii) the serializing random access memory interface die.
[0053] Clause 22. The method of clause 14, wherein coupling the serializing random access memory interface die to the package substrate comprises flip-chip attaching the serializing random access memory interface die to the package substrate.
[0054] Clause 23. The method of clause 14, wherein coupling the serializing random access memory interface die to the package substrate comprises wire bonding the serializing random access memory die to (i) the package substrate and (ii) the random access memor die.
[0055] The description may use the phrases "in an embodiment," or "in embodiments," which may each refer to one or more of the same or different embodiments. The phrase "in some embodiments" is used repeatedly. The phrase generally does not refer to the same embodiments; however, it may. The terms "comprising," "having," and "including" are synonymous, unless the context dictates otherwise. The phrase "A and/or B" means (A), (B), or (A and B). The phrase "A/B" means (A), (B), or (A and B), similar to the phrase "A and/or B." The phrase "at least one of A, B and C" means (A), (B), (C), (A and B), (A and C), (B and C) or (A, B and C). The phrase "(A) B" means (B) or (A and B), that is, A is optional.
[0056] Although certain embodiments have been illustrated and described herein, a wide variety of alternate and/or equivalent embodiments or implementations calculated to achieve the same purposes may be substituted for the embodiments illustrated and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the embodiments discussed herein. Therefore, it is manifestly intended that embodiments in accordance with the present invention be limited only by the claims and the equivalents thereof.

Claims

Claims What is claimed is:
1. A packaging arrangement comprising:
a package substrate;
a random access memory die coupled to the package substrate; and
a serializing random access memory interface die coupled to (i) the package substrate and (ii) the random access memory die,
2. The packaging arrangement of claim 1, wherein the serializing random access memory interface die is located on the random access memory die,
3. The packaging arrangement of claim 1, wherein the serializing random access memory interface die is located on the package substrate beside the random access memory die located on the package substrate.
4. The packaging arrangement of claim 1, wherein:
the random access memory die is a first random access memory die; and the packaging arrangement further comprises a second random access memory die coupled to (i) the package substrate and (ii) the first random access memory die.
5. The packaging arrangement of claim 4, wherein the second random access memory die is located on the first random access memory die.
6. The packaging arrangement of claim 4, wherein the second random access memory die is located on the package substrate beside the first random access memory die located on the package substrate.
7. The packaging arrangement of claim 4, wherein the second random access memory die is directly coupled to the serializing random access memory interface die.
8. The packaging arrangement of claim 1, wherein the random access memory die is directly coupled to the serializing random access memory interface die.
9. The packaging arrangement of claim 1, wherein the random access memory die is flip-chip attached to the package substrate.
10. The packaging arrangement of claim 1, wherein the random access memory die is wire bonded to (i) the package substrate and (ii) the serializing random access memory interface die.
11. The packaging arrangement of claim 1, wherein the serializing random access memory interface die is flip-chip attached to the package substrate.
12. The packaging arrangement of claim 1, wherein the serializing random access memory die is wire bonded to (i) the package substrate and (ii) the random access memory die.
13. The packaging arrangement of claim 1, wherein the random access memory die is configured as dynamic random access memory.
14. A method comprising:
providing a package substrate;
coupling a random access memory die to the package substrate; and
coupling a serializing random access memor interface die to (i) the package substrate and (ii) the random access memory die.
15. The method of claim 14, wherein coupling the serializing random access memory interface die to (i) the package substrate and (ii) the random access memory die comprises placing the serializing random access memory interface die on the random access memory die.
16. The method of claim 14, wherein coupling the serializing random access memory interface die to (i) the package substrate and (ii) the random access memory die comprises placing the serializing random access memory interface die on the package substrate beside the random access memory die located on the package substrate.
17. The method of claim 14, wherein;
the random access memory die is a first random access memory die; and the method further comprises coupling a second random access memory die to (i) the package substrate and (ii) the first random access memory die.
18. The method of claim 17, wherein coupling the second random access memory die to (i) the package substrate and (ii) the first random access memory die comprises placing the second random access memory die on the first random access memory die.
19. The method of claim 17, wherein coupling the second random access memory die to (i) the package substrate and (ii) the first random access memory die comprises placing the second random access memory die on the package substrate beside the first random access memory die located on the package substrate.
20. The method of claim 14, wherein coupling the random access memory die to the package substrate comprises flip-chip attaching the random access memory die to the package substrate.
21. The method of claim 14, wherein coupling the random access memory die to the package substrate comprises wire bonding the random access memory die to (i) the package substrate and (ii) the serializing random access memory interface die.
22. The method of claim 14, wherein coupling the serializing random access memory interface die to the package substrate comprises flip-chip attaching the serializing random access memory interface die to the package substrate.
23. The method of claim 14, wherein coupling the serializing random access memory interface die to the package substrate comprises wire bonding the serializing random access memory die to (i) the package substrate and (ii) the random access memory die.
PCT/US2016/045975 2015-08-13 2016-08-08 Packaging arrangements including a serializing dram interface die Ceased WO2017027445A1 (en)

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