WO2017024782A1

WO2017024782A1 - Clock synchronization method, device, base station and storage medium in a satellite communication network

Info

Publication number: WO2017024782A1
Application number: PCT/CN2016/073780
Authority: WO
Inventors: 石乔; 胡晓鹏; 尧小安
Original assignee: 中兴通讯股份有限公司
Priority date: 2015-08-07
Filing date: 2016-02-15
Publication date: 2017-02-16
Also published as: CN106452642A

Abstract

A clock synchronization method, a device, a base station and a computer storage medium in a satellite communication network are provided by the present invention. An end station receives data frames carrying standard clock information sent from a main station periodically, obtains the standard clock information in the data frames and synchronizes with the clock locally instead of GPS, thus reducing the cost of using the GPS receiver on the end station and ensuring the required signal strength during the clock synchronization.

Description

Satellite communication network clock synchronization method and device, base station and storage medium

Technical field

The present invention relates to the field of wireless communication technologies, and in particular, to a satellite communication network clock synchronization method and apparatus, and a base station and a computer storage medium.

Background technique

On a ship going offshore, it takes a long time to go to sea to maintain communication with the land. However, due to the limitation of the maritime environment, the traditional base station cannot be deployed. The communication between the ground and the ship terminal can only be realized by satellite communication. There are various base stations, such as a Base Transceiver Station (BTS) or other types of base stations.

The BTS is a base station based on the multi-frequency time division multiple access (MF-TDMA) method. During the operation of the BTS base station, it is necessary to maintain the clock of the BTS as the end station and the BTS as the primary station. Clock synchronization or frequency synchronization, if the frequency deviation between the end station and the main station is large, it will cause a frequency offset, which makes the user unable to access, and even has problems such as dropped calls and call timeouts. At present, the clock synchronization with the primary station on the end station is realized by using a Global Positioning System (GPS) receiver, but using a GPS receiver for clock synchronization or frequency synchronization has the following disadvantages:

1. To ensure the normal use of the GPS receiver, it is necessary to receive signals from at least three satellites in the sky above. Of course, when you need to synchronize, the top of the head will not always be "a whole blue sky", so the lack of signal strength is one of the GPS injuries.

2. Installing a GPS receiver on the BTS as an end station increases the cost.

Summary of the invention

In order to solve the existing technical problems, an embodiment of the present invention provides a method and device for clock synchronization of a satellite communication network, a base station, and a computer storage medium, which overcomes the problem of insufficient signal strength when the existing end station uses the GPS receiver for clock synchronization. High cost defects.

The technical solution adopted by the embodiment of the present invention is that the satellite communication network clock synchronization method includes:

Receiving a data frame forwarded by the primary station through the satellite, acquiring standard clock information from the data frame, and performing clock synchronization locally at the end station based on the standard clock information.

In the above solution, the data frame is encapsulated based on a second generation DVB System for Satellite Broadcasting (DVB-S2) protocol.

In the above solution, the data frame received by the primary station through the satellite is received, including:

Based on the frame start information of the header portion of the received data frame, it is determined that the corresponding data frame forwarded by the primary station through the satellite has been received.

In the above solution, the receiving the data frame forwarded by the primary station through the satellite, and acquiring the standard clock information from the data frame, includes:

The received data frame is processed by the demodulation chip, and the processing result of the frame header portion of the data frame is output by the serial port data description information bus, and the processing result of the data portion of the data frame is output by the data bus;

Whenever the serial port data description information bus is detected to output a frame start information, the standard clock information is obtained from the processing result of the data portion of the corresponding data frame output from the data bus.

In the above solution, when detecting that the serial port data description information bus outputs a frame start information, the standard clock information is obtained from the processing result of the data portion of the corresponding data frame outputted by the data bus, including:

Whenever the serial port data description information bus is detected to output a frame start message, perform the following steps:

Extracting the frame counter value of the frame header portion of the data frame from the processing result outputted by the serial port data description information bus, which is called the first frame counter value; and extracting the frame counter of the data portion of the data frame from the processing result outputted by the data bus The value is called the second frame counter value;

If the first frame counter value is equal to the second frame counter value, the standard clock information is obtained from the processing result of the data portion of the corresponding data frame output from the data bus;

If the first frame counter value is greater than the second frame counter value, recording a difference between the first frame counter value and the second frame counter value, and waiting for the difference number of data frames to arrive, the output from the data bus The standard clock information is obtained from the processing result of the data portion of the data frame.

The embodiment of the present invention further provides a satellite communication network clock synchronization device, which is disposed in a BTS as an end station, and the device includes:

An information acquiring module, configured to receive a data frame forwarded by the primary station through the satellite, and obtain standard clock information from the data frame;

A clock synchronization module configured to perform clock synchronization locally at the end station based on the standard clock information.

In the above solution, the data frame is encapsulated based on the DVB-S2 protocol.

In the above solution, the clock synchronization module is further configured to:

In the above solution, the information acquiring module is configured to:

In the above solution, the information acquiring module is further configured to:

Whenever the serial port data description information bus is detected to output a frame start message,

Extracting the frame counter value of the frame header portion of the data frame from the processing result outputted by the serial port data description information bus, which is called the first frame counter value; and processing result output from the data bus Extracting the frame counter value of the data portion of the data frame, referred to as the second frame counter value;

The embodiment of the invention further provides a BTS, which is operated as an end station, and the BTS includes the above-mentioned satellite communication network clock synchronization device.

The embodiment of the invention further provides a computer storage medium, wherein the computer storage medium stores computer executable instructions, and the computer executable instructions are used to execute the foregoing satellite communication network clock synchronization method.

With the above technical solution, the present invention has at least the following advantages:

The satellite communication network clock synchronization method and device, the base station and the computer storage medium in the embodiment of the present invention receive the data frame carrying the standard clock information periodically sent from the primary station at the end station, and obtain the data frame from the data frame. The standard clock information is clocked locally, which can be used instead of GPS for clock synchronization, reducing the cost of using the GPS receiver at the end station and ensuring the strength of the signal required for the clock synchronization process.

DRAWINGS

1 is a schematic structural diagram of a system for clock synchronization between an end station and a primary station of a BTS according to a first embodiment of the present invention;

2 is a flowchart of a method for clock synchronization of a satellite communication network according to a first embodiment of the present invention;

3 is a schematic structural diagram of a data frame of a DVB-S2 format according to a first embodiment of the present invention;

4 is a schematic structural diagram of a clock synchronization apparatus of a satellite communication network according to a third embodiment of the present invention;

FIG. 5 is a schematic diagram showing the internal connection of an end station according to a sixth embodiment of the present invention; FIG.

6 is a timing diagram showing an output data bus output signal of a demodulation chip according to a sixth embodiment of the present invention;

FIG. 7 is a timing diagram of an output signal of an SDD bus according to a sixth embodiment of the present invention; FIG.

FIG. 8 is a flow chart showing the process of analyzing and matching the SOF of the SDD bus and the data on the data bus by the end station according to the sixth embodiment of the present invention.

detailed description

The present invention will be described in detail below with reference to the accompanying drawings and preferred embodiments.

A first embodiment of the present invention, a method for clock synchronization of a satellite communication network, as shown in FIG. 2, includes the following specific steps:

Step S101, receiving a data frame forwarded by the primary station through the satellite, and acquiring standard clock information from the data frame;

Specifically, the data frame is encapsulated based on the DVB-S2 protocol. As a successor to the Digital Video Broadcasting System for Satellite Broadcasting (DVB-S), DVB-S2, which makes bandwidth utilization more efficient, is designed to handle high-quality video and advanced services over satellite. Supporting DVB-S2 requires only a small capital investment, because it only involves two aspects of the broadcast front end: modulation encoder and receiving demodulation decoder, the modulation encoder can be located on the primary station, and the receiving decoder can be located at the end. stand on.

The system for clock synchronization between the end station and the primary station of the BTS is shown in Figure 1. The ground primary station accesses the Internet through the gateway. On the primary station, the original data message is encapsulated into a data frame of the DVB-S2 format. After the modulator modulates to the frequency corresponding to the satellite, the primary station generates a radio frequency signal and sends it to the satellite transponder through the antenna. The signal is amplified by the transponder and forwarded to the end station on the surface vessel; after receiving the radio frequency signal, the end station is down-converted. Processing becomes a baseband signal, then demodulated and solved The code recovers the original data message. If the end station is connected to the WiFi module and the mobile phone is installed with a specific app, it can realize functions such as making calls, surfing the Internet, and watching videos on the ocean-going ship.

On the primary station, the DVB-S2 format data frame after modulation coding and encapsulation is shown in Figure 3. The header part PLHEADER is divided into SOF (Start Of Frame) segment and PLSCODE (Physical Layer Signaling Code). A layer signal code segment, where XFECFRAME (complex Forward Error Correction Frame) represents a data portion. The frame header consists of 90 symbols, of which SOF occupies 26 symbols. This piece of data information is fixed in the DVB-S2 protocol. For the DVB-S2 protocol frame format, this can be cycled on the primary station. The DVB-S2 format data frame carrying standard clock information is sent. Before the end station receives the demodulation and decoding, the SOF of the frame header portion of the arriving data frame is detected, and the GPS clock can be used as the timing source to send the standard clock information. The phase-locked loop to the end station is calibrated to achieve the purpose of keeping the clock synchronized with the master station. Therefore, the data frame received by the primary station through the satellite may be determined by: determining, according to the frame start information SOF of the frame header portion of the received data frame, that the corresponding data received by the primary station through the satellite is received. frame.

In an embodiment, step S101 includes:

The received data frame is processed by the demodulation chip, and the processing result of the frame header portion of the data frame is output by the serial port data description information bus, and the processing result of the data portion of the data frame is output by the data bus; the data of the data frame is output Part of the processing includes: demodulating and decoding the data portion of the received data frame by using a demodulation chip.

Further, for a specific demodulation chip, a fixed GPIO pin is selected as a serial port data description information bus output port by configuring a GPIO switch matrix in the demodulation chip;

The data part of the received data frame is processed by the demodulation chip, and the original data message is outputted on the data bus by the transport stream management module; the original data message can be obtained from the original data message Take standard clock information.

Step S102, performing clock synchronization locally at the end station based on the standard clock information.

Specifically, the standard clock information can be sent to the phase locked loop for calibration, and the clock synchronization with the primary station is achieved.

A second embodiment of the present invention is a satellite communication network clock synchronization method. The method in this embodiment is substantially the same as the first embodiment. The difference is that, in step S101, a serial port data description information bus is outputted every time a frame is detected. When starting the information, the standard clock information is obtained from the processing result of the data part of the corresponding data frame outputted by the data bus, and specifically includes:

Extracting the frame counter value of the frame header portion of the data frame from the processing result outputted by the serial port data description information bus, which is called the first frame counter value; and extracting the frame counter of the data portion of the data frame from the processing result outputted by the data bus The value is called the second frame counter value; the first frame counter value and the second frame counter value are used to record the number of the current data frame, that is, the current frame is the first few frames;

The first frame counter value and the second frame counter value are all counted from small to large. If the first frame counter value is greater than the second frame counter value, the difference between the first frame counter value and the second frame counter value is recorded. After the arrival of the data frame of the difference amount, the standard clock information is obtained from the processing result of the data portion of the data frame outputted by the data bus, and is used for clock synchronization locally at the end station.

In this embodiment, the frame counter values in the two buses are separately extracted for comparison to determine which data frame should be used to obtain the standard clock signal, in consideration of processing the received data frame by the demodulation chip, The processing of the frame header portion of the data frame does not require demodulation The code, and the processing of the data portion of the data frame must undergo demodulation and decoding processing, so the value of the frame counter in the signal outputted by the data bus may be later than the value of the frame counter in the signal output from the serial data description information bus. That is to say, the data frame in which the frame start information of the data frame header portion reached by the judgment data frame and the data frame in which the data portion just decoded and decoded is located may not be the same data frame, in order to ensure the same For a data frame, it is necessary to see whether the frame counter value of the frame header portion of the data frame is consistent with the frame counter value extracted by the data portion after demodulation and decoding, and if it is consistent, it can be extracted from the data portion of the data frame. Standard clock information. Otherwise, it is necessary to wait for the corresponding number of data frames to arrive according to the difference between the two frame counter values, and then extract standard clock information from the data portion of the arriving data frame.

Corresponding to the first embodiment, the present embodiment introduces a satellite communication network clock synchronization apparatus, which is disposed in a BTS as an end station. As shown in FIG. 4, the apparatus includes the following components:

1) The information obtaining module 401 is configured to receive a data frame forwarded by the primary station through the satellite, and obtain standard clock information from the data frame;

Specifically, the data frame is encapsulated based on the DVB-S2 protocol.

The information acquiring module 401 is specifically configured to:

The information acquisition module 401 processes the received data frame through the demodulation chip, and the processing result of the frame header portion of the data frame is output by the serial port data description information bus, and the processing result of the data portion of the data frame is output by the data bus; When it is detected that the serial port data description information bus outputs a frame start information, the standard clock information is obtained from the processing result of the data portion of the corresponding data frame output from the data bus.

2) A clock synchronization module 402 configured to perform clock synchronization locally at the end station based on the standard clock information.

In an actual application, the information acquiring module 401 and the clock synchronization module 402 may each be a central processing unit (CPU), or a digital signal processing (DSP), or a microprocessor (MPU, Micro Processor Unit), or Field Programmable Gate Array (FPGA).

In the fourth embodiment of the present invention, a satellite communication network clock synchronization device is introduced corresponding to the second embodiment. The device in this embodiment is substantially the same as the third embodiment. The difference is that the information acquisition module 401 is specifically configured to: When detecting that the serial port data description information bus outputs a frame start message, perform the following steps:

A fifth embodiment of the present invention, a BTS, can be understood as a physical device, including the satellite communication network clock synchronization device in the third embodiment or the fourth embodiment.

The sixth embodiment of the present invention is based on the above embodiments, and an application example of the present invention is described with reference to Figs.

In this embodiment, an independent tuner Tuner and a demodulation chip Demod are used on the end station. As shown in FIG. 5, the external controller uController, the tuner Tuner and the demodulator Demod are in accordance with the I2C (Inter-Integrated Circuit) protocol. Communicate.

Tuner is responsible for moving the RF signal received by the antenna to near zero frequency, and then sending the analog IQ (Inphase and Quadrature) signal to Demod. Inside Demod, the analog IQ signal is sampled and quantized by the ADC into a digital IQ signal, which is then demodulated and decoded. Finally, the Transport stream managers module outputs the original data frame on the data bus. The data bus includes CLKOUT, STROUT, and D/P. , DATA, etc., the specific timing diagram is shown in Figure 6.

In order to correctly enable Demod to output SOF, you can configure the GPIO switch matrix to select a fixed GPIO pin as the SDD bus output, and SDD (Serial Data Description) bus output SOF, Symbol Clock and SD_data. Shown.

Comparing Figure 6 with Figure 7, it is important to note that the data bus STROUT also has a frame start information SOF that identifies the start frame, which indicates that the entire DVB-S2 data frame is demodulated and decoded before being output, and the SDD bus The upper SOF is the header of the DVB-S2 data frame that is identified and output, without subsequent demodulation and decoding processes. It is well known that DVB-S2 supports code rates ranging from 1/4 to 9/10, and supports four demodulation modes of QPSK, 8PSK, 16PSK and 32APSK, and the time of combination of different code rates and demodulation modes varies. If SOF on STROUT is used as the timing synchronization clock source, the delays are not fixed due to different bit rates and demodulation methods, so the clock synchronization must use the SOF output on the SDD bus. To distinguish them, they are called STROUT_SOF and SDD_SOF, respectively.

At the transmitting end of the primary station, the SOF and the data XFECFRAME on a single frame are one-to-one correspondence, but at the receiving end of the terminal station, the SDD_SOF is output on the SDD bus, the data is output on the data bus DATA, and the SOF and data output of the same frame. There are also deviations at the moment, SOF always precedes the number According to, in order to ensure that the SOF and the data do not misalign, use the SD_data and the data bus Data to indicate which frame of the data frame PLFRAME_counter belongs to, and extract the two fields, and then compare, you can judge whether SDD_SOF and DATA are Is the same frame, as shown in Figure 8, the specific measures are as follows:

Step 1, open up two large enough buffer Buffer 0 and Buffer 1, Buffer 0 continuously charge SDD_SOF, SD_data; Buffer 1 reads STROUT and DATA on the data bus;

Step 2, parsing Buffer 0, when detecting the SDD_SOF outputted by the SDD bus, extracting PLFRAME_couter1 in SD_data, and there is queue 1;

Step 3, parsing Buffer 1 , when detecting the STROUT_SOF outputted by the data bus, fetching data from DATA, and extracting PLFRAME_couter2 contained in DATA, which exists in queue 2;

Step 4: Compare PLFRAME_couter2 and PLFRAME_couter1. If the sizes are equal, it is judged to be the same data frame. If there is a difference between the two PLFRAME_couters, the corresponding step size is moved in the queue 2 according to the difference, that is, waits in the queue 2 corresponding to the current SDD_SOF. data.

The satellite communication network clock synchronization method and device, the base station and the computer storage medium in the embodiment of the present invention receive the data frame carrying the standard clock information periodically sent from the primary station at the end station, and the slave data frame The acquisition of standard clock information for local clock synchronization can replace the GPS for clock synchronization, reducing the cost of using the GPS receiver at the end station and ensuring the strength of the signal required for the clock synchronization process.

The technical means and functions of the present invention for achieving the intended purpose can be more deeply and specifically understood by the description of the specific embodiments. However, the accompanying drawings are only for the purpose of illustration and description, and are not intended to limit.

An embodiment of the present invention further provides a computer storage medium, where the computer storage medium stores computer executable instructions, where the computer executable instructions are used to perform the foregoing satellite communication. Network clock synchronization method.

Those skilled in the art will appreciate that embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention can take the form of a hardware embodiment, a software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.

The present invention has been described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (system), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or FIG. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing device to produce a machine for the execution of instructions for execution by a processor of a computer or other programmable data processing device. Means for implementing the functions specified in one or more of the flow or in a block or blocks of the flow chart.

The computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device. The apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.

These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device. The instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

The above is only the preferred embodiment of the present invention and is not intended to limit the scope of the present invention.

Industrial applicability

Claims

A satellite communication network clock synchronization method, the method comprising:

Receiving a data frame forwarded by the primary station through the satellite, acquiring standard clock information from the data frame, and performing clock synchronization locally at the end station based on the standard clock information.
The satellite communication network clock synchronization method according to claim 1, wherein said data frame is encapsulated based on a second generation digital satellite broadcasting system standard DVB-S2 protocol.
The satellite communication network clock synchronization method according to claim 1, wherein the receiving the data frame forwarded by the primary station through the satellite comprises:

Based on the frame start information of the header portion of the received data frame, it is determined that the corresponding data frame forwarded by the primary station through the satellite has been received.
The satellite communication network clock synchronization method according to any one of claims 1 to 3, wherein the receiving the data frame forwarded by the primary station through the satellite, and acquiring the standard clock information from the data frame, includes:

The received data frame is processed by the demodulation chip, and the processing result of the frame header portion of the data frame is output by the serial port data description information bus, and the processing result of the data portion of the data frame is output by the data bus;

Whenever the serial port data description information bus is detected to output a frame start information, the standard clock information is obtained from the processing result of the data portion of the corresponding data frame output from the data bus.
The satellite communication network clock synchronization method according to claim 4, wherein each time the serial port data description information bus is detected to output a frame start information, the data portion of the corresponding data frame outputted from the data bus is processed. Get standard clock information, including:

Whenever the serial port data description information bus is detected to output a frame start message, perform the following steps:

Extracting the frame counter value of the frame header portion of the data frame from the processing result outputted by the serial port data description information bus, which is called the first frame counter value; and processing result output from the data bus Extracting the frame counter value of the data portion of the data frame, referred to as the second frame counter value;

If the first frame counter value is equal to the second frame counter value, the standard clock information is obtained from the processing result of the data portion of the corresponding data frame output from the data bus;

If the first frame counter value is greater than the second frame counter value, recording a difference between the first frame counter value and the second frame counter value, and waiting for the difference number of data frames to arrive, the output from the data bus The standard clock information is obtained from the processing result of the data portion of the data frame.
A satellite communication network clock synchronization device, the device comprising:

An information acquiring module, configured to receive a data frame forwarded by the primary station through the satellite, and obtain standard clock information from the data frame;

A clock synchronization module configured to perform clock synchronization locally at the end station based on the standard clock information.
The satellite communication network clock synchronization apparatus according to claim 6, wherein said data frame is encapsulated based on a DVB-S2 protocol.
The satellite communication network clock synchronization apparatus according to claim 6, wherein the information acquisition module is further configured to:

Based on the frame start information of the header portion of the received data frame, it is determined that the corresponding data frame forwarded by the primary station through the satellite has been received.
The satellite communication network clock synchronization device according to any one of claims 6 to 8, wherein the information acquisition module is further configured to:

The received data frame is processed by the demodulation chip, and the processing result of the frame header portion of the data frame is output by the serial port data description information bus, and the processing result of the data portion of the data frame is output by the data bus;

Whenever the serial port data description information bus is detected to output a frame start information, the standard clock information is obtained from the processing result of the data portion of the corresponding data frame output from the data bus.
A satellite communication network clock synchronization apparatus according to claim 9, wherein said said The information acquisition module is also configured to:

Whenever the serial port data description information bus is detected to output a frame start message,

Extracting the frame counter value of the frame header portion of the data frame from the processing result outputted by the serial port data description information bus, which is called the first frame counter value; and extracting the frame counter of the data portion of the data frame from the processing result outputted by the data bus The value is called the second frame counter value;

If the first frame counter value is equal to the second frame counter value, the standard clock information is obtained from the processing result of the data portion of the corresponding data frame output from the data bus;

If the first frame counter value is greater than the second frame counter value, recording a difference between the first frame counter value and the second frame counter value, and waiting for the difference number of data frames to arrive, the output from the data bus The standard clock information is obtained from the processing result of the data portion of the data frame.
A BTS operating as an end station, the BTS comprising a satellite communication network clock synchronization device according to any one of claims 6-10.
A computer storage medium having stored therein computer executable instructions for performing the method of any one of claims 1 to 5.