CN113726467A

CN113726467A - Electronic product data transmission method, system, storage medium and program product

Info

Publication number: CN113726467A
Application number: CN202110869810.0A
Authority: CN
Inventors: 黎兴荣
Original assignee: Individual
Current assignee: Individual
Priority date: 2021-07-29
Filing date: 2021-07-29
Publication date: 2021-11-30
Anticipated expiration: 2041-07-29
Also published as: CN113726467B

Abstract

The application discloses a data transmission method, a data transmission system, a storage medium and a program product of an electronic product, which are applied to a test equipment terminal. The method comprises the following steps: sending a preset handshake signal to a product to be tested, and receiving a first feedback signal of the product to be tested so as to realize a link establishment operation with the product to be tested; sending equipment attribute information to the product to be tested, wherein the equipment attribute information at least comprises bus sampling clock frequency information; interacting a frame header signal with the product to be detected to realize the synchronization of a frame structure transmitted with the data of the product to be detected; and under the bus sampling clock, performing data interaction with the product to be tested according to the synchronized frame structure. The application aims to realize high-speed data transmission by using fewer physical signal lines in production and test of electronic products.

Description

Electronic product data transmission method, system, storage medium and program product

Technical Field

The present application relates to the field of communications technologies, and in particular, to a method, a system, a storage medium, and a program product for transmitting data of an electronic product.

Background

The single-wire communication is valuable in board level communication or small electronic product production test and debugging communication. The single-wire communication has the advantages that the communication line is simple, the corresponding line structure is simple, and the single-wire communication is very suitable for testing electronic products. The method is also an ideal communication mode for some components with limited pin number. For example, the tws earphone (true wireless bluetooth earphone) communicates with the test equipment during the production test process, and if single-wire high-speed communication is available, low-delay and high-bandwidth information transmission can be realized.

At present, board-level single-wire data transmission (a communication mode formed by only 1 physical wire on the basis of common ground of a transceiver) has various methods, such as a well-known I2C bus, SPDIF, 1wire bus, and the like. The I2C transmission supports single-wire half-duplex transmission, and the implementation is simple and the expansion is convenient. But the transmission rate is not high, the standard rate is 100kbps, and the standard rate is 400kbps in a high-speed mode, so the method can not be applied to the scene of high-speed data communication; the SPDIF is also a single-wire transmission bus, but it cannot implement state feedback and retransmission of data, cannot ensure accuracy of data transmission, and has a low bandwidth; the 1wire bus is also a single wire transmission bus, but similarly, the transmission bandwidth is low, and the highest rate is generally below 100 kbps; the UART transmission bus has more data lines, physical realization is not as simple as I2C, and bandwidth is lower; the SPI bus requires at least 4 data lines for communication.

From the current known situation, no application of single-wire high-speed communication bus in small electronic products has been found in the industry. From the above analysis, these known data buses are either low in bandwidth; or the check and retransmission are not supported, and the accuracy of data transmission cannot be ensured; or more physical signal lines are needed to realize the physical connection; in addition, these bus systems do not guarantee a complete synchronization of the data of the nodes of the network.

Disclosure of Invention

The embodiment of the application provides a data transmission method, a data transmission system, a storage medium and a program product of an electronic product, and aims to realize high-speed data transmission by using fewer physical signal lines in production and test of the electronic product.

The embodiment of the application provides an electronic product data transmission method which is applied to a test equipment end; the method comprises the following steps:

sending a preset handshake signal to a product to be tested, and receiving a first feedback signal of the product to be tested so as to realize a link establishment operation with the product to be tested;

sending equipment attribute information to the product to be tested, wherein the equipment attribute information at least comprises bus sampling clock frequency information;

interacting a frame header signal with the product to be detected to realize the synchronization of a frame structure transmitted with the data of the product to be detected;

and under the bus sampling clock, performing data interaction with the product to be tested according to the synchronized frame structure.

The embodiment of the application further provides an electronic product data transmission method, which is applied to a product end to be detected, and the method comprises the following steps:

receiving a preset handshake signal of test equipment, and sending a first feedback signal to the test equipment to realize a link establishment operation with the product to be tested;

receiving bus sampling clock frequency information sent by the product to be tested, and adjusting the bus sampling clock frequency information of the local terminal according to the bus sampling clock frequency information;

interacting a frame header signal with the product to be tested to realize the synchronization of a frame structure for data transmission with the test equipment;

and carrying out data interaction with the test equipment according to the frame structure under the bus sampling clock.

The embodiment of the present application further provides an electronic product production testing system, which includes: the device comprises a test device, a product to be tested and at most two physical signal lines for communicating the test device with the product to be tested;

the test equipment is used for sending a preset handshake signal to a product to be tested and receiving a first feedback signal of the product to be tested so as to realize the link establishment operation with the product to be tested; sending equipment attribute information to the product to be tested, wherein the equipment attribute information at least comprises bus sampling clock frequency information; interacting a frame header signal with the product to be detected to realize the synchronization of a frame structure transmitted with the data of the product to be detected; and under the bus sampling clock, performing data interaction with the product to be tested according to the synchronized frame structure;

the product to be tested is used for receiving a preset handshake signal of the test equipment and sending a first feedback signal to the test equipment so as to realize the link establishment operation with the product to be tested; receiving bus sampling clock frequency information sent by the product to be tested, and adjusting a bus sampling clock of the local terminal according to the bus sampling clock frequency information; interacting a frame header signal with the product to be tested to realize the synchronization of a frame structure for data transmission with the test equipment; and carrying out data interaction with the test equipment according to the frame structure under the bus sampling clock.

The embodiment of the present application also provides a computer-readable storage medium, which stores one or more programs, where the one or more programs are executable by one or more processors to implement the steps in the data transmission method for electronic products.

An embodiment of the present application further provides a computer program product, which includes a computer program, and when the computer program is executed by a processor, the steps of the data transmission method for an electronic product are implemented.

The method comprises the steps that a preset handshake signal is sent to a product to be tested, and a first feedback signal of the product to be tested is received, so that the link establishment operation with the product to be tested is realized; and sending equipment attribute information to the product to be tested, wherein the equipment attribute information at least comprises bus sampling clock frequency information. So that the bus sampling clocks of the test equipment and the product to be tested form a basic same frequency relationship. Then, frame head signals are interacted with the product to be detected, so that the synchronization of a frame structure for data transmission with the product to be detected is realized; and performing data interaction with the product to be tested according to the synchronized frame structure under the bus sampling clock. Therefore, under the bus sampling clock, the test equipment and the product to be tested perform data interaction at most through two physical signal lines, and high-speed data interaction between the test equipment and the product to be tested in a synchronous frame transmission mode is realized.

Drawings

FIG. 1 is a schematic diagram of an embodiment of a headset testing system of the present application;

FIG. 2 is a hardware framework diagram of one embodiment of the test equipment of the present application;

FIG. 3 is a flowchart illustrating an embodiment of a data transmission method of an electronic product according to the present application;

FIG. 4 is a schematic circuit diagram of an embodiment of the test equipment and the headset under test of the present application over a single physical signal line;

FIG. 5 is a schematic circuit diagram of another embodiment of the test equipment and the headset under test of the present application over a single physical signal line;

fig. 6 is a schematic structural diagram of a frame structure of an embodiment when duplex high-speed communication is realized by a single physical signal line;

fig. 7 is a schematic structural diagram of a frame structure of an embodiment when simplex high-speed communication is realized by a single physical signal line;

fig. 8 is a schematic structural diagram showing a frame structure of still another embodiment when simplex unidirectional communication is realized by a single physical signal line;

FIG. 9 is a schematic diagram of a frame structure that does not carry a synchronous sampling clock;

FIG. 10 is a schematic diagram of a frame structure carrying a synchronous sampling clock;

fig. 11 is a schematic structural diagram showing a frame structure of an embodiment in which duplex high-speed communication is realized by two physical signal lines;

FIG. 12 is a flowchart of a data transmission method of an electronic product according to another embodiment of the present application;

FIG. 13 illustrates a schematic diagram of one embodiment of bus sample clock calibration.

Detailed Description

In order to better understand the above technical solutions, exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

As is well known, no single-wire high-speed communication bus has been found in the industry for miniaturized electronic products. From the above analysis, these known data buses are either low in bandwidth; or the check and retransmission are not supported, and the accuracy of data transmission cannot be ensured; or more physical signal lines are needed to realize the physical connection; in addition, these bus systems do not guarantee a complete synchronization of the data of the nodes of the network.

In view of this, the present application provides a method, a system, a storage medium, and a program product for data transmission of an electronic product, which aim to realize high-speed data transmission using fewer physical signal lines in production and test of the electronic product.

Referring to fig. 1, an electronic product production testing system is described below, which includes: test equipment 20, product under test 10, and at most two physical signal lines 100 that enable the test equipment to communicate with the product under test.

It should be noted that the product to be tested may be various electronic products that need to be tested or calibrated before being shipped from a factory. Such as earphones, microphones, electric toothbrushes, electric shavers, and the like. In this embodiment, taking an earphone as an example, the earphone 10 to be tested further includes a first modulation transceiver module 11 for receiving a test signal and sending an interaction signal, a built-in speaker 13, and a built-in microphone 12, where the built-in microphone 12 is electrically connected to the first modulation transceiver module 11. The first modulation transceiving module 11 modulates response data of the built-in microphone 12 responding to the test signal and transmits the modulated response data to the second modulation transceiving module 24 of the test equipment 20.

The testing equipment sends a testing signal to a product to be tested (namely, an earphone to be tested) through a single physical signal line; the earphone to be tested responds to the test signal to generate an interaction signal, and the interaction signal is sent to the test equipment through a single physical signal line; based on the test signal and the interactive signal of the earphone to be tested and the test equipment, the test equipment calculates the calibration parameters of the earphone to be tested; the test equipment sends the calibration parameters to the earphone to be tested through a single physical signal line; and controlling the to-be-tested earphone to configure the calibration parameters to the to-be-tested earphone, and controlling the test equipment to test the to-be-tested earphone after the calibration parameters are configured.

Referring to fig. 2, a test apparatus 20 is described, which may include: processor 1001, such as a Central Processing Unit (CPU), the processor 1001 may also be other general purpose processors, such as: digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs), other programmable logic devices, and the like. Memory 1005, user interface 1003, network interface 1004, communication bus 1002. Wherein a communication bus 1002 is used to enable connective communication between these components. The user interface 1003 may include an input unit such as a keypad (Keyboard), and the optional user interface 1003 may also include a standard wired interface, a wireless interface. The network interface 1004 may optionally include a wireless interface (e.g., a WI-FI interface). The memory 1005 may be a high-speed RAM memory or a non-volatile memory (e.g., a magnetic disk memory). The memory 1005 may alternatively be a storage device separate from the processor 1001.

The test equipment 20 further comprises a second modulation transceiving module 24 for sending the test signal and receiving the interaction signal, a test speaker 21 for sending the test signal to the headset 10 to be tested, and a test microphone 22 for picking up a response signal of the built-in speaker 13 of the headset 10 to be tested.

It will be appreciated by those skilled in the art that the test device configuration shown in figure 2 does not constitute a definition of a headset production calibration device and may include more or fewer components than shown, or some components in combination, or a different arrangement of components.

As shown in fig. 2, a memory 1005, which is a kind of computer storage medium, may include therein an operating system, a network communication module, a user interface module, and a production test data transmission program. The operating system is a program for managing and controlling hardware and software resources of the headset production testing calibration equipment and supports the production testing data transmission program and the running of other software or programs.

In the earphone production measurement and calibration apparatus shown in fig. 2, the network interface 1004 is mainly used for a background server, and is in data communication with the background server; the processor 1001 may be configured to invoke a production test data transfer program stored in the memory 1005 and perform the steps of the headset production calibration method as described above.

In one embodiment, the processor 1001 may be configured to call a production test data transfer program stored in the memory 1005 and execute the method including:

sending a preset handshake signal to a product to be tested, and receiving a first feedback signal of the product to be tested responding to the preset handshake signal;

and if the times of receiving the first feedback signal exceed a set threshold value, the test equipment and the product to be tested are successfully linked.

and sending a downlink frame header signal to a product to be tested, and receiving an uplink frame header signal of the product to be tested so as to realize the frame structure synchronization of the test equipment and the product to be tested.

sending a downlink frame header signal to a product to be detected, and receiving a second feedback signal of the product to be detected responding to the downlink frame header signal;

if the frequency of receiving the second feedback signal exceeds a set threshold, receiving an uplink frame header signal of the product to be detected;

and if the frequency of receiving the uplink frame header signal exceeds a set threshold, realizing the frame structure synchronization of the test equipment and the product to be tested.

the test equipment and the product to be tested carry out data interaction at most through two physical signal lines.

when one physical signal line is adopted, the frame structure sequentially comprises a downlink frame head area, a downlink data area, an uplink frame head area and an uplink data area.

when one physical signal line is adopted, the frame structure comprises a downlink frame head area and a downlink data area; or the frame structure comprises an uplink frame header area and an uplink data area.

when the physical signal line includes a downlink signal line and an uplink signal line, the frame structure includes a downlink frame header area and a downlink data area in the downlink signal line; the frame structure in the uplink signal line includes an uplink frame header region and an uplink data region.

The downlink data area includes: the system comprises a downlink state area and a downlink real data area, wherein the downlink state area at least comprises a verification result of uplink data of a product to be detected and address information of production test data to be sent to the product to be detected; the downlink real data area at least comprises production and test data sent to a product to be tested and verification information of the production and test data;

the uplink data region includes: the device comprises an uplink state area and an uplink real data area, wherein the uplink state area at least comprises a verification result of production test data of the test equipment and address information of response data to be sent to the test equipment; the uplink real data area at least comprises response data sent to the test equipment and verification information of the response data.

the frame structure further comprises a synchronous sampling clock as a reference for the sampling clocks of the test equipment and the headset to be tested.

The electronic product production testing system sends a preset handshake signal to a product to be tested and receives a first feedback signal of the product to be tested so as to realize the link establishment operation with the product to be tested; and sending equipment attribute information to the product to be tested, wherein the equipment attribute information at least comprises bus sampling clock frequency information. So that the bus sampling clocks of the test equipment and the product to be tested form a basic same frequency relationship. Then, frame head signals are interacted with the product to be detected and a real-time bus sampling clock synchronization calibration mechanism is adopted, so that synchronization with a frame structure of data transmission of the product to be detected is realized; and performing data interaction with the product to be tested according to the synchronized frame structure under the bus sampling clock. Therefore, under the bus sampling clock, the test equipment and the product to be tested perform data interaction at most through two physical signal lines, and high-speed data interaction between the test equipment and the product to be tested in a synchronous frame transmission mode is realized.

Referring to fig. 3, based on the hardware architecture of the electronic product production test system, a first embodiment of the electronic product data transmission method of the present application is provided below, where the electronic product data transmission method is applied to a test equipment end; the data transmission method of the electronic product comprises the following steps:

s100, sending a preset handshake signal to a product to be tested, and receiving a first feedback signal of the product to be tested to realize a link establishment operation with the product to be tested;

the test equipment sends a preset handshake signal to a product to be tested and receives a first feedback signal of the product to be tested so as to realize the link establishment operation with the product to be tested.

In a possible embodiment, step S100 specifically includes:

s110, sending a preset handshake signal to a product to be tested, and receiving a first feedback signal of the product to be tested responding to the preset handshake signal;

the test equipment sends a preset handshake signal to a product to be tested, and receives a first feedback signal of the product to be tested responding to the preset handshake signal.

In particular, in one possible embodiment, the preset handshake signal may be a preset level signal. The testing equipment forms a series of predetermined high and low level sequences on a physical signal line (namely a bus), and then releases the bus to wait for the response of the to-be-tested earphone end; after the earphone terminal to be tested samples the high-low level sequence, it responds to the predetermined high-low level sequence (i.e. the first feedback signal).

It can be understood that the preset handshake signal and the first feedback signal may be various high and low level sequences, and may be freely set according to actual requirements. For example, the preset handshake signal may be set to 1010, and the first feedback signal may be set to 0101.

It should be understood that the specific examples "1010", "0101" of the specific high-low level sequence listed above are only for better understanding of the technical solution of the present application by those skilled in the art, and should not be understood as a specific limitation of the preset handshake signal, the first feedback signal of the present application.

S120, if the number of times of receiving the first feedback signal exceeds a set threshold value, the test equipment and the product to be tested are successfully linked.

When the frequency of receiving the first feedback signal by the test equipment exceeds a set threshold value, the correctness of the connection between the test equipment and the earphone to be tested through the physical signal line is indicated, and the successful link establishment between the test equipment and the product to be tested is indicated. Preparation can be made for the next step of interacting with the device attribute information.

It should be noted that the set threshold may be various values, such as 2,3, 4, 5, etc. For example, if the number of times of receiving the first feedback signal exceeds 3 times, the test equipment and the product to be tested are successfully linked.

S200, sending equipment attribute information to the product to be tested, wherein the equipment attribute information at least comprises bus sampling clock frequency information;

after the testing equipment and the to-be-tested earphone are successfully linked, the testing equipment sends equipment attribute information to the to-be-tested product, wherein the equipment attribute information at least comprises bus sampling clock frequency information.

In particular, in some embodiments, the device attribute information includes version information and bus sampling clock frequency information. And after the link is successfully established, the test equipment sends the version information and the bus sampling clock frequency information to the earphone to be tested. And the earphone to be tested receives the version information and the bus.

And the clock frequency is used for inquiring whether the version information of the local terminal and the bus sampling clock frequency are consistent with those of the test equipment or not. If the bus sampling clock frequency of the to-be-tested earphone does not accord with the bus clock frequency sent by the testing equipment, the to-be-tested earphone adjusts the bus sampling clock frequency of the local end to the bus sampling clock frequency sent by the testing equipment;

and the earphone to be tested replies and sends the version information of the local terminal and the bus sampling clock frequency information to the test equipment. It is understood that in other embodiments, the test device may also adjust its own bus sampling clock frequency according to the reply bus sampling clock frequency information of the headset under test.

And the test equipment and the earphone to be tested interact the attribute information of the equipment through establishing a link. The method not only confirms the correctness of the physical connection of the bus, but also ensures that two communication parties mutually confirm the version information of opposite terminals and the frequency information of the bus sampling clock. After the handshake, both communicating parties confirm that the communicating components are ready.

It is worth mentioning that a set of bus sampling clock calibration mechanism is arranged in the test equipment and the earphone to be tested. It is because the frequency of the bus sampling clock is always in the process of auto-calibration, which enables the communication parties to transition from the link establishment state to the frame synchronization state.

S300, interacting a frame header signal with the product to be detected to realize the synchronization of a frame structure transmitted with the data of the product to be detected;

in this embodiment, when one physical signal line is used, the circuit structures of the test device, the to-be-tested earphone and the physical signal line may refer to the circuit structures of the first embodiment and the fourth embodiment in an invention patent named as "earphone production measurement and calibration system" applied on the same day as this application. Please refer to the circuit structures of fig. 4 and 5. Fig. 4 shows a simplified circuit schematic diagram of an embodiment of the invention patent of headset production calibration system. M1 and M2 in fig. 4 denote NMOS transistors. The physical signal lines in fig. 4 are made up of metal contacts 101,102. Fig. 5 shows a simplified circuit schematic diagram of the fourth embodiment of the invention patent of headset production calibration system. M4 and M5 in fig. 5 denote PMOS transistors. The physical signal lines in fig. 5 are made up of metal contacts 107,108.

To prevent bus deadlock (the communicating parties occupy the bus at the same time and then release the bus at the same time), the communicating parties make the following conventions: (1) when both sides initiate the bus occupation, the testing device can continue to send, and the earphone to be tested should immediately release the bus to receive the signal of the testing device. The earphone to be tested can occupy the bus only when the test equipment does not occupy the bus. (2) After the communication parties send the information, the communication parties should release the bus immediately and must not occupy the bus. The purpose of bus agreement is to prevent the deadlock of the bus, and in order to achieve the purpose, a plurality of agreement modes can be provided; the contents of the convention should not be construed as limiting the present invention.

The physical signal lines may be metal contacts on the headset 10, the test equipment 20 under test. Wherein the metal contacts may be charging contacts or additional contacts in addition to the charging contacts. It should be understood that the physical signal line may also be other components of the headset 10 to be tested that can implement communication connection, such as a metal housing of the headset or a metal fitting that can conduct electricity on the housing.

In the present embodiment, high-speed duplex communication is realized by a single physical signal line. Referring to fig. 6, the frame structure includes a downlink frame header area, a downlink data area, an uplink frame header area, and an uplink data area in sequence.

The method comprises the steps that a test device sends a downlink frame header signal to a product to be tested and receives an uplink frame header signal of the product to be tested so as to achieve frame structure synchronization of the test device and the product to be tested.

In some possible embodiments, the step of sending a downlink frame header signal to a product to be tested and receiving an uplink frame header signal of the product to be tested to achieve frame structure synchronization between the test equipment and the product to be tested specifically includes:

s310, sending a downlink frame header signal to a product to be detected, and receiving a second feedback signal of the product to be detected responding to the downlink frame header signal;

after the test equipment and the earphone to be tested successfully establish a link and the attribute information of the equipment is interacted, the test equipment enters a frame synchronization stage, the test equipment actively initiates frame structure transmission, and a well agreed synchronization sequence is carried at the position of a downlink frame header. For example, in some embodiments, a level signal of '0101' change (i.e. a downlink frame header signal) can be formed on the physical signal line by controlling the on-off state of the MOS transistor in the circuit structure of fig. 4 and 5.

The earphone end to be tested searches the downlink frame header signal '0101', replies a second feedback signal to the test equipment, and informs the test equipment that the earphone to be tested has received the downlink frame header signal. The second feedback signal may be other level signals. The second feedback signal is not specifically limited here.

It should be noted that what is called the second feedback signal is actually: before the earphone to be tested successfully searches frames for N times continuously, the product to be tested releases the bus, so that the testing equipment finds that the uplink frame header signal is always in a bus release state at this time and does not turn over; and after the equipment to be tested continuously searches the downlink frame header signals for N times, starting to send the uplink frame header signals at the corresponding time slot position. When the testing equipment finds that the earphone to be tested starts to send the uplink frame header signal (namely the bus starts to turn over), the testing equipment knows that the earphone to be tested is successfully synchronized. Then the test equipment starts to search frames and feeds back whether the frames are searched successfully or not in the downlink data area. And the earphone to be tested informs the test equipment that the message of successful frame searching is received through the uplink data area of the frame structure. After the test equipment receives the confirmation messages in the continuous N frames, the synchronization of the frame headers of the two sides is confirmed. Whereupon the check and retransmission functions are tested.

S320, if the frequency of receiving the second feedback signal exceeds a set threshold, receiving an uplink frame header signal of the product to be detected;

when the number of times that the to-be-tested earphone continuously and successfully searches the downlink frame header signal exceeds a set threshold value, namely the number of times that the testing equipment receives the second feedback signal exceeds the set threshold value, the bus sampling clock of the to-be-tested earphone end is basically fine-tuned to be consistent with that of the testing equipment end; at the moment, the testing equipment receives the uplink frame head signal sent by the earphone to be tested at the corresponding uplink frame head position; similarly, the uplink frame header signal may also adopt a '0101' level signal.

S330, if the frequency of receiving the uplink frame header signal exceeds a set threshold, the frame structure synchronization of the test equipment and the product to be tested is realized.

The test equipment searches for the uplink frame header signal on the physical signal line, and it should be mentioned that the test equipment can also fine-tune the local bus sampling clock while searching for the uplink frame header. When the number of times that the testing equipment continuously receives the uplink frame header signal of the earphone to be tested exceeds a set threshold value, the transmitting side and the receiving side basically form a synchronous transmission relation.

And S400, performing data interaction with the product to be tested according to the synchronized frame structure under the bus sampling clock.

After both parties can normally receive the header signals (i.e. the downlink header signal and the uplink header signal) of the opposite end, both parties start to fill test data in their respective data areas (before this, these areas are in a bus release state), test the checksum retransmission mechanism, and basically complete frame synchronization after the checksum retransmission mechanism also passes the test.

Specifically, the downlink data region in the frame structure includes: the system comprises a downlink state area and a downlink real data area, wherein the downlink state area at least comprises a verification result of uplink data of a product to be detected and address information of production and test data to be sent to the product to be detected.

Wherein, the downlink status area comprises the check result of the uplink data of the previous frame. If the check fails, the information such as retransmission is needed. In order to reduce the retransmission probability and improve the bus utilization rate, the invention adopts ECC check, and can directly correct a small amount of error codes without retransmission.

In addition, the downlink status area also includes address information of the data to be transmitted in the frame. The two communication parties distinguish the data content through the address information.

The downlink real data area at least comprises production and test data sent to a product to be tested and verification information of the production and test data. Specifically, the test equipment fills test data or configuration data to be issued, performs a verification operation on the test data or the configuration data, and issues the test data or the configuration data together with the tail of the test data or the configuration data.

The uplink data region includes: the device comprises an uplink state area and an uplink real data area, wherein the uplink state area at least comprises a verification result of production test data of the test equipment and address information of response data to be sent to the test equipment.

The uplink state area includes the check result of the previous frame of downlink data, and if the check fails, information such as retransmission is required. The uplink state area also comprises the address of the response data to be transmitted in the frame. The two communication parties distinguish the data content through the address information.

The uplink real data area at least comprises response data sent to the test equipment and verification information of the response data. And filling the response data of the real data area through the earphone to be tested, carrying out verification operation on the response data, adding the response data to the tail part of the data and reporting the response data together.

After the frame synchronization is completed, the following effects are achieved: (1) the bus sampling clocks of both communication parties are highly consistent, an automatic calibration mechanism of the bus sampling clocks is established, and the frequency and the phase of the bus sampling clocks can be aligned in real time; (2) both communication parties have completed negotiation of data checking and retransmission mechanism; in order to reduce the retransmission probability and improve the bus utilization rate, the invention adopts ECC check, and can directly correct a small amount of error codes without retransmission.

After the frame structure synchronization is completed, the communication channel between the test equipment and the headset to be tested is completely stable. And the test equipment and the earphone to be tested perform high-speed data interaction in a synchronous frame transmission mode.

It is noted that in other embodiments, a single physical signal line may also enable high-speed simplex communication. Data of the earphone to be tested and the test equipment are transmitted in a single direction, so that the MOS tube design shown in fig. 4 or fig. 5 is not needed, and only a known inverter output scheme is adopted.

And because of the unidirectional transmission, one end of both communication parties is fixed as a sending party, and the other end is fixed as a receiving end. For example, referring to fig. 7, if the fixed testing device is a sender and the headset to be tested is a receiver, the frame structure includes a downlink frame header signal and a downlink data area. The downlink data area includes: a downlink status area and a downlink real data area. The downlink state area at least comprises a verification result of the uplink data of the product to be detected and address information of the production test data to be sent to the product to be detected. The downlink real data area at least comprises production and test data sent to a product to be tested and verification information of the production and test data.

On the contrary, referring to fig. 8, if the fixed testing device is the receiving side and the headset to be tested is the sending side, the frame structure includes the uplink frame header signal and the uplink data area. The uplink data region includes: an uplink state region and an uplink real data region. The uplink data region includes: the device comprises an uplink state area and an uplink real data area, wherein the uplink state area at least comprises a verification result of production test data of the test equipment and address information of response data to be sent to the test equipment. The uplink real data area at least comprises response data sent to the test equipment and verification information of the response data.

Because this embodiment test equipment and the earphone that awaits measuring have adopted the mode of synchronous frame transmission, and both sides of communication support the automatic calibration of bus sampling clock, and each side of bus all supports data check, error correction, and supports retransmission mechanism, and its transmission bandwidth can reach more than 6Mbps, and through optimizing circuit design, communication rate can be stabilized more than 12Mbps, even higher.

The following describes a schematic structure of a typical frame structure without carrying a synchronous sampling clock through the figures. Referring to fig. 9, fig. 9 is a schematic structural diagram of a frame structure not carrying a synchronous sampling clock in this embodiment. It should be noted that both parties of communication maintain a frame counter. After frame synchronization, the frame counters of the transceiver and transmitter are fully synchronized. Both the transmitter and the receiver transmit and receive bus data in their respective time slots. The data transmitted over the communication channel, denoted b0m, b1m …, is referred to as a bus symbol for ease of description. A sender sends a bus code element under a bus sampling clock; and the receiving party receives the bus code element under the bus sampling clock.

It is worth mentioning that the electronic product data transmission method of the application is not only applied to a production testing system of an electronic product, but also can be applied to communication of some miniaturized electronic components. For example, the electronic product data transmission method is applied to a digital microphone, and the digital microphone can transmit more internal information to the soc chip.

In the embodiment, a preset handshake signal is sent to a product to be tested, and a first feedback signal of the product to be tested is received, so that a link establishment operation with the product to be tested is realized; and sending equipment attribute information to the product to be tested, wherein the equipment attribute information at least comprises bus sampling clock frequency information. So that the bus sampling clocks of the test equipment and the product to be tested form a basic same frequency relationship. Then, frame head signals are interacted with the product to be detected, so that the synchronization of a frame structure for data transmission with the product to be detected is realized; and performing data interaction with the product to be tested according to the synchronized frame structure under the bus sampling clock. Therefore, under the bus sampling clock, the test equipment and the product to be tested perform data interaction at most through two physical signal lines, and high-speed data interaction between the test equipment and the product to be tested in a synchronous frame transmission mode is realized.

Example two

Based on the same inventive concept, the application also provides an embodiment two, which is different from the embodiment one in that the frame structure further comprises a synchronous sampling clock serving as a reference of sampling clocks of the test equipment and the earphone to be tested.

In some embodiments, referring to the invention patent of the invention patent name of earphone calibration method, equipment, earphone test system and storage medium filed on the same day, under the application of earphone production equipment, the synchronous sampling clock is the sampling clock reference of the test equipment and the earphone to be tested, and under the clock reference, the playing clock of the test signal and the sampling clock of analog-to-digital conversion corresponding to the microphone are obtained by the two parties through methods of frequency multiplication or frequency division and the like. On the premise of strict synchronization of playing and sampling, the transfer function H of the system can be calculated by using the formula H ═ fft (x)/fft (y), and the headphone to be tested is calibrated. Wherein x represents an excitation signal, and in this patent, x is a played test signal; y represents a response signal.

By inserting the synchronous sampling clock to be carried at a predetermined position of the frame structure. Referring to fig. 10, fig. 10 is a schematic diagram illustrating a frame structure carrying a synchronous sampling clock. It should be noted that both parties of communication maintain a frame counter. After frame synchronization, the frame counters of the transceiver and transmitter are fully synchronized. Both the transmitter and the receiver transmit and receive bus data in their respective time slots. The data after the modulated synchronous clock is denoted as b0m and b1m …, and is referred to as a bus symbol for convenience of description. A sender sends a bus code element under a bus sampling clock; and the receiving party receives the bus code element under the bus sampling clock.

It should be noted that the modulated synchronous clock in the frame structure is suitable for the single-wire duplex high-speed communication or the single-wire simplex high-speed communication in the first embodiment. It is worth mentioning that, for single-wire simplex high-speed communication, one end of both communication parties is fixed as a sender, and the other end is fixed as a receiver. The synchronous clock is transmitted unidirectionally. The receiver needs to resolve the synchronous clock carried on the bus at the corresponding frame time slot according to the timing sequence agreed by both parties. If necessary, the resolved clock may also be multiplied or divided by a phase-locked loop to be used as a sampling clock for local digital-to-analog conversion or analog-to-digital conversion.

In some other embodiments, referring to fig. 11, the testing device and the to-be-tested earphone use two physical signal lines for data transmission, and the frame structure in the signal line sent by the testing device to the to-be-tested earphone includes a downlink frame header signal and a downlink data area. The downlink data area includes: a downlink status area and a downlink real data area. The downlink state area at least comprises a verification result of the uplink data of the product to be detected and address information of the production test data to be sent to the product to be detected. The downlink real data area at least comprises production and test data sent to a product to be tested and verification information of the production and test data.

The frame structure in the signal line sent by the test equipment to the earphone to be tested comprises an uplink frame head signal and an uplink data area. The uplink data region includes: an uplink state region and an uplink real data region. The uplink data region includes: the device comprises an uplink state area and an uplink real data area, wherein the uplink state area at least comprises a verification result of production test data of the test equipment and address information of response data to be sent to the test equipment. The uplink real data area at least comprises response data sent to the test equipment and verification information of the response data.

The synchronous clock can be modulated and added at the preset position of the frame structure of the communication of the two physical signal lines, namely, the synchronous sampling clock of the testing equipment and the earphone to be tested can be mutually transmitted. In embodiment 1, however, the synchronous sampling clock can be transmitted only in one direction. And the data is transmitted by splitting two signal lines, and the bus bandwidth of each signal line is twice of that of a single signal line in the embodiment.

EXAMPLE III

Based on the same inventive concept, the present application further provides a third embodiment, please refer to fig. 12, and the data transmission method of the electronic product of the third embodiment is applied to a product end to be tested or a testing device end, and considering that a clock synchronization mechanism requires a high-speed bus sampling clock, which may cause power consumption to increase, so that the preferred scheme is to place the data transmission method on one side of the testing device unless one testing device is connected to multiple devices to be tested at the same time, in this case, a clock calibration mechanism is placed on one side of the devices to be tested, and for convenience of description, the present embodiment is described by taking as an example that the clock calibration mechanism is placed on the devices to be tested, and the method includes:

s500, receiving a preset handshake signal of the test equipment, and sending a first feedback signal to the test equipment to realize a link establishment operation with the product to be tested;

s600, receiving bus sampling clock frequency information sent by the product to be tested, and adjusting a bus sampling clock of the local terminal according to the bus sampling clock frequency information;

s700, interacting a frame header signal with the product to be tested to realize the synchronization of a frame structure of data transmission with the test equipment;

and S800, performing data interaction with the test equipment according to the frame structure under the bus sampling clock.

The specific steps of steps S500-S800 can be referred to the corresponding descriptions of embodiments one and two. Only the differences from the first and second embodiments will be described below. The electronic product data transmission method further comprises the following steps:

s910, collecting a downlink signal sent by the test equipment by adopting the bus sampling clock;

for both communication parties, in order to maintain synchronous transmission, the bus sampling clock of each end needs an automatic synchronous calibration mechanism. Since the transceiver modules of the nodes of the communication network are substantially identical, this embodiment takes the transceiver at the end of the to-be-tested earphone as an example to describe the bus clock calibration mechanism of the to-be-tested earphone. The clock calibration mechanism of the test equipment end is the same as that of the earphone end to be tested.

At the end of the earphone to be tested, a receiving module at the end of the earphone to be tested adopts a high-speed clock to acquire bus data in real time. The clock frequency of payload data is taken as a reference clock frequency, and in order to realize the synchronization of clocks of a transmitter and a receiver and realize the anti-interference and anti-jitter of a bus, a bus sampling clock with higher frequency is suggested to be adopted to receive data, namely, a test sampling clock which is in a preset multiplying power with the bus sampling clock is adopted to collect downlink signals sent by test equipment. For example, clk _8X, which is 8 times the frequency of the reference clock, is used as the bus reception clock.

S920, adjusting the bus sampling clock frequency of the product end to be detected according to the relation between the counting result of the bus sampling counter and the preset threshold value.

And the to-be-tested earphone adjusts the bus sampling clock frequency of the to-be-tested product end according to the relation between the counting result of the bus sampling counter and the preset threshold value. Referring to fig. 13, fig. 13 is a schematic diagram illustrating bus sampling clock calibration performed by an earphone terminal to be tested. At clk _8X (i.e., the bus sample clock), the theoretical number of samples per symbol on the bus by the receiving end is 8, i.e., the bus sample counter would count in the order of 1,2,3 … 8. If the count of the bus sampling counter is 8 times when the to-be-tested earphone receives each code element on the bus, the bus sampling clock of the to-be-tested earphone end is consistent with the bus sampling clock of the testing equipment end.

S921, if the counting result of the bus sampling counter is smaller than a preset threshold value, increasing the bus sampling clock frequency of the local terminal;

in the counting process of the bus sampling counter, the bus level is abnormally turned, for example, when the bus sampling counter counts to 6 or 7, different levels are sampled next time, and the bus sampling counter can directly jump to 1; in this case, it is described that the bus sampling clock frequency of the local side (i.e., the side of the earphone to be tested) is lower than the bus clock frequency of the transmitting side (i.e., the side of the test equipment), and the local side should increase the bus sampling clock frequency.

And S922, if the counting result of the bus sampling counter is larger than a preset threshold value, reducing the bus sampling clock frequency of the product end to be detected.

In the counting process of the bus sampling counter, the bus level is abnormally turned, for example, when the bus sampling counter counts to 9 or 10, different levels are sampled next time, and the bus sampling counter can directly jump to 1; in this case, it is described that the bus sampling clock frequency of the local side (i.e., the side of the earphone to be tested) is higher than the bus clock frequency of the transmitting side (i.e., the side of the test equipment), and the local side should decrease the bus sampling clock frequency.

In this embodiment, the bus sampling clock is used to collect the downlink signal sent by the test equipment, and the frequency of the bus sampling clock at the end of the product to be tested is adjusted according to the relationship between the counting result of the bus sampling counter and the preset threshold. The bus sampling clock frequency of the test equipment and the earphone to be tested is adjusted in time, data interaction between the test equipment and the earphone to be tested is guaranteed through two physical signal lines under the same bus sampling clock, and high-speed data interaction between the test equipment and a product to be tested in a synchronous frame transmission mode is achieved. The effect of realizing high-speed data transmission by using fewer physical signal lines is further improved.

The present application also proposes a computer-readable storage medium storing one or more programs, which are executable by one or more processors to implement the steps in the electronic product data transmission method.

The invention also proposes a computer program product comprising a computer program which, when executed by a processor, implements the steps of the electronic product data transmission method as described above.

It should be noted that, for various embodiments of the data transmission method of the electronic product according to the present invention, reference may be made to various embodiments of the computer-readable storage medium and the computer program product of the present invention, which are not further described herein.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It should be noted that in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The application can be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.

While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the application.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.

Claims

1. The data transmission method of the electronic product is characterized by being applied to a test equipment terminal, and comprises the following steps:

2. The method of claim 1, wherein the sending a preset handshake signal to a product under test and receiving a first feedback signal of the product under test to implement a chain establishment operation with the product under test comprises:

3. The method of claim 1, wherein the interacting of the frame header signal with the product under test to achieve synchronization with the frame structure of the data transmission of the product under test comprises:

4. The method of claim 3, wherein the sending a downlink frame header signal to a product under test and receiving an uplink frame header signal of the product under test to achieve frame structure synchronization between the test equipment and the product under test comprises:

5. The method of claim 1, wherein the test equipment and the product under test are in data communication via at most two physical signal lines.

6. The method according to claim 5, wherein when one physical signal line is used, the frame structure comprises a downlink frame header region, a downlink data region, an uplink frame header region, and an uplink data region in this order.

7. The method according to claim 5, wherein when one physical signal line is used, the frame structure includes a downlink frame header area and a downlink data area; or the frame structure comprises an uplink frame header area and an uplink data area.

8. The method according to claim 5, wherein when the physical signal line includes a downlink signal line and an uplink signal line, the frame structure includes a downlink frame header area and a downlink data area in the downlink signal line; the frame structure in the uplink signal line includes an uplink frame header region and an uplink data region.

9. The method according to any of claims 6-8, wherein the downlink data region comprises: the system comprises a downlink state area and a downlink real data area, wherein the downlink state area at least comprises a verification result of uplink data of a product to be detected and address information of production test data to be sent to the product to be detected; the downlink real data area at least comprises production and test data sent to a product to be tested and verification information of the production and test data;

10. The method according to any of claims 1-8, wherein the frame structure further comprises a synchronous sampling clock as a reference for the sampling clocks of the test equipment and the headset under test.

11. A data transmission method of an electronic product is characterized by being applied to a product end to be detected, and the method comprises the following steps:

receiving bus sampling clock frequency information sent by the product to be tested, and adjusting a bus sampling clock of the local terminal according to the bus sampling clock frequency information;

12. The method of claim 11, wherein the product under test comprises a bus sample counter, and wherein the electronic product data transmission method further comprises:

adopting the bus sampling clock to acquire a downlink signal sent by the test equipment;

and adjusting the bus sampling clock frequency of the product end to be detected according to the relation between the counting result of the bus sampling counter and the preset threshold value.

13. The method according to claim 12, wherein the adjusting the bus sampling clock frequency of the product side to be tested according to the relationship between the counting result of the bus sampling counter and the preset threshold value comprises:

if the counting result of the bus sampling counter is smaller than the preset threshold value, increasing the bus sampling clock frequency of the local terminal;

and if the counting result of the bus sampling counter is greater than the preset threshold value, reducing the bus sampling clock frequency of the product end to be detected.

14. An electronic product production testing system, comprising: the device comprises a test device, a product to be tested and at most two physical signal lines for communicating the test device with the product to be tested;

15. A computer readable storage medium, storing one or more programs, which are executable by one or more processors, to implement the steps in the electronic product data transmission method according to any one of claims 1 to 13.

16. A computer program product, characterized in that it comprises a computer program which, when being executed by a processor, carries out the steps of the electronic product data transmission method according to any one of claims 1 to 13.