WO2017024656A1 - 一种降低pwm脉冲调制信号的电磁干扰电路 - Google Patents
一种降低pwm脉冲调制信号的电磁干扰电路 Download PDFInfo
- Publication number
- WO2017024656A1 WO2017024656A1 PCT/CN2015/089466 CN2015089466W WO2017024656A1 WO 2017024656 A1 WO2017024656 A1 WO 2017024656A1 CN 2015089466 W CN2015089466 W CN 2015089466W WO 2017024656 A1 WO2017024656 A1 WO 2017024656A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- circuit
- resistance
- control
- resistor
- load
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/125—Discriminating pulses
- H03K5/1252—Suppression or limitation of noise or interference
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
Definitions
- the present invention relates to the field of electronic technologies, and in particular, to an electromagnetic interference circuit for reducing a PWM pulse modulation signal.
- Embodiments of the present invention provide an electromagnetic interference circuit that reduces a PWM pulse modulation signal.
- the driving frequency of the PWM pulse modulation signal can be adjusted in the heavy load mode, thereby effectively reducing electromagnetic interference.
- Embodiments of the present invention provide an electromagnetic interference circuit for reducing a PWM pulse modulation signal, the circuit including a load detection circuit, a control circuit, a resistance adjustment circuit, and a pulse generation circuit, wherein:
- the load detecting circuit is configured to detect when a load is connected to the load detecting circuit Outputting a mode detection signal to the control circuit according to a current generated by the load;
- the control circuit is connected to the load detection circuit, and configured to output a voltage control signal to the resistance adjustment circuit according to the mode detection signal;
- the resistance adjusting circuit is connected to the control circuit, and is configured to adjust a resistance value of the driving resistor in the resistance adjusting circuit according to the voltage control signal, thereby adjusting a driving frequency of the pulse generating circuit;
- the pulse generating circuit is connected to the resistance adjusting circuit for outputting a PWM pulse modulation signal according to the adjusted driving frequency.
- the control circuit is specifically configured to: if the mode detection signal is at a high level, determine that the circuit is in a heavy load state, and further output the voltage control signal to the resistance adjustment circuit.
- the resistance adjusting circuit comprises a first resistor, a first switching tube and at least one resistance control unit, wherein:
- One end of the first resistor is connected to an input end of the pulse generating circuit, the other end of the first resistor is connected to a first end of the resistance control unit, and a second end point of the resistance control unit a first control port of the control circuit is connected, a third end of the resistance control unit is connected to a first pin of the first switch tube, and a second pin of the first switch tube is connected to the control circuit The second control port is connected, and the third pin of the first switch tube is grounded.
- the resistance control unit comprises a second switching tube and a second resistor, wherein:
- the first pin of the second switch tube and one end of the second resistor are respectively connected to the first end of the resistance control unit, the second pin of the second switch tube, and the first The other end of the two resistors is respectively connected to the third end of the resistance control unit, and the third pin of the second switch tube is connected to the second end of the resistance control unit.
- the at least one resistance control unit is combined into a first series control group and a second series control group, and the first series control group is connected in parallel with the second series control group.
- the load detection circuit comprises a third resistor and an operational amplifier, wherein:
- One end of the third resistor is connected to a first input port of the operational amplifier, and the other end of the third resistor is connected to a second input port of the operational amplifier, an output port of the operational amplifier and the control The input port of the circuit is connected.
- the operational amplifier is a subtractor.
- the switch tube comprises a MOS tube or a triode tube.
- the load detecting circuit when detecting that the load is connected to the load detecting circuit, the load detecting circuit outputs a mode detecting signal to the control circuit according to the current generated by the load; and then the control circuit detects the signal according to the mode. And outputting a voltage control signal to the resistance adjusting circuit; secondly, the resistance adjusting circuit adjusts a resistance value of the driving resistor in the resistance adjusting circuit according to the voltage control signal, thereby adjusting a driving frequency of the pulse generating circuit; The generating circuit outputs a PWM pulse modulation signal according to the adjusted driving frequency.
- the driving frequency of the PWM pulse modulation signal can be adjusted in the heavy load mode, thereby effectively reducing electromagnetic interference.
- FIG. 1 is a schematic structural diagram of a first embodiment of an electromagnetic interference circuit for reducing a PWM pulse modulation signal according to the present invention
- FIG. 2 is a schematic structural diagram of a load detection circuit according to an embodiment of the present invention.
- FIG. 3 is a schematic structural diagram of a second embodiment of an electromagnetic interference circuit for reducing a PWM pulse modulation signal according to the present invention
- FIG. 4 is a schematic structural view of a third embodiment of an electromagnetic interference circuit for reducing a PWM pulse modulation signal according to the present invention.
- FIG. 1 is a schematic structural diagram of a first embodiment of an electromagnetic interference circuit for reducing a PWM pulse modulation signal according to the present invention.
- the circuit package in the embodiment of the present invention include:
- the load detecting circuit 101 is configured to output a mode detection signal to the control circuit according to a current generated by the load when detecting that the load is connected to the load detecting circuit.
- the load detecting circuit 101 includes a third resistor R8 and an operational amplifier, one end of the third resistor is connected to the first input port of the operational amplifier, and the other end of the third resistor is The second input port of the operational amplifier is connected, and an output port of the operational amplifier is connected to an input port of the control circuit, wherein the operational amplifier can be a subtractor.
- the control circuit 102 is coupled to the load detection circuit 101 for outputting the voltage control signal to the resistance adjustment circuit according to the mode detection signal, wherein the control circuit 102 can include a microprocessor.
- the mode detection signal is at a high level, determining that the circuit is in the heavy load state, and further outputting a voltage control signal to the resistance adjustment circuit.
- the voltage control signal can be a high and low level signal, and each of the plurality of control ports of the microprocessor can output different level signals to control the switching of the switch tube in the resistance adjusting circuit 103 to be turned on or off. .
- the resistance adjusting circuit 103 is connected to the control circuit 102, and configured to adjust a resistance value of the driving resistor in the resistance adjusting circuit according to the voltage control signal, thereby adjusting a driving frequency of the pulse generating circuit, wherein the resistor
- the regulating circuit 103 includes at least one resistance control unit, each of which includes a resistor and a switching transistor.
- the pulse generating circuit 104 is connected to the resistance adjusting circuit 103 for outputting a PWM pulse modulated signal according to the adjusted driving frequency.
- the subtractor output The mode detection signal is low level. If the voltage drop is greater than the preset voltage, the subtracter output mode detection signal is at a high level. After the control circuit 102 receives the high level, the control circuit 102 starts the output voltage control signal.
- the voltage control signal can control the conduction of the switch tube, thereby adjusting the resistance value of the resistance adjustment circuit 103, thereby adjusting the driving frequency of the pulse generation circuit, and the pulse generation circuit 104 outputs the PWM pulse modulation signal according to the adjusted drive frequency. To reduce electromagnetic interference.
- the load detection circuit detects that the load is connected to the load check.
- the control circuit outputs a voltage control signal to the resistance adjustment circuit according to the mode detection signal;
- the resistance adjustment circuit is configured according to the And a voltage control signal for adjusting a resistance of the driving resistor in the resistance adjusting circuit to adjust a driving frequency of the pulse generating circuit; and finally a pulse generating circuit outputs a PWM pulse modulation signal according to the adjusted driving frequency.
- the driving frequency of the PWM pulse modulation signal can be adjusted in the heavy load mode, thereby effectively reducing electromagnetic interference.
- FIG. 3 is a schematic structural diagram of a second embodiment of an electromagnetic interference circuit for reducing PWM pulse modulation signals according to the present invention.
- the circuit in the embodiment of the present invention includes:
- the load detecting circuit 301 is configured to output a mode detection signal to the control circuit according to a current generated by the load when detecting that the load is connected to the load detecting circuit.
- the load detection circuit 301 includes a third resistor and an operational amplifier, one end of the third resistor is connected to the first input port of the operational amplifier, and the other end of the third resistor is The second input port of the operational amplifier is connected, and an output port of the operational amplifier is connected to an input port of the control circuit, wherein the operational amplifier can be a subtractor.
- the control circuit 302 is coupled to the load detection circuit 301 for outputting a voltage control signal to the resistance adjustment circuit according to the mode detection signal, wherein the control circuit 302 can include a microprocessor.
- the mode detection signal is at a high level, determining that the circuit is in a heavy load state, and further outputting the voltage control signal to the resistance adjustment circuit.
- the voltage control signal can be a high and low level signal, and each of the plurality of control ports of the microprocessor can output different level signals to control the switching of the switch tube in the resistance adjusting circuit 303 to be turned on or off. .
- the resistance adjusting circuit 303 is connected to the control circuit 302 for adjusting the resistance of the driving resistor in the resistance adjusting circuit according to the voltage control signal, thereby adjusting the driving frequency of the pulse generating circuit.
- the resistance adjusting circuit 303 includes a first resistor, a first switching tube, and at least one resistance control unit, wherein: one end of the first resistor is connected to an input end of the pulse generating circuit, and the first resistor is another One end is connected to the first end of the resistance control unit, and the resistance control a second end of the unit is connected to the first control port of the control circuit, a third end of the resistance control unit is connected to the first pin of the first switch tube, and a second tube of the first switch tube The pin is connected to the second control port of the control circuit, and the third pin of the first switch tube is grounded, wherein the switch tube may include a MOS tube or a triode.
- the resistance control unit includes a second switch tube and a second resistor, wherein: the first pin of the second switch tube and one end of the second resistor are respectively opposite to the resistor control unit An end point is connected, the second pin of the second switch tube and the other end of the second resistor are respectively connected to the third end of the resistance control unit, and the third tube of the second switch tube A foot is coupled to the second end of the resistance control unit.
- the first switch tube can be in an on state according to the voltage control signal output by the control circuit 302.
- the second switch tube is in an off state according to the voltage control signal output by the control circuit 302
- the first resistor and the second The resistors are connected in series, and the resistance of the resistance adjusting circuit 303 is the sum of the resistances of the first resistor and the second resistor; when the second switching transistor is in the conducting state according to the voltage control signal output by the control circuit 302, the second resistor is short-circuited, and the resistor
- the resistance of the adjustment circuit 303 is the resistance of the first resistor.
- the pulse generating circuit 304 is connected to the resistance adjusting circuit 303 for outputting a PWM pulse modulated signal according to the adjusted driving frequency.
- the control circuit 302 starts the output voltage control signal.
- the voltage control signal can control the conduction of the switch tube, thereby adjusting the resistance value of the resistance adjusting circuit 303, thereby adjusting the driving frequency of the pulse generating circuit, and the pulse generating circuit 304 outputs the PWM pulse modulation according to the adjusted driving frequency. Signals to reduce electromagnetic interference.
- the load detecting circuit when detecting that the load is connected to the load detecting circuit, the load detecting circuit outputs a mode detecting signal to the control circuit according to the current generated by the load; and then the control circuit detects the mode according to the mode. a signal outputting a voltage control signal to the resistance adjusting circuit; and secondly, a resistance adjusting circuit adjusts the resistance adjusting circuit according to the voltage control signal.
- the resistance of the driving resistor is further adjusted to further adjust the driving frequency of the pulse generating circuit; finally, the pulse generating circuit outputs a PWM pulse modulation signal according to the adjusted driving frequency.
- the driving frequency of the PWM pulse modulation signal can be adjusted in the heavy load mode, thereby effectively reducing electromagnetic interference.
- FIG. 4 is a schematic structural diagram of a third embodiment of an electromagnetic interference circuit for reducing PWM pulse modulation signals according to the present invention.
- the circuit in the embodiment of the present invention includes:
- the load detecting circuit 401 is configured to output a mode detection signal to the control circuit according to a current generated by the load when detecting that the load is connected to the load detecting circuit.
- the load detection circuit 401 includes a third resistor and an operational amplifier, one end of the third resistor is connected to the first input port of the operational amplifier, and the other end of the third resistor is The second input port of the operational amplifier is connected, and an output port of the operational amplifier is connected to an input port of the control circuit, wherein the operational amplifier can be a subtractor.
- the control circuit 402 is coupled to the load detection circuit 401 for outputting a voltage control signal to the resistance adjustment circuit according to the mode detection signal, wherein the control circuit 402 can include a microprocessor.
- the mode detection signal is at a high level, determining that the circuit is in a heavy load state, and further outputting the voltage control signal to the resistance adjustment circuit.
- the voltage control signal can be a high and low level signal, and each of the plurality of control ports of the microprocessor can output different level signals to control the switching of the switching tube in the resistance adjusting circuit 403 to be turned on or off. . .
- the resistance adjusting circuit 403 is connected to the control circuit 402 for adjusting the resistance of the driving resistor in the resistance adjusting circuit according to the voltage control signal, thereby adjusting the driving frequency of the pulse generating circuit.
- the resistance adjusting circuit 403 includes a first resistor, a first switching tube, and at least one resistance control unit, wherein: one end of the first resistor is connected to an input end of the pulse generating circuit, and the first resistor is another One end is connected to the first end of the resistance control unit, the second end of the resistance control unit is connected to the first control port of the control circuit, and the third end of the resistance control unit is opposite to the first switch a first pin of the tube is connected, a second pin of the first switch is connected to a second control port of the control circuit, and a third pin of the first switch is grounded, wherein
- the switch tube may include a MOS tube or a triode.
- the resistance control unit includes a second switch tube and a second resistor, wherein: the first pin of the second switch tube and one end of the second resistor are respectively opposite to the resistor control unit An end point is connected, the second pin of the second switch tube and the other end of the second resistor are respectively connected to the third end of the resistance control unit, and the third tube of the second switch tube A foot is coupled to the second end of the resistance control unit.
- the at least one resistance control unit is combined into a first series control group and a second series control group, and the first series control group is connected in parallel with the second series control group.
- the resistance adjusting circuit 403 includes six resistance control units, and the first series control group and the second series control group respectively include three resistance control units, the first series control group and the The second series control group is respectively connected to the first pin and the third pin of the first switch, and the second pin of the switch tube in each resistance control unit is connected to the control port of the control circuit 402, when a certain resistor When the switching transistor in the control unit is in an on state according to the voltage control signal output from the control circuit 402, the resistance in the resistance control unit is short-circuited.
- the resistance of the resistance adjusting circuit 403 is the resistance R1.
- the resistance value of the resistance adjusting circuit 403 is the parallel resistance of R1+(R2+R4+R6) and (R3+R5+R7) if the switching tube in each resistance control unit is in the off state.
- the resistor R2 is short-circuited, and the resistance of the resistance adjusting circuit 403 is a parallel resistance of R1+(R4+R6) and (R3+R5+R7). Therefore, the resistance of the resistance adjusting circuit 403 can be adjusted by controlling the on or off of each of the at least one resistance control unit.
- the pulse generation circuit 404 is connected to the resistance adjustment circuit 403 for outputting a PWM pulse modulation signal according to the adjusted drive frequency.
- the control circuit 402 starts the output voltage control signal.
- the voltage control signal can control the conduction of the switch tube, thereby adjusting the resistance value of the resistance adjustment circuit 403, thereby adjusting the driving frequency of the pulse generation circuit.
- the rush generation circuit 404 outputs a PWM pulse modulation signal according to the adjusted drive frequency, thereby reducing electromagnetic interference.
- the load detecting circuit when detecting that the load is connected to the load detecting circuit, the load detecting circuit outputs a mode detecting signal to the control circuit according to the current generated by the load; and then the control circuit detects the mode according to the mode. a signal outputting a voltage control signal to the resistance adjusting circuit; secondly, the resistance adjusting circuit adjusts a resistance value of the driving resistor in the resistance adjusting circuit according to the voltage control signal, thereby adjusting a driving frequency of the pulse generating circuit; The pulse generating circuit outputs a PWM pulse modulation signal according to the adjusted driving frequency.
- the driving frequency of the PWM pulse modulation signal can be adjusted in the heavy load mode, thereby effectively reducing electromagnetic interference.
- the program may be stored in a computer readable storage medium, and the storage medium may include: Flash disk, read-only memory (English: Read-Only Memory, referred to as: ROM), random accessor (English: Random Access Memory, referred to as: RAM), disk or optical disk.
- ROM Read-Only Memory
- RAM Random Access Memory
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Electromagnetism (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electronic Switches (AREA)
- Amplifiers (AREA)
Abstract
一种降低PWM脉冲调制信号的电磁干扰电路,包括:负载检测电路(101),用于当检测到负载连接到所述负载检测电路(101)时,根据所述负载产生的电流,向控制电路(102)输出模式检测信号;控制电路(102),与所述负载检测电路(101)连接,用于根据所述模式检测信号,向电阻调节电路(103)输出电压控制信号;电阻调节电路(103),与所述控制电路(102)连接,用于根据所述电压控制信号,调节所述电阻调节电路(103)中的驱动电阻的阻值,进而调整脉冲发生电路(104)的驱动频率;脉冲发生电路(104),与所述电阻调节电路(103)连接,用于根据调整的所述驱动频率,输出PWM脉冲调制信号。可以在重载模式下,调整PWM脉冲调制信号的驱动频率,从而有效的减少电磁干扰。
Description
本发明要求2015年8月12日递交的发明名称为“一种降低PWM脉冲调制信号的电磁干扰电路”的申请号201510492764.1的在先申请优先权,上述在先申请的内容以引入的方式并入本文本中。
本发明涉及电子技术领域,尤其涉及一种降低PWM脉冲调制信号的电磁干扰电路。
随着脉宽调制(PWM,Pulse Width Modulation)技术的开关电源的开关频率不断提高,导致引发产生电磁干扰。开关变换器的电磁干扰的峰值主要集中在开关频率的倍频处,由于它是一个以开关频率为基波的离散频谱,这些谐波成分通过传输线和空间电磁场向外传播,从而造成了传导和辐射干扰问题,不但严重污染了周围电磁环境,而且对附近的电气设备造成电磁干扰。在现有技术方案中,为了降低开关变换器的电磁干扰,通常采用增加少量的电阻、电容及一些集成运放元件来实现,并且PWM集成电路多使用固定模式,不能根据重轻载的变化做出模式的调整,在重载的情况下,由于电流的变化会比较大,电压纹波的变化也会比较大,造成严重的电磁干扰。
发明内容
本发明实施例提供一种降低PWM脉冲调制信号的电磁干扰电路。可以在重载模式下,调整PWM脉冲调制信号的驱动频率,从而有效的减少电磁干扰。
本发明实施例提供了一种降低PWM脉冲调制信号的电磁干扰电路,所述电路包括负载检测电路、控制电路、电阻调节电路以及脉冲发生电路,其中:
所述负载检测电路,用于当检测到负载连接到所述负载检测电路时,根
据所述负载产生的电流,向所述控制电路输出模式检测信号;
所述控制电路,与所述负载检测电路连接,用于根据所述模式检测信号,向所述电阻调节电路输出电压控制信号;
所述电阻调节电路,与所述控制电路连接,用于根据所述电压控制信号,调节所述电阻调节电路中的驱动电阻的阻值,进而调整所述脉冲发生电路的驱动频率;
所述脉冲发生电路,与所述电阻调节电路连接,用于根据调整的所述驱动频率,输出PWM脉冲调制信号。
其中,所述控制电路具体用于:若所述模式检测信号为高电平,则确定所述电路处于重载状态,进而向所述电阻调节电路输出所述电压控制信号。
其中,所述电阻调节电路包括第一电阻、第一开关管以及至少一个电阻控制单元,其中:
所述第一电阻的一端与所述脉冲发生电路的输入端连接,所述第一电阻的另一端与所述电阻控制单元的第一端点连接,所述电阻控制单元的第二端点与所述控制电路的第一控制端口连接,所述电阻控制单元的第三端点与所述第一开关管的第一管脚连接,所述第一开关管的第二管脚与所述控制电路的第二控制端口连接,所述第一开关管的第三管脚接地。
其中,所述电阻控制单元包括第二开关管以及第二电阻,其中:
所述第二开关管的第一管脚以及所述第二电阻的一端分别与所述电阻控制单元的所述第一端点连接,所述第二开关管的第二管脚以及所述第二电阻的另一端分别与所述电阻控制单元的所述第三端点连接,所述第二开关管的第三管脚与所述电阻控制单元的所述第二端点连接。
其中,所述至少一个电阻控制单元组合成第一串联控制组以及第二串联控制组,所述第一串联控制组与所述第二串联控制组并联。
其中,所述负载检测电路包括第三电阻以及运算放大器,其中:
所述第三电阻的一端与所述运算放大器的第一输入端口连接,所述第三电阻的另一端与所述运算放大器的第二输入端口连接,所述运算放大器的输出端口与所述控制电路的输入端口连接。
其中,所述运算放大器为减法器。
其中,所述开关管包括MOS管或三极管。
实施本发明实施例,首先负载检测电路当检测到负载连接到所述负载检测电路时,根据所述负载产生的电流,向所述控制电路输出模式检测信号;然后控制电路根据所述模式检测信号,向所述电阻调节电路输出电压控制信号;其次电阻调节电路根据所述电压控制信号,调节所述电阻调节电路中的驱动电阻的阻值,进而调整所述脉冲发生电路的驱动频率;最后脉冲发生电路根据调整的所述驱动频率,输出PWM脉冲调制信号。可以在重载模式下,调整PWM脉冲调制信号的驱动频率,从而有效的减少电磁干扰。
为了更清楚地说明本发明实施例的技术方案,下面将对实施例描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1是本发明提出的一种降低PWM脉冲调制信号的电磁干扰电路的第一实施例的结构示意图;
图2是本发明实施例提出的一种负载检测电路的结构示意图;
图3是本发明提出的一种降低PWM脉冲调制信号的电磁干扰电路的第二实施例的结构示意图;
图4是本发明提出的一种降低PWM脉冲调制信号的电磁干扰电路的第三实施例的结构示意图。
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
请参考图1,图1是本发明提出的一种降低PWM脉冲调制信号的电磁干扰电路的第一实施例的结构示意图。如图所示,本发明实施例中的电路包
括:
负载检测电路101,用于当检测到负载连接到所述负载检测电路时,根据所述负载产生的电流,向所述控制电路输出模式检测信号。
具体的,如图2所示,负载检测电路101包括第三电阻R8以及运算放大器,所述第三电阻的一端与所述运算放大器的第一输入端口连接,所述第三电阻的另一端与所述运算放大器的第二输入端口连接,所述运算放大器的输出端口与所述控制电路的输入端口连接,其中,运算放大器可以为减法器。
控制电路102,与负载检测电路101连接,用于根据所述模式检测信号,向所述电阻调节电路输出所述电压控制信号,其中,控制电路102可以包括微处理器。
具体的,若所述模式检测信号为高电平,则确定所述电路处于所述重载状态,进而向所述电阻调节电路输出电压控制信号。其中,电压控制信号可以为高低电平信号,微处理器的多个控制端口中的每个控制端口可以输出不同的电平信号,以控制电阻调节电路103中开关管的到导通或断开。
电阻调节电路103,与所述控制电路102连接,用于根据所述电压控制信号,调节所述电阻调节电路中的驱动电阻的阻值,进而调整所述脉冲发生电路的驱动频率,其中,电阻调节电路103包括至少一个电阻控制单元,每个电阻控制单元包括一个电阻和一个开关管。
脉冲发生电路104,与电阻调节电路103连接,用于根据调整的所述驱动频率,输出PWM脉冲调制信号。
需要说明的是,当检测到负载连接到电阻R8的两端时,产生的电流流经电阻R8,在电阻R8的两端形成压降,如果该压降不大于预设电压,则减法器输出的模式检测信号为低电平,如果该压降大于预设电压,则减法器输出模式检测信号为高电平,在控制电路102接收到高电平之后,控制电路102启动输出电压控制信号,该电压控制信号可以控制开关管的导通,从而调节电阻调节电路103的阻值,进而调整所述脉冲发生电路的驱动频率,脉冲发生电路104根据调整的所述驱动频率,输出PWM脉冲调制信号,从而降低电磁干扰。
在本发明实施例中,首先负载检测电路当检测到负载连接到所述负载检
测电路时,根据所述负载产生的电流,向所述控制电路输出模式检测信号;然后控制电路根据所述模式检测信号,向所述电阻调节电路输出电压控制信号;其次电阻调节电路根据所述电压控制信号,调节所述电阻调节电路中的驱动电阻的阻值,进而调整所述脉冲发生电路的驱动频率;最后脉冲发生电路根据调整的所述驱动频率,输出PWM脉冲调制信号。可以在重载模式下,调整PWM脉冲调制信号的驱动频率,从而有效的减少电磁干扰。
请参考图3,图3是本发明提出的一种降低PWM脉冲调制信号的电磁干扰电路的第二实施例的结构示意图。如图所示,本发明实施例中的电路包括:
负载检测电路301,用于当检测到负载连接到所述负载检测电路时,根据所述负载产生的电流,向所述控制电路输出模式检测信号。
具体的,如图2所示,负载检测电路301包括第三电阻以及运算放大器,所述第三电阻的一端与所述运算放大器的第一输入端口连接,所述第三电阻的另一端与所述运算放大器的第二输入端口连接,所述运算放大器的输出端口与所述控制电路的输入端口连接,其中,运算放大器可以为减法器。
控制电路302,与负载检测电路301连接,用于根据所述模式检测信号,向所述电阻调节电路输出电压控制信号,其中,控制电路302可以包括微处理器。
具体的,若所述模式检测信号为高电平,则确定所述电路处于重载状态,进而向所述电阻调节电路输出所述电压控制信号。其中,电压控制信号可以为高低电平信号,微处理器的多个控制端口中的每个控制端口可以输出不同的电平信号,以控制电阻调节电路303中开关管的到导通或断开。
电阻调节电路303,与所述控制电路302连接,用于根据所述电压控制信号,调节所述电阻调节电路中的驱动电阻的阻值,进而调整所述脉冲发生电路的驱动频率。
具体的,电阻调节电路303包括第一电阻、第一开关管以及至少一个电阻控制单元,其中:所述第一电阻的一端与所述脉冲发生电路的输入端连接,所述第一电阻的另一端与所述电阻控制单元的第一端点连接,所述电阻控制
单元的第二端点与所述控制电路的第一控制端口连接,所述电阻控制单元的第三端点与所述第一开关管的第一管脚连接,所述第一开关管的第二管脚与所述控制电路的第二控制端口连接,所述第一开关管的第三管脚接地,其中,开关管可以包括MOS管或三极管。
进一步的,所述电阻控制单元包括第二开关管以及第二电阻,其中:所述第二开关管的第一管脚以及所述第二电阻的一端分别与所述电阻控制单元的所述第一端点连接,所述第二开关管的第二管脚以及所述第二电阻的另一端分别与所述电阻控制单元的所述第三端点连接,所述第二开关管的第三管脚与所述电阻控制单元的所述第二端点连接。
需要说明的是,第一开关管可以根据控制电路302输出的电压控制信号处于导通状态,当第二开关管根据控制电路302输出的电压控制信号处于断开状态时,第一电阻与第二电阻串联,电阻调节电路303的阻值为第一电阻和第二电阻的阻值之和;当第二开关管根据控制电路302输出的电压控制信号处于导通状态时,第二电阻短路,电阻调节电路303的阻值为第一电阻的阻值。
脉冲发生电路304,与电阻调节电路303连接,用于根据调整的所述驱动频率,输出PWM脉冲调制信号。
需要说明的是,当检测到负载连接到电阻R8的两端时,产生的电流流经电阻R8,在电阻R8的两端形成压降,如果该压降不大于预设电压,则减法器输出的模式检测信号为低电平,如果该压降大于预设电压,则减法器输出模式检测信号为高电平,在控制电路302接收到高电平之后,则控制电路302启动输出电压控制信号,该电压控制信号可以控制开关管的导通,从而调节电阻调节电路303的阻值,进而调整所述脉冲发生电路的驱动频率,脉冲发生电路304根据调整的所述驱动频率,输出PWM脉冲调制信号,从而降低电磁干扰。
在本发明实施例中,首先负载检测电路当检测到负载连接到所述负载检测电路时,根据所述负载产生的电流,向所述控制电路输出模式检测信号;然后控制电路根据所述模式检测信号,向所述电阻调节电路输出电压控制信号;其次电阻调节电路根据所述电压控制信号,调节所述电阻调节电路中的
驱动电阻的阻值,进而调整所述脉冲发生电路的驱动频率;最后脉冲发生电路根据调整的所述驱动频率,输出PWM脉冲调制信号。可以在重载模式下,调整PWM脉冲调制信号的驱动频率,从而有效的减少电磁干扰。
请参考图4,图4是本发明提出的一种降低PWM脉冲调制信号的电磁干扰电路的第三实施例的结构示意图。如图所示,本发明实施例中的电路包括:
负载检测电路401,用于当检测到负载连接到所述负载检测电路时,根据所述负载产生的电流,向所述控制电路输出模式检测信号。
具体的,如图2所示,负载检测电路401包括第三电阻以及运算放大器,所述第三电阻的一端与所述运算放大器的第一输入端口连接,所述第三电阻的另一端与所述运算放大器的第二输入端口连接,所述运算放大器的输出端口与所述控制电路的输入端口连接,其中,运算放大器可以为减法器。
控制电路402,与负载检测电路401连接,用于根据所述模式检测信号,向所述电阻调节电路输出电压控制信号,其中,控制电路402可以包括微处理器。
具体的,若所述模式检测信号为高电平,则确定所述电路处于重载状态,进而向所述电阻调节电路输出所述电压控制信号。其中,电压控制信号可以为高低电平信号,微处理器的多个控制端口中的每个控制端口可以输出不同的电平信号,以控制电阻调节电路403中开关管的到导通或断开。。
电阻调节电路403,与所述控制电路402连接,用于根据所述电压控制信号,调节所述电阻调节电路中的驱动电阻的阻值,进而调整所述脉冲发生电路的驱动频率。
具体的,电阻调节电路403包括第一电阻、第一开关管以及至少一个电阻控制单元,其中:所述第一电阻的一端与所述脉冲发生电路的输入端连接,所述第一电阻的另一端与所述电阻控制单元的第一端点连接,所述电阻控制单元的第二端点与所述控制电路的第一控制端口连接,所述电阻控制单元的第三端点与所述第一开关管的第一管脚连接,所述第一开关管的第二管脚与所述控制电路的第二控制端口连接,所述第一开关管的第三管脚接地,其中,
开关管可以包括MOS管或三极管。
进一步的,所述电阻控制单元包括第二开关管以及第二电阻,其中:所述第二开关管的第一管脚以及所述第二电阻的一端分别与所述电阻控制单元的所述第一端点连接,所述第二开关管的第二管脚以及所述第二电阻的另一端分别与所述电阻控制单元的所述第三端点连接,所述第二开关管的第三管脚与所述电阻控制单元的所述第二端点连接。
进一步的,所述至少一个电阻控制单元组合成第一串联控制组以及第二串联控制组,所述第一串联控制组与所述第二串联控制组并联。
如图4所示,电阻调节电路403包括6个电阻控制单元,所述第一串联控制组与所述第二串联控制组分别包括3个电阻控制单元,所述第一串联控制组与所述第二串联控制组分别连接到第一开关的第一管脚以及第三管脚,并且每个电阻控制单元中的开关管的第二管脚与控制电路402的控制端口连接,当某个电阻控制单元中的开关管根据控制电路402输出的电压控制信号处于导通状态时,该电阻控制单元中的电阻短路。例如:在第一开关管Q7根据控制电路402输出的电压控制信号处于导通状态时,若每个电阻控制单元中的开关管均处于导通状态,则电阻调节电路403的阻值为电阻R1的阻值,若每个电阻控制单元中的开关管均处于断开状态,则电阻调节电路403的阻值为R1+(R2+R4+R6)与(R3+R5+R7)并联阻值,若Q1处于导通状态,则电阻R2短路,电阻调节电路403的阻值为R1+(R4+R6)与(R3+R5+R7)并联阻值。因此,通过对至少一个电阻控制单元中的每个开关管的导通或断开控制,可以调节电阻调节电路403的阻值。
脉冲发生电路404,与电阻调节电路403连接,用于根据调整的所述驱动频率,输出PWM脉冲调制信号。
需要说明的是,当检测到负载连接到电阻R8的两端时,产生的电流流经电阻R8,在电阻R8的两端形成压降,如果该压降不大于预设电压,则减法器输出的模式检测信号为低电平,如果该压降大于预设电压,则减法器输出模式检测信号为高电平,在控制电路402接收到高电平之后,则控制电路402启动输出电压控制信号,该电压控制信号可以控制开关管的导通,从而调节电阻调节电路403的阻值,进而调整所述脉冲发生电路的驱动频率,脉
冲发生电路404根据调整的所述驱动频率,输出PWM脉冲调制信号,从而降低电磁干扰。
在本发明实施例中,首先负载检测电路当检测到负载连接到所述负载检测电路时,根据所述负载产生的电流,向所述控制电路输出模式检测信号;然后控制电路根据所述模式检测信号,向所述电阻调节电路输出电压控制信号;其次电阻调节电路根据所述电压控制信号,调节所述电阻调节电路中的驱动电阻的阻值,进而调整所述脉冲发生电路的驱动频率;最后脉冲发生电路根据调整的所述驱动频率,输出PWM脉冲调制信号。可以在重载模式下,调整PWM脉冲调制信号的驱动频率,从而有效的减少电磁干扰。
需要说明的是,对于前述的各个方法实施例,为了简单描述,故将其都表述为一系列的动作组合,但是本领域技术人员应该知悉,本发明并不受所描述的动作顺序的限制,因为依据本发明,某一些步骤可以采用其他顺序或者同时进行。其次,本领域技术人员也应该知悉,说明书中所描述的实施例均属于优选实施例,所涉及的动作和模块并不一定是本发明所必须的。
在上述实施例中,对各个实施例的描述都各有侧重,某个实施例中没有详细描述的部分,可以参见其他实施例的相关描述。
本领域普通技术人员可以理解上述实施例的各种方法中的全部或部分步骤是可以通过程序来指令相关的硬件来完成,该程序可以存储于一计算机可读存储介质中,存储介质可以包括:闪存盘、只读存储器(英文:Read-Only Memory,简称:ROM)、随机存取器(英文:Random Access Memory,简称:RAM)、磁盘或光盘等。
以上对本发明实施例所提供的内容下载方法及相关设备、系统进行了详细介绍,本文中应用了具体个例对本发明的原理及实施方式进行了阐述,以上实施例的说明只是用于帮助理解本发明的方法及其核心思想;同时,对于本领域的一般技术人员,依据本发明的思想,在具体实施方式及应用范围上均会有改变之处,综上所述,本说明书内容不应理解为对本发明的限制。
Claims (14)
- 一种降低PWM脉冲调制信号的电磁干扰电路,其中,所述电路包括负载检测电路、控制电路、电阻调节电路以及脉冲发生电路,其中:所述负载检测电路,用于当检测到负载连接到所述负载检测电路时,根据所述负载产生的电流,向所述控制电路输出模式检测信号;所述控制电路,与所述负载检测电路连接,用于根据所述模式检测信号,向所述电阻调节电路输出电压控制信号;所述电阻调节电路,与所述控制电路连接,用于根据所述电压控制信号,调节所述电阻调节电路中的驱动电阻的阻值,进而调整所述脉冲发生电路的驱动频率;所述脉冲发生电路,与所述电阻调节电路连接,用于根据调整的所述驱动频率,输出PWM脉冲调制信号。
- 如权利要求1所述的电路,其中,所述控制电路具体用于:若所述模式检测信号为高电平,则确定所述电路处于重载状态,进而向所述电阻调节电路输出所述电压控制信号。
- 如权利要求1所述的电路,其中,所述电阻调节电路包括第一电阻、第一开关管以及至少一个电阻控制单元,其中:所述第一电阻的一端与所述脉冲发生电路的输入端连接,所述第一电阻的另一端与所述电阻控制单元的第一端点连接,所述电阻控制单元的第二端点与所述控制电路的第一控制端口连接,所述电阻控制单元的第三端点与所述第一开关管的第一管脚连接,所述第一开关管的第二管脚与所述控制电路的第二控制端口连接,所述第一开关管的第三管脚接地。
- 如权利要求3所述的电路,其中,所述电阻控制单元包括第二开关管以及第二电阻,其中:所述第二开关管的第一管脚以及所述第二电阻的一端分别与所述电阻控制单元的所述第一端点连接,所述第二开关管的第二管脚以及所述第二电阻的另一端分别与所述电阻控制单元的所述第三端点连接,所述第二开关管的第三管脚与所述电阻控制单元的所述第二端点连接。
- 如权利要求4所述的电路,其中,所述至少一个电阻控制单元组合成第一串联控制组以及第二串联控制组,所述第一串联控制组与所述第二串联控制组并联。
- 如权利要求1所述的电路,其中,所述负载检测电路包括第三电阻以及运算放大器,其中:所述第三电阻的一端与所述运算放大器的第一输入端口连接,所述第三电阻的另一端与所述运算放大器的第二输入端口连接,所述运算放大器的输出端口与所述控制电路的输入端口连接。
- 如权利要求6所述的电路,其中,所述运算放大器为减法器。
- 如权利要求1所述的电路,其中,所述开关管包括MOS管或三极管。
- 如权利要求2所述的电路,其中,所述开关管包括MOS管或三极管。
- 如权利要求3所述的电路,其中,所述开关管包括MOS管或三极管。
- 如权利要求4所述的电路,其中,所述开关管包括MOS管或三极管。
- 如权利要求5所述的电路,其中,所述开关管包括MOS管或三极管。
- 如权利要求6所述的电路,其中,所述开关管包括MOS管或三极管。
- 如权利要求7所述的电路,其中,所述开关管包括MOS管或三极管。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/904,863 US9819333B2 (en) | 2015-08-12 | 2015-09-11 | Circuit for decreasing an electromagnetic interference of a PWM pulse modulation signal |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510492764.1 | 2015-08-12 | ||
| CN201510492764.1A CN105186856A (zh) | 2015-08-12 | 2015-08-12 | 一种降低pwm脉冲调制信号的电磁干扰电路 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2017024656A1 true WO2017024656A1 (zh) | 2017-02-16 |
Family
ID=54908759
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/CN2015/089466 Ceased WO2017024656A1 (zh) | 2015-08-12 | 2015-09-11 | 一种降低pwm脉冲调制信号的电磁干扰电路 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US9819333B2 (zh) |
| CN (1) | CN105186856A (zh) |
| WO (1) | WO2017024656A1 (zh) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111063723A (zh) * | 2019-11-25 | 2020-04-24 | 深圳深爱半导体股份有限公司 | 开关集成控制器和三极管芯片 |
| US11029545B2 (en) * | 2018-05-18 | 2021-06-08 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Thin film transistor liquid crystal display (TFT-LCD) and the driving circuit and switching power supply thereof |
| CN113852145A (zh) * | 2021-08-16 | 2021-12-28 | 芯海科技(深圳)股份有限公司 | 一种负载检测电路及其检测方法、集成电路以及电子设备 |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108667289B (zh) * | 2017-03-29 | 2020-11-27 | 赤多尼科两合股份有限公司 | 一种供电装置及供电方法 |
| CN108665859B (zh) * | 2018-08-01 | 2023-12-29 | 合肥惠科金扬科技有限公司 | 背光源控制电路及背光源 |
| CN110992863B (zh) * | 2019-11-25 | 2023-05-30 | 京东方科技集团股份有限公司 | 电磁干扰抑制电路及其驱动方法、电子设备 |
| CN112234806B (zh) * | 2020-10-15 | 2025-01-28 | 珠海格力电器股份有限公司 | 一种功率开关驱动电路、方法及电器设备 |
| CN114640402B (zh) * | 2022-03-11 | 2024-03-15 | 云南创芯微电子科技有限公司 | 一种双共模电感接收通信脉冲电流信号的方法及其电路 |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1767304A (zh) * | 2004-10-29 | 2006-05-03 | 三星电子株式会社 | 功率因子补偿装置及方法 |
| US20120194227A1 (en) * | 2011-02-01 | 2012-08-02 | Richpower Microelectronics Corporation | Jittering frequency control circuit and method for a switching mode power supply |
| CN103036447A (zh) * | 2012-12-14 | 2013-04-10 | 深圳市新国都技术股份有限公司 | 一种最大功率可调式开关电源 |
| CN103904899A (zh) * | 2012-12-25 | 2014-07-02 | 比亚迪股份有限公司 | 一种开关电源 |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100670181B1 (ko) * | 2005-07-27 | 2007-01-16 | 삼성에스디아이 주식회사 | 전원 공급 장치 및 이를 포함하는 플라즈마 표시 장치 |
| TWI491889B (zh) * | 2011-02-28 | 2015-07-11 | Hon Hai Prec Ind Co Ltd | 電阻測量電路及具有該電阻測量電路的電子裝置 |
| TW201238227A (en) * | 2011-03-04 | 2012-09-16 | Asian Power Devices Inc | A switch power supply with frequency tuner |
| CN103312146A (zh) * | 2012-03-16 | 2013-09-18 | 鸿富锦精密工业(深圳)有限公司 | 电源开关电路 |
-
2015
- 2015-08-12 CN CN201510492764.1A patent/CN105186856A/zh active Pending
- 2015-09-11 US US14/904,863 patent/US9819333B2/en active Active
- 2015-09-11 WO PCT/CN2015/089466 patent/WO2017024656A1/zh not_active Ceased
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1767304A (zh) * | 2004-10-29 | 2006-05-03 | 三星电子株式会社 | 功率因子补偿装置及方法 |
| US20120194227A1 (en) * | 2011-02-01 | 2012-08-02 | Richpower Microelectronics Corporation | Jittering frequency control circuit and method for a switching mode power supply |
| CN103036447A (zh) * | 2012-12-14 | 2013-04-10 | 深圳市新国都技术股份有限公司 | 一种最大功率可调式开关电源 |
| CN103904899A (zh) * | 2012-12-25 | 2014-07-02 | 比亚迪股份有限公司 | 一种开关电源 |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11029545B2 (en) * | 2018-05-18 | 2021-06-08 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Thin film transistor liquid crystal display (TFT-LCD) and the driving circuit and switching power supply thereof |
| CN111063723A (zh) * | 2019-11-25 | 2020-04-24 | 深圳深爱半导体股份有限公司 | 开关集成控制器和三极管芯片 |
| CN111063723B (zh) * | 2019-11-25 | 2021-12-28 | 深圳深爱半导体股份有限公司 | 开关集成控制器 |
| CN113852145A (zh) * | 2021-08-16 | 2021-12-28 | 芯海科技(深圳)股份有限公司 | 一种负载检测电路及其检测方法、集成电路以及电子设备 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105186856A (zh) | 2015-12-23 |
| US20170222636A1 (en) | 2017-08-03 |
| US9819333B2 (en) | 2017-11-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| WO2017024656A1 (zh) | 一种降低pwm脉冲调制信号的电磁干扰电路 | |
| TWI527362B (zh) | 電子裝置的風扇轉速控制方法及應用其之電子裝置 | |
| US9935543B2 (en) | Digital control power circuit, control circuit thereof, control method, and electronic device using the same | |
| JP6360560B2 (ja) | 出力クランピング回路のためのイントリンシックコンパレータ遅延 | |
| US10141840B2 (en) | Feedback control circuit and power management module shortening feedback response time | |
| US8482265B2 (en) | Current balance circuit utilizing multiplexers and triangular wave generators | |
| US10116206B2 (en) | Loop compensation circuit and switching power supply circuit | |
| JP6203688B2 (ja) | 電源回路とその制御方法 | |
| US9237614B2 (en) | Capacitance amplifying circuit applied to a controller of a power convertor and operation method thereof | |
| TWI630591B (zh) | 顯示裝置及其保護電路 | |
| CN106878863A (zh) | 供电电源和功放系统和功放系统的电压调整方法 | |
| CN108809072B (zh) | 适用于功率因数校正电路的相位补偿方法 | |
| US9134738B2 (en) | Voltage converter | |
| TWI645692B (zh) | 供電裝置、偵測電路與其供電方法 | |
| US20180316272A1 (en) | System and method for automatically and adaptively enhancing transient response for a plurality of output voltages | |
| US9502965B1 (en) | Burst mode power supply method and burst mode power supply apparatus | |
| CN103809719B (zh) | 电路板及用于电路板的电源管理系统 | |
| US9122295B2 (en) | Power supply apparatus with reducing voltage overshooting | |
| CN114512996B (zh) | 配电系统及其电网侧功率波动的平滑控制装置和方法 | |
| US9538606B2 (en) | Electronic ballast for operating at least a first and a second cascade of LEDS | |
| US20170288536A1 (en) | Voltage controlling circuit of t-con load variation, display panel and display device | |
| CN114039475A (zh) | 一种斜坡补偿电路及包含该电路的开关电源 | |
| CN106921288B (zh) | 低功率损耗的升压型功率因子校正装置 | |
| CN204119101U (zh) | 一种电机的多环路功率驱动装置 | |
| CN102436280A (zh) | 电压稳定输出装置和整机中的风扇转速控制系统及方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WWE | Wipo information: entry into national phase |
Ref document number: 14904863 Country of ref document: US |
|
| 121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 15900852 Country of ref document: EP Kind code of ref document: A1 |
|
| NENP | Non-entry into the national phase |
Ref country code: DE |
|
| 122 | Ep: pct application non-entry in european phase |
Ref document number: 15900852 Country of ref document: EP Kind code of ref document: A1 |