WO2017017842A1 - Memory control device, storage device, and memory write method - Google Patents
Memory control device, storage device, and memory write method Download PDFInfo
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- WO2017017842A1 WO2017017842A1 PCT/JP2015/071667 JP2015071667W WO2017017842A1 WO 2017017842 A1 WO2017017842 A1 WO 2017017842A1 JP 2015071667 W JP2015071667 W JP 2015071667W WO 2017017842 A1 WO2017017842 A1 WO 2017017842A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
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- the present invention relates to a storage device, and more particularly to a storage device including a nonvolatile memory device.
- phase change memory using a chalcogenite material as a recording material has been actively studied as a nonvolatile memory device.
- a phase change memory is a type of resistance change memory that stores information by utilizing the fact that recording materials between electrodes have different resistance states.
- phase change memory information is stored by utilizing the fact that the resistance value of a phase change material such as Ge 2 Sb 2 Te 5 is different between an amorphous state and a crystalline state. In the amorphous state, the resistance is high (high resistance state), and in the crystal state, the resistance is low (low resistance state). Therefore, reading of information from the phase change memory is realized by applying a potential difference to both ends of the element, measuring the current flowing through the element, and determining the high resistance state / low resistance state of the element.
- a phase change material such as Ge 2 Sb 2 Te 5
- the data is rewritten by changing the electric resistance of the phase change film formed of the phase change material to a different state by Joule heat generated by current.
- FIG. 28 is a diagram showing the relationship between the pulse width and temperature necessary for the phase change of the resistive memory element using the phase change material.
- the vertical axis represents temperature and the horizontal axis represents time.
- the memory element when the memory information “1” is written, the memory element is kept in a temperature range lower than the melting point Ta but higher than the crystallization temperature Tx (same or higher than the glass transition temperature). A set pulse is applied for a long time so that a sufficient current flows. Thereby, the chalcogenide material is in a low-resistance polycrystalline state.
- Patent Document 1 discloses that in a resistance change type memory such as a phase change memory, M-byte data stored in a buffer is written in n-byte (M> n) units in a time-sharing manner. .
- Patent Document 2 in the writing method of the resistance change type memory such as ReRAM, when the number of bits of a specific value exceeds the reference value in the data to be written, the data is inverted and the data is transferred to the nonvolatile memory. It is shown that data is transferred and written to a resistance change type memory.
- Patent Document 3 in the resistance change memory writing method, when the number of bit data of “1” is larger than the number of bit data of “0”, each bit of the write data is inverted and the data is inverted. It is shown that the data is transferred to the nonvolatile memory and written to the nonvolatile memory.
- the present inventors examined a control method of the resistance change type memory.
- the power consumption during writing to the resistance change memory increases as the number of bits to be rewritten increases.
- there is a limit to the number of bits that can be rewritten at one time due to the limitation on the maximum power consumption of the resistance change type memory.
- the writing method to the resistance change type memory shown in Patent Documents 2 and 3 when the number of bits of a specific value exceeds the reference value in the data to be written, the data is inverted, and the nonvolatile memory By writing to, the number of bits to be rewritten can be reduced, and the power consumption at the time of writing can be reduced.
- the write speed cannot be improved because the number of selections of the internal address of the resistance change type memory to be selected during the write operation, that is, the write count cannot be reduced.
- a first object of the present invention is to provide a semiconductor device that realizes high performance and low power.
- One aspect of the present invention is a memory control device that includes an information processing circuit and controls a memory.
- This information processing circuit provides a boundary flag for each data unit obtained by dividing write data into the memory every m bits.
- the boundary flag indicates a continuous range of data units in which the number of bits having a specific value in the write data becomes a maximum value that does not exceed the threshold value.
- Another aspect of the present invention is a storage device including a nonvolatile memory and a control circuit that performs writing to the nonvolatile memory.
- the control circuit provides a boundary flag for each of the data units m1 to mn (where n is a natural number) obtained by dividing write data to the nonvolatile memory for each m bits.
- the boundary flag indicates a continuous range of data units in which the number of bits having a specific value in the write data is a maximum value that does not exceed the threshold value.
- the boundary flag is set to a first value, and the boundary flag for other data units is set to a second value.
- Still another aspect of the present invention is a method for writing data to a memory that includes a plurality of memory cells that can transition to at least two states and writes data by transitioning the state of the memory cells.
- the input data is divided into m-bit data units, and the number of data bits that need to change the state of the memory cell in order to write the data has a maximum value less than or equal to the threshold value. Write consecutive data units in a range.
- a high-performance and low-power semiconductor device including a nonvolatile memory can be provided.
- FIG. 2 is a block diagram illustrating a configuration example of a control circuit NMV-CTL in FIG. 1. It is a flowchart which shows an example of the write-in operation
- FIG. 3 is a block diagram showing a configuration example of nonvolatile memory devices NMV0 to 31 in FIG.
- FIG. 8 is a circuit diagram illustrating a configuration example of the chain memory array in FIG. 7.
- FIG. 9 is an explanatory diagram illustrating an operation example of the chain memory array of FIG. 8.
- FIG. 9 is an explanatory diagram illustrating another operation example of the chain memory array of FIG. 8. It is a schematic diagram which shows an example of the block configuration of the memory array of a non-volatile memory device.
- 3 is a flowchart illustrating an example of an operation of an address range determination circuit FADCTL in the nonvolatile memory device according to the embodiment.
- FIG. 3 is a flowchart of a data copy operation performed by an information processing circuit MNGR in FIG. 2 during a garbage collection operation according to an embodiment.
- 10 is a flowchart of an example of a read operation of the memory module NVMD0 when a read request from the host device CPU_CP is input to the memory module NVMD0.
- FIG. 10 is a table showing a list of NVM command functions that the information processing circuit MNGR controls the nonvolatile memory device NVM via the memory control circuits (NVCT0 to NVCT3). It is a table
- the constituent elements are not necessarily indispensable unless otherwise specified or apparently indispensable in principle.
- the shapes when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numbers and the like (including the number, numerical value, quantity, range, etc.).
- the circuit elements constituting each block are not particularly limited, but are formed on a single semiconductor substrate such as single crystal silicon by a known integrated circuit technology such as a CMOS (complementary MOS transistor).
- CMOS complementary MOS transistor
- a resistive memory element such as a phase change memory or a ReRAM (Resistive Random Access Memory) is used.
- the semiconductor device of the present embodiment shown below includes a nonvolatile memory including a plurality of memory cells and a control circuit that accesses the nonvolatile memory.
- the control circuit generates the boundary flag BD for each m bits of the write data, and then transfers the write data and the boundary flag BD to the nonvolatile memory.
- the nonvolatile memory associates the internal address with the boundary flag BD, and simultaneously selects and writes a plurality of consecutive addresses included up to the upper limit of the number of “0” data bits that can be rewritten at one time.
- all data bits are “1”, and data writing is performed by rewriting “1” to “0” data bits.
- the number of memory cells whose states can be changed at a time is limited by the amount of current that can be supplied by the circuit.
- writing can be performed at high speed. It becomes.
- the number of times of writing “0” data bits is reduced by recording up to the upper limit of the number of “0” data bits that can be rewritten at one time. Thereby, the writing time and the number of address selections can be reduced, the data transfer speed of the semiconductor device can be improved, and the power consumption can be reduced.
- the configuration will be specifically described below.
- FIG. 1 is a block diagram showing a schematic configuration example of a memory module and an information processing system according to an embodiment of the present invention.
- the information processing system illustrated in FIG. 1 includes a host device (for example, a processor that is an information processing device) CPU_CP and a memory module NVMD0.
- the host device CPU_CP is a host controller that manages data stored in the memory module NVMD0 with a logical address LAD in units of 512 bytes, although not particularly limited.
- the host device CPU_CP reads / writes data from / to this memory module NVMD0 through the interface signal HDH_IF.
- the memory module NVMD0 is not particularly limited, but corresponds to, for example, SSD (Solid State Drive).
- serial interface signal system There are a serial interface signal system, a parallel interface signal system, an optical interface signal system, etc. as signal systems for connecting the host device CPU_CP and the memory module NVMD0, and all systems can be used.
- clock methods There are common clock methods, source synchronous clock methods, embedded clock methods that embed clock information in data signals, etc., and all clock methods can be used to operate the host device CPU_CP and memory module NVMD0.
- a serial interface signal system and an embedded clock system are used as an example, and the operation will be described below.
- a read request RQ is input to the memory module NVMD0 through the interface signal HDH_IF.
- the read request RQ includes a logical address LAD, a data read command RD, a sector count SEC, and the like.
- the write request includes a logical address LAD, a data write command WRT, a sector count SEC, write data DATA, and the like.
- the memory module NVMD0 includes memory devices M0, M1, and M2, nonvolatile memory devices NVM0 to NVM3, and a control circuit (controller) NVM-CTL that controls these memory devices.
- Non-volatile memory devices NVM0 to NVM3 have, for example, the same configuration and performance. These memory devices NVM0 to NVM3 include NAND flash memory, NOR flash memory, phase change memory PCM, resistance change memory ReRAM, spin transfer magnetization reversal memory STT-MRAM, ferroelectric memory, etc. Either memory can be used.
- Memory devices M0 and M1 are buffers BUF0 and BUF1 for temporarily storing data, and each has a write area WAREA and a copy area CAREA.
- the write area WAREA is an area for storing write data from the host
- the copy area CAREA is an area used for data movement between the nonvolatile memory devices NVM0 to NVM3 at the time of garbage collection or static wear leveling.
- the memory device M2 has a logic that performs correspondence between the logical address LAD from the host device CPU_CP managed by the control circuit NVM-CTL and the physical addresses PAD of the nonvolatile memory devices NVM0 to NVM3 in the memory module NVMD0.
- a physical address conversion table LPTBL, a physical logical address conversion table PLTBL, an erase count table ERSTBL for each block, and an address map ADMAP are stored.
- the control circuit NVM-CTL selects the physical address PAD and writes data so that the number of erases for each block of the nonvolatile memory devices NVM0 to NVM3 is leveled. After the data writing is completed, the control circuit NVM-CTL updates the address conversion table LPTBL.
- control circuit NVM-CTL When the control circuit NVM-CTL reads data from the nonvolatile memory devices NVM0 to NVM3, the control circuit NVM-CTL refers to the address conversion table LPTBL, determines the physical address PAD for the logical address LAD, and determines the physical address. Read data stored in PAD.
- the host device CPU_CP reads and executes data, OS, and application programs from the memory module NVMD0. The execution result is written into the memory module NVMD0 by the host device CPU_CP.
- FIG. 2 is a block diagram of the control circuit NVM-CTL in FIG.
- the control circuit NVM-CTL includes an interface circuit NVM_IF, an address / command buffer ADCBUF, a map register MAPREG, an arbitration circuit ARB, an information processing circuit MNGR, and memory control circuits RAMC and NVCT0 to NVCT3.
- the memory control circuit RAMC directly controls the memory devices M0 to M2 in FIG. 1, and the memory control circuits NVCT0 to NVCT3 directly control the nonvolatile memory devices NVM0 to NVM3 in FIG.
- the memory control circuits NVCT0 to NVCT3 include queue circuits WTQ0 to WTQ3 and RDQ0 to RDQ for writing and reading, respectively.
- the address / command buffer ADCBUF temporarily stores the logical address LAD, the data read command RD, and the data write command WT input from the host device CPU_CP to the control circuit NVM-CTL.
- map register MAPREG an address map ADDMAP is stored, and correspondence between the X address, Y address and Z address in the nonvolatile memory devices NVM0 to NVM3 for each block size is shown.
- the selected physical address PAD is stored so that the number of erases for each block of the nonvolatile memory devices NVM0 to NVM3 is equalized, and is used when data is written.
- FIG. 3 shows an example of a write operation to the buffer BUF0 and the non-volatile memory devices NVM0 to NVM3 of the memory module NVMD0 of this embodiment in response to a write request WQ from the host device CPU_CP.
- the information processing circuit MNGR that has received the write request WQ first checks whether the access from the host device CPU_CP is the write request WQ (Step 1). If the access is a write request WQ, Step 2 is performed. If it is not the write request WQ, it waits for access from the host device CPU_CP again. In Step 2, the information processing circuit MNGR checks the following conditions.
- the buffer BUF0 is a buffer to be written to the nonvolatile memory devices NVM0 to NVM3, and the buffer BUF0 has a free space for storing data” or “the buffer BUF1 is a nonvolatile memory device NVM0 to NVM3. BUF1 has no free space, and buffer BUF0 has free space to store data. '' If this condition is satisfied, Step 3 is executed, and if not satisfied, Step 5 is executed.
- M is a write data amount (bit), which is 8 KB in this embodiment), and associates a 1 or 0 value of the boundary flag BDi.
- the i-th boundary flag BDi value is assigned to the i-th data mi obtained by dividing the write data DATA every m bits.
- Step 301 the total number of “0” bits is calculated (SUM0).
- Step 304 after Step 303 is finished, it is checked whether the total number SUM0 of “0” bits is equal to m. If the total number SUM0 of “0” bits is equal to m, Step 303 is executed, otherwise Step 306 is executed. In Step 305, the boundary flag BD is set to 0, and then Step 309 is executed.
- Step 306 after confirming that the total number SUM0 of “0” bits is larger than m, BDi-1 is set to 0 in Step 307.
- Step 307 a value obtained by subtracting 1 from the current i value in Step 308 is set as the i value, and Step 309 is executed.
- Step 309 the total number SUM0 of “0” bits is set to zero.
- the i-th boundary flag BD value is assigned to the i-th data mi divided into m bits in the write data DATA by a series of processes in Step 3.
- the boundary flag BDi value of mi + 3 is 0 in mi to mi + 3 consecutive from the i-th data mi and 1 otherwise, m is included in the data of mi to mi + 3. It indicates that there is no “0” data bit exceeding the bit. Therefore, by writing the data from mi to mi + 3 to the addresses in the non-volatile memory devices NVM0 to NVM3, the “0” data bits included in the data from mi to mi + 3 can be written at once. Can do. That is, the number of BDi values of 0 is the number of times of writing “0” data bits. The smaller the number of BDi values of 0, the smaller the number of times of writing “0” data bits and the shorter the write time. be able to.
- the information processing circuit MNGR can program m values of m bits.
- the m value of m bits corresponds to the maximum number of data bits that can be written at one time in the nonvolatile memory devices NVM0 to NVM3, and the maximum number of data bits differs in various nonvolatile memory devices. There is a case. Therefore, the information processing circuit MNGR can change the m value in accordance with the nonvolatile memory device to be used, and can configure an appropriate memory module NVMD0.
- FIG. 5 is a diagram showing the association of the boundary flag BDi with the write data DATA.
- FIG. 5 shows a state immediately after Step 3 of FIG. 3 described in detail in FIG. 4 is executed.
- the write data DATA is divided into D0 [0] to D0 [7], each having 1024 bits of data. In the figure, white circles indicate “1” bits of write data DATA, and black circles indicate “0” bits.
- D0 [0] is divided into data m0 to m255, and boundary flags BD0 to 255 are assigned to each.
- D0 [1] is divided into data m256 to m511, and boundary flags BD256 to 511 are assigned to the data m256 to m511, respectively.
- D0 [2] is divided into data m512 to m767, and boundary flags BD512 to 767 are assigned to the respective data.
- D0 [3] is divided into data m768 to m1023, and boundary flags BD768 to 1023 are assigned to the respective data.
- D0 [4] is divided into data m1024 to m1279, and boundary flags BD1024 to 1279 are assigned to the data m1024 to m1279, respectively.
- D0 [5] is divided into data m1280 to m1535, to which boundary flags BD1280 to 1535 are assigned, respectively.
- D0 [6] is divided into data m1536 to m1791, and boundary flags BD1536 to 1791 are assigned to the respective data.
- D0 [7] is divided into data m1792 to m2047, and boundary flags BD1792 to 2047 are assigned to them.
- Step 4 write data DATA and the boundary flag BDi value assigned to each data mi divided into m bits in write data DATA are written to buffer BUF0.
- FIG. 6 is a table showing an example of the data stored in the buffer and the boundary flag BD.
- FIG. 6A1 shows the write data DATAD0 to D7 stored in the buffer BUF0 in Step 4 of FIG. 3 and the boundary flags D0_BD to D7_BD corresponding to these data.
- Each of the write data D0 to D7 has a size of 8192 bytes, and each of the boundary flags D0_BD to D7_BD has a size of 256 bytes.
- BDV is a flag indicating whether the boundary flag is valid / invalid. For example, “0” indicates valid and “1” indicates invalid. Valid / invalid can be switched, for example, by selecting a write command PRG00 and PRG01 or PRG10 shown in FIG. 26, which will be described later, and giving an instruction from the information processing circuit MNGR via the memory control circuit NVCT.
- BDV is valid, the boundary flag BD is written to the memory, and when it is invalid, the boundary flag BD is not written to the memory. If it is disabled, writing becomes faster and memory capacity can be saved.
- the boundary flag BD once calculated can be reused for garbage collection or the like.
- FIG. 6 (A2) shows allocation to the four channels CH0 to CH3 for writing each write data to the nonvolatile memory devices NVM0 to NVM3.
- four channels are assigned to data in order (by rotation).
- Step 5 the information processing circuit MNGR checks the following conditions.
- Step 6 is executed, and if not satisfied, Step 1 is executed. Step 1 to Step 5 are repeated until the buffer BUF0 is filled with the write data.
- Step 6 the information processing circuit MNGR transfers the write data stored in the buffer BUF0 to the nonvolatile memory devices NVM0 to NVM3 and performs writing.
- the information processing circuit MNGR reads the physical address PAD stored in the physical address register Next PAD, and further corresponds to the write data DATA stored in the buffer BUF0.
- the boundary flag BD is read and transferred to the memory control circuits NVCT0 to NVCT3 through the arbitration circuit ARB together with the write command WRT.
- the memory control circuit NVCT0 generates ECC related to the write data DATA and the boundary flag BD corresponding to the write data DATA, converts the physical address PAD into the row address and the column address of the nonvolatile memory device NVCT0, and program instruction PRG01 (or PRG10 ), The row address and the column address, the boundary flag BD, and the write data DATA and ECC are transferred to the nonvolatile memory device NVM0.
- This program instruction PRG01 is an instruction for the non-volatile memory device NVM0 to write to its own internal memory cell using the boundary flag BD. See FIG. 26 for a list of instructions. In FIG. 26, PRG01 that uses the boundary flag BD and the boundary flag BD itself writes to the memory cell and PRG10 that uses the boundary flag BD but does not write to the memory cell are supported. Therefore, it may be selected as appropriate.
- the address range determination circuit FADCTL in the nonvolatile memory device NVM0 When the nonvolatile memory device NVM0 receives the program instruction PRG01, the row address and the column address, the boundary flag BD, and the write data DATA and ECC, the address range determination circuit FADCTL in the nonvolatile memory device NVM0 generates a row address signal. Using the column address signal and the boundary flag BD, the boundary flag BD value is associated with the internal X address, Y address, and Z address necessary for writing the write data DATA.
- Step 6 the i-th boundary flag BDi value assigned to the i-th data mi divided into m bits in the write data DATA is changed to the write data DATA.
- the i-th boundary flag BDi value assigned to the i-th data mi divided into m bits in the write data DATA is changed to the write data DATA.
- the internal X address, Y address, and Z address necessary for writing.
- the boundary flag BDi value of yi + 3 is 0 in the consecutive i-th Y addresses yi to yi + 3, 1 otherwise, Y
- the boundary flag BDi value of yi + 3 is 0 in the consecutive i-th Y addresses yi to yi + 3, 1 otherwise, Y
- Y This indicates that there is no “0” data bit exceeding m bits in the data of the addresses yi to yi + 3. Therefore, “0” data bits within the range of Y addresses yi to yi + 3 can be written at a time. That is, the number of BDi values of 0 is the number of times of writing “0” data bits. The smaller the number of BDi values of 0, the smaller the number of times of writing “0” data bits and the shorter the write time. be able to.
- Step 7 it is checked whether all the data in the buffer BUF0 has been written to the nonvolatile memory devices NVM0 to NVM0. If not, Step 6 is performed. When all the data in the buffer BUF0 is written to the nonvolatile memory devices NVM0 to NVM3, Step 8 is performed.
- Step 8 the information processing circuit MNGR updates the address conversion table LPTBL stored in the memory device M2 and the erase count table ERSTBL for each block.
- the buffer BUF1 is a buffer to be written to the nonvolatile memory devices NVM0 to NVM3.
- the information processing circuit MNGR can perform a write operation to the buffer BUF1 when performing Step 6 to Step 9 in the buffer BUF0. Further, the information processing circuit MNGR erases a new physical address PAD for writing the data stored in the buffer BUF0 after Step 9 is completed to the physical address register NextPAD for each of the nonvolatile memory devices NVM0 to NVM3. Select and save so that the number of times is leveled.
- the write operation to the buffer BUF1 and the write operation from the buffer BUF1 to the nonvolatile memory devices NVM0 to NVM3 are the same operation as the buffer BUF0. That is, BUF0 and BUF1 in FIG. 3 are switched and processed.
- “0” data bits are written at once by associating the boundary flag BDi value with the internal X address, Y address, and Z address necessary for writing the write data DATA. Since the internal address range in which data can be written can be specified and written, the number of times of writing “0” data bits is reduced, and the writing time can be shortened. Furthermore, since the write operation from the buffer BUF0 to the nonvolatile memory devices NVM0 to NVM3, the write operation to the buffer BUF1, and the storage of a new physical address in the physical address register NextPAD can be performed simultaneously, the writing speed can be improved.
- FIG. 7 is a block diagram showing a configuration example of the nonvolatile memory devices NMV0 to NMV31 in FIG.
- a phase change nonvolatile memory phase change memory
- the nonvolatile memory device includes a clock generation circuit SYMD, a status register STREG, an erase size designation register NVREG, an address / command interface circuit ADCMDIF, an IO buffer IOBUF, a control circuit CTLOG, a temperature sensor THMO, a data control circuit DATCTL, and memory banks BK0 to Equipped with BK3.
- a bit line selection circuit BSWx that selects either one and connects to the data line DTx is provided.
- the interface for operating the nonvolatile memory device shown in FIG. 7 employs a memory interface such as a NAND flash memory interface or a DRAM interface, the compatibility of the interface with the conventional system can be maintained, which is convenient. A good nonvolatile memory device can be provided.
- the block size of the nonvolatile memory device shown in FIG. 7 is not physically fixed, and can be easily changed as a control management unit by the control circuit NVM-CTL. For this reason, the performance and reliability of the information processing system can be improved by analyzing the characteristics of access to the memory module NVMD of the host device CPU_CP and dynamically optimizing the block size of the nonvolatile memory device.
- FIG. 8 is a circuit diagram showing a configuration example of the chain memory array in FIG.
- each chain memory array CY has a configuration in which a plurality of phase change memory cells CL0 to CLn are connected in series.
- One end of the memory cell CL is connected to the word line WL via the chain selection transistor Tch2, and the other end is connected to the bit line BL via the chain selection transistors Tch0 and Tch1.
- the plurality of phase change memory cells CL0 to CLn are sequentially stacked in the height direction with respect to the semiconductor substrate and connected in series to each other.
- Each phase change memory cell CL includes a variable resistance storage element R and a memory cell selection transistor Tc1 connected in parallel thereto.
- the memory element R is made of, for example, a chalcogenide material.
- two chain memory arrays CY share the chain selection transistor Tch2, and the chain selection transistors Tch0, 1, 2 in each chain memory array CY are connected by the chain memory array selection lines SL0, SL1, SL2. Are controlled, and thereby one of the chain memory arrays is selected.
- the memory cell selection lines LY0 to LYn are connected to the gate electrodes of the corresponding phase change memory cells.
- the memory cell selection lines LY control the memory cell selection transistors Tc1 in the phase change memory cells CL0 to CLn, Thus, each phase change memory cell is appropriately selected.
- the chain memory array selection lines SL0, SL1, SL2 and the memory cell selection lines LY0 to LYn are appropriately driven as the chain control line CH via the chain selection address latch CHLT and the chain decoder CHDEC in FIG.
- control circuit CTLOG receives a control signal CTL via the address / command interface circuit ADCMDIF.
- the control signal CTL is not particularly limited.
- the command latch enable signal (CLE), the chip enable signal (CEB), the address latch signal (ALE), the write enable signal (WEB), the read enable signal (REB), A ready busy signal (RBB) is included.
- a read command, a row address signal, and a column address signal input in synchronization with the clock signal CLK from the input / output signal IO are taken in by a combination of these control signals CTL.
- the control circuit CTLOG appropriately generates internal X address, Y address and Z address, and transmits them to the row address latch RADLT, the column address latch CADLT and the chain selection address latch CHLT, respectively.
- the row decoder ROWDEC receives the output of the row address latch RADLT and selects the word lines WL0 to WLk
- the chain decoder CHDEC receives the output of the chain selection address latch CHLT and selects the chain control line CH. When a read command is input, data is read from the chain memory array CY selected by the combination of the word line, the bit line, and the chain control line, via the bit line selection circuits BSW0 to BSWm.
- the read data is amplified by the sense amplifiers SA0 to SAm and transmitted to the data buffer DBUF0 (or DBUF1) via the data selection circuit DSW1.
- Data on the data buffer DBUF0 (or DBUF1) is sequentially transmitted to the input / output signal IO via the data control circuit DATCTL and the IO buffer IOBUF.
- a write command, a row address signal, a column address signal, a boundary flag BD, and write data DATA which are input in synchronization with the clock signal CLK from the input / output signal IO, are captured by a combination of these control signals CTL.
- the address range determination circuit FADCTL uses the row address signal, the column address signal, and the boundary flag BD, and uses the internal X address, Y address, and Z necessary for writing the write data DATA. Associate a boundary flag BD value with the address. Further, the combination of the internal X address, Y address, and Z address corresponding to the boundary flag BD value 0, that is, all of the boundary addresses BADxyz are transferred to the control circuit CTLOG. This indicates a continuous address range in which 0 data of m bits or less can be written at a time.
- the control circuit CTLOG transmits the X address, Y address, and Z address of the boundary address BADxyz to the row address latch RADLT, the column address latch CADLT, and the chain selection address latch CHLT, respectively.
- the row decoder ROWDEC receives the output of the row address latch RADLT and selects the word lines WL0 to WLk
- the chain decoder CHDEC receives the output of the chain selection address latch CHLT and selects the chain control line CH.
- a data signal is transmitted to the input / output signal IO following the address signal described above, and the data signal is input to the data buffer DBUF0 (or DBUF1) via the data control circuit DATCTL.
- the data signal on the data buffer DBUF0 (or DBUF1) is selected by the combination of the word lines, bit lines, and chain control lines described above via the data selection circuit DSW1, write drivers WDR0 to WDRm, and bit line selection circuits BSW0 to BSWm. Is written in the chain memory array CY.
- the write data verification circuits WV0 to WVm verify whether or not the write level has reached a sufficient level while appropriately reading the written data through the sense amplifiers SA0 to SAm. The write operation is performed again using the write drivers WDR0 to WDRm until it reaches.
- the current I0 is changed from the word line WL0 to the chain selection transistor Tch2, the variable resistance storage element R0, the memory cell selection transistors Tcl1 to Tcln, and the chain selection. It flows to the bit line BL0 via the transistor Tch1.
- the variable resistance memory element R0 has a high resistance.
- the current I0 is controlled in the form of the Set current pulse shown in FIG. 28, so that the variable resistance memory element R0 has a low resistance.
- Data “1” and “0” are distinguished by the difference in resistance values of the variable resistance memory elements R0 to Rn.
- the writing speed can be improved by passing the current I0 to the plurality of bit lines BL0_0 to BL0_m.
- data “1” is recorded when the variable resistance memory element becomes low resistance, and data “0” is recorded when it becomes high resistance.
- a current is applied through the same path as the data writing so that the resistance value of the variable resistance memory element R0 does not change.
- a voltage value corresponding to the resistance value of the variable resistance memory element R0 is detected by a sense amplifier (SA0 in FIG. 7 in this example), and data “0” and “1” are determined.
- a current is applied through a path similar to that for data writing to the extent that the resistance value of the variable resistance memory element R0 does not change through the plurality of bit lines BL0_0 to BL0_m.
- data “0” and “1” are determined in SA0 to SAm in FIG. 7, and the reading speed can be improved.
- the current I2 is changed from the word line WL0 through the chain selection transistor Tch2, the memory cell selection transistors Tcl0 to Tcln, and the chain selection transistor Tch1. Flow to line BL0. Joule heat due to the current I2 is conducted to the variable resistance memory elements R0 to Rn, and the variable resistance memory elements R0 to Rn collectively have a low resistance. This current I2 is controlled to a value that allows the variable resistance memory elements R0 to Rn to be collectively reduced in resistance.
- the memory cells in the plurality of chain memory arrays can be made low resistance at the same time, and the erase data rate can be improved.
- FIG. 11A shows an example of a block configuration of the memory array of the nonvolatile memory device NMV constructed by the control circuit NVM-CTL using the address map ADMAP information, and an example of the block configuration when the block size is 64 KB. It is.
- a large number of these blocks are arranged to constitute a memory array of the nonvolatile memory shown in FIG.
- the display method of the chain memory array CY is the same as that in FIG.
- data DATA-AREA and the management area MG-ARE data DATA and redundant data Rdata shown in FIG. 11B are stored, respectively.
- FIG. 11B shows an example of the configuration of data PDATA written from the control circuit NVM-CTL to the nonvolatile memory devices NVM0 to NVM31.
- Data PDATA is composed of data DATA (8192 bytes) and redundant data Rdata (1024 bytes).
- the redundant data Rdata includes a data inversion flag IVF, a boundary flag BDF, ECC codes ECC1 and ECC2, a spare area RSV, and the like. This format is supported by the command PRG01 in FIG.
- the data inversion flag IVF indicates whether the data DATA written by the control circuit NVM-CTL to the non-volatile memory device (NVM10 to NVM17) is data obtained by inverting each bit of the original write data. When 1 is written to the data inversion flag IVF, it indicates that the data has been written without inverting each bit of the original data. When 0 is written, each bit of the original main data is inverted. Indicates that the data has been written. An example using the data inversion flag will be described in detail in the third embodiment.
- the ECC code ECC1 is data necessary for detecting and correcting the error of the data DATA and the data inversion flag IVF
- the ECC code ECC2 is data necessary for detecting and correcting the error of the boundary flag BDF.
- These ECC codes are generated by the control circuit NVM-CTL when the control circuit NVM-CTL writes the data DATA to the non-volatile memory device (NVM0 to NVM3).
- Bad block information BADBLK indicates whether data DATA written to a nonvolatile memory device (NVM0 to NVM3) is available.
- the bad block information BADBLK when 1 is written to the bad block information BADBLK, the data DATA is usable, and when 0 is written, the data DATA is not usable.
- the bad block information BADBLK is 1 when error correction by ECC is possible, and the bad block information BADBLK is 0 when error correction is impossible.
- the spare area RSV exists as an area where the control circuit NVM-CTL can be freely defined.
- FIG. 11C shows another example of the configuration of data PDATA written from the control circuit NVM-CTL to the nonvolatile memory devices NVM0 to NVM31.
- the redundant data Rdata does not include the boundary flag BDF and the ECC code ECC2. This format is supported by the command PRG10 of FIG.
- the data DATA, the data inversion flag IVF, the boundary flag BDF, and the ECC code ECC1 are transferred from the control circuit NVM-CTL to the nonvolatile memory devices NVM0 to NVM31. Since the boundary flag BDF and the ECC code ECC2 are not written in the devices NVM0 to NVM31, the capacity of the nonvolatile memory device NVM can be effectively increased.
- FIG. 12 shows the operation of the address range determination circuit FADCTL in the nonvolatile memory device NVM0 in Step 6 of FIG.
- Step 601 when the nonvolatile memory device NVM0 receives the program instruction PRG01 (or PRG10), the row address and column address, the boundary flag BD, and the write data DATA, in Step 602, the nonvolatile memory device NVM0
- the address range determination circuit FADCTL uses the row address signal, the column address signal, and the boundary flags BD0 to 2047, and each of the boundary flags BD0 to 2047, the internal X address necessary for writing the write data DATA, and Y Associate the address with the Z address.
- Step 603 the combination of the internal X address, Y address and Z address corresponding to the boundary flag BD value 0, that is, all of the boundary addresses BADxyz are transferred to the control circuit CTLOG.
- the control circuit CTLOG writes to the memory array while associating the boundary address BADxyz with m0 to m2047 in the write data DATA.
- FIG. 13 shows the correspondence between the boundary flags BD0 to 2047 and the internal X address, Y address, and Z address immediately after executing Step 602 in FIG.
- the correspondence between the internal X address and Y address and the boundary flags BD0 to 2047 when the write data DATA is written to the internal Z address Z0 is shown.
- Boundary flags BD0-255 and data m0-255 are assigned to Y addresses Y0-Y255 in X address X0.
- Boundary flags BD256 to 511 and data m256 to 511 are assigned to Y addresses Y0 to Y255 in X address X1, respectively.
- Boundary flags BD512 to 767 and data m512 to 767 are assigned to Y addresses Y0 to Y255 in X address X2.
- Boundary flags BD768 to 1023 and data m768 to 1023 are assigned to Y addresses Y0 to Y255 in X address X3, respectively.
- Boundary flags BD1024 to 1279 and data m1024 to 1279 are assigned to Y addresses Y0 to Y255 in X address X4, respectively.
- Boundary flags BD1280 to 1535 and data m1280 to 1535 are assigned to Y addresses Y0 to Y255 in X address X5.
- Boundary flags BD1536 to 1791 and data m1536 to 1791 are assigned to Y addresses Y0 to Y255 in X address X6, respectively.
- Boundary flags BD1792 to 2047 and data m1792 to 2047 are assigned to Y addresses Y0 to Y255 in X address X7, respectively.
- these boundary flags BD0 to 2047 there are 1365 boundary flags BD having a zero value.
- the number of BDi values of 0 is 1365
- the number of times “0” data bits are written is 1365 times.
- the number of times of writing is 2048, so that the number of times of writing can be reduced by 683 times according to the present embodiment.
- the boundary flag is added to the data unit at the end of the continuous m-bit data unit in which the included “0” data bits do not exceed 32 bits.
- the first data unit may be used.
- the boundary flag BD value of 0 may be arbitrarily set to other values such as 1.
- FIG. 14 shows another example of the write operation to the buffer BUF0 of the memory module NVMD0 and the nonvolatile memory devices NVM0 to NVM3 in response to the write request WQ from the host device CPU_CP in FIG.
- the system configuration is the same as that shown in FIGS.
- Step 3 and Step 6 of the operation described in FIG. 3 are changed to the operations of Step 31 and Step 61, and the other operations are the same as those in FIG.
- FIG. 15 shows the detailed operation of Step31.
- the m bits represent the number of bits of “0” data that can be written at once by the nonvolatile memory devices NVM0 to NVM3.
- Step 331 the total number of “0” bits is calculated (SUM0).
- Step 332 it is checked whether the total number SUM0 of “0” bits is smaller than m. If the total number SUM0 of “0” bits is smaller than m, Step 333 is executed, otherwise Step 334 is executed. In Step 333, the boundary flag BDFi is set to 1, and then Step 342 is executed.
- Step 334 after Step 333 is completed, it is checked whether the total number SUM0 of “0” bits is equal to m. If the total number SUM0 of “0” bits is equal to m, Step 333 is executed, otherwise Step 337 is executed. In step 335, the boundary flag BDFi is set to 0. After that, in step 336, the number of the boundary flag BDFi value 0 is increased by 1, so 1 is added to the total number SUMF0 of the boundary flag BDFi value 0. Thereafter, Step 341 is executed.
- Step 337 after confirming that the total number SUM0 of “0” bits is larger than m, BDFi-1 is set to 0 in Step 338. Thereafter, in Step 339, since the number of boundary flag BDFi values 0 is increased by 1, 1 is added to the total number SUMF0 of boundary flag BDFi values 0. Thereafter, in Step 340, a value obtained by subtracting 1 from the current i value is set as the i value, and then Step 341 is executed.
- Step 341 the total number SUM0 of “0” bits is set to 0.
- the boundary flag BDFi value and the total number SUMF0 of the boundary flag BDFi value 0 are written to the buffer BUF0 in the next Step 4.
- i 0, 1, 2,..., M / m.
- Step4 write data DATA and the boundary flag BDi value assigned to each data mi divided into m bits in the write data DATA, and 0 value of the boundary flag BDi Total number SUMF0 is written to buffer BUF0.
- FIG. 16 is a table showing an example of the data stored in the buffer and the boundary flag BD.
- the write data DATA D0 to D7 stored in the buffer BUF0 or the buffer BUF1 in Step 4 and the boundary flags D0_BD to D7_BD corresponding to these data and the boundary flag are displayed.
- information BDSUM0 of the total number of 0 values is added.
- Step 61 first, in order to shorten the maximum write time of the data D0 to D7 in the buffer BUF0 to the nonvolatile memory devices NVM0 to NVM3, the data D0 to D7 are set so that the total number BDSUM0 of each becomes as uniform as possible. Is assigned (channel assignment for shortening the write time), and then these data D0 to D7 are written to the nonvolatile memory devices NVM0 to NVM3 (writing to NVM).
- the information processing circuit MNGR has the total number BDSUM0 (1300, 1600, 950, 800, 1050, 1200, 700, 500) of the zero values of the boundary flags D0_BD to D7_BD corresponding to the write data DATA D0 to D7 stored in the buffer BUF0. ).
- rank from 1 to 8 in descending order. Furthermore, in these ranks, write data D1 and D7 corresponding to ranks 1 and 8 are assigned to channel CH0, write data D0 and D6 corresponding to ranks 2 and 7 are assigned to channel CH1, and writes corresponding to ranks 3 and 6 are assigned. Data D5 and D3 are assigned to channel CH2, and write data D4 and D2 corresponding to ranks 4 and 5 are assigned to channel CH3.
- FIG. 16C2 shows the correspondence between the rank BDRank corresponding to the write data D1 to D7 and the assigned channel CH.
- the information processing circuit MNGR reads the write data D1 and the boundary flag D1_BD, the data D7 and the boundary flag D7_BD assigned to the channel CH0 stored in the buffer BUF0, and the physical address PAD0 of the nonvolatile memory device NVM0 from the physical address register NextPAD , PAD1 is read and transferred to the memory control circuit NVCT0.
- write data D0 and boundary flag D0_BD, data D6 and boundary flag D6_BD assigned to channel CH1 are read, physical addresses PAD2 and PAD3 of nonvolatile memory device NVM1 are read from physical address register NextPAD, and memory control circuit NVCT1 Forward to.
- write data D5 and boundary flag D5_BD, data D3 and boundary flag D3_BD assigned to channel CH2 are read, physical addresses PAD4 and PAD5 of nonvolatile memory device NVM2 are read from physical address register NextPAD, and memory control circuit NVCT2 Forward to.
- write data D4 and boundary flag D4_BD, data D2 and boundary flag D2_BD assigned to channel CH3 are read, physical addresses PAD6 and PAD7 of nonvolatile memory device NVM3 are read from physical address register NextPAD, and memory control circuit NVCT3 Forward to.
- the memory control circuit NVCT0 generates an error correction code ECC1 related to the write data D1 and the boundary flag D1_BD, converts the physical address PAD0 into the row address 1 and the column address 1 of the nonvolatile memory device NVM0, and generates the program instruction PRG01 and the row address. 1 and column address 1, boundary flag D1_BD, write data D1 and ECC1 are transferred to nonvolatile memory device NVM0.
- the memory control circuit NVCT0 generates an error correction code ECC7 related to the data D7 and the boundary flag D7_BD, converts the physical address PAD1 into the row address 7 and the column address 7 of the nonvolatile memory device NVM0, and generates a program instruction PRG01 and a row Address 7, column address 7, boundary flag D7_BD, and write data D7 and ECC7 are transferred to nonvolatile memory device NVM0.
- ECC7 error correction code
- the memory control circuit NVCT1 generates an error correction code ECC0 related to the write data D0 boundary flag D0_BD, converts the physical address PAD2 into the row address 0 and the column address 0 of the nonvolatile memory device NVM1, and generates the program instruction PRG01 and the row address 0.
- ECC0 error correction code
- the column address 0, the boundary flag D0_BD, the write data D0, and ECC0 are transferred to the nonvolatile memory device NVM1.
- the memory control circuit NVCT0 generates an error correction code ECC6 related to the data D6 and the boundary flag D6_BD, converts the physical address PAD3 into the row address 6 and the column address 6 of the nonvolatile memory device NVM1, and sets the program instruction PRG01 and the row Address 6, column address 6, boundary flag D7_BD, and write data D6 and ECC6 are transferred to nonvolatile memory device NVM1.
- ECC6 error correction code
- the memory control circuit NVCT2 generates an error correction code ECC5 related to the write data D5 boundary flag D5_BD, converts the physical address PAD4 into the row address 5 and the column address 5 of the nonvolatile memory device NVM2, and generates the program instruction PRG01 and the row address 5
- ECC5 error correction code
- the column address 5, the boundary flag D5_BD, the write data D5 and ECC5 are transferred to the nonvolatile memory device NVM2.
- the memory control circuit NVCT2 generates an error correction code ECC3 related to the data D3 and the boundary flag D3_BD, converts the physical address PAD5 into the row address 3 and the column address 3 of the nonvolatile memory device NVM2, and sets the program instruction PRG01 and the row Address 3 and column address 3, boundary flag D3_BD, and write data D3 and ECC3 are transferred to nonvolatile memory device NVM2.
- ECC3 error correction code
- the memory control circuit NVCT3 generates an error correction code ECC4 related to the write data D4 boundary flag D4_BD, converts the physical address PAD6 into the row address 4 and the column address 4 of the nonvolatile memory device NVM3, and generates the program instruction PRG01 and the row address 4
- ECC4 error correction code
- the memory control circuit NVCT3 generates an error correction code ECC2 related to the data D2 and the boundary flag D2_BD, converts the physical address PAD7 into the row address 7 and the column address 7 of the nonvolatile memory device NVM3, the program instruction PRG01, and the row Address 7 and column address 7, boundary flag D2_BD, and write data D2 and ECC2 are transferred to nonvolatile memory device NVM3.
- the subsequent operations of the non-volatile memory devices NVM0 to NVM3 in Step 61 are the same as in Step 6 of FIG. 3.
- FIG. 17 shows that the address range determination circuit FADCTL in the non-volatile memory device NVM0 is in Step 61 of FIG.
- the correspondence between the boundary flags BD0 to 2047 by the processing performed and the internal X address, Y address, and Z address is shown.
- the correspondence between the internal X address and Y address and the boundary flags BD0 to 2047 when the internal Z address writes the write data DATA to Z0 is shown.
- the energy for changing the state of the memory cell is suppressed to a predetermined level or less, and is restricted by the power supply of the device and the circuit scale. It is possible to write at high speed within the range of writing ability.
- FIG. 16B2 shows a state in which channels are assigned in order to the data D0 to D7 without performing write time reduction channel assignment
- FIG. 16B3 shows the total number SUM_BDC for each channel at that time. Indicates.
- write data D0 and D4 are assigned to channel CH0
- write data D1 and D5 are assigned to channel CH1
- write data D2 and D6 are assigned to channel CH2
- write data D3 and D7 are assigned to channel CH3.
- the total number SUM_BDC of the channel CH0 is 2350
- the total number SUM_BDC of the channel CH1 is 2800
- the total number SUM_BDC of the channel CH2 is 1650
- the total number SUM_BDC of the channel CH3 is 1300.
- 2800 which is the total number SUM_BDC of the channel CH1 is the maximum number of times of writing to the nonvolatile memory device NVM, and this is the maximum write time.
- FIG. 16 (C2) shows the channel assignment for the data D0 to D7 when the write time reduction channel assignment is performed
- FIG. 16 (C3) shows the total number SUM_BDC for each channel at that time.
- the total number SUM_BDC of the channel CH0 is 2100
- the total number SUM_BDC of the channel CH1 is 2000
- the total number SUM_BDC of the channel CH2 is 2000
- the total number SUM_BDC of the channel CH3 is 2000.
- the maximum value of the total number SUM_BDC is 2100, which is about 700 lower than the case where the write time reduction channel assignment is not performed.
- the maximum number of writes to the nonvolatile memory device NVM that is, the maximum write time can be shortened by reducing the maximum value of the total number SUM_BDC by channel assignment for write time reduction.
- the update timing of the address conversion table LPTBL and the erase count table ERSTBL for each block can be advanced, so that high-speed writing is possible.
- FIG. 18 shows another example of the write operation to the buffer BUF0 of the memory module NVMD0 and the nonvolatile memory devices NVM0 to NVM3 in response to the write request WQ from the host device CPU_CP in FIG.
- Step 31 of the operation described in FIG. 14 is changed to the operation of Step 32, and other operations are the same as those in FIG.
- Step 32 first, data bit inversion processing is performed as necessary on the write data DATA, and then the same operation as Step 31 described in FIG. 14 is performed.
- Step 351 the “0” bit number ZBCi in the m bit data mi is compared with the “1” bit number (m ⁇ ZBCi).
- the m-bit data mi is bit-inverted (Step 352), and the bit inversion flag IVFi is set to 0 (Step 353).
- the bit inversion flag IVFi is set to 1 (Step 354).
- the subsequent operation is the same as Step 31 described in FIG. Since the number of bits of the “0” data in the write data DATA can be reduced to half or less by the data bit inversion process, the total number SUMF0 of 0 values of the boundary flag BD for the write data DATA obtained by the subsequent process can be reduced. . That is, by the data bit inversion process, the number of times of writing to the nonvolatile memory devices NVM0 to NVM3 is reduced, and the writing time can be shortened.
- Step 4 the write data DATA, the boundary flag BD corresponding to these data, the bit inversion flag IVF, and the total number BDSUM0 of the boundary flag BD0 values are written into the buffer BUF0.
- the number of 0 data bits in the write data DATA is 5440 ⁇ 8 bits, which is 2/3
- the data bit inversion processing of FIG. 19 is executed, and the state immediately after Step 32 of FIG. 18 is executed is shown.
- the correspondence method between the write data DATA and the data mi is the same as in FIG.
- Data bit inversion reduces the number of 0 data bits in write data DATA to 1/3 of 2752 x 8 bits.
- the number of 0 of the BD value is 688, and the number of times of writing “0” data bits is 688 times. If the present embodiment is not used, the number of times of writing is 2048, so the number of times of writing can be reduced by 1360 times according to the present embodiment.
- the smaller the number of 0 of the boundary flag BD value the smaller the number of times of writing “0” data bits, and the write time can be shortened.
- FIG. 21 is a table showing an example of the data stored in the buffer and the boundary flag BD, which corresponds to FIG. 6 and FIG. 16, but is an example in which a data bit inversion process is further applied thereto.
- the total number BDSUM0 of 0 values of the boundary flags D0_BD to D7_BD corresponding to the write data DATA D0 to D7 is 710, 420, 950, 800, 960, 810, 700, and 500, respectively.
- FIG. 16C1 shows the total number of BDSUM0 values when the data bit inversion process is not performed. Compared with these values, the value of the total number BDSUM0 is obtained by performing the data bit inversion process. Can be greatly reduced.
- FIG. 21 (B2) shows the channel assignment for data D0 to D7 when the write time reduction channel assignment is not performed, and FIG. 21 (B3) shows the total number SUM_BDC for each channel at that time.
- Write data D0 and D4 are assigned to channel CH0
- write data D1 and D5 are assigned to channel CH1
- write data D2 and D6 are assigned to channel CH2
- write data D3 and D7 are assigned to channel CH3.
- the total number SUM_BDC of the channel CH0 is 1670
- the total number SUM_BDC of the channel CH1 is 1230
- the total number SUM_BDC of the channel CH2 is 1650
- the total number SUM_BDC of the channel CH3 is 1300.
- the total number SUM_BDC of channel CH0 1670 is the maximum number of times of writing to the nonvolatile memory device NVM, and this is the maximum write time.
- FIG. 21 (C2) shows the conventional channel assignment for data D0 to D7 when the write time reduction channel assignment is performed in Step 61 in FIG. 18, and FIG. Indicates the total number SUM_BDC for each channel.
- the total number SUM_BDC of the channel CH0 is 1380
- the total number SUM_BDC of the channel CH1 is 1450
- the total number SUM_BDC of the channel CH2 is 1510
- the total number SUM_BDC of the channel CH3 is 1510.
- the maximum value of the total number SUM_BDC is 1510, which is reduced by about 160 compared with the case where the write time reduction channel assignment is not performed.
- the maximum number of writes to the nonvolatile memory device NVM that is, the maximum write time can be shortened.
- the update timing of the address conversion table LPTBL and the erase count table ERSTBL for each block can be advanced, so that high-speed writing is possible.
- FIG. 22A shows the writing time of data D0 to D7 in the memory module NVMD0 when this embodiment is not used.
- FIG. 22B shows the writing time of the data D0 to D7 in the memory module NVMD0 in the control using the “boundary flag BD” of the present embodiment.
- FIG. 22C shows the writing time of the data D0 to D7 in the memory module NVMD0 in the control using the “boundary flag BD” and “channel allocation” of the present embodiment.
- FIG. 22A corresponds to a conventional example
- FIG. 22B corresponds to an example using the control shown in FIG. 6 or 16B
- FIG. 22C corresponds to FIG. This corresponds to an example using the control shown.
- the maximum number of writes to channel CH0 (nonvolatile memory device NVM0) is 4096.
- the number of times of writing to each channel is reduced and the writing time is shortened by the control using the “boundary flag BD” of the present embodiment.
- the maximum write count of the channel CH1 is reduced and the write time is shortened by the control using the “boundary flag BD” and “channel allocation” of the present embodiment.
- FIG. 23A shows the write time of data D0 to D7 in the memory module NVMD0 when this embodiment is not used
- FIG. 23B shows the “bit inversion processing” and “boundary” of this embodiment
- FIG. 23C shows the write time of the data D0 to D7 in the memory module NVMD0 under the control using the flag BD.
- FIG. 23C shows the “bit inversion process”, the “boundary flag BD” of this embodiment, The write time of data D0 to D7 in the memory module NVMD0 in the control using “channel allocation” is shown.
- FIG. 23A corresponds to a conventional example
- FIG. 23B corresponds to an example using the control shown in FIG. 21B
- FIG. 23C shows the control shown in FIG. Corresponds to an example using.
- the maximum number of writes to channel CH0 is 4096.
- the number of times of writing to each channel is greatly reduced and the writing time is shortened by the control using the “bit inversion processing” and the “boundary flag BD” of the present embodiment.
- the maximum number of times of writing to the channel CH0 is reduced by the control using the “bit inversion processing”, the “boundary flag BD”, and the “channel allocation” of the present embodiment, and the writing time is reduced. Shortened.
- FIG. 24 shows a data copy operation performed by the information processing circuit MNGR in FIG. 2 during the garbage collection operation of this embodiment.
- the garbage collection process is started from the point when Step 7 in FIG. 14 ends (Step 0).
- Garbage collection itself is a well-known technique, but in the following, features specific to this embodiment will be mainly described.
- the information processing circuit MNGR reads the number of erased blocks of the memory module NVMD0 stored in the storage device M2 from the nonvolatile memory devices NVM0 to NVM3, and compares the number of erased blocks with a specified value B (Step 1). If the number of erased blocks is B or less, Step 2 is executed, otherwise Step 15 (end) is executed.
- Step 2 the information processing circuit MNGR selects L1 written blocks of the non-volatile memory devices NVM0 to NVM3 whose erase count is N1 or more.
- Step 3 L2 erased blocks of the non-volatile memory devices NVM0 to NVM3 whose erase count is N2 or less are selected.
- the valid page data PDATA in the L1 blocks of the nonvolatile memory devices NVM0 to NVM3 selected in Step 2 are sequentially read.
- the data PDATA is composed of data DATA and redundant data Rdata.
- the redundant data Rdata includes a data inversion flag IVF, a boundary flag BDF, and ECC codes ECC1 and ECC2.
- the information processing circuit MNGR transfers the read instruction RDgc and the physical address PAD10 to the read queue circuits RDQ0 to RDQ3 via the arbitration circuit ARB.
- this read command RDgc is a read command generated from other than a read request of the host device CPU_CP.
- the memory control circuits (NVCT0 to NVCT3) read the read instruction RDgc from the read queue circuits RDQ0 to RDQ3, and transfer the read instruction RD10 corresponding to the read instruction RDgc and the physical address PAD10 to the nonvolatile memory devices (NVM0 to 3) To do.
- the read command RD10 is a command for reading the boundary flag BD, data DATA0, and ECC codes ECC1 and ECC2 (a list of commands will be described later with reference to FIG. 26).
- the non-volatile memory devices use the read command RD10 and the physical address PAD10, the data DATA10 corresponding to the physical address PAD10, the inversion flag IVF of the data DATA10, the ECC code ECC1, the boundary flag BD, and the boundary flag BD.
- the ECC code ECC2 is transferred to the memory control circuit (NVCT0 to NVCT3).
- Step 5 the memory control circuit NVCT uses the ECC code ECC1 to check whether there is an error in the data DATA10 and the inversion flag IVF. Also, using the ECC code ECC2, it is checked whether there is an error in the boundary flag BD. If there is an error in these, correction is performed, and data DATA10, inversion flag IVF, boundary flag BD, ECC code ECC1, and ECC code ECC2 are transferred to read queue circuits (buffers) RDQ0 to RDQ3.
- the information processing circuit MNGR reads the data by the read command RDgc and stores the NDATA low for the data DATA10, the inversion flag IVF, the boundary flag BD, the ECC code ECC1, and the ECC code ECC2 stored in the read queue circuits RDQ0 to RDQ3.
- Step 6 it is checked whether all the valid page data PDATA in the L1 blocks of the nonvolatile memory devices NVM0 to NVM3 selected in Step 2 have been transferred to the buffer BUF0. If the transfer has not been completed, Step 7 is executed. If the transfer has been completed, Step 8 is executed.
- Step 7 it is checked whether the copy area CAREA of the buffer BUF0 is filled with the data read from the nonvolatile memory device NVM. If it is satisfied, Step 8 is executed, and if not satisfied, Step 4 is executed.
- Step 8 the information processing circuit MNGR, the physical address PAD10 in the erased block selected in Step 3 in the copy area CAREA, the inversion flag INVF, the boundary flag BD stored in the copy area CARARE of the buffer BUF0, Data DATA10, ECC codes ECC1, ECC2, and program instruction PRGgc are transferred to write queue circuits WTQ0 to WTQ3.
- the memory control circuit NVCT reads the inversion flag INVF, the boundary flag BD, DATA10, and the ECC codes ECC1 and ECC2 stored in the write queue circuits WTQ0 to WTQ3, and programs the nonvolatile memory devices NVM0 to NVM3.
- the instruction PRG01, physical address PAD100, inversion flag INVF, boundary flag BD, data DATA10, and ECC codes ECC1 and ECC2 are transferred.
- Program instruction PRG01 is an instruction for writing inversion flag INVF, boundary flag BD, data DATA10, and ECC codes ECC1 and ECC2 to nonvolatile memory devices NVM0 to NVM3. Since the program instruction PRG01 writes the boundary flag BD into the memory, the nonvolatile memory devices NVM0 to NVM3 can reuse the boundary flag BD for garbage collection processing.
- Nonvolatile memory devices NVM0 to NVM3 write inversion flag INVF, boundary flag BD, DATA10, and ECC codes ECC1 and ECC2 to internal memory cells by program instruction PRG01.
- Step 9 it is checked whether all the valid page data PDATA in the L1 blocks of the nonvolatile memory devices NVM0 to NVM3 selected in Step 2 have been transferred to the nonvolatile memory device. If all of the data PDATA has been transferred to the nonvolatile memory devices NVM0 to NVM3, Step 10 is executed, and if not, Step 4 is executed. In Step 10, the written block selected in Step 2 is erased.
- the information processing circuit MNGR sends the priority read instruction RDpri and physical address to the read queue circuits RDQ0 to RDQ3 via the arbitration circuit ARB. Transfer PAD20.
- the memory control devices (NVCT0 to NVCT3) read the priority read instruction RDpri and the physical address PAD50 from the read queue circuits RDQ0 to RDQ3, and the physical address PAD50 is in the nonvolatile memory device (NVM0 to 3) that is currently performing the erase operation. If it is a physical address, the erase operation temporary interruption command Erase_pause is transferred to the nonvolatile memory devices (NVM0 to NVM3) that are performing the erase operation.
- the nonvolatile memory device in the erasing operation receives the erase operation temporary interruption command Erase_pause, the non-volatile memory device completes the erasing operation to the chain memory array for L bytes currently being erased, and temporarily suspends the erasing operation. The maximum time until the erasing operation is temporarily interrupted is t10.
- the memory control devices (NVCT0 to NVCT3) transfer the read command RD01 and the physical address PAD50 to the nonvolatile memory devices (NVM0 to NVM3).
- the nonvolatile memory devices (NVM0 to NVM3) output the data DATA50 of the physical address PAD50, the inversion flag IVF, and the ECC code ECC1 to the memory control device, and further transfer them to the read queue circuits RDQ0 to RDQ3 by the memory control device.
- the memory control devices (NVCT0 to NVCT3) transfer the erase operation restart command Erase_restart to the nonvolatile memory devices (NVM0 to 3) that have temporarily suspended the erase operation.
- the nonvolatile memory device that has temporarily suspended the erase operation resumes the next erase operation to the chain memory array for L bytes.
- the memory controller NVCT uses the ECC code ECC1 to check whether there is an error in the data DATA50 and the inversion flag IVF. If there is an error, the memory controller NVCT corrects the error and sends the data DATA50 and the read queue circuit RDQ0 to RDQ3. Transfer the inversion flag IVF.
- the information processing circuit MNGR checks whether the inversion flag IVF value is zero. If the inversion flag IVF value is 0, each bit of the data DATA50 is inverted, data DATA50R is generated, and transferred to the host device CPU_CP through the interface circuit NVM_IF.
- Step 12 it is checked whether all written blocks selected in Step 2 have been erased. If all the written blocks selected in Step 2 are erased, Step 13 is performed. If all the written blocks selected in Step 2 are not erased, Step 10 is performed.
- Step 13 it is checked whether the number of erased blocks is greater than B. If the number of erased blocks is greater than B, Step 14 is performed, otherwise Step 2 is performed.
- Step 14 the information processing circuit MNGR updates the logical / physical address conversion table LPTBL, the physical address conversion table PLTBL, the erase count table ERSTBL for each block, and the erase block count table ERSTBL1 stored in the memory device M2.
- the inversion flag IVF and the boundary flag BD are stored in the nonvolatile memory device NVM.
- the data bit inversion operation in FIG. 18 and the series of boundary detection operations in Step 3 in FIG. 3, Step 31 in FIG. 14, and Step 32 in FIG. 18 are re-executed. There is no need to do. Therefore, the speed of the garbage collection operation and the data copy operation during the static wear leveling operation can be increased.
- the inversion flag IVF, the boundary flag BD, and the ECC codes ECC1 and ECC2 are already prepared. There is no need to execute the boundary processing shown in FIG. 4 by the circuit MNGR and the data bit inversion processing shown in FIG. 19, and it is not necessary to generate the ECC codes ECC1 and ECC2 in the memory control circuit NVCT. Data transfer to the device NVM can be performed at high speed.
- the read command from the host can be preferentially executed during the erase operation of the block by the temporary interrupt command Erase_pause of the erase operation, the read from the host can be accelerated. Further, since the erase operation to the next L bytes of the chain memory array can be resumed by the erase operation restart instruction Erase_restart, it is necessary to perform the erase operation redundantly on the same L bytes of the chain memory array. In addition, reading from the host can be speeded up without causing unnecessary erasing operation.
- Erase_pause and Erase_restart are included in various commands shown in FIG. 26 that can be used in the memory control circuits NVCT0 to NVCT3.
- Various settings can be made by setting the validity of each command as shown in FIG. It is possible to support this system.
- FIG. 25 is an example of a read operation of the memory module NVMD0 when a read request from the host device CPU_CP is input to the memory module NVMD0.
- Step 1 the read request RQ including the logical address LAD, the data read command RD, the sector count SEC, etc. is sent from the host device CPU_CP of FIG. 1 through the interface circuit NVM-IF of the control circuit NVM-CTL. Input to MNGR.
- the information processing circuit MNGR that has received the request first checks whether the access from the higher-level device CPU_CP is a read request RQ. If the access is the read request RQ, Step 2 is performed.
- Step 2 the information processing circuit MNGR stores the logical address LAD, the data read command RD, the sector count SEC, etc. in the address / command buffer ADCBUF.
- Step 3 the information processing circuit MANAGER decodes the logical address value LAD0, the data read instruction RD, and the sector count SEC1, and stores the physical address stored in the address LAD0 in the address conversion table LPTBL stored in the memory device M2.
- the value CPAD0 and the valid flag CVF value corresponding to the physical address value CPAD0 are read.
- Step 4 the information processing circuit MANAGER checks whether or not the read valid flag CVF value is 1. When the valid flag CVF value is 0, it indicates that the physical address CPAD is not assigned to the logical address LAD0, and data cannot be read from the non-volatile memory device NVM. This is transmitted to the host device CPU_CP through the interface circuit NVM_IF (Step 10). If the valid flag CVF value is 1 (valid), Step 5 is performed.
- Step 5 when the physical address CPAD0 corresponds to the logical address LAD0, the information processing circuit MNGR transfers the read instruction RDht and the physical address value CPAD0 to the read queue circuits RDQ0 to RDQ3 via the arbitration circuit ARB. Further, this read command RDht indicates that it is a read command in response to a read request RQ from the host device CPU_CP.
- FIG. 26 is a table showing a list of NVM command functions issued by the information processing circuit (MNGR) to the nonvolatile memory device NVM via the memory control circuits (NVCT0 to NVCT3).
- MNGR information processing circuit
- NVCT0 to NVCT3 memory control circuits
- RD01 and RD10 described below are defined as commands.
- the commands shown in FIG. 26 are cited and described. For example, in this embodiment, writing using the boundary flag, writing command PRG01 that writes the boundary flag to the memory cell, writing using the boundary flag, writing command PRG10 that does not write the boundary flag to the memory cell, and boundary flag
- the conventional write command PRG00 that is not used can be supported.
- RD10 or the like for reading the boundary flag BD and RD01 or the like for not reading can be selected.
- the reading time can be shortened by using RD00 or RD01.
- the boundary flag BD is necessary for reading at the time of garbage collection assuming writing, RD10 or RD22 is used.
- FIG. 27 is an example of setting data stored in the register SPREG in FIG. 7 in order to switch the mode of the NVM command in FIG. This setting is performed by the command Set SPREG in FIG.
- the memory control circuit (NVCT0 to NVCT3) reads the read command RDht from the read queue circuits RDQ0 to RDQ3, recognizes that the read command RDht is a read command based on the read request RQ from the host device CPU_CP, and reads the read command RD01,
- the physical address CPAD0 is transferred to the nonvolatile memory devices (NVM0 to NVM3).
- the read instruction RD01 is an instruction for reading only the data DATA, the inversion flag IVF, and the ECC code ECC1 without reading the boundary flag.
- the non-volatile memory device uses the read command RD01 and the physical address CPAD0 to send data DATA0 corresponding to the physical address CPAD0 and the inversion flag IVF and ECC1 corresponding to the data DATA0 to the memory control circuit (NVCT0 to NVCT3). ).
- Step 6 the memory control circuit NVCT uses the ECC code ECC1 to check whether there is an error in the data DATA0 and the inversion flag IVF. If there is an error, the memory control circuit NVCT corrects the error and sends data DATA0 and RDQ3 to the read queue circuit RDQ0 Transfer the inversion flag IVF.
- Step 7 the information processing circuit MNGR checks whether the inversion flag IVF value is 0. If the inversion flag IVF value is 0, each bit of the data DATA is inverted to generate data DATA_R (Step 8) and transferred to the host device CPU_CP through the interface circuit NVM_IF (Step 9).
- the nonvolatile memory devices NVM0 to NVM3 support a read-only command RD01 from the host device and a read command RD10 that reads all flags together with data.
- the control circuit (controller) NVM-CTL issues a read instruction RD01 to the non-volatile memory devices NVM0 to NVM3 in response to a read request from the host device, during garbage collection or static wear leveling operation, etc.
- a read command RD10 can be issued, so that optimum control according to the request source is possible.
- the “0” data bit is set. Since the internal address range that can be written at one time can be specified and written, the number of times of writing is reduced, the writing time is shortened, the power consumption of the memory module is reduced, and the writing speed can be improved.
- the total number of boundary flag BD values 0 for the write data is obtained, and by assigning the write data to the channels so that the total number of boundary flag BD values 0 is uniform among the channels, The writing time can be shortened and the writing speed of the memory module can be improved.
- the boundary flag BD for the write data that has undergone bit inversion processing, the number of boundary flag BD values 0 can be greatly reduced, the writing time of the nonvolatile memory can be shortened, and the memory module Can improve the writing speed.
- the present invention made by the present inventor has been specifically described based on the embodiment.
- the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.
- the above-described embodiment has been described in detail for easy understanding of the present invention, and is not necessarily limited to one having all the configurations described.
- a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. .
- the phase change memory has been mainly described as a representative, but a resistance change type memory including a ReRAM or the like can be similarly applied to obtain the same effect.
- the description has been given by taking as an example a memory having a three-dimensional structure in which a plurality of memory cells are sequentially stacked in the height direction with respect to the semiconductor substrate.
- the same effect can be obtained by applying the same to a two-dimensional memory in which one memory cell is arranged.
- CPU_CP Host device, NMV-CTL ... Control circuit, MNGR ... Information processing circuit, NVM0-3 ... Nonvolatile memory device, NVMD0 ... Memory module, NVCT0-NVCT3 ... Memory control circuit
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Abstract
Disclosed is a method of writing data to memory which comprises a plurality of memory cells which are capable of being made to transition into at least two states, said method writing data by causing the transition of the states of the memory cells. When writing the data to the memory, inputted data is divided into data units of m bits, and the data units which are contiguous in a range in which the number of bits of data for which the transition of the memory cell state is necessary to write the data takes a maximum which is less than or equal to a threshold is written in a single operation.
Description
本発明は、記憶装置に関し、特に不揮発性メモリ装置を備えた記憶装置に関する。
The present invention relates to a storage device, and more particularly to a storage device including a nonvolatile memory device.
近年、不揮発性メモリ装置として、記録材料にカルコゲナイト材料を用いた相変化メモリが盛んに研究されている。相変化メモリとは、電極間の記録材料が異なる抵抗状態を持つことを利用し、情報を記憶する抵抗変化型メモリの一種である。
Recently, a phase change memory using a chalcogenite material as a recording material has been actively studied as a nonvolatile memory device. A phase change memory is a type of resistance change memory that stores information by utilizing the fact that recording materials between electrodes have different resistance states.
相変化メモリにおいては、Ge2Sb2Te5などの相変化材料の抵抗値がアモルファス状態と結晶状態とで異なることを利用して情報を記憶する。アモルファス状態では抵抗が高く(高抵抗状態)、結晶状態では抵抗が低い(低抵抗状態)。従って、相変化メモリからの情報読み出しは、素子の両端に電位差を与え、素子に流れる電流を測定し、素子の高抵抗状態/低抵抗状態を判別することにより実現する。
In the phase change memory, information is stored by utilizing the fact that the resistance value of a phase change material such as Ge 2 Sb 2 Te 5 is different between an amorphous state and a crystalline state. In the amorphous state, the resistance is high (high resistance state), and in the crystal state, the resistance is low (low resistance state). Therefore, reading of information from the phase change memory is realized by applying a potential difference to both ends of the element, measuring the current flowing through the element, and determining the high resistance state / low resistance state of the element.
相変化メモリにおいては、電流により発生するジュール熱によって、相変化材料により構成されたところの相変化膜の電気抵抗を異なる状態に変化させることによりデータを書き換える。
In the phase change memory, the data is rewritten by changing the electric resistance of the phase change film formed of the phase change material to a different state by Joule heat generated by current.
図28は、相変化材料を用いた抵抗性記憶素子の相変化に必要なパルス幅と温度との関係を示す図である。同図において、縦軸は温度を表し、横軸は時間を表す。この記憶素子に記憶情報“0”を書込む場合には、図28に示す様に、大電流を流して記憶素子をカルコゲナイド材料の融点Ta以上に熱してから急冷する様なリセットパルスを印加する。この場合、冷却時間t1を短くすることにより(例えば約1nsに設定することにより)、カルコゲナイド材料は高抵抗のアモルファス(非晶質)状態となる。逆に、記憶情報“1”を書込む場合には、記憶素子を融点Taよりも低いが、結晶化温度Tx(ガラス転移点と同じかそれよりも高い)よりも高い温度領域に保つ様な十分な電流を流すようにセットパルスを長時間印加する。これにより、カルコゲナイド材料は低抵抗の多結晶状態となる。
FIG. 28 is a diagram showing the relationship between the pulse width and temperature necessary for the phase change of the resistive memory element using the phase change material. In the figure, the vertical axis represents temperature and the horizontal axis represents time. When the storage information “0” is written in the storage element, as shown in FIG. 28, a reset pulse is applied so that a large current is passed to heat the storage element to the melting point Ta or higher of the chalcogenide material and then rapidly cool. . In this case, by shortening the cooling time t1 (for example, by setting to about 1 ns), the chalcogenide material becomes a high resistance amorphous state. On the other hand, when the memory information “1” is written, the memory element is kept in a temperature range lower than the melting point Ta but higher than the crystallization temperature Tx (same or higher than the glass transition temperature). A set pulse is applied for a long time so that a sufficient current flows. Thereby, the chalcogenide material is in a low-resistance polycrystalline state.
特許文献1には、相変化メモリなどの抵抗変化型メモリにおいて、バッファに保存されているMバイトのデータを、nバイト(M>n)単位で、時分割で書込むことが示されている。
Patent Document 1 discloses that in a resistance change type memory such as a phase change memory, M-byte data stored in a buffer is written in n-byte (M> n) units in a time-sharing manner. .
特許文献2には、ReRAMなどの抵抗変化型メモリの書込み方法において、書込むデータの中で、特定の値のビット数が基準値を超えた場合、そのデータを反転し、不揮発性メモリへそのデータを転送し、抵抗変化型メモリへ書込むことが示されている。
In Patent Document 2, in the writing method of the resistance change type memory such as ReRAM, when the number of bits of a specific value exceeds the reference value in the data to be written, the data is inverted and the data is transferred to the nonvolatile memory. It is shown that data is transferred and written to a resistance change type memory.
また、特許文献3には抵抗変化型メモリの書込み方法において、“1”のビットデータの数が“0”のビットデータの数より大きい場合は、書込みデータの各ビットを反転させそのデータを反転し、不揮発性メモリへそのデータを転送し、不揮発性メモリへ書込むことが示されている。
Further, in Patent Document 3, in the resistance change memory writing method, when the number of bit data of “1” is larger than the number of bit data of “0”, each bit of the write data is inverted and the data is inverted. It is shown that the data is transferred to the nonvolatile memory and written to the nonvolatile memory.
本発明者らは、本願に先立ち、抵抗変化型メモリの制御方法について検討した。抵抗変化型メモリへの書込み時の消費電力は、一般に書き換えるビット数が多いほど大きくなる。言い換えると、抵抗変化型メモリの最大消費電力の制限により、一度に書き換えるビット数にも制限がある。特許文献2および3に示されている抵抗変化型メモリへの書込み方法では、書込むデータの中で、特定の値のビット数が基準値を超えた場合、そのデータを反転し、不揮発性メモリへ書込むことで、書き換えるビット数を削減し、書込み時の消費電力を低減することができる。
Prior to the present application, the present inventors examined a control method of the resistance change type memory. In general, the power consumption during writing to the resistance change memory increases as the number of bits to be rewritten increases. In other words, there is a limit to the number of bits that can be rewritten at one time due to the limitation on the maximum power consumption of the resistance change type memory. In the writing method to the resistance change type memory shown in Patent Documents 2 and 3, when the number of bits of a specific value exceeds the reference value in the data to be written, the data is inverted, and the nonvolatile memory By writing to, the number of bits to be rewritten can be reduced, and the power consumption at the time of writing can be reduced.
しかし、書込み動作時に選択する抵抗変化型メモリの内部アドレスの選択回数、つまり書込み回数を削減できないため、書込み速度を向上できないことが判明した。
However, it has been found that the write speed cannot be improved because the number of selections of the internal address of the resistance change type memory to be selected during the write operation, that is, the write count cannot be reduced.
本願発明は、上記のような課題に鑑みてなされたものである。本願発明の第1の目的は、高性能化、低電力化を実現する半導体装置を提供することにある。
The present invention has been made in view of the above problems. A first object of the present invention is to provide a semiconductor device that realizes high performance and low power.
本願発明の前記並びにその他の目的と新規な特徴は、本明細書の記述及び添付図面から明らかになるであろう。
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、次のとおりである。
本発明の一側面は、情報処理回路を具備し、メモリを制御するメモリの制御装置である。この情報処理回路は、メモリへの書込みデータをmビット毎に分けた各データ単位に対して、バウンダリフラグを設ける。バウンダリフラグは、書込みデータの中で、特定の値のビットの数が閾値を超えない最大値になるような、データ単位の連続する範囲を示す。 Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.
One aspect of the present invention is a memory control device that includes an information processing circuit and controls a memory. This information processing circuit provides a boundary flag for each data unit obtained by dividing write data into the memory every m bits. The boundary flag indicates a continuous range of data units in which the number of bits having a specific value in the write data becomes a maximum value that does not exceed the threshold value.
本発明の一側面は、情報処理回路を具備し、メモリを制御するメモリの制御装置である。この情報処理回路は、メモリへの書込みデータをmビット毎に分けた各データ単位に対して、バウンダリフラグを設ける。バウンダリフラグは、書込みデータの中で、特定の値のビットの数が閾値を超えない最大値になるような、データ単位の連続する範囲を示す。 Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.
One aspect of the present invention is a memory control device that includes an information processing circuit and controls a memory. This information processing circuit provides a boundary flag for each data unit obtained by dividing write data into the memory every m bits. The boundary flag indicates a continuous range of data units in which the number of bits having a specific value in the write data becomes a maximum value that does not exceed the threshold value.
本発明の他の一側面は、不揮発性メモリと、不揮発性メモリへ書込みを行う制御回路と、を有する記憶装置である。制御回路は、不揮発性メモリへの書込みデータをmビット毎に分けた、それぞれのデータ単位m1~mn(ただし、nは自然数)に対して、バウンダリフラグを設ける。バウンダリフラグは、書込みデータの中で、特定の値のビットの数が閾値を超えない最大値になる、データ単位の連続する範囲を示す。データ単位の連続する範囲mx~my(ただし、n≧y≧x≧1)の中で、特定の値のビットの数が閾値を超えない場合には、データ単位mxおよびmyの少なくとも一つに対する前記バウンダリフラグを第1の値とし、それ以外のデータ単位に対する前記バウンダリフラグを第2の値とする。
Another aspect of the present invention is a storage device including a nonvolatile memory and a control circuit that performs writing to the nonvolatile memory. The control circuit provides a boundary flag for each of the data units m1 to mn (where n is a natural number) obtained by dividing write data to the nonvolatile memory for each m bits. The boundary flag indicates a continuous range of data units in which the number of bits having a specific value in the write data is a maximum value that does not exceed the threshold value. For at least one of the data units mx and my if the number of bits of a specific value does not exceed the threshold within the continuous range of data units mx to my (where n ≧ y ≧ x ≧ 1) The boundary flag is set to a first value, and the boundary flag for other data units is set to a second value.
本発明のさらに他の一側面は、少なくとも2つの状態に遷移可能なメモリセルを複数備え、メモリセルの状態を遷移させることでデータを書込むメモリに対するデータの書込み方法である。データをメモリに書込む際に、入力されたデータをmビットのデータ単位に分け、データを書込むためにメモリセルの状態を遷移させる必要のあるデータのビット数が、閾値以下の最大値をとる範囲の連続するデータ単位を一括して書込む。
Still another aspect of the present invention is a method for writing data to a memory that includes a plurality of memory cells that can transition to at least two states and writes data by transitioning the state of the memory cells. When writing data to the memory, the input data is divided into m-bit data units, and the number of data bits that need to change the state of the memory cell in order to write the data has a maximum value less than or equal to the threshold value. Write consecutive data units in a range.
本願において開示される発明のうち、代表的なものによって得られる効果を簡単に説明すれば以下のとおりである。
Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.
すなわち、不揮発性メモリを備えた、高性能で、低電力を実現する半導体装置を提供することができる。
That is, a high-performance and low-power semiconductor device including a nonvolatile memory can be provided.
以下の実施の形態においては、便宜上その必要があるときは、複数のセクションまたは実施の形態に分割して説明する。特に明示した場合を除き、それらは互いに無関係ではなく、一方は他方の一部または全部の変形例、応用例、詳細説明、補足説明等の関係にある。また、以下の実施の形態において、要素の数等(個数、数値、量、範囲等を含む)に言及する場合、特に明示した場合および原理的に明らかに特定の数に限定される場合等を除き、その特定の数に限定されるものではなく、特定の数以上でも以下でもよい。
In the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. Unless otherwise specified, they are not irrelevant to each other, and one is in the relationship of some or all of the other, modification, application, detailed explanation, supplementary explanation, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.
さらに、以下の実施の形態において、その構成要素(要素ステップ等も含む)は、特に明示した場合および原理的に明らかに必須であると考えられる場合等を除き、必ずしも必須のものではない。同様に、以下の実施の形態において、構成要素等の形状、位置関係等に言及するときは、特に明示した場合および原理的に明らかにそうでないと考えられる場合等を除き、実質的にその形状等に近似または類似するもの等を含むものとする。このことは、上記数等(個数、数値、量、範囲等を含む)についても同様である。
Furthermore, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified or apparently indispensable in principle. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numbers and the like (including the number, numerical value, quantity, range, etc.).
以下、本発明の実施の形態を図面に基づいて詳細に説明する。なお、実施の形態を説明するための全図において、同一の機能を有する部材には同一または関連する符号を付し、その繰り返しの説明は省略する。また、以下の実施の形態では、特に必要なとき以外は同一または同様な部分の説明を原則として繰り返さない。
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same or related reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.
実施の形態において各ブロックを構成する回路素子は特に制限されないが、公知のCMOS(相補型MOSトランジスタ)等の集積回路技術によって、単結晶シリコンのような1個の半導体基板上に形成される。また、実施の形態で述べるメモリセルとしては、相変化メモリ、ReRAM(Resistive Ramdam Access Memory)のような抵抗性記憶素子を用いるものとする。
In the embodiment, the circuit elements constituting each block are not particularly limited, but are formed on a single semiconductor substrate such as single crystal silicon by a known integrated circuit technology such as a CMOS (complementary MOS transistor). In addition, as a memory cell described in the embodiment, a resistive memory element such as a phase change memory or a ReRAM (Resistive Random Access Memory) is used.
以下で示される本実施例の半導体装置は、複数のメモリセルを含む不揮発性メモリと、不揮発性メモリをアクセスする制御回路とを具備している。制御回路は、書込みデータのmビット毎にバウンダリフラグBDを生成した後、書込みデータとバウンダリフラグBDを不揮発性メモリへ転送する。不揮発性メモリは、内部アドレスとバウンダリフラグBDを対応付けることで、一度に書き換えられる“0”データビット数の上限値まで含まれる複数の連続したアドレスを同時に選択し、書込みを行う。
The semiconductor device of the present embodiment shown below includes a nonvolatile memory including a plurality of memory cells and a control circuit that accesses the nonvolatile memory. The control circuit generates the boundary flag BD for each m bits of the write data, and then transfers the write data and the boundary flag BD to the nonvolatile memory. The nonvolatile memory associates the internal address with the boundary flag BD, and simultaneously selects and writes a plurality of consecutive addresses included up to the upper limit of the number of “0” data bits that can be rewritten at one time.
具体例を示すと、例えば消去状態ではデータビットは全て“1”になっており、データの書き込みは“1”を“0”データビットに書き換える。これは、物理的には、例えば電流による熱作用でメモリセルの状態を変更することに相当する。一度に状態を変更できるメモリセルの数は、回路が供給できる電流量などにより制約を受けるが、制約の範囲でなるべく多くのメモリセルを一括して“0”に書き換えれば、高速に書き込みが可能となる。理想的には、一度に書き換えられる“0”データビット数の上限値までを1回の書込みで記録することによって、“0”データビットの書込み回数が減少する。これにより、書込み時間とアドレス選択回数を削減でき、半導体装置のデータ転送速度が向上し、消費電力を削減できる。以下具体的に構成を説明する。
Specifically, for example, in the erase state, all data bits are “1”, and data writing is performed by rewriting “1” to “0” data bits. This physically corresponds to, for example, changing the state of the memory cell by a thermal action caused by an electric current. The number of memory cells whose states can be changed at a time is limited by the amount of current that can be supplied by the circuit. However, if as many memory cells as possible can be rewritten to “0” within the limits, writing can be performed at high speed. It becomes. Ideally, the number of times of writing “0” data bits is reduced by recording up to the upper limit of the number of “0” data bits that can be rewritten at one time. Thereby, the writing time and the number of address selections can be reduced, the data transfer speed of the semiconductor device can be improved, and the power consumption can be reduced. The configuration will be specifically described below.
図1は、本発明の一実施の形態によるメモリモジュールおよび情報処理システムの概略構成例を示すブロック図である。図1に示す情報処理システムは、上位装置(情報処理装置である例えばプロセッサ)CPU_CPとメモリモジュールNVMD0とを備える。上位装置CPU_CPは、特に限定しないがメモリモジュールNVMD0へ保存されているデータを512バイト単位の論理アドレスLADにて管理するホストコントローラである。上位装置CPU_CPは、インターフェース信号HDH_IFを通じ、このメモリモジュールNVMD0に対してデータの読み出しや書込みを行う。メモリモジュールNVMD0は、特に限定しないが、例えばSSD(Solid State Drive)等に該当するものである。
FIG. 1 is a block diagram showing a schematic configuration example of a memory module and an information processing system according to an embodiment of the present invention. The information processing system illustrated in FIG. 1 includes a host device (for example, a processor that is an information processing device) CPU_CP and a memory module NVMD0. The host device CPU_CP is a host controller that manages data stored in the memory module NVMD0 with a logical address LAD in units of 512 bytes, although not particularly limited. The host device CPU_CP reads / writes data from / to this memory module NVMD0 through the interface signal HDH_IF. The memory module NVMD0 is not particularly limited, but corresponds to, for example, SSD (Solid State Drive).
上位装置CPU_CPとメモリモジュールNVMD0を接続する信号方式には、シリアルインターフェース信号方式、パラレルインターフェース信号方式、光インターフェース信号方式などがあり、全ての方式を利用することができる。上位装置CPU_CPとメモリモジュールNVMD0を動作させるクロック方式には、コモンクロック方式およびソースシンクロナスクロック方式や、データ信号にクロック情報を埋め込むエンベデッドクロック方式などがあり、全てのクロック方式を利用することができる。本実施の形態では、一例としてシリアルインターフェース信号方式ならびにエンベデッドクロック方式を用いるものとし、以下に動作を説明する。
There are a serial interface signal system, a parallel interface signal system, an optical interface signal system, etc. as signal systems for connecting the host device CPU_CP and the memory module NVMD0, and all systems can be used. There are common clock methods, source synchronous clock methods, embedded clock methods that embed clock information in data signals, etc., and all clock methods can be used to operate the host device CPU_CP and memory module NVMD0. . In this embodiment, a serial interface signal system and an embedded clock system are used as an example, and the operation will be described below.
上位装置CPU_CPから、クロック情報が埋め込まれ、シリアルデータへ変換された読出し要求RQや書込み要求などがインターフェース信号HDH_IFを通じてメモリモジュールNVMD0へ入力される。読出し要求RQには論理アドレスLAD、データ読み出し命令RD、セクタカウントSECなどが含まれる。また、書込み要求には論理アドレスLAD、データ書込み命令WRT、セクタカウントSECおよび書込みデータDATAなどが含まれる。
From the host device CPU_CP, a read request RQ, a write request, etc., embedded with clock information and converted into serial data, are input to the memory module NVMD0 through the interface signal HDH_IF. The read request RQ includes a logical address LAD, a data read command RD, a sector count SEC, and the like. The write request includes a logical address LAD, a data write command WRT, a sector count SEC, write data DATA, and the like.
メモリモジュールNVMD0は、メモリ装置M0と、M1と、M2と、不揮発性メモリ装置NVM0~NVM3と、これらメモリ装置を制御する制御回路(コントローラ)NVM-CTLを備える。
The memory module NVMD0 includes memory devices M0, M1, and M2, nonvolatile memory devices NVM0 to NVM3, and a control circuit (controller) NVM-CTL that controls these memory devices.
不揮発性メモリ装置NVM0~NVM3は、例えば同じ構成および性能を備えている。また、これらのメモリ装置NVM0~NVM3には、NAND型フラッシュメモリ、NOR型フラッシュメモリ、相変化型メモリPCM、抵抗変化型メモリReRAM、スピン注入磁化反転型メモリSTT-MRAM、強誘電体メモリなどのいずれのメモリも利用できる。
Non-volatile memory devices NVM0 to NVM3 have, for example, the same configuration and performance. These memory devices NVM0 to NVM3 include NAND flash memory, NOR flash memory, phase change memory PCM, resistance change memory ReRAM, spin transfer magnetization reversal memory STT-MRAM, ferroelectric memory, etc. Either memory can be used.
メモリ装置M0およびM1はデータを一時的に格納する,バッファBUF0およびBUF1であり、それぞれには、書込み領域WAREAと、コピー領域CAREAが存在する。書込み領域WAREAはホストからの書込みデータを格納する領域であり、コピー領域CAREAは、ガーベージコレクションやスタティックウエアレベリング時の、不揮発性メモリ装置NVM0~NVM3の間のデータ移動に利用される領域である。また、メモリ装置M2には、制御回路NVM-CTLにて管理される上位装置CPU_CPからの論理アドレスLADと、メモリモジュールNVMD0内の不揮発性メモリ装置NVM0~NVM3の物理アドレスPADとの対応を行う論理物理アドレス変換テーブルLPTBLと、物理論理アドレス変換テーブルPLTBLと、ブロック毎の消去回数テーブルERSTBLと、アドレスマップADMAPが格納される。
Memory devices M0 and M1 are buffers BUF0 and BUF1 for temporarily storing data, and each has a write area WAREA and a copy area CAREA. The write area WAREA is an area for storing write data from the host, and the copy area CAREA is an area used for data movement between the nonvolatile memory devices NVM0 to NVM3 at the time of garbage collection or static wear leveling. In addition, the memory device M2 has a logic that performs correspondence between the logical address LAD from the host device CPU_CP managed by the control circuit NVM-CTL and the physical addresses PAD of the nonvolatile memory devices NVM0 to NVM3 in the memory module NVMD0. A physical address conversion table LPTBL, a physical logical address conversion table PLTBL, an erase count table ERSTBL for each block, and an address map ADMAP are stored.
制御回路NVM-CTLは、不揮発性メモリ装置NVM0~NVM3のブロック毎の消去回数が平準化するように、その物理アドレスPADを選択し、データの書込みを行う。データの書込みが終了した後、制御回路NVM-CTLは、アドレス変換テーブルLPTBLを更新する。
The control circuit NVM-CTL selects the physical address PAD and writes data so that the number of erases for each block of the nonvolatile memory devices NVM0 to NVM3 is leveled. After the data writing is completed, the control circuit NVM-CTL updates the address conversion table LPTBL.
また、制御回路NVM-CTLが、データを不揮発性メモリ装置NVM0~NVM3から読み出す場合、制御回路NVM-CTLは、アドレス変換テーブルLPTBLを参照し、論理アドレスLADに対する物理アドレスPADを決定し、物理アドレスPADに格納されたデータを読み出す。
When the control circuit NVM-CTL reads data from the nonvolatile memory devices NVM0 to NVM3, the control circuit NVM-CTL refers to the address conversion table LPTBL, determines the physical address PAD for the logical address LAD, and determines the physical address. Read data stored in PAD.
上位装置CPU_CPは、メモリモジュールNVMD0から、データ、OS、アプリケーションプログラムを読出し、実行する。また、上位装置CPU_CPによって、その実行結果はメモリモジュールNVMD0へ書き込まれる。
The host device CPU_CP reads and executes data, OS, and application programs from the memory module NVMD0. The execution result is written into the memory module NVMD0 by the host device CPU_CP.
図2は図1における制御回路NVM-CTLのブロック図である。制御回路NVM-CTLは、インターフェース回路NVM_IFと、アドレス/コマンドバッファADCBUFと、マップレジスタMAPREGと、調停回路ARBと、情報処理回路MNGRと、メモリ制御回路RAMC、NVCT0~NVCT3とを備える。
FIG. 2 is a block diagram of the control circuit NVM-CTL in FIG. The control circuit NVM-CTL includes an interface circuit NVM_IF, an address / command buffer ADCBUF, a map register MAPREG, an arbitration circuit ARB, an information processing circuit MNGR, and memory control circuits RAMC and NVCT0 to NVCT3.
メモリ制御回路RAMCは、図1のメモリ装置M0~M2を直接制御し、メモリ制御回路NVCT0~NVCT3は、図1の不揮発性メモリ装置NVM0~NVM3をそれぞれ直接制御する。メモリ制御回路NVCT0~NVCT3は、其々書込みと読み出しのためのキュー回路WTQ0~WTQ3、RDQ0~RDQを備える。
The memory control circuit RAMC directly controls the memory devices M0 to M2 in FIG. 1, and the memory control circuits NVCT0 to NVCT3 directly control the nonvolatile memory devices NVM0 to NVM3 in FIG. The memory control circuits NVCT0 to NVCT3 include queue circuits WTQ0 to WTQ3 and RDQ0 to RDQ for writing and reading, respectively.
アドレス/コマンドバッファADCBUFは、上位装置CPU_CPから制御回路NVM-CTLへ入力した論理アドレスLADと、データ読み出し命令RDと、データ書込み命令WTを一時的に蓄える。
The address / command buffer ADCBUF temporarily stores the logical address LAD, the data read command RD, and the data write command WT input from the host device CPU_CP to the control circuit NVM-CTL.
マップレジスタMAPREGには、アドレスマップADDMAPが格納され、1ブロックサイズ毎の不揮発性メモリ装置NVM0~NVM3内部のXアドレス、YアドレスおよびZアドレスの対応が示されている。
In the map register MAPREG, an address map ADDMAP is stored, and correspondence between the X address, Y address and Z address in the nonvolatile memory devices NVM0 to NVM3 for each block size is shown.
物理アドレスレジスタNext PADには、不揮発性メモリ装置NVM0~NVM3のブロック毎の消去回数が平準化するように、選択された物理アドレスPADが格納され、データの書込みの際に、利用される。
In the physical address register Next 格納 PAD, the selected physical address PAD is stored so that the number of erases for each block of the nonvolatile memory devices NVM0 to NVM3 is equalized, and is used when data is written.
図3は、上位装置CPU_CPからの書込み要求WQに対する、本実施例のメモリモジュールNVMD0の、バッファBUF0および不揮発性メモリ装置NVM0~NVM3への書込み動作の一例を示す。
FIG. 3 shows an example of a write operation to the buffer BUF0 and the non-volatile memory devices NVM0 to NVM3 of the memory module NVMD0 of this embodiment in response to a write request WQ from the host device CPU_CP.
書込みは、上位装置CPU_CPから書込み要求WQが、制御回路NVM_CTLのインターフェース回路NVM_IFを通じて、情報処理回路MNGRへ入力されることにより開始される。書込み要求WQには、論理アドレスLAD、データ書込み命令WRT、セクタカウントSECおよび書込みデータDATA(例えば8KB=8192ビット)などが含まれる。
Writing is started when a write request WQ is input from the host device CPU_CP to the information processing circuit MNGR through the interface circuit NVM_IF of the control circuit NVM_CTL. The write request WQ includes a logical address LAD, a data write command WRT, a sector count SEC, write data DATA (for example, 8 KB = 8192 bits), and the like.
書込み要求WQを受けた情報処理回路MNGRは、先ず、上位装置CPU_CPからのアクセスが書込み要求WQかをチェックする(Step1)。そのアクセスが書込み要求WQである場合、Step2を行う。書込み要求WQでは無い場合、再度上位装置CPU_CPからのアクセスを待つ。Step2では、情報処理回路MNGRは、以下の条件をチェックする。
The information processing circuit MNGR that has received the write request WQ first checks whether the access from the host device CPU_CP is the write request WQ (Step 1). If the access is a write request WQ, Step 2 is performed. If it is not the write request WQ, it waits for access from the host device CPU_CP again. In Step 2, the information processing circuit MNGR checks the following conditions.
条件:「バッファBUF0が不揮発性メモリ装置NVM0~NVM3への書込み対象となるバッファであり、且つ、バッファBUF0にはデータを格納する空き領域がある」あるいは
「バッファBUF1が不揮発性メモリ装置NVM0~NVM3への書込み対象となるバッファであり、且つ、バッファBUF1は空き領域が無い、且つバッファBUF0にはデータを格納する空き領域がある」
この条件を満たした場合、Step3を実行し、満たさなかった場合、Step5を実行する。 Condition: “The buffer BUF0 is a buffer to be written to the nonvolatile memory devices NVM0 to NVM3, and the buffer BUF0 has a free space for storing data” or “the buffer BUF1 is a nonvolatile memory device NVM0 to NVM3. BUF1 has no free space, and buffer BUF0 has free space to store data. ''
If this condition is satisfied,Step 3 is executed, and if not satisfied, Step 5 is executed.
「バッファBUF1が不揮発性メモリ装置NVM0~NVM3への書込み対象となるバッファであり、且つ、バッファBUF1は空き領域が無い、且つバッファBUF0にはデータを格納する空き領域がある」
この条件を満たした場合、Step3を実行し、満たさなかった場合、Step5を実行する。 Condition: “The buffer BUF0 is a buffer to be written to the nonvolatile memory devices NVM0 to NVM3, and the buffer BUF0 has a free space for storing data” or “the buffer BUF1 is a nonvolatile memory device NVM0 to NVM3. BUF1 has no free space, and buffer BUF0 has free space to store data. ''
If this condition is satisfied,
Step3では、情報処理回路MNGRは、書込みデータDATA(8KB=8192ビット)の中をmビット毎に分けたそれぞれのmビットのデータmi(i=0,1,2,~,M/m;ただしMは書込みデータ量(ビット)で本実施例では8KB)に対して、バウンダリフラグBDiの1値あるいは0値を対応付ける。この、Step3内での一連の処理によって、書込みデータDATAの中をmビット毎に分けたi番目のデータmiに対して,それぞれi番目のバウンダリフラグBDi値が割り当てられる。
In Step 3, the information processing circuit MNGR is configured to write the data m (i = 0, 1, 2, ..., M / m) for each m bits obtained by dividing the write data DATA (8 KB = 8192 bits) into m bits. M is a write data amount (bit), which is 8 KB in this embodiment), and associates a 1 or 0 value of the boundary flag BDi. Through a series of processes in Step 3, the i-th boundary flag BDi value is assigned to the i-th data mi obtained by dividing the write data DATA every m bits.
図4を用いて、Step3の詳細動作を説明する。先ず、Step3の実行開始時STARTでi=0とし、次のStep300で書込みデータDATA(8KB=8192ビット)の中を、mビット毎に分けて、i番目のmビットデータmiの中の“0”ビットの数を計算する(SUMi)。mビットは、不揮発性メモリ装置NVM0~NVM3が、一度に書き込める“0”データのビット数を超えない値に設定するが、本実施例では、不揮発性メモリ装置NVM0~NVM3が、一度に書き込める“0”データのビット数とした。
The detailed operation of Step 3 will be described with reference to FIG. First, at the start of execution of Step 3, i = 0 is set at START, and in the next Step 300, write data DATA (8 KB = 8192 bits) is divided into m bits, and “0” in i-th m-bit data mi “Calculate the number of bits (SUMi). The m bit is set to a value that does not exceed the number of bits of “0” data that can be written at once by the nonvolatile memory devices NVM0 to NVM3. In this embodiment, the nonvolatile memory devices NVM0 to NVM3 can write at a time “ The number of bits of 0 ”data was used.
次のStep301で、“0”ビットの総数を計算する(SUM0)。次のStep302で、“0”ビットの総数SUM0が所定の閾値s(ここではs=mとする)より小さいかをチェックする。“0”ビットの総数SUM0がmより小さい場合、Step303を実行し、それ以外は、Step304を実行する。Step303ではバウンダリフラグBDを1に設定し、その後、Step310を実行する。
In the next Step 301, the total number of “0” bits is calculated (SUM0). In the next Step 302, it is checked whether the total number SUM0 of “0” bits is smaller than a predetermined threshold s (here, s = m). If the total number SUM0 of “0” bits is smaller than m, Step 303 is executed, otherwise Step 304 is executed. In Step 303, the boundary flag BD is set to 1, and then Step 310 is executed.
Step304では、Step303終了後は、“0”ビットの総数SUM0がmと等しいかをチェックする。“0”ビットの総数SUM0がmと等しければ、Step303を実行し、それ以外では、Step306を実行する。Step305ではバウンダリフラグBDを0に設定し、その後、Step309を実行する。
In Step 304, after Step 303 is finished, it is checked whether the total number SUM0 of “0” bits is equal to m. If the total number SUM0 of “0” bits is equal to m, Step 303 is executed, otherwise Step 306 is executed. In Step 305, the boundary flag BD is set to 0, and then Step 309 is executed.
Step306で、“0”ビットの総数SUM0がmより大きいことを確認した後、Step307にてBDi-1を0に設定する。Step307が終了した後、Step308にて現在のi値から1を減算した値をi値とした後、Step309を実行する。Step309では、“0”ビットの総数SUM0を、0に設定する。Step310では、現在のi値へ1を加算した値をi値とし、その後のStep311ではi値がM(=8KB=8192ビット)をmで除算した値以上かどうかをチェックする。i値がMをmで除算した値以上であれば、一連の処理を終了し、それ以外は、Step300を実行する。
In Step 306, after confirming that the total number SUM0 of “0” bits is larger than m, BDi-1 is set to 0 in Step 307. After Step 307 is completed, a value obtained by subtracting 1 from the current i value in Step 308 is set as the i value, and Step 309 is executed. In Step 309, the total number SUM0 of “0” bits is set to zero. In Step 310, a value obtained by adding 1 to the current i value is set as an i value, and in subsequent Step 311, it is checked whether or not the i value is equal to or larger than a value obtained by dividing M (= 8 KB = 8192 bits) by m. If the i value is equal to or greater than the value obtained by dividing M by m, the series of processing ends, and otherwise, Step 300 is executed.
図4に示す、Step3内での一連の処理によって、書込みデータDATAの中を、mビット毎に分けたi番目のデータmiに対して,それぞれi番目のバウンダリフラグBD値が割り当てられる。
As shown in FIG. 4, the i-th boundary flag BD value is assigned to the i-th data mi divided into m bits in the write data DATA by a series of processes in Step 3.
例えば、i番目のデータmiから連続したmi~mi+3の中で、mi+3のバウンダリフラグBDi値が0で、それ以外は1の場合、mi~mi+3のデータの中に、mビットを超える“0”データビットは存在しないことを示す。そこで、mi~mi+3のデータを、不揮発性メモリ装置NVM0~NVM3内部のアドレスへ対応させることにより、mi~mi+3のデータに含まれている“0”データビットを一度に書込むことができる。つまり、BDi値が0の数が、“0”データビットを書込む回数となり、このBDi値が0の数が少ないほど、“0”データビットを書込む回数は減少し、書込み時間を短縮することができる。
For example, if the boundary flag BDi value of mi + 3 is 0 in mi to mi + 3 consecutive from the i-th data mi and 1 otherwise, m is included in the data of mi to mi + 3. It indicates that there is no “0” data bit exceeding the bit. Therefore, by writing the data from mi to mi + 3 to the addresses in the non-volatile memory devices NVM0 to NVM3, the “0” data bits included in the data from mi to mi + 3 can be written at once. Can do. That is, the number of BDi values of 0 is the number of times of writing “0” data bits. The smaller the number of BDi values of 0, the smaller the number of times of writing “0” data bits and the shorter the write time. be able to.
また、情報処理回路MNGRは、mビットのm値を、プログラム可能である。mビットのm値は、不揮発性メモリ装置NVM0~NVM3内にて、一度に書込みを行えるデータビットの最大数に対応しており、各種不揮発性メモリ装置にて、このデータビットの最大数が異なる場合がある。そこで、情報処理回路MNGRは、このm値を、利用する不揮発性メモリ装置に合わせて変更することができ、適切なメモリモジュールNVMD0を構成できる。なお、上記の閾値sとmは必ずしも同じでなくてよいが、mを上記のように書込み可能なデータビットの最大値とすれば、m≧sが必要であり、s=mとするのが書込み速度の点からは好ましい。
Also, the information processing circuit MNGR can program m values of m bits. The m value of m bits corresponds to the maximum number of data bits that can be written at one time in the nonvolatile memory devices NVM0 to NVM3, and the maximum number of data bits differs in various nonvolatile memory devices. There is a case. Therefore, the information processing circuit MNGR can change the m value in accordance with the nonvolatile memory device to be used, and can configure an appropriate memory module NVMD0. Note that the threshold values s and m are not necessarily the same, but if m is the maximum value of writable data bits as described above, m ≧ s is required, and s = m This is preferable from the viewpoint of writing speed.
図5は、書込みデータDATAに対するバウンダリフラグBDiの対応付けを示す図である。図4で詳細を説明した図3のStep3が実行された直後の状態を示している。書込みデータDATA(8KB=8192ビット)の中を、mビット毎に分け、それぞれのmビット単位のデータmi(i=0,1,2,~,M/m)に対するバウンダリフラグBDiの対応付けを示している。書込みデータDATAは、D0[0]~D0[7]に分かれており、それぞれが1024ビットのデータを持つ。図中白丸が書込みデータDATAの“1”ビットを、黒丸が“0”ビットを示している。
FIG. 5 is a diagram showing the association of the boundary flag BDi with the write data DATA. FIG. 5 shows a state immediately after Step 3 of FIG. 3 described in detail in FIG. 4 is executed. The write data DATA (8KB = 8192 bits) is divided into m bits, and the boundary flag BDi is associated with each data mi (i = 0, 1, 2, ..., M / m) in m bits. Show. The write data DATA is divided into D0 [0] to D0 [7], each having 1024 bits of data. In the figure, white circles indicate “1” bits of write data DATA, and black circles indicate “0” bits.
D0[0]はデータm0~m255に分かれ、それぞれにバウンダリフラグBD0~255が割り当てられている。D0[1]はデータm256~m511に分かれ、それぞれにバウンダリフラグBD256~511が割り当てられている。D0[2]はデータm512~m767に分かれ、それぞれにバウンダリフラグBD512~767が割り当てられている。D0[3]はデータm768~m1023に分かれ、それぞれにバウンダリフラグBD768~1023が割り当てられている。D0[4]はデータm1024~m1279に分かれ、それぞれにバウンダリフラグBD1024~1279が割り当てられている。D0[5]はデータm1280~m1535に分かれ、それぞれにバウンダリフラグBD1280~1535が割り当てられている。D0[6]はデータm1536~m1791に分かれ、それぞれにバウンダリフラグBD1536~1791が割り当てられている。D0[7]はデータm1792~m2047に分かれ、それぞれにバウンダリフラグBD1792~2047が割り当てられている。これら、バウンダリフラグBD0~2047の中で、0値を持つバウンダリフラグBDは1365個ある。
D0 [0] is divided into data m0 to m255, and boundary flags BD0 to 255 are assigned to each. D0 [1] is divided into data m256 to m511, and boundary flags BD256 to 511 are assigned to the data m256 to m511, respectively. D0 [2] is divided into data m512 to m767, and boundary flags BD512 to 767 are assigned to the respective data. D0 [3] is divided into data m768 to m1023, and boundary flags BD768 to 1023 are assigned to the respective data. D0 [4] is divided into data m1024 to m1279, and boundary flags BD1024 to 1279 are assigned to the data m1024 to m1279, respectively. D0 [5] is divided into data m1280 to m1535, to which boundary flags BD1280 to 1535 are assigned, respectively. D0 [6] is divided into data m1536 to m1791, and boundary flags BD1536 to 1791 are assigned to the respective data. D0 [7] is divided into data m1792 to m2047, and boundary flags BD1792 to 2047 are assigned to them. Among these boundary flags BD0 to 2047, there are 1365 boundary flags BD having a zero value.
図3に戻り説明を続ける。Step3が終了した後、Step4にて、書込みデータDATAと、書込みデータDATAの中を、mビット毎に分けたそれぞれのデータmiに対して割り当てられたバウンダリフラグBDi値を、バッファBUF0へ書込む。
Referring back to FIG. After Step 3 ends, in Step 4, write data DATA and the boundary flag BDi value assigned to each data mi divided into m bits in write data DATA are written to buffer BUF0.
図6は、バッファに格納されるデータおよびバウンダリフラグBDの例を示す表図である。図6(A1)には上記図3のStep4にて、バッファBUF0へ格納した書込みデータDATAD0~D7と、これらデータに対応するバウンダリフラグD0_BD~D7_BDを示す。書込みデータD0~D7のそれぞれは8192バイトのサイズで、バウンダリフラグD0_BD~D7_BDのそれぞれは、256バイトのサイズである。
FIG. 6 is a table showing an example of the data stored in the buffer and the boundary flag BD. FIG. 6A1 shows the write data DATAD0 to D7 stored in the buffer BUF0 in Step 4 of FIG. 3 and the boundary flags D0_BD to D7_BD corresponding to these data. Each of the write data D0 to D7 has a size of 8192 bytes, and each of the boundary flags D0_BD to D7_BD has a size of 256 bytes.
BDVは、バウンダリフラグの有効/無効を示すフラグで、例えば“0”が有効を示し“1”が無効を示す。有効/無効は、例えば後述する図26の書込みコマンドPRG00とPRG01またはPRG10を選択して、情報処理回路MNGRからメモリ制御回路NVCTを介して指示することで切り替えることができる。BDVが有効の場合はバウンダリフラグBDをメモリに書込み、無効の場合はバウンダリフラグBDをメモリに書き込まない。無効にしておけば書込みが早くなり、またメモリ容量が節約できる。一方、有効にしておくと一度計算したバウンダリフラグBDを、ガーベージコレクション等で再利用することができる。
BDV is a flag indicating whether the boundary flag is valid / invalid. For example, “0” indicates valid and “1” indicates invalid. Valid / invalid can be switched, for example, by selecting a write command PRG00 and PRG01 or PRG10 shown in FIG. 26, which will be described later, and giving an instruction from the information processing circuit MNGR via the memory control circuit NVCT. When BDV is valid, the boundary flag BD is written to the memory, and when it is invalid, the boundary flag BD is not written to the memory. If it is disabled, writing becomes faster and memory capacity can be saved. On the other hand, once enabled, the boundary flag BD once calculated can be reused for garbage collection or the like.
図6(A2)は、其々の書込みデータを不揮発性メモリ装置NVM0~NVM3へ書込む、4つのチャネルCH0~CH3への割り当てを示している。ここでは、4つのチャネルを順番に(ローテーションで)データに割り当てている。
FIG. 6 (A2) shows allocation to the four channels CH0 to CH3 for writing each write data to the nonvolatile memory devices NVM0 to NVM3. Here, four channels are assigned to data in order (by rotation).
図3に戻り、Step5では、情報処理回路MNGRは、以下の条件をチェックする。
Returning to FIG. 3, in Step 5, the information processing circuit MNGR checks the following conditions.
条件:「バッファBUF0が不揮発性メモリ装置NVM0~NVM3への書込み対象となるバッファであり、且つ、バッファBUF0が書込みデータで満たされた」
この条件を満たした場合、Step6を実行し、満たさなかった場合、Step1を実行する。バッファBUF0が書込みデータによって満たされるまで、Step1~Step5を繰り返す。 Condition: “Buffer BUF0 is a buffer to be written to nonvolatile memory devices NVM0 to NVM3, and buffer BUF0 is filled with write data.”
If this condition is satisfied,Step 6 is executed, and if not satisfied, Step 1 is executed. Step 1 to Step 5 are repeated until the buffer BUF0 is filled with the write data.
この条件を満たした場合、Step6を実行し、満たさなかった場合、Step1を実行する。バッファBUF0が書込みデータによって満たされるまで、Step1~Step5を繰り返す。 Condition: “Buffer BUF0 is a buffer to be written to nonvolatile memory devices NVM0 to NVM3, and buffer BUF0 is filled with write data.”
If this condition is satisfied,
Step6では、情報処理回路MNGRはバッファBUF0に格納されている、書込みデータを不揮発性メモリ装置NVM0~NVM3へ転送し、書込みを行う。
In Step 6, the information processing circuit MNGR transfers the write data stored in the buffer BUF0 to the nonvolatile memory devices NVM0 to NVM3 and performs writing.
具体的には、この書込み動作では、情報処理回路MNGRは物理アドレスレジスタNext PADに保存されている物理アドレスPADを読み出し、さらに、バッファBUF0に格納されている書込みデータDATAとこれに対応しているバウンダリフラグBDを読み出し、書込み命令WRTとともに、調停回路ARBを通じてメモリ制御回路NVCT0~NVCT3へ転送する。
Specifically, in this write operation, the information processing circuit MNGR reads the physical address PAD stored in the physical address register Next PAD, and further corresponds to the write data DATA stored in the buffer BUF0. The boundary flag BD is read and transferred to the memory control circuits NVCT0 to NVCT3 through the arbitration circuit ARB together with the write command WRT.
メモリ制御回路NVCT0では、書込みデータDATAとこれに対応しているバウンダリフラグBDに関するECCを生成し、物理アドレスPADを不揮発性メモリ装置NVCT0のロウアドレスとカラムアドレスへ変換し、プログラム命令PRG01(あるいはPRG10)と、ロウアドレスおよびカラムアドレスと、バウンダリフラグBDと、書込みデータDATAとECCを、不揮発性メモリ装置NVM0へ転送する。このプログラム命令PRG01は、不揮発性メモリ装置NVM0が、バウンダリフラグBDを利用し、自身の内部メモリセルへの書込みを行うための命令である。命令一覧は図26参照。なお、図26では、バウンダリフラグBDを利用し、バウンダリフラグBD自体もメモリセルに書込むPRG01と、バウンダリフラグBDを利用するが、バウンダリフラグBD自体はメモリセルに書き込まないPRG10をサポートしているので、適宜選択すればよい。
The memory control circuit NVCT0 generates ECC related to the write data DATA and the boundary flag BD corresponding to the write data DATA, converts the physical address PAD into the row address and the column address of the nonvolatile memory device NVCT0, and program instruction PRG01 (or PRG10 ), The row address and the column address, the boundary flag BD, and the write data DATA and ECC are transferred to the nonvolatile memory device NVM0. This program instruction PRG01 is an instruction for the non-volatile memory device NVM0 to write to its own internal memory cell using the boundary flag BD. See FIG. 26 for a list of instructions. In FIG. 26, PRG01 that uses the boundary flag BD and the boundary flag BD itself writes to the memory cell and PRG10 that uses the boundary flag BD but does not write to the memory cell are supported. Therefore, it may be selected as appropriate.
不揮発性メモリ装置NVM0が、プログラム命令PRG01と、ロウアドレスおよびカラムアドレスと、バウンダリフラグBDと、書込みデータDATAおよびECCを受け取ると、不揮発性メモリ装置NVM0内のアドレス範囲決定回路FADCTLは、ロウアドレス信号、カラムアドレス信号およびバウンダリフラグBDを利用し、書込みデータDATAを書込むために必要な内部のXアドレスと、Yアドレスと、ZアドレスへバウンダリフラグBD値を対応させる。
When the nonvolatile memory device NVM0 receives the program instruction PRG01, the row address and the column address, the boundary flag BD, and the write data DATA and ECC, the address range determination circuit FADCTL in the nonvolatile memory device NVM0 generates a row address signal. Using the column address signal and the boundary flag BD, the boundary flag BD value is associated with the internal X address, Y address, and Z address necessary for writing the write data DATA.
さらに、バウンダリフラグBD値が0に対応した内部XアドレスとYアドレスとZアドレスの組み合わせ、つまりバウンダリアドレスBADxyzの全てを、制御回路CTLOGへ転送する。
Furthermore, the combination of the internal X address, Y address, and Z address corresponding to the boundary flag BD value 0, that is, all of the boundary addresses BADxyz are transferred to the control circuit CTLOG.
この、Step6内での一連の処理によって、書込みデータDATAの中を、mビット毎に分けたi番目のデータmiに対して、割り当てられているi番目のバウンダリフラグBDi値が、書込みデータDATAを書込むために必要な内部のXアドレスと、Yアドレスと、Zアドレスへ対応付けられる。
Through this series of processing in Step 6, the i-th boundary flag BDi value assigned to the i-th data mi divided into m bits in the write data DATA is changed to the write data DATA. Corresponding to the internal X address, Y address, and Z address necessary for writing.
たとえば、Xアドレスがx0で、Zアドレスがz0で、連続したi番目のYアドレスyi~yi+3の中で、yi+3のバウンダリフラグBDi値が0で、それ以外は1の場合、Yアドレスyi~yi+3のデータの中に、mビットを超える“0”データビットは存在しないことを示す。そのため、Yアドレスyi~yi+3の範囲内の“0”データビットを一度に書込むことができる。つまり、BDi値が0の数が、“0”データビットを書込む回数となり、このBDi値が0の数が少ないほど、“0”データビットを書込む回数は減少し、書込み時間を短縮することができる。
For example, if the X address is x0, the Z address is z0, and the boundary flag BDi value of yi + 3 is 0 in the consecutive i-th Y addresses yi to yi + 3, 1 otherwise, Y This indicates that there is no “0” data bit exceeding m bits in the data of the addresses yi to yi + 3. Therefore, “0” data bits within the range of Y addresses yi to yi + 3 can be written at a time. That is, the number of BDi values of 0 is the number of times of writing “0” data bits. The smaller the number of BDi values of 0, the smaller the number of times of writing “0” data bits and the shorter the write time. be able to.
次のStep7では、バッファBUF0内のデータが全て、不揮発性メモリ装置NVM0~3へ書き込まれたかをチェックし、書き込まれていない場合は、Step6を行う。バッファBUF0内のデータが全て、不揮発性メモリ装置NVM0~3へ書き込まれた場合はStep8を行う。
In the next Step 7, it is checked whether all the data in the buffer BUF0 has been written to the nonvolatile memory devices NVM0 to NVM0. If not, Step 6 is performed. When all the data in the buffer BUF0 is written to the nonvolatile memory devices NVM0 to NVM3, Step 8 is performed.
Step8では、情報処理回路MNGRは、メモリ装置M2に格納されているアドレス変換テーブルLPTBLと、ブロック毎の消去回数テーブルERSTBLを更新する。次の、Step9では、バッファBUF1を不揮発性メモリ装置NVM0~NVM3への書込み対象となるバッファとする。
In Step 8, the information processing circuit MNGR updates the address conversion table LPTBL stored in the memory device M2 and the erase count table ERSTBL for each block. In the next Step 9, the buffer BUF1 is a buffer to be written to the nonvolatile memory devices NVM0 to NVM3.
情報処理回路MNGRは、バッファBUF0にてStep6からStep9を行っている際は、バッファBUF1への書込み動作を行うことができる。さらに、情報処理回路MNGRは、物理アドレスレジスタNextPADへ、Step9が終了した後にバッファBUF0へ格納されるデータを不揮発性メモリ装置NVM0~NVM3へ書込むための新たな物理アドレスPADを、ブロック毎の消去回数が平準化するように、選択し、保存する。
The information processing circuit MNGR can perform a write operation to the buffer BUF1 when performing Step 6 to Step 9 in the buffer BUF0. Further, the information processing circuit MNGR erases a new physical address PAD for writing the data stored in the buffer BUF0 after Step 9 is completed to the physical address register NextPAD for each of the nonvolatile memory devices NVM0 to NVM3. Select and save so that the number of times is leveled.
また、バッファBUF1への書込みおよびバッファBUF1から不揮発性メモリ装置NVM0~NVM3への書込み動作は、バッファBUF0同様の動作となる。すなわち、図3のBUF0とBUF1が入れ替わって処理される。
In addition, the write operation to the buffer BUF1 and the write operation from the buffer BUF1 to the nonvolatile memory devices NVM0 to NVM3 are the same operation as the buffer BUF0. That is, BUF0 and BUF1 in FIG. 3 are switched and processed.
以上説明した様に、バウンダリフラグBDi値が、書込みデータDATAを書込むために必要な内部のXアドレスと、Yアドレスと、Zアドレスへ対応付けることで、“0”データビットを一度に書込むことができる内部アドレス範囲を特定し、書込みことができるため、“0”データビットを書込む回数は減少し、書込み時間を短縮することができる。さらに、バッファBUF0からの不揮発性メモリ装置NVM0~NVM3への書込み動作と、バッファBUF1への書込み動作と、物理アドレスレジスタNextPADへの新たな物理アドレスの格納を同時にできるため、書込み速度を向上できる。
As described above, “0” data bits are written at once by associating the boundary flag BDi value with the internal X address, Y address, and Z address necessary for writing the write data DATA. Since the internal address range in which data can be written can be specified and written, the number of times of writing “0” data bits is reduced, and the writing time can be shortened. Furthermore, since the write operation from the buffer BUF0 to the nonvolatile memory devices NVM0 to NVM3, the write operation to the buffer BUF1, and the storage of a new physical address in the physical address register NextPAD can be performed simultaneously, the writing speed can be improved.
図7は、図1における不揮発性メモリ装置NMV0~NMV31の構成例を示すブロック図である。ここでは、一例として相変化型の不揮発性メモリ(相変化メモリ)が用いられている。当該不揮発性メモリ装置は、クロック生成回路SYMD、ステータスレジスタSTREG、イレースサイズ指定レジスタNVREG、アドレス・コマンドインターフェース回路ADCMDIF、IOバッファIOBUF、制御回路CTLOG、温度センサTHMO、データ制御回路DATCTL、メモリバンクBK0~BK3を備える。
FIG. 7 is a block diagram showing a configuration example of the nonvolatile memory devices NMV0 to NMV31 in FIG. Here, as an example, a phase change nonvolatile memory (phase change memory) is used. The nonvolatile memory device includes a clock generation circuit SYMD, a status register STREG, an erase size designation register NVREG, an address / command interface circuit ADCMDIF, an IO buffer IOBUF, a control circuit CTLOG, a temperature sensor THMO, a data control circuit DATCTL, and memory banks BK0 to Equipped with BK3.
各メモリバンクBK0~BK3は、メモリアレイARYx(x=0~m)と、各メモリアレイにそれぞれ対応して設けられる読み書き制御ブロックSWBx(x=0~m)と、これらを制御する各種周辺回路を備える。当該各種周辺回路の中には、ロウアドレスラッチRADLT、カラムアドレスラッチCADLT、ロウデコーダROWDEC、カラムデコーダCOLDEC、チェイン選択アドレスラッチCHLT、チェインデコーダCHDEC、データ選択回路DSW1、データバッファDBUF0,DBUF1、アドレス範囲決定回路FADCTL、レジスタSPREGが含まれる。
Each of the memory banks BK0 to BK3 includes a memory array ARYx (x = 0 to m), a read / write control block SWBx (x = 0 to m) provided corresponding to each memory array, and various peripheral circuits for controlling them. Is provided. Among these various peripheral circuits are row address latch RADLT, column address latch CADLT, row decoder ROWDEC, column decoder COLDEC, chain selection address latch CHLT, chain decoder CHDEC, data selection circuit DSW1, data buffers DBUF0 and DBUF1, address range A determination circuit FADCTL and a register SPREG are included.
各メモリアレイARYxは、複数のワード線WL0~WLkと複数のビット線BL0_x~BLi_xの交点に配置される複数のチェインメモリアレイCYと、複数のビット線BL0_x~BLi_x(x=0~m)のいずれかを選択してデータ線DTxに接続するビット線選択回路BSWxを備える。各読み書き制御ブロックSWBxは、データ線DTx(x=0~m)に接続されるセンスアンプSAx(x=0~m)およびライトドライバWDRx(x=0~m)と、書込み動作時に、これらを用いてデータの検証を行う書込みデータ検証回路WVx(x=0~m)を備える。また、図7に示した不揮発性メモリ装置を動作させるインターフェースはNAND型フラッシュメモリインターエースやDRAMインターフェースなどのメモリインターフェースを採用すると、従来システムとのインターフェースの互換性を保つことができ、利便性が良い不揮発性メモリ装置を提供できる。
Each memory array ARYx includes a plurality of chain memory arrays CY arranged at intersections of a plurality of word lines WL0 to WLk and a plurality of bit lines BL0_x to BLi_x, and a plurality of bit lines BL0_x to BLi_x (x = 0 to m). A bit line selection circuit BSWx that selects either one and connects to the data line DTx is provided. Each read / write control block SWBx has a sense amplifier SAx (x = 0 to m) and write driver WDRx (x = 0 to m) connected to the data line DTx (x = 0 to m), A write data verification circuit WVx (x = 0 to m) is used for verifying data. In addition, if the interface for operating the nonvolatile memory device shown in FIG. 7 employs a memory interface such as a NAND flash memory interface or a DRAM interface, the compatibility of the interface with the conventional system can be maintained, which is convenient. A good nonvolatile memory device can be provided.
さらに、図7に示した不揮発性メモリ装置は、ブロックサイズが物理的に固定しておらず、制御回路NVM-CTLにて、制御上の管理単位として容易に変更可能である。このため、上位装置CPU_CPのメモリモジュールNVMDへのアクセスの特徴を分析し、不揮発性メモリ装置のブロックサイズ動的に最適化することで、情報処理システムの性能や信頼性の向上が図れる。
Furthermore, the block size of the nonvolatile memory device shown in FIG. 7 is not physically fixed, and can be easily changed as a control management unit by the control circuit NVM-CTL. For this reason, the performance and reliability of the information processing system can be improved by analyzing the characteristics of access to the memory module NVMD of the host device CPU_CP and dynamically optimizing the block size of the nonvolatile memory device.
図8は、図7におけるチェインメモリアレイの構成例を示す回路図である。各チェインメモリアレイCYは、図8に示すように、複数の相変化メモリセルCL0~CLnが直列に接続された構成を備える。メモリセルCLの一端はチェイン選択トランジスタTch2を介してワード線WLに接続され、他端はチェイン選択トランジスタTch0およびTch1を介してビット線BLに接続される。複数の相変化メモリセルCL0~CLnは、図示は省略するが、半導体基板に対して高さ方向に順に積層配置され、互いに直列接続される。また、各相変化メモリセルCLは、可変抵抗型の記憶素子Rと、それに並列接続されるメモリセル選択トランジスタTc1を備える。記憶素子Rは、例えばカルコゲナイド材料で形成される。
FIG. 8 is a circuit diagram showing a configuration example of the chain memory array in FIG. As shown in FIG. 8, each chain memory array CY has a configuration in which a plurality of phase change memory cells CL0 to CLn are connected in series. One end of the memory cell CL is connected to the word line WL via the chain selection transistor Tch2, and the other end is connected to the bit line BL via the chain selection transistors Tch0 and Tch1. Although not shown, the plurality of phase change memory cells CL0 to CLn are sequentially stacked in the height direction with respect to the semiconductor substrate and connected in series to each other. Each phase change memory cell CL includes a variable resistance storage element R and a memory cell selection transistor Tc1 connected in parallel thereto. The memory element R is made of, for example, a chalcogenide material.
図8の例では、2個のチェインメモリアレイCYがチェイン選択トランジスタTch2を共有しており、チェインメモリアレイ選択線SL0,SL1,SL2によって各チェインメモリアレイCY内のチェイン選択トランジスタTch0,1,2がそれぞれ制御され、これによっていずれか一方のチェインメモリアレイが選択される。また、メモリセル選択線LY0~LYnは、対応する相変化メモリセルのゲート電極に接続され、メモリセル選択線LYによって、相変化メモリセルCL0~CLn内のメモリセル選択トランジスタTc1がそれぞれ制御され、これによって各相変化メモリセルが適宜選択される。なお、チェインメモリアレイ選択線SL0、SL1、SL2およびメモリセル選択線LY0~LYnは、チェイン制御線CHとして、図7のチェイン選択アドレスラッチCHLTおよびチェインデコーダCHDECを介して適宜駆動される。
In the example of FIG. 8, two chain memory arrays CY share the chain selection transistor Tch2, and the chain selection transistors Tch0, 1, 2 in each chain memory array CY are connected by the chain memory array selection lines SL0, SL1, SL2. Are controlled, and thereby one of the chain memory arrays is selected. The memory cell selection lines LY0 to LYn are connected to the gate electrodes of the corresponding phase change memory cells. The memory cell selection lines LY control the memory cell selection transistors Tc1 in the phase change memory cells CL0 to CLn, Thus, each phase change memory cell is appropriately selected. The chain memory array selection lines SL0, SL1, SL2 and the memory cell selection lines LY0 to LYn are appropriately driven as the chain control line CH via the chain selection address latch CHLT and the chain decoder CHDEC in FIG.
図7に戻り、不揮発性メモリ装置の動作について説明する。まず、制御回路CTLOGは、アドレス・コマンドインターフェース回路ADCMDIFを介して制御信号CTLを受ける。制御信号CTLは、特に限定しないが、例えば、コマンド・ラッチイネーブル信号(CLE)、チップイネーブル信号(CEB)、アドレス・ラッチ信号(ALE)、ライトイネーブル信号(WEB)、リードイネーブル信号(REB)、レディビジー信号(RBB)を含む。
Returning to FIG. 7, the operation of the nonvolatile memory device will be described. First, the control circuit CTLOG receives a control signal CTL via the address / command interface circuit ADCMDIF. The control signal CTL is not particularly limited. For example, the command latch enable signal (CLE), the chip enable signal (CEB), the address latch signal (ALE), the write enable signal (WEB), the read enable signal (REB), A ready busy signal (RBB) is included.
読み出し動作では、これら制御信号CTLの組み合わせによって、入出力信号IOからクロック信号CLKに同期し入力される読み出し命令、ロウアドレス信号、カラムアドレス信号がとり込まれる。
In the read operation, a read command, a row address signal, and a column address signal input in synchronization with the clock signal CLK from the input / output signal IO are taken in by a combination of these control signals CTL.
制御回路CTLOGは、適宜内部Xアドレス、YアドレスおよびZアドレスを生成し、それぞれ、ロウアドレスラッチRADLT、カラムアドレスラッチCADLTならびにチェイン選択アドレスラッチCHLTにそれぞれ伝送する。
The control circuit CTLOG appropriately generates internal X address, Y address and Z address, and transmits them to the row address latch RADLT, the column address latch CADLT and the chain selection address latch CHLT, respectively.
ロウデコーダROWDECは、ロウアドレスラッチRADLTの出力を受けてワード線WL0~WLkの選択を行い、カラムデコーダCOLDECは、カラムアドレスラッチCADLTの出力を受けてビット線BL0_x~BLi_x(x=0~m)の選択を行う。また、チェインデコーダCHDECは、チェイン選択アドレスラッチCHLTの出力を受けて、チェイン制御線CHの選択を行う。読み出し命令が入力された際、前述したワード線、ビット線およびチェイン制御線の組み合わせによって選択されたチェインメモリアレイCYからビット線選択回路BSW0~BSWmを介してデータが読み出される。当該読み出されたデータは、センスアンプSA0~SAmで増幅され、データ選択回路DSW1を介してデータバッファDBUF0(又はDBUF1)に伝送される。そして、データバッファDBUF0(又はDBUF1)上のデータは、データ制御回路DATCTLおよびIOバッファIOBUFを介して入出力信号IOに順次伝送される。
The row decoder ROWDEC receives the output of the row address latch RADLT and selects the word lines WL0 to WLk, and the column decoder COLDEC receives the output of the column address latch CADLT and receives the bit lines BL0_x to BLi_x (x = 0 to m). Make a selection. The chain decoder CHDEC receives the output of the chain selection address latch CHLT and selects the chain control line CH. When a read command is input, data is read from the chain memory array CY selected by the combination of the word line, the bit line, and the chain control line, via the bit line selection circuits BSW0 to BSWm. The read data is amplified by the sense amplifiers SA0 to SAm and transmitted to the data buffer DBUF0 (or DBUF1) via the data selection circuit DSW1. Data on the data buffer DBUF0 (or DBUF1) is sequentially transmitted to the input / output signal IO via the data control circuit DATCTL and the IO buffer IOBUF.
書込み動作では、これら制御信号CTLの組み合わせによって、入出力信号IOからクロック信号CLKに同期し入力される書込み命令、ロウアドレス信号、カラムアドレス信号、バウンダリフラグBD、書込みデータDATAが取り込まれる。
In the write operation, a write command, a row address signal, a column address signal, a boundary flag BD, and write data DATA, which are input in synchronization with the clock signal CLK from the input / output signal IO, are captured by a combination of these control signals CTL.
書込み命令が入力した場合、アドレス範囲決定回路FADCTLは、ロウアドレス信号、カラムアドレス信号およびバウンダリフラグBDを利用し、書込みデータDATAを書込むために必要な内部のXアドレスと、Yアドレスと、ZアドレスへバウンダリフラグBD値を対応させる。さらに、バウンダリフラグBD値が0に対応した内部XアドレスとYアドレスとZアドレスの組み合わせ、つまりバウンダリアドレスBADxyzの全て、を制御回路CTLOGへ転送する。これは、mビット分以下の0データを一度に書き込める連続したアドレス範囲を示す。
When a write command is input, the address range determination circuit FADCTL uses the row address signal, the column address signal, and the boundary flag BD, and uses the internal X address, Y address, and Z necessary for writing the write data DATA. Associate a boundary flag BD value with the address. Further, the combination of the internal X address, Y address, and Z address corresponding to the boundary flag BD value 0, that is, all of the boundary addresses BADxyz are transferred to the control circuit CTLOG. This indicates a continuous address range in which 0 data of m bits or less can be written at a time.
制御回路CTLOGは、バウンダリアドレスBADxyzのXアドレス、YアドレスおよびZアドレスをロウアドレスラッチRADLT、カラムアドレスラッチCADLTならびにチェイン選択アドレスラッチCHLTにそれぞれ伝送する。
The control circuit CTLOG transmits the X address, Y address, and Z address of the boundary address BADxyz to the row address latch RADLT, the column address latch CADLT, and the chain selection address latch CHLT, respectively.
ロウデコーダROWDECは、ロウアドレスラッチRADLTの出力を受けてワード線WL0~WLkの選択を行い、カラムデコーダCOLDECは、カラムアドレスラッチCADLTの出力を受けてビット線BL0_x~BLi_x(x=0~m)の選択を行う。また、チェインデコーダCHDECは、チェイン選択アドレスラッチCHLTの出力を受けて、チェイン制御線CHの選択を行う。
The row decoder ROWDEC receives the output of the row address latch RADLT and selects the word lines WL0 to WLk, and the column decoder COLDEC receives the output of the column address latch CADLT and receives the bit lines BL0_x to BLi_x (x = 0 to m). Make a selection. The chain decoder CHDEC receives the output of the chain selection address latch CHLT and selects the chain control line CH.
書込み命令が入力された際、入出力信号IOには、前述したアドレス信号に続いてデータ信号が伝送され、当該データ信号は、データ制御回路DATCTLを介してデータバッファDBUF0(又はDBUF1)に入力される。データバッファDBUF0(又はDBUF1)上のデータ信号は、データ選択回路DSW1、ライトドライバWDR0~WDRmおよびビット線選択回路BSW0~BSWmを介して、前述したワード線、ビット線およびチェイン制御線の組み合わせによって選択されたチェインメモリアレイCYに書き込まれる。また、この際に、書込みデータ検証回路WV0~WVmは、書込みを行ったデータをセンスアンプSA0~SAmを介して適宜読み出しながら書込みレベルが十分なレベルに達したかを検証し、十分なレベルに達するまでライトドライバWDR0~WDRmを用いて再度の書込み動作を行う。
When a write command is input, a data signal is transmitted to the input / output signal IO following the address signal described above, and the data signal is input to the data buffer DBUF0 (or DBUF1) via the data control circuit DATCTL. The The data signal on the data buffer DBUF0 (or DBUF1) is selected by the combination of the word lines, bit lines, and chain control lines described above via the data selection circuit DSW1, write drivers WDR0 to WDRm, and bit line selection circuits BSW0 to BSWm. Is written in the chain memory array CY. At this time, the write data verification circuits WV0 to WVm verify whether or not the write level has reached a sufficient level while appropriately reading the written data through the sense amplifiers SA0 to SAm. The write operation is performed again using the write drivers WDR0 to WDRm until it reaches.
以上説明した様に、バウンダリフラグBD値が0の数が少ないほど、Xアドレス、YアドレスおよびZアドレスの選択回数が少なくなるため、データ書込み回数が減少し、プログラム時間が短縮できる。
As described above, the smaller the number of boundary flag BD values is, the smaller the number of selections of the X address, Y address, and Z address is. Therefore, the number of data writes is reduced, and the program time can be shortened.
図9は、図8のチェインメモリアレイの動作例を示す説明図である。この図9を用いて、チェインメモリアレイCY1内の相変化メモリセルCL0における可変抵抗型記憶素子R0を高抵抗や低抵抗にする際の動作を例に説明する。図7のチェインデコーダCHDECによって、チェインメモリアレイ選択線SL1のみが活性化(SL0=Low、SL1=High、SL2=High)され、チェイン選択トランジスタTch1およびTch2が導通状態となる。続いて、メモリセル選択線LY0のみが非活性化(LY0=Low、LY1~LYn=High)され、相変化メモリセルCL0のメモリセル選択トランジスタTcl0はカットオフ状態となり、残りのメモリセルCL1~CLnのメモリセル選択トランジスタTcl1~Tclnは導通状態となる。
FIG. 9 is an explanatory diagram showing an operation example of the chain memory array of FIG. With reference to FIG. 9, the operation when the variable resistance memory element R0 in the phase change memory cell CL0 in the chain memory array CY1 is set to high resistance or low resistance will be described as an example. Only the chain memory array selection line SL1 is activated (SL0 = Low, SL1 = High, SL2 = High) by the chain decoder CHDEC in FIG. 7, and the chain selection transistors Tch1 and Tch2 are turned on. Subsequently, only the memory cell selection line LY0 is deactivated (LY0 = Low, LY1 to LYn = High), the memory cell selection transistor Tcl0 of the phase change memory cell CL0 is cut off, and the remaining memory cells CL1 to CLn The memory cell selection transistors Tcl1 to Tcln are turned on.
次に、ワード線WL0がHighとなり、続いてビット線BL0がLowになると、電流I0がワード線WL0から、チェイン選択トランジスタTch2、可変抵抗型記憶素子R0、メモリセル選択トランジスタTcl1~Tclnおよびチェイン選択トランジスタTch1を経由してビット線BL0へ流れる。この電流I0が図28に示したReset電流パルスの形に制御されることで、可変抵抗型記憶素子R0は高抵抗となる。また、この電流I0が図28に示したSet電流パルスの形に制御されることで、可変抵抗型記憶素子R0は低抵抗となる。可変抵抗型記憶素子R0~Rnの抵抗値の違いによってデータ“1”と“0”が区別される。
Next, when the word line WL0 becomes High and then the bit line BL0 becomes Low, the current I0 is changed from the word line WL0 to the chain selection transistor Tch2, the variable resistance storage element R0, the memory cell selection transistors Tcl1 to Tcln, and the chain selection. It flows to the bit line BL0 via the transistor Tch1. By controlling the current I0 in the form of the Reset current pulse shown in FIG. 28, the variable resistance memory element R0 has a high resistance. Further, the current I0 is controlled in the form of the Set current pulse shown in FIG. 28, so that the variable resistance memory element R0 has a low resistance. Data “1” and “0” are distinguished by the difference in resistance values of the variable resistance memory elements R0 to Rn.
また、図7で示すように複数のビット線BL0_0~BL0_mへ電流I0を流すことで、書込み速度を向上することができる。
Further, as shown in FIG. 7, the writing speed can be improved by passing the current I0 to the plurality of bit lines BL0_0 to BL0_m.
特に限定しないが、可変抵抗型記憶素子が低抵抗になった場合に、データ“1”が記録され、高抵抗になった場合にデータ“0”が記録されるものとする。
Although not particularly limited, data “1” is recorded when the variable resistance memory element becomes low resistance, and data “0” is recorded when it becomes high resistance.
なお、可変抵抗型記憶素子R0に記録されたデータを読み出す場合は、可変抵抗型記憶素子R0の抵抗値が変化しない程度に、データ書込みと同様の経路で電流が印加される。この場合、可変抵抗型記憶素子R0の抵抗値に応じた電圧値がセンスアンプ(この例では図7のSA0)で検出され、データ“0”および“1”が判定される。
In addition, when reading the data recorded in the variable resistance memory element R0, a current is applied through the same path as the data writing so that the resistance value of the variable resistance memory element R0 does not change. In this case, a voltage value corresponding to the resistance value of the variable resistance memory element R0 is detected by a sense amplifier (SA0 in FIG. 7 in this example), and data “0” and “1” are determined.
また、図7で示すように複数のビット線BL0_0~BL0_mを通じて可変抵抗型記憶素子R0の抵抗値が変化しない程度に、データ書込みと同様の経路で電流が印加することで、複数のセンスアンプ(この例では図7のSA0~SAm)にてデータ“0”および“1”が判定され、読み出し速度を向上することができる。
In addition, as shown in FIG. 7, a current is applied through a path similar to that for data writing to the extent that the resistance value of the variable resistance memory element R0 does not change through the plurality of bit lines BL0_0 to BL0_m. In this example, data “0” and “1” are determined in SA0 to SAm in FIG. 7, and the reading speed can be improved.
図10は、図8のチェインメモリアレイの別の動作例を示す説明図である。図10を用いて、1チェインメモリアレイCY1内の全可変抵抗型記憶素子R0~Rnを一括で低抵抗にする際の動作を説明する。図7のチェインデコーダCHDECによって、チェインメモリアレイ選択線SL1のみが活性化(SL0=Low、SL1=High、SL2=High)され、チェイン選択トランジスタTch1およびTch2が導通状態となる。続いて、メモリセル選択線LY0~LYnが活性化(LY0~LYn=High)され、メモリセルCL0~CLnのメモリセル選択トランジスタTcl0~Tclnは導通状態となる。次に、ワード線WL0がHighとなり、続いてビット線BL0がLowになると、電流I2がワード線WL0から、チェイン選択トランジスタTch2、メモリセル選択トランジスタTcl0~Tclnおよびチェイン選択トランジスタTch1を経由してビット線BL0へ流れる。この電流I2によるジュール熱が、可変抵抗型記憶素子R0~Rnへ伝導し、可変抵抗型記憶素子R0~Rnは一括して低抵抗となる。この電流I2は、可変抵抗型記憶素子R0~Rnを一括して低抵抗にすることができる値に制御される。
FIG. 10 is an explanatory diagram showing another example of the operation of the chain memory array of FIG. The operation when all the variable resistance memory elements R0 to Rn in the one-chain memory array CY1 are collectively reduced in resistance will be described with reference to FIG. Only the chain memory array selection line SL1 is activated (SL0 = Low, SL1 = High, SL2 = High) by the chain decoder CHDEC in FIG. 7, and the chain selection transistors Tch1 and Tch2 are turned on. Subsequently, the memory cell selection lines LY0 to LYn are activated (LY0 to LYn = High), and the memory cell selection transistors Tcl0 to Tcln of the memory cells CL0 to CLn are turned on. Next, when the word line WL0 becomes High and then the bit line BL0 becomes Low, the current I2 is changed from the word line WL0 through the chain selection transistor Tch2, the memory cell selection transistors Tcl0 to Tcln, and the chain selection transistor Tch1. Flow to line BL0. Joule heat due to the current I2 is conducted to the variable resistance memory elements R0 to Rn, and the variable resistance memory elements R0 to Rn collectively have a low resistance. This current I2 is controlled to a value that allows the variable resistance memory elements R0 to Rn to be collectively reduced in resistance.
以上説明したように、必要に応じて、同時に複数のチェインメモリアレイ内のメモリセルを低抵抗にすることができ、消去データレートを向上することができる。
As described above, if necessary, the memory cells in the plurality of chain memory arrays can be made low resistance at the same time, and the erase data rate can be improved.
図11で、不揮発性メモリ装置のメモリアレイARYのブロック構成を説明する。図11(A)は、制御回路NVM-CTLがアドレスマップADMAP情報を利用し、構築する不揮発性メモリ装置NMVのメモリアレイのブロック構成の一例であり、ブロックサイズが64KBの場合のブロック構成の一例である。
Referring to FIG. 11, the block configuration of the memory array ARY of the nonvolatile memory device will be described. FIG. 11A shows an example of a block configuration of the memory array of the nonvolatile memory device NMV constructed by the control circuit NVM-CTL using the address map ADMAP information, and an example of the block configuration when the block size is 64 KB. It is.
一つのブロックは、8(X方向:X0~7)×(32×288)(Y方向:Y0~287)×8(Z方向:Z0~7)のチェインメモリアレイにて構成され、そのサイズは73728バイト(=8(X方向)×(32×288)(Y方向)×8(Z方向))である。このブロックが多数個配置され、図7に示す不揮発性メモリのメモリアレイを構成する。チェインメモリアレイCYの表示方法は図7と同様である。
One block is composed of a chain memory array of 8 (X direction: X0 to 7) × (32 × 288) (Y direction: Y0 to 287) × 8 (Z direction: Z0 to 7), and its size is It is 73728 bytes (= 8 (X direction) × (32 × 288) (Y direction) × 8 (Z direction)). A large number of these blocks are arranged to constitute a memory array of the nonvolatile memory shown in FIG. The display method of the chain memory array CY is the same as that in FIG.
データ領域DATA-AREAのサイズは65536バイト(=8(X方向)×(32×256)(Y方向)×8(Z方向))で、管理領域MG-AREAのサイズは8192バイト(=8(X方向)×(32×32)(Y方向)×8(Z方向))である。
The size of the data area DATA-AREA is 65536 bytes (= 8 (X direction) × (32 × 256) (Y direction) × 8 (Z direction)), and the size of the management area MG-AREA is 8192 bytes (= 8 ( X direction) × (32 × 32) (Y direction) × 8 (Z direction)).
データ領域DATA-AREAおよび管理領域MG-AREには、それぞれ、図11(B)で示すデータDATAおよび冗長データRdataが保存される。
In the data area DATA-AREA and the management area MG-ARE, data DATA and redundant data Rdata shown in FIG. 11B are stored, respectively.
図11(B)は、制御回路NVM-CTLから、不揮発性メモリ装置NVM0~NVM31へ書き込まれたデータPDATAの構成の一例を示している。データPDATAはデータDATA(8192バイト)と、冗長データRdata(1024バイト)から構成される。冗長データRdataには、データ反転フラグIVF、バウンダリフラグBDF、ECCコードECC1およびECC2、予備領域RSVなどが含まれる。このフォーマットは、図26のコマンドPRG01でサポートされる。
FIG. 11B shows an example of the configuration of data PDATA written from the control circuit NVM-CTL to the nonvolatile memory devices NVM0 to NVM31. Data PDATA is composed of data DATA (8192 bytes) and redundant data Rdata (1024 bytes). The redundant data Rdata includes a data inversion flag IVF, a boundary flag BDF, ECC codes ECC1 and ECC2, a spare area RSV, and the like. This format is supported by the command PRG01 in FIG.
データ反転フラグIVFは、制御回路NVM-CTLが不揮発性メモリ装置(NVM10からNVM17の中)へ書き込んだデータDATAが元の書込みデータの各ビットを反転させたデータかどうかを示す。データ反転フラグIVFへ1が書き込まれた場合は、元のデータの各ビットを反転させずにデータが書き込まれたことを示し、0が書き込まれた場合は元のメインデータの各ビットを反転させたデータが書き込まれたことを示す。データ反転フラグを利用した例については、実施例3で詳述される。
The data inversion flag IVF indicates whether the data DATA written by the control circuit NVM-CTL to the non-volatile memory device (NVM10 to NVM17) is data obtained by inverting each bit of the original write data. When 1 is written to the data inversion flag IVF, it indicates that the data has been written without inverting each bit of the original data. When 0 is written, each bit of the original main data is inverted. Indicates that the data has been written. An example using the data inversion flag will be described in detail in the third embodiment.
バウンダリフラグBDは、制御回路NVM-CTLによって、図3のStep3で生成されるフラグ情報であり書込みデータDATAの中を、mビット毎に分けたそれぞれのmビットのデータmi(i=0,1,2,~,M/m)に対して割り当てたフラグである。
The boundary flag BD is flag information generated in Step 3 of FIG. 3 by the control circuit NVM-CTL, and each m-bit data mi (i = 0,1) obtained by dividing the write data DATA into m bits. , 2, ..., M / m).
ECCコードECC1は、データDATAと、データ反転フラグIVFのエラーを検出し修正するために必要なデータで、ECCコードECC2はバウンダリフラグBDFのエラーを検出し修正するために必要なデータである。これらのECCコードは、制御回路NVM-CTLが不揮発性メモリ装置(NVM0からNVM3の中)へデータDATAを書込む際に、制御回路NVM-CTLによって生成される。バッドブロック情報BADBLKは、不揮発性メモリ装置(NVM0からNVM3の中)へ書き込まれたデータDATAが利用可能かどうかを示す。
The ECC code ECC1 is data necessary for detecting and correcting the error of the data DATA and the data inversion flag IVF, and the ECC code ECC2 is data necessary for detecting and correcting the error of the boundary flag BDF. These ECC codes are generated by the control circuit NVM-CTL when the control circuit NVM-CTL writes the data DATA to the non-volatile memory device (NVM0 to NVM3). Bad block information BADBLK indicates whether data DATA written to a nonvolatile memory device (NVM0 to NVM3) is available.
特に限定しないが、バッドブロック情報BADBLKへ1が書き込まれた場合は、データDATAは利用可能であり、0が書き込まれた場合は、データDATAは利用不可能であることを示す。ECCによるエラー訂正が可能である場合はバッドブロック情報BADBLKは1となり、エラー訂正が不可能である場合はバッドブロック情報BADBLKは0となる。予備領域RSVは、制御回路NVM-CTLが自由に定義できる領域として存在する。
Although not particularly limited, when 1 is written to the bad block information BADBLK, the data DATA is usable, and when 0 is written, the data DATA is not usable. The bad block information BADBLK is 1 when error correction by ECC is possible, and the bad block information BADBLK is 0 when error correction is impossible. The spare area RSV exists as an area where the control circuit NVM-CTL can be freely defined.
図11(C)は、制御回路NVM-CTLから、不揮発性メモリ装置NVM0~NVM31へ書き込まれたデータPDATAの構成の別の一例を示している。図11(B)と異なる点は、冗長データRdataには、バウンダリフラグBDFとECCコードECC2が存在しない点である。このフォーマットは、図26のコマンドPRG10でサポートされる。
FIG. 11C shows another example of the configuration of data PDATA written from the control circuit NVM-CTL to the nonvolatile memory devices NVM0 to NVM31. A difference from FIG. 11B is that the redundant data Rdata does not include the boundary flag BDF and the ECC code ECC2. This format is supported by the command PRG10 of FIG.
つまり、このデータPDATAの構成では、制御回路NVM-CTLから、不揮発性メモリ装置NVM0~NVM31へ、データDATAと、データ反転フラグIVF、バウンダリフラグBDF、ECCコードECC1が転送されるが、不揮発性メモリ装置NVM0~NVM31へは、バウンダリフラグBDFとECCコードECC2は書き込まないため、実効的に、不揮発性メモリ装置NVMの容量を大きくできる。
That is, in this data PDATA configuration, the data DATA, the data inversion flag IVF, the boundary flag BDF, and the ECC code ECC1 are transferred from the control circuit NVM-CTL to the nonvolatile memory devices NVM0 to NVM31. Since the boundary flag BDF and the ECC code ECC2 are not written in the devices NVM0 to NVM31, the capacity of the nonvolatile memory device NVM can be effectively increased.
図12は、図3のStep6での、不揮発性メモリ装置NVM0内部のアドレス範囲決定回路FADCTLの動作を示している。
FIG. 12 shows the operation of the address range determination circuit FADCTL in the nonvolatile memory device NVM0 in Step 6 of FIG.
Step601で、不揮発性メモリ装置NVM0が、プログラム命令PRG01(またはPRG10)と、ロウアドレスおよびカラムアドレスと、バウンダリフラグBDと、書込みデータDATAを、受け取ると、Step602にて、不揮発性メモリ装置NVM0内のアドレス範囲決定回路FADCTLは、ロウアドレス信号、カラムアドレス信号およびバウンダリフラグBD0~2047を利用し、バウンダリフラグBD0~2047のそれぞれと、書込みデータDATAを書込むために必要な内部のXアドレスと、Yアドレスと、Zアドレスを対応させる。
In Step 601, when the nonvolatile memory device NVM0 receives the program instruction PRG01 (or PRG10), the row address and column address, the boundary flag BD, and the write data DATA, in Step 602, the nonvolatile memory device NVM0 The address range determination circuit FADCTL uses the row address signal, the column address signal, and the boundary flags BD0 to 2047, and each of the boundary flags BD0 to 2047, the internal X address necessary for writing the write data DATA, and Y Associate the address with the Z address.
Step603にて、バウンダリフラグBD値が0に対応した内部XアドレスとYアドレスとZアドレスの組み合わせ、つまりバウンダリアドレスBADxyzの全てを、制御回路CTLOGへ転送する。制御回路CTLOGはこのバウンダリアドレスBADxyzと、書込みデータDATA内のm0~m2047とを対応付けながら、メモリアレイへ書込む。
In Step 603, the combination of the internal X address, Y address and Z address corresponding to the boundary flag BD value 0, that is, all of the boundary addresses BADxyz are transferred to the control circuit CTLOG. The control circuit CTLOG writes to the memory array while associating the boundary address BADxyz with m0 to m2047 in the write data DATA.
図13は、図12のStep602を実行した直後の、バウンダリフラグBD0~2047と、内部のXアドレス、YアドレスおよびZアドレスとの対応を示す。内部ZアドレスがZ0へ、書込みデータDATAを書込む際の、内部のXアドレス、Yアドレスと、バウンダリフラグBD0~2047との対応を示す。
FIG. 13 shows the correspondence between the boundary flags BD0 to 2047 and the internal X address, Y address, and Z address immediately after executing Step 602 in FIG. The correspondence between the internal X address and Y address and the boundary flags BD0 to 2047 when the write data DATA is written to the internal Z address Z0 is shown.
XアドレスX0内のYアドレスY0~Y255のそれぞれに、バウンダリフラグBD0~255と、データm0~255が割り当てられている。XアドレスX1内のYアドレスY0~Y255のそれぞれに、バウンダリフラグBD256~511と、データm256~511が割り当てられている。XアドレスX2内のYアドレスY0~Y255のそれぞれに、バウンダリフラグBD512~767と、データm512~767が割り当てられている。XアドレスX3内のYアドレスY0~Y255の、それぞれにバウンダリフラグBD768~1023と、データm768~1023が割り当てられている。XアドレスX4内のYアドレスY0~Y255の、それぞれにバウンダリフラグBD1024~1279と、データm1024~1279が割り当てられている。XアドレスX5内のYアドレスY0~Y255のそれぞれに、バウンダリフラグBD1280~1535と、データm1280~1535が割り当てられている。XアドレスX6内のYアドレスY0~Y255の、それぞれにバウンダリフラグBD1536~1791と、データm1536~1791が割り当てられている。XアドレスX7内のYアドレスY0~Y255のそれぞれに、バウンダリフラグBD1792~2047と、データm1792~2047が割り当てられている。これら、バウンダリフラグBD0~2047の中で、0値を持つバウンダリフラグBDは1365個ある。
Boundary flags BD0-255 and data m0-255 are assigned to Y addresses Y0-Y255 in X address X0. Boundary flags BD256 to 511 and data m256 to 511 are assigned to Y addresses Y0 to Y255 in X address X1, respectively. Boundary flags BD512 to 767 and data m512 to 767 are assigned to Y addresses Y0 to Y255 in X address X2. Boundary flags BD768 to 1023 and data m768 to 1023 are assigned to Y addresses Y0 to Y255 in X address X3, respectively. Boundary flags BD1024 to 1279 and data m1024 to 1279 are assigned to Y addresses Y0 to Y255 in X address X4, respectively. Boundary flags BD1280 to 1535 and data m1280 to 1535 are assigned to Y addresses Y0 to Y255 in X address X5. Boundary flags BD1536 to 1791 and data m1536 to 1791 are assigned to Y addresses Y0 to Y255 in X address X6, respectively. Boundary flags BD1792 to 2047 and data m1792 to 2047 are assigned to Y addresses Y0 to Y255 in X address X7, respectively. Among these boundary flags BD0 to 2047, there are 1365 boundary flags BD having a zero value.
ZアドレスがZ0、XアドレスがX0の際の、YアドレスY2のバウンダリフラグBD2の値は1、YアドレスY3のバウンダリフラグBD3の値は0であることから、YアドレスY2~Y3へ書込むデータm2~m3の中には、32ビットを超える“0”データビットは存在しないことを示す。そのため、YアドレスY2~Y3の範囲内のデータm2~m3を一度に書込むことができる。このように、例えば32ビットを超えない範囲の“0”データビットを纏めて書込むことにより、メモリセルの状態を変化させるためのエネルギーを所定以下に抑制しつつ、装置の電源や回路規模により制約される書込み能力(例えば書込み電流の最大値)の範囲で高速に書込むことができる。具体的な書込みは、図7~図10で説明したメモリセルの構成を用いることができる。
When the Z address is Z0 and the X address is X0, the value of the boundary flag BD2 of the Y address Y2 is 1, and the value of the boundary flag BD3 of the Y address Y3 is 0. Therefore, the data to be written to the Y addresses Y2 to Y3 In m2 to m3, there is no “0” data bit exceeding 32 bits. Therefore, data m2 to m3 within the range of Y addresses Y2 to Y3 can be written at a time. In this way, for example, by writing collectively “0” data bits in a range not exceeding 32 bits, the energy for changing the state of the memory cell is suppressed to a predetermined level or less, and depending on the power supply and circuit scale of the device. Data can be written at high speed within a limited range of write capability (for example, the maximum value of the write current). For specific writing, the memory cell structure described with reference to FIGS. 7 to 10 can be used.
たとえば、BDi値が0の数が1365個あれば、“0”データビットを書込む回数も1365回となる。本実施例を用いない場合は、書込む回数は2048回となるため、本実施例によって書込み回数は683回減少可能となる。バウンダリフラグBD値が0の数が少ないほど、“0”データビットを書込む回数は減少し、書込み時間を短縮することができる。なお、本実施例では、バウンダリフラグは、含まれる“0”データビットが32ビットを超えない連続したmビットのデータ単位の末尾のデータ単位に付加しているが、境界が分かればよいので、先頭のデータ単位でもよい。またバウンダリフラグBD値の0は、1など他の値を任意に定めてよい。
For example, if the number of BDi values of 0 is 1365, the number of times “0” data bits are written is 1365 times. When the present embodiment is not used, the number of times of writing is 2048, so that the number of times of writing can be reduced by 683 times according to the present embodiment. The smaller the number of 0 of the boundary flag BD value, the smaller the number of times of writing “0” data bits, and the write time can be shortened. In this embodiment, the boundary flag is added to the data unit at the end of the continuous m-bit data unit in which the included “0” data bits do not exceed 32 bits. The first data unit may be used. In addition, the boundary flag BD value of 0 may be arbitrarily set to other values such as 1.
実施例2では、バウンダリフラグの数をカウントし、不揮発性メモリ装置NVM0~NVM3へのチャネルに均等に割り当てる例を説明する。
In the second embodiment, an example will be described in which the number of boundary flags is counted and equally allocated to the channels to the nonvolatile memory devices NVM0 to NVM3.
図14は、図1における上位装置CPU_CPからの書込み要求WQに対する、メモリモジュールNVMD0のバッファBUF0および不揮発性メモリ装置NVM0~NVM3への書込み動作の別の一例を示す。システム構成は、図1、図2、図7の構成と同様である。
FIG. 14 shows another example of the write operation to the buffer BUF0 of the memory module NVMD0 and the nonvolatile memory devices NVM0 to NVM3 in response to the write request WQ from the host device CPU_CP in FIG. The system configuration is the same as that shown in FIGS.
図14の動作は、図3で説明した動作のStep3とStep6のみが、Step31およびStep61の動作に変更されており、これら以外の動作は、図3と同等である。
In the operation of FIG. 14, only Step 3 and Step 6 of the operation described in FIG. 3 are changed to the operations of Step 31 and Step 61, and the other operations are the same as those in FIG.
Step31について説明する。Step31では、書込みデータDATA(8KB=8192ビット)の中を、mビット毎に分けたそれぞれのmビットのデータmi(i=0,1,2,~,M/m)に対して、バウンダリフラグBDiの1値あるいは0値を対応付ける。さらに、バウンダリフラグBDiの0値の総数SUMF0を求める。
Step 31 will be explained. In Step 31, the boundary flag is set for each mi data (i = 0, 1, 2, ..., M / m) divided into m bits in the write data DATA (8KB = 8192 bits) Associate 1 or 0 value of BDi. Further, the total number SUMF0 of 0 values of the boundary flag BDi is obtained.
図15では、Step31の詳細動作を示す。先ず、Step31の実行開始時STARTでi=0, SUM0=0, SUMF=0とし、次のStep330で書込みデータDATA(8KB=8192ビット)の中を、mビット毎に分けて、i番目のmビットデータmiの中の“0”ビットの数を計算する(SUMi)。mビットは、不揮発性メモリ装置NVM0~NVM3が、一度に書き込める“0”データのビット数を表す。
FIG. 15 shows the detailed operation of Step31. First, at the start of execution of Step 31, i = 0, SUM0 = 0, SUMF = 0, and in the next Step330, write data DATA (8KB = 8192 bits) is divided into m bits and the i-th m The number of “0” bits in the bit data mi is calculated (SUMi). The m bits represent the number of bits of “0” data that can be written at once by the nonvolatile memory devices NVM0 to NVM3.
次のStep331で、“0”ビットの総数を計算する(SUM0)。次のStep332で、“0”ビットの総数SUM0がmより小さいかをチェックする。“0”ビットの総数SUM0がmより小さい場合、Step333を実行し、それ以外は、Step334を実行する。Step333ではバウンダリフラグBDFiを1に設定し、その後、Step342を実行する。
In the next Step 331, the total number of “0” bits is calculated (SUM0). In the next Step 332, it is checked whether the total number SUM0 of “0” bits is smaller than m. If the total number SUM0 of “0” bits is smaller than m, Step 333 is executed, otherwise Step 334 is executed. In Step 333, the boundary flag BDFi is set to 1, and then Step 342 is executed.
Step334では、Step333終了後は、“0”ビットの総数SUM0がmと等しいかをチェックする。“0”ビットの総数SUM0がmと等しければ、Step333を実行し、それ以外では、Step337 を実行する。Step335ではバウンダリフラグBDFiを0に設定し、その後、Step336では、バウンダリフラグBDFi値0の数が一つ増えたので、バウンダリフラグBDFi値0の総数SUMF0へ1を加算する。その後、Step341を実行する。
In Step 334, after Step 333 is completed, it is checked whether the total number SUM0 of “0” bits is equal to m. If the total number SUM0 of “0” bits is equal to m, Step 333 is executed, otherwise Step 337 is executed. In step 335, the boundary flag BDFi is set to 0. After that, in step 336, the number of the boundary flag BDFi value 0 is increased by 1, so 1 is added to the total number SUMF0 of the boundary flag BDFi value 0. Thereafter, Step 341 is executed.
Step337で、“0”ビットの総数SUM0がmより大きいことを確認した後、Step338にてBDFi-1を0に設定する。その後、Step339では、バウンダリフラグBDFi値0の数が一つ増えたので、バウンダリフラグBDFi値0の総数SUMF0へ1を加算する。その後、Step340にて現在のi値から1を減算した値をi値とした後、Step341を実行する。
In Step 337, after confirming that the total number SUM0 of “0” bits is larger than m, BDFi-1 is set to 0 in Step 338. Thereafter, in Step 339, since the number of boundary flag BDFi values 0 is increased by 1, 1 is added to the total number SUMF0 of boundary flag BDFi values 0. Thereafter, in Step 340, a value obtained by subtracting 1 from the current i value is set as the i value, and then Step 341 is executed.
Step341では、“0”ビットの総数SUM0を、0に設定する。Step342では、現在のi値へ1を加算した値をi値とし、その後のStep343ではi値がM(=8KB=8192ビット)をmで除算した値以上かどうかをチェックする。i値がM(=8KB=8192ビット)をmで除算した値以上であれば、一連の処理を終了(END)し、それ以外は、Step330を実行する。
In Step 341, the total number SUM0 of “0” bits is set to 0. In Step 342, a value obtained by adding 1 to the current i value is set as the i value, and in subsequent Step 343, it is checked whether or not the i value is equal to or larger than a value obtained by dividing M (= 8 KB = 8192 bits) by m. If the i value is equal to or greater than the value obtained by dividing M (= 8 KB = 8192 bits) by m, the series of processing ends (END), otherwise, Step 330 is executed.
バウンダリフラグBDFi値と、バウンダリフラグBDFi値0の総数SUMF0は、次のStep4にてバッファBUF0へ書き込まれる。
The boundary flag BDFi value and the total number SUMF0 of the boundary flag BDFi value 0 are written to the buffer BUF0 in the next Step 4.
この、Step31内での一連の処理によって、書込みデータDATA(8KB=8192ビット)の中を、mビット毎に分けたi番目のデータmiに対して,
それぞれi番目のバウンダリフラグBDFi値が割り当てられる(i=0,1,2,~,M/m)。実施例1と同様、バウンダリフラグBDFiを利用することにより、mビットを超える“0”データビットが含まれない連続したデータ範囲を知ることができる。このデータ範囲のデータビットを一度に書込むことにより、書込み回数は減少し、書込み時間を短縮することができる。 Through this series of processing in Step 31, the write data DATA (8KB = 8192 bits) is divided into m bits for the i-th data mi,
Each i-th boundary flag BDFi value is assigned (i = 0, 1, 2,..., M / m). As in the first embodiment, by using the boundary flag BDFi, it is possible to know a continuous data range that does not include “0” data bits exceeding m bits. By writing data bits in this data range at a time, the number of times of writing can be reduced and the writing time can be shortened.
それぞれi番目のバウンダリフラグBDFi値が割り当てられる(i=0,1,2,~,M/m)。実施例1と同様、バウンダリフラグBDFiを利用することにより、mビットを超える“0”データビットが含まれない連続したデータ範囲を知ることができる。このデータ範囲のデータビットを一度に書込むことにより、書込み回数は減少し、書込み時間を短縮することができる。 Through this series of processing in Step 31, the write data DATA (8KB = 8192 bits) is divided into m bits for the i-th data mi,
Each i-th boundary flag BDFi value is assigned (i = 0, 1, 2,..., M / m). As in the first embodiment, by using the boundary flag BDFi, it is possible to know a continuous data range that does not include “0” data bits exceeding m bits. By writing data bits in this data range at a time, the number of times of writing can be reduced and the writing time can be shortened.
図14に戻って説明を続ける。Step31が終了した後、Step4にて、書込みデータDATAと、書込みデータDATAの中を、mビット毎に分けたそれぞれのデータmiに対して割り当てられたバウンダリフラグBDi値と、バウンダリフラグBDiの0値の総数SUMF0を、バッファBUF0へ書込む。
Referring back to FIG. After Step31 is completed, in Step4, write data DATA and the boundary flag BDi value assigned to each data mi divided into m bits in the write data DATA, and 0 value of the boundary flag BDi Total number SUMF0 is written to buffer BUF0.
図16は、バッファに格納されるデータおよびバウンダリフラグBDの一例を示す表図である。図16(C1)に、図14のStep31が終了した後、Step4にて、バッファBUF0あるいはバッファBUF1へ格納した書込みデータDATA D0~D7と、これらデータに対応するバウンダリフラグD0_BD~D7_BDと、バウンダリフラグの有効/無効フラグD0_BDV~D7_BDV(この例では全て有効とする)と、バウンダリフラグD0_BD~D7_BD内の0値の総数BDSUM0を示す。図6の例に比べ、0値の総数の情報BDSUM0が追加されている。
FIG. 16 is a table showing an example of the data stored in the buffer and the boundary flag BD. In FIG. 16C1, after Step 31 of FIG. 14 is completed, the write data DATA D0 to D7 stored in the buffer BUF0 or the buffer BUF1 in Step 4 and the boundary flags D0_BD to D7_BD corresponding to these data and the boundary flag are displayed. Valid / invalid flags D0_BDV to D7_BDV (all valid in this example) and the total number BDSUM0 of 0 values in the boundary flags D0_BD to D7_BD. Compared to the example of FIG. 6, information BDSUM0 of the total number of 0 values is added.
図14に戻り、Step61について説明する。Step61では、先ず、バッファBUF0内のデータD0~D7の不揮発性メモリ装置NVM0~3への書込み時間の最大値を短縮するために、それぞれの総数BDSUM0ができるだけ均一になるように、データD0~D7を書込むチャネルを割り当て(書込み時間短縮チャネル割り当て)、その後、不揮発性メモリ装置NVM0~3へ、これらデータD0~D7を書込む(NVMへの書込み)。
Referring back to FIG. 14, Step 61 will be described. In Step 61, first, in order to shorten the maximum write time of the data D0 to D7 in the buffer BUF0 to the nonvolatile memory devices NVM0 to NVM3, the data D0 to D7 are set so that the total number BDSUM0 of each becomes as uniform as possible. Is assigned (channel assignment for shortening the write time), and then these data D0 to D7 are written to the nonvolatile memory devices NVM0 to NVM3 (writing to NVM).
先ず、書込み時間短縮チャネル割り当てを説明する。情報処理回路MNGRはバッファBUF0に格納されている書込みデータDATA D0~D7に対応しているバウンダリフラグD0_BD~D7_BDの0値の総数BDSUM0(1300、1600、950、800、1050、1200、700、500)を読み出す。
First, write time reduction channel assignment will be described. The information processing circuit MNGR has the total number BDSUM0 (1300, 1600, 950, 800, 1050, 1200, 700, 500) of the zero values of the boundary flags D0_BD to D7_BD corresponding to the write data DATA D0 to D7 stored in the buffer BUF0. ).
次に、これらの総数BDSUM0で、大きい順に1~8までのランクを付ける。さらに、これらランクで、ランク1と8に対応する書込みデータD1とD7をチャネルCH0へ割り当て、ランク2と7に対応する書込みデータD0とD6をチャネルCH1へ割り当て、ランク3と6に対応する書込みデータD5とD3をチャネルCH2へ割り当て、ランク4と5に対応する書込みデータD4とD2をチャネルCH3へ割り当てる。図16(C2)に、書込みデータD1~D7に対応するランクBDRankと、割り当てチャネルCHの対応を示す。
Next, with these total number BDSUM0, rank from 1 to 8 in descending order. Furthermore, in these ranks, write data D1 and D7 corresponding to ranks 1 and 8 are assigned to channel CH0, write data D0 and D6 corresponding to ranks 2 and 7 are assigned to channel CH1, and writes corresponding to ranks 3 and 6 are assigned. Data D5 and D3 are assigned to channel CH2, and write data D4 and D2 corresponding to ranks 4 and 5 are assigned to channel CH3. FIG. 16C2 shows the correspondence between the rank BDRank corresponding to the write data D1 to D7 and the assigned channel CH.
次に、図14のStep61のNVMへの書込みについて、図1と図16(C2)を参照して説明する。情報処理回路MNGRはバッファBUF0に格納されているチャネルCH0へ割り当てられている書込みデータD1とバウンダリフラグD1_BD、データD7とバウンダリフラグD7_BDを読み出し、物理アドレスレジスタNextPADから不揮発性メモリ装置NVM0の物理アドレスPAD0、PAD1を読み出し、メモリ制御回路NVCT0へ転送する。
Next, writing to NVM in Step 61 of FIG. 14 will be described with reference to FIG. 1 and FIG. 16 (C2). The information processing circuit MNGR reads the write data D1 and the boundary flag D1_BD, the data D7 and the boundary flag D7_BD assigned to the channel CH0 stored in the buffer BUF0, and the physical address PAD0 of the nonvolatile memory device NVM0 from the physical address register NextPAD , PAD1 is read and transferred to the memory control circuit NVCT0.
次に、チャネルCH1へ割り当てられている書込みデータD0とバウンダリフラグD0_BD、データD6とバウンダリフラグD6_BDを読み出し、物理アドレスレジスタNextPADから不揮発性メモリ装置NVM1の物理アドレスPAD2、PAD3を読み出し、メモリ制御回路NVCT1へ転送する。
Next, write data D0 and boundary flag D0_BD, data D6 and boundary flag D6_BD assigned to channel CH1 are read, physical addresses PAD2 and PAD3 of nonvolatile memory device NVM1 are read from physical address register NextPAD, and memory control circuit NVCT1 Forward to.
次に、チャネルCH2へ割り当てられている書込みデータD5とバウンダリフラグD5_BD、データD3とバウンダリフラグD3_BDを読み出し、物理アドレスレジスタNextPADから不揮発性メモリ装置NVM2の物理アドレスPAD4、PAD5を読み出し、メモリ制御回路NVCT2へ転送する。
Next, write data D5 and boundary flag D5_BD, data D3 and boundary flag D3_BD assigned to channel CH2 are read, physical addresses PAD4 and PAD5 of nonvolatile memory device NVM2 are read from physical address register NextPAD, and memory control circuit NVCT2 Forward to.
次に、チャネルCH3へ割り当てられている書込みデータD4とバウンダリフラグD4_BD、データD2とバウンダリフラグD2_BDを読み出し、物理アドレスレジスタNextPADから不揮発性メモリ装置NVM3の物理アドレスPAD6、PAD7を読み出し、メモリ制御回路NVCT3へ転送する。
Next, write data D4 and boundary flag D4_BD, data D2 and boundary flag D2_BD assigned to channel CH3 are read, physical addresses PAD6 and PAD7 of nonvolatile memory device NVM3 are read from physical address register NextPAD, and memory control circuit NVCT3 Forward to.
メモリ制御回路NVCT0では、書込みデータD1とバウンダリフラグD1_BDに関するエラーコレクションコードECC1を生成し、物理アドレスPAD0を不揮発性メモリ装置NVM0のロウアドレス1とカラムアドレス1へ変換し、プログラム命令PRG01と、ロウアドレス1およびカラムアドレス1と、バウンダリフラグD1_BDと、書込みデータD1とECC1を、不揮発性メモリ装置NVM0へ転送する。
The memory control circuit NVCT0 generates an error correction code ECC1 related to the write data D1 and the boundary flag D1_BD, converts the physical address PAD0 into the row address 1 and the column address 1 of the nonvolatile memory device NVM0, and generates the program instruction PRG01 and the row address. 1 and column address 1, boundary flag D1_BD, write data D1 and ECC1 are transferred to nonvolatile memory device NVM0.
次に、メモリ制御回路NVCT0はデータD7とバウンダリフラグD7_BDに関するエラーコレクションコードECC7を生成し、物理アドレスPAD1を不揮発性メモリ装置NVM0のロウアドレス7とカラムアドレス7へ変換し、プログラム命令PRG01と、ロウアドレス7およびカラムアドレス7、バウンダリフラグD7_BDと、書込みデータD7とECC7を、不揮発性メモリ装置NVM0へ転送する。
Next, the memory control circuit NVCT0 generates an error correction code ECC7 related to the data D7 and the boundary flag D7_BD, converts the physical address PAD1 into the row address 7 and the column address 7 of the nonvolatile memory device NVM0, and generates a program instruction PRG01 and a row Address 7, column address 7, boundary flag D7_BD, and write data D7 and ECC7 are transferred to nonvolatile memory device NVM0.
メモリ制御回路NVCT1は、書込みデータD0バウンダリフラグD0_BDに関するエラーコレクションコードECC0を生成し、物理アドレスPAD2を不揮発性メモリ装置NVM1のロウアドレス0とカラムアドレス0へ変換し、プログラム命令PRG01と、ロウアドレス0およびカラムアドレス0と、バウンダリフラグD0_BDと、書込みデータD0とECC0を、不揮発性メモリ装置NVM1へ転送する。
The memory control circuit NVCT1 generates an error correction code ECC0 related to the write data D0 boundary flag D0_BD, converts the physical address PAD2 into the row address 0 and the column address 0 of the nonvolatile memory device NVM1, and generates the program instruction PRG01 and the row address 0. The column address 0, the boundary flag D0_BD, the write data D0, and ECC0 are transferred to the nonvolatile memory device NVM1.
次に、メモリ制御回路NVCT0はデータD6とバウンダリフラグD6_BDに関するエラーコレクションコードECC6を生成し、物理アドレスPAD3を不揮発性メモリ装置NVM1のロウアドレス6とカラムアドレス6へ変換し、プログラム命令PRG01と、ロウアドレス6およびカラムアドレス6、バウンダリフラグD7_BDと、書込みデータD6とECC6を、不揮発性メモリ装置NVM1へ転送する。
Next, the memory control circuit NVCT0 generates an error correction code ECC6 related to the data D6 and the boundary flag D6_BD, converts the physical address PAD3 into the row address 6 and the column address 6 of the nonvolatile memory device NVM1, and sets the program instruction PRG01 and the row Address 6, column address 6, boundary flag D7_BD, and write data D6 and ECC6 are transferred to nonvolatile memory device NVM1.
メモリ制御回路NVCT2は、書込みデータD5バウンダリフラグD5_BDに関するエラーコレクションコードECC5を生成し、物理アドレスPAD4を不揮発性メモリ装置NVM2のロウアドレス5とカラムアドレス5へ変換し、プログラム命令PRG01と、ロウアドレス5およびカラムアドレス5と、バウンダリフラグD5_BDと、書込みデータD5とECC5を、不揮発性メモリ装置NVM2へ転送する。
The memory control circuit NVCT2 generates an error correction code ECC5 related to the write data D5 boundary flag D5_BD, converts the physical address PAD4 into the row address 5 and the column address 5 of the nonvolatile memory device NVM2, and generates the program instruction PRG01 and the row address 5 The column address 5, the boundary flag D5_BD, the write data D5 and ECC5 are transferred to the nonvolatile memory device NVM2.
次に、メモリ制御回路NVCT2はデータD3とバウンダリフラグD3_BDに関するエラーコレクションコードECC3を生成し、物理アドレスPAD5を不揮発性メモリ装置NVM2のロウアドレス3とカラムアドレス3へ変換し、プログラム命令PRG01と、ロウアドレス3およびカラムアドレス3、バウンダリフラグD3_BDと、書込みデータD3とECC3を、不揮発性メモリ装置NVM2へ転送する。
Next, the memory control circuit NVCT2 generates an error correction code ECC3 related to the data D3 and the boundary flag D3_BD, converts the physical address PAD5 into the row address 3 and the column address 3 of the nonvolatile memory device NVM2, and sets the program instruction PRG01 and the row Address 3 and column address 3, boundary flag D3_BD, and write data D3 and ECC3 are transferred to nonvolatile memory device NVM2.
メモリ制御回路NVCT3は、書込みデータD4バウンダリフラグD4_BDに関するエラーコレクションコードECC4を生成し、物理アドレスPAD6を不揮発性メモリ装置NVM3のロウアドレス4とカラムアドレス4へ変換し、プログラム命令PRG01と、ロウアドレス4およびカラムアドレス4と、バウンダリフラグD4_BDと、書込みデータD4とECC4を、不揮発性メモリ装置NVM3へ転送する。
The memory control circuit NVCT3 generates an error correction code ECC4 related to the write data D4 boundary flag D4_BD, converts the physical address PAD6 into the row address 4 and the column address 4 of the nonvolatile memory device NVM3, and generates the program instruction PRG01 and the row address 4 The column address 4, the boundary flag D4_BD, the write data D4, and ECC4 are transferred to the nonvolatile memory device NVM3.
次に、メモリ制御回路NVCT3はデータD2とバウンダリフラグD2_BDに関するエラーコレクションコードECC2を生成し、物理アドレスPAD7を不揮発性メモリ装置NVM3のロウアドレス7とカラムアドレス7へ変換し、プログラム命令PRG01と、ロウアドレス7およびカラムアドレス7、バウンダリフラグD2_BDと、書込みデータD2とECC2を、不揮発性メモリ装置NVM3へ転送する。Step61での、これ以降の不揮発性メモリ装置NVM0~3の動作は図3のStep6と同様である
図17は、図14のStep61の中で、不揮発性メモリ装置NVM0内部のアドレス範囲決定回路FADCTLが行った処理によるバウンダリフラグBD0~2047と、内部のXアドレス、YアドレスおよびZアドレスとの対応を示す。内部ZアドレスがZ0へ書込みデータDATAを書込む際の、内部のXアドレス、Yアドレスと、バウンダリフラグBD0~2047との対応が示されている。この内部のXアドレス、Yアドレスと、バウンダリフラグBD0~2047との対応方法は、図13と同様である。また、これら、バウンダリフラグBD0~2047の中で、0値を持つバウンダリフラグBDは688=86×8個まで、削減されている。 Next, the memory control circuit NVCT3 generates an error correction code ECC2 related to the data D2 and the boundary flag D2_BD, converts the physical address PAD7 into therow address 7 and the column address 7 of the nonvolatile memory device NVM3, the program instruction PRG01, and the row Address 7 and column address 7, boundary flag D2_BD, and write data D2 and ECC2 are transferred to nonvolatile memory device NVM3. The subsequent operations of the non-volatile memory devices NVM0 to NVM3 in Step 61 are the same as in Step 6 of FIG. 3. FIG. 17 shows that the address range determination circuit FADCTL in the non-volatile memory device NVM0 is in Step 61 of FIG. The correspondence between the boundary flags BD0 to 2047 by the processing performed and the internal X address, Y address, and Z address is shown. The correspondence between the internal X address and Y address and the boundary flags BD0 to 2047 when the internal Z address writes the write data DATA to Z0 is shown. The correspondence method between the internal X address and Y address and the boundary flags BD0 to 2047 is the same as in FIG. Further, among the boundary flags BD0 to 2047, the number of boundary flags BD having a zero value is reduced to 688 = 86 × 8.
図17は、図14のStep61の中で、不揮発性メモリ装置NVM0内部のアドレス範囲決定回路FADCTLが行った処理によるバウンダリフラグBD0~2047と、内部のXアドレス、YアドレスおよびZアドレスとの対応を示す。内部ZアドレスがZ0へ書込みデータDATAを書込む際の、内部のXアドレス、Yアドレスと、バウンダリフラグBD0~2047との対応が示されている。この内部のXアドレス、Yアドレスと、バウンダリフラグBD0~2047との対応方法は、図13と同様である。また、これら、バウンダリフラグBD0~2047の中で、0値を持つバウンダリフラグBDは688=86×8個まで、削減されている。 Next, the memory control circuit NVCT3 generates an error correction code ECC2 related to the data D2 and the boundary flag D2_BD, converts the physical address PAD7 into the
ZアドレスがZ0、XアドレスがX0の際の、YアドレスY0のバウンダリフラグBD0の値は1、YアドレスY1のバウンダリフラグBD1の値は1、YアドレスY2のバウンダリフラグBD2の値は0、であることから、YアドレスY0~Y2へ書込むデータm0~m2の中には、32ビットを超える“0”データビットは存在しないことを示す。そのため、YアドレスY0~Y2の範囲内のデータm0~m2を一度にメモリセルに書込むことができる。このように、32ビットを超えない範囲の“0”データビットを纏めて書込むことにより、メモリセルの状態を変化させるためのエネルギーを所定以下に抑制しつつ、装置の電源や回路規模により制約される書込み能力の範囲で高速に書込むことができる。
When the Z address is Z0 and the X address is X0, the value of the boundary flag BD0 of the Y address Y0 is 1, the value of the boundary flag BD1 of the Y address Y1 is 1, and the value of the boundary flag BD2 of the Y address Y2 is 0 This indicates that there is no “0” data bit exceeding 32 bits in the data m0 to m2 to be written to the Y addresses Y0 to Y2. Therefore, data m0 to m2 within the range of Y addresses Y0 to Y2 can be written to the memory cells at a time. As described above, by collectively writing “0” data bits in a range not exceeding 32 bits, the energy for changing the state of the memory cell is suppressed to a predetermined level or less, and is restricted by the power supply of the device and the circuit scale. It is possible to write at high speed within the range of writing ability.
図16(B2)に、書込み時間短縮チャネル割り当てを行なわずに、データD0~D7に対して順番にチャネルを割り当てた状態を示し、図16(B3)に、その際の、チャネル毎の総数SUM_BDCを示す。
FIG. 16B2 shows a state in which channels are assigned in order to the data D0 to D7 without performing write time reduction channel assignment, and FIG. 16B3 shows the total number SUM_BDC for each channel at that time. Indicates.
書込みデータD0とD4をチャネルCH0へ割り当て、書込みデータD1とD5をチャネルCH1へ割り当て、書込みデータD2とD6をチャネルCH2へ割り当て、書込みデータD3とD7をチャネルCH3へ割り当てる。この際の、チャネルCH0の総数SUM_BDCは2350、チャネルCH1の総数SUM_BDCは2800、チャネルCH2の総数SUM_BDCは1650、チャネルCH3の総数SUM_BDCは1300となる。チャネルCH1の総数SUM_BDCである2800が、不揮発性メモリ装置NVMへの最大書込み回数となり、これが最大書込み時間となる。
Write data D0 and D4 are assigned to channel CH0, write data D1 and D5 are assigned to channel CH1, write data D2 and D6 are assigned to channel CH2, and write data D3 and D7 are assigned to channel CH3. At this time, the total number SUM_BDC of the channel CH0 is 2350, the total number SUM_BDC of the channel CH1 is 2800, the total number SUM_BDC of the channel CH2 is 1650, and the total number SUM_BDC of the channel CH3 is 1300. 2800 which is the total number SUM_BDC of the channel CH1 is the maximum number of times of writing to the nonvolatile memory device NVM, and this is the maximum write time.
一方、図16(C2)に、書込み時間短縮チャネル割り当てを行なった場合の、データD0~D7に対するチャネル割り当てを示し、図16(C3)に、その際の、チャネル毎の総数SUM_BDCを示す。
On the other hand, FIG. 16 (C2) shows the channel assignment for the data D0 to D7 when the write time reduction channel assignment is performed, and FIG. 16 (C3) shows the total number SUM_BDC for each channel at that time.
この際の、チャネルCH0の総数SUM_BDCは2100、チャネルCH1の総数SUM_BDCは2000、チャネルCH2の総数SUM_BDCは2000、チャネルCH3の総数SUM_BDCは2000となる。
At this time, the total number SUM_BDC of the channel CH0 is 2100, the total number SUM_BDC of the channel CH1 is 2000, the total number SUM_BDC of the channel CH2 is 2000, and the total number SUM_BDC of the channel CH3 is 2000.
書込み時間短縮チャネル割り当てを行なった場合、総数SUM_BDCの最大値は2100となり、書込み時間短縮チャネル割り当てを行わなかった場合と比較し、700ほど減少している。
When the write time reduction channel assignment is performed, the maximum value of the total number SUM_BDC is 2100, which is about 700 lower than the case where the write time reduction channel assignment is not performed.
この様に、書込み時間短縮チャネル割り当てにより、総数SUM_BDCの最大値を減少させることで、不揮発性メモリ装置NVMへの最大書込み回数、つまり、最大書込み時間を短縮できる。これによって、アドレス変換テーブルLPTBLと、ブロック毎の消去回数テーブルERSTBLの更新タイミングを早めることができるため、高速書込みが可能となる。
In this way, the maximum number of writes to the nonvolatile memory device NVM, that is, the maximum write time can be shortened by reducing the maximum value of the total number SUM_BDC by channel assignment for write time reduction. As a result, the update timing of the address conversion table LPTBL and the erase count table ERSTBL for each block can be advanced, so that high-speed writing is possible.
図18~図25を用いて、データビット反転処理を行う実施例3を説明する。
A third embodiment in which data bit inversion processing is performed will be described with reference to FIGS.
図18は、図1における上位装置CPU_CPからの書込み要求WQに対する、メモリモジュールNVMD0のバッファBUF0および不揮発性メモリ装置NVM0~NVM3への書込み動作の別の例を示す。図18の動作は、図14で説明した動作のStep31のみを、Step32の動作に変更しており、これら以外の動作は、図14と同等である。
FIG. 18 shows another example of the write operation to the buffer BUF0 of the memory module NVMD0 and the nonvolatile memory devices NVM0 to NVM3 in response to the write request WQ from the host device CPU_CP in FIG. In the operation of FIG. 18, only Step 31 of the operation described in FIG. 14 is changed to the operation of Step 32, and other operations are the same as those in FIG.
Step32では、先ず、書込みデータDATAに対して、必要に応じてデータビット反転処理を行い、その後、図14で説明したStep31と同じ動作を行う。
In Step 32, first, data bit inversion processing is performed as necessary on the write data DATA, and then the same operation as Step 31 described in FIG. 14 is performed.
図19でStep32のデータビット反転処理を説明する。情報処理回路MNGRは、先ず、Step32の実行開始時STARTでi=0とし、次のStep350で書込みデータDATA(8KB=8192ビット)の中を、mビット毎に分けて、i番目のmビットデータmiの中の“0”ビットの数ZBCiを計測する。
Referring to FIG. 19, the data bit inversion process in Step 32 will be described. The information processing circuit MNGR first sets i = 0 at START at the start of execution of Step 32, and in the next Step 350, the write data DATA (8 KB = 8192 bits) is divided into m bits, and the i-th m-bit data. The number ZBCi of “0” bits in mi is measured.
次のStep351で、mビットデータmiの中の“0”ビットの数ZBCiと、“1”ビットの数(m-ZBCi)を比較する。“0”ビットの数ZBCiが“1”ビットの数より多い場合は、mビットデータmiをビット反転し(Step352)、ビット反転フラグIVFiを0に設定する(Step353)。“0”ビットの数ZBCiが“1”ビットの数以下の場合は、mビットデータmiをビット反転せず、ビット反転フラグIVFiを1に設定する(Step354)。
In the next Step 351, the “0” bit number ZBCi in the m bit data mi is compared with the “1” bit number (m−ZBCi). When the number of “0” bits ZBCi is larger than the number of “1” bits, the m-bit data mi is bit-inverted (Step 352), and the bit inversion flag IVFi is set to 0 (Step 353). When the number of “0” bits ZBCi is equal to or less than the number of “1” bits, the m-bit data mi is not bit-inverted, and the bit inversion flag IVFi is set to 1 (Step 354).
次のStep355では、現在のi値へ1を加算した値をi値とし、その後のStep356ではi値がM(=8KB=8192ビット)をmで除算した値以上かどうかをチェックする。i値がMをmで除算した値以上であれば、一連の処理を終了し、それ以外は、Step350を実行する。
In the next Step 355, the value obtained by adding 1 to the current i value is used as the i value, and in the subsequent Step 356, it is checked whether the i value is equal to or larger than the value obtained by dividing M (= 8 KB = 8192 bits) by m. If the i value is equal to or greater than the value obtained by dividing M by m, the series of processing is terminated, otherwise Step 350 is executed.
この後の動作は、図14で説明したStep31と同様である。データビット反転処理によって、書込みデータDATA内の“0”データのビット数を半数以下にできるため、この後の処理によって求める書込みデータDATAに対するバウンダリフラグBDの0値の総数SUMF0を減少することができる。つまり、データビット反転処理によって、不揮発性メモリ装置NVM0~NVM3の書込む回数は減少し、書込み時間を短縮することができる。
The subsequent operation is the same as Step 31 described in FIG. Since the number of bits of the “0” data in the write data DATA can be reduced to half or less by the data bit inversion process, the total number SUMF0 of 0 values of the boundary flag BD for the write data DATA obtained by the subsequent process can be reduced. . That is, by the data bit inversion process, the number of times of writing to the nonvolatile memory devices NVM0 to NVM3 is reduced, and the writing time can be shortened.
図18に戻ると、Step32が終了した後、Step4にて、書込みデータDATAと、これらデータに対応するバウンダリフラグBDと、ビット反転フラグIVF、バウンダリフラグBD0値の総数BDSUM0をバッファBUF0へ書込む。
Referring back to FIG. 18, after Step 32 is completed, in Step 4, the write data DATA, the boundary flag BD corresponding to these data, the bit inversion flag IVF, and the total number BDSUM0 of the boundary flag BD0 values are written into the buffer BUF0.
図20は、書込みデータDATAの中を、mビット毎に分けたそれぞれのmビットのデータmi(i=0,1,2,~,M/m)に対するバウンダリフラグBDiの対応付けを示す図である。書込みデータDATAの中の0データビット数が2/3の5440×8ビットの場合に、図19のデータビット反転処理を実行し、図18のStep32が実行された直後の状態を示している。書込みデータDATAとデータmiの対応方法は、図5と同様である。
FIG. 20 is a diagram showing the correspondence of the boundary flag BDi to each m-bit data mi (i = 0, 1, 2,..., M / m) divided into m bits in the write data DATA. is there. When the number of 0 data bits in the write data DATA is 5440 × 8 bits, which is 2/3, the data bit inversion processing of FIG. 19 is executed, and the state immediately after Step 32 of FIG. 18 is executed is shown. The correspondence method between the write data DATA and the data mi is the same as in FIG.
データビット反転処理によって、書込みデータDATAの中の0データビット数が1/3の2752×8ビットに削減され、その結果、バウンダリフラグBDの0の数も(2752/32)×8=688まで、削減できる。このように、図19のデータビット反転処理を実行した結果、BD値の0の数が688となり、“0”データビットを書込む回数も688回となる。本実施例を用いない場合は、書込む回数は2048回となるため、本実施例によって書込み回数は1360回分減少可能となる。バウンダリフラグBD値が0の数が少ないほど、“0”データビットを書込む回数は減少し、書込み時間を短縮することができる。
Data bit inversion reduces the number of 0 data bits in write data DATA to 1/3 of 2752 x 8 bits. As a result, the number of 0 of boundary flag BD is also (2752/32) x 8 = 688 Can be reduced. Thus, as a result of executing the data bit inversion processing of FIG. 19, the number of 0 of the BD value is 688, and the number of times of writing “0” data bits is 688 times. If the present embodiment is not used, the number of times of writing is 2048, so the number of times of writing can be reduced by 1360 times according to the present embodiment. The smaller the number of 0 of the boundary flag BD value, the smaller the number of times of writing “0” data bits, and the write time can be shortened.
図21はバッファに格納されるデータおよびバウンダリフラグBDの一例を示す表図であり、図6、図16に対応するものであるが、これらにさらにデータビット反転処理を適用した例である。
FIG. 21 is a table showing an example of the data stored in the buffer and the boundary flag BD, which corresponds to FIG. 6 and FIG. 16, but is an example in which a data bit inversion process is further applied thereto.
図21(C1)に、図18でのStep32にてデータビット反転処理を行った後に、Step4にてバッファBUF0へ格納された書込みデータDATA D0~D7と、これらデータに対応するバウンダリフラグD0_BD~D7_BDと、バウンダリフラグの有効/無効フラグD0_BDV~D7_BDV(この例では全て有効とする)と、ビット反転フラグD0_IVF~D7_IVFと、バウンダリフラグD0_BD~D7_BD内の0値の総数BDSUM0を示す。
In FIG. 21C1, after performing the data bit inversion processing in Step 32 of FIG. 18, the write data DATA D0 to D7 stored in the buffer BUF0 in Step 4 and the boundary flags D0_BD to D7_BD corresponding to these data are stored. Boundary flag valid / invalid flags D0_BDV to D7_BDV (all valid in this example), bit inversion flags D0_IVF to D7_IVF, and the total number of zero values BDSUM0 in the boundary flags D0_BD to D7_BD.
書込みデータDATA D0~D7に対応しているバウンダリフラグD0_BD~D7_BDの0値の総数BDSUM0は、それぞれ、710、420、950、800、960、810、700、500となっている。
The total number BDSUM0 of 0 values of the boundary flags D0_BD to D7_BD corresponding to the write data DATA D0 to D7 is 710, 420, 950, 800, 960, 810, 700, and 500, respectively.
一方、先の図16(C1)は、データビット反転処理を行わない場合の、総数BDSUM0値を示しており、これらの値と比較すると、データビット反転処理を行うことで、これら総数BDSUM0の値を大幅に減少させることができる。
On the other hand, FIG. 16C1 shows the total number of BDSUM0 values when the data bit inversion process is not performed. Compared with these values, the value of the total number BDSUM0 is obtained by performing the data bit inversion process. Can be greatly reduced.
図21(B2)に、書込み時間短縮チャネル割り当てを行わなかった場合の、データD0~D7に対するチャネル割り当てを示し、図21(B3)に、その際の、チャネル毎の総数SUM_BDCを示す。
FIG. 21 (B2) shows the channel assignment for data D0 to D7 when the write time reduction channel assignment is not performed, and FIG. 21 (B3) shows the total number SUM_BDC for each channel at that time.
書込みデータD0とD4をチャネルCH0へ割り当て、書込みデータD1とD5をチャネルCH1へ割り当て、書込みデータD2とD6をチャネルCH2へ割り当て、書込みデータD3とD7をチャネルCH3へ割り当てる。
Write data D0 and D4 are assigned to channel CH0, write data D1 and D5 are assigned to channel CH1, write data D2 and D6 are assigned to channel CH2, and write data D3 and D7 are assigned to channel CH3.
この際の、チャネルCH0の総数SUM_BDCは1670、チャネルCH1の総数SUM_BDCは1230、チャネルCH2の総数SUM_BDCは1650、チャネルCH3の総数SUM_BDCは1300となる。チャネルCH0の総数SUM_BDCである1670が、不揮発性メモリ装置NVMへの最大書込み回数となり、これが最大書込み時間となる。
At this time, the total number SUM_BDC of the channel CH0 is 1670, the total number SUM_BDC of the channel CH1 is 1230, the total number SUM_BDC of the channel CH2 is 1650, and the total number SUM_BDC of the channel CH3 is 1300. The total number SUM_BDC of channel CH0 1670 is the maximum number of times of writing to the nonvolatile memory device NVM, and this is the maximum write time.
一方、図21(C2)に、図18でのStep61にて書込み時間短縮チャネル割り当てを行なった場合の、データD0~D7に対する従来のチャネル割り当てを示し、図21(C3)に、その際の、チャネル毎の総数SUM_BDCを示す。この際の、チャネルCH0の総数SUM_BDCは1380、チャネルCH1の総数SUM_BDCは1450、チャネルCH2の総数SUM_BDCは1510、チャネルCH3の総数SUM_BDCは1510となる。
On the other hand, FIG. 21 (C2) shows the conventional channel assignment for data D0 to D7 when the write time reduction channel assignment is performed in Step 61 in FIG. 18, and FIG. Indicates the total number SUM_BDC for each channel. At this time, the total number SUM_BDC of the channel CH0 is 1380, the total number SUM_BDC of the channel CH1 is 1450, the total number SUM_BDC of the channel CH2 is 1510, and the total number SUM_BDC of the channel CH3 is 1510.
書込み時間短縮チャネル割り当てを行なった場合、総数SUM_BDCの最大値は1510となり、書込み時間短縮チャネル割り当てを行わなかった場合と比較し、160ほど減少している。この様に、書込み時間短縮チャネル割り当てにより、総数SUM_BDCの最大値を減少させることで、不揮発性メモリ装置NVMへの最大書込み回数、つまり、最大書込み時間を短縮できる。これによって、アドレス変換テーブルLPTBLと、ブロック毎の消去回数テーブルERSTBLの更新タイミングを早めることができるため、高速書込みが可能となる。
When the write time reduction channel assignment is performed, the maximum value of the total number SUM_BDC is 1510, which is reduced by about 160 compared with the case where the write time reduction channel assignment is not performed. In this way, by reducing the maximum value of the total number SUM_BDC by channel assignment for shortening the write time, the maximum number of writes to the nonvolatile memory device NVM, that is, the maximum write time can be shortened. As a result, the update timing of the address conversion table LPTBL and the erase count table ERSTBL for each block can be advanced, so that high-speed writing is possible.
図22で、本実施例による書込み時間の短縮効果を説明する。図22(A)は、本実施例を利用しない場合の、メモリモジュールNVMD0でのデータD0~D7の書込み時間を示す。図22(B)は、本実施例の「バウンダリフラグBD」を利用した制御での、メモリモジュールNVMD0でのデータD0~D7の書込み時間を示す。図22(C)は、本実施例の「バウンダリフラグBD」と、「チャネル割り当て」を利用した制御での、メモリモジュールNVMD0でのデータD0~D7の書込み時間を示す。
Referring to FIG. 22, the effect of shortening the writing time according to the present embodiment will be described. FIG. 22A shows the writing time of data D0 to D7 in the memory module NVMD0 when this embodiment is not used. FIG. 22B shows the writing time of the data D0 to D7 in the memory module NVMD0 in the control using the “boundary flag BD” of the present embodiment. FIG. 22C shows the writing time of the data D0 to D7 in the memory module NVMD0 in the control using the “boundary flag BD” and “channel allocation” of the present embodiment.
図22(A)は従来例に相当し、図22(B)は図6あるいは図16(B)で示した制御を用いた例に相当し、図22(C)は図16(C)で示した制御を用いた例に相当する。
22A corresponds to a conventional example, FIG. 22B corresponds to an example using the control shown in FIG. 6 or 16B, and FIG. 22C corresponds to FIG. This corresponds to an example using the control shown.
図22(A)での、チャネルCH0(不揮発性メモリ装置NVM0)への書込み回数が最大で4096となる。また、図22(B)では、本実施例の「バウンダリフラグBD」を利用した制御によって、各チャネルへの書込み回数が削減され、書込み時間が短縮される。さらに、図22(C)では、本実施例の「バウンダリフラグBD」と、「チャネル割り当て」を利用した制御によって、チャネルCH1の最大書込み回数が削減され、書込み時間が短縮される。
In FIG. 22A, the maximum number of writes to channel CH0 (nonvolatile memory device NVM0) is 4096. In FIG. 22B, the number of times of writing to each channel is reduced and the writing time is shortened by the control using the “boundary flag BD” of the present embodiment. Further, in FIG. 22C, the maximum write count of the channel CH1 is reduced and the write time is shortened by the control using the “boundary flag BD” and “channel allocation” of the present embodiment.
図23(A)は、本実施例を利用しない場合の、メモリモジュールNVMD0でのデータD0~D7の書込み時間を示し、図23(B)は、本実施例の「ビット反転処理」と「バウンダリフラグBD」を利用した制御での、メモリモジュールNVMD0でのデータD0~D7の書込み時間を示し、図23(C)は、本実施例の「ビット反転処理」と、「バウンダリフラグBD」と、「チャネル割り当て」を利用した制御での、メモリモジュールNVMD0でのデータD0~D7の書込み時間を示す。
FIG. 23A shows the write time of data D0 to D7 in the memory module NVMD0 when this embodiment is not used, and FIG. 23B shows the “bit inversion processing” and “boundary” of this embodiment. FIG. 23C shows the write time of the data D0 to D7 in the memory module NVMD0 under the control using the flag BD. FIG. 23C shows the “bit inversion process”, the “boundary flag BD” of this embodiment, The write time of data D0 to D7 in the memory module NVMD0 in the control using “channel allocation” is shown.
図23(A)は従来例に相当し、図23(B)は図21(B)で示した制御を用いた例に相当し、図23(C)は図21(C)で示した制御を用いた例に相当する。
FIG. 23A corresponds to a conventional example, FIG. 23B corresponds to an example using the control shown in FIG. 21B, and FIG. 23C shows the control shown in FIG. Corresponds to an example using.
図23(A)での、チャネルCH0(不揮発性メモリ装置NVM0)への書込み回数が最大で4096となる。また、図23(B)では、本実施例の「ビット反転処理」と「バウンダリフラグBD」を利用した制御によって、各チャネルへの書込み回数が大幅に削減され、書込み時間が短縮される。さらに、図23(C)では、本実施例の「ビット反転処理」と、「バウンダリフラグBD」と、「チャネル割り当て」を利用した制御によって、チャネルCH0の最大書込み回数が削減され、書込み時間が短縮される。
In FIG. 23A, the maximum number of writes to channel CH0 (nonvolatile memory device NVM0) is 4096. In FIG. 23B, the number of times of writing to each channel is greatly reduced and the writing time is shortened by the control using the “bit inversion processing” and the “boundary flag BD” of the present embodiment. Further, in FIG. 23C, the maximum number of times of writing to the channel CH0 is reduced by the control using the “bit inversion processing”, the “boundary flag BD”, and the “channel allocation” of the present embodiment, and the writing time is reduced. Shortened.
以下、実施例1~3を採用したシステムに適用するのに好適な、ガーベージコレクションの処理について説明する。システム構成は、図1、図2、図7の構成と同様である。
Hereinafter, a garbage collection process suitable for application to a system employing the first to third embodiments will be described. The system configuration is the same as that shown in FIGS.
図24は本実施例のガーベージコレクション動作時に、図2の情報処理回路MNGRが行うデータコピー動作である。限定するものではないが、この例では図14のStep7が終了した時点からガーベージコレクションの処理を開始する(Step0)。ガーベージコレクション自体は公知技術であるが、以下では本実施例に特有の特徴を主に説明する。
FIG. 24 shows a data copy operation performed by the information processing circuit MNGR in FIG. 2 during the garbage collection operation of this embodiment. Although not limited, in this example, the garbage collection process is started from the point when Step 7 in FIG. 14 ends (Step 0). Garbage collection itself is a well-known technique, but in the following, features specific to this embodiment will be mainly described.
情報処理回路MNGRは、不揮発性メモリ装置NVM0~NVM3から記憶装置M2へ格納されているメモリモジュールNVMD0の消去済ブロック数を読み出し、その消去済ブロック数と規定値Bを比較する(Step1)。この、消去済ブロック数がB個以下であれば、Step2を実行し、それ以外では、Step15(終了)を行う。
The information processing circuit MNGR reads the number of erased blocks of the memory module NVMD0 stored in the storage device M2 from the nonvolatile memory devices NVM0 to NVM3, and compares the number of erased blocks with a specified value B (Step 1). If the number of erased blocks is B or less, Step 2 is executed, otherwise Step 15 (end) is executed.
Step2では、情報処理回路MNGRが、消去回数がN1回以上の不揮発性メモリ装置NVM0~NVM3の書込み済ブロックをL1個選択する。次のStep3では、消去回数がN2以下の、不揮発性メモリ装置NVM0~NVM3の消去済ブロックをL2個選択する。
In Step 2, the information processing circuit MNGR selects L1 written blocks of the non-volatile memory devices NVM0 to NVM3 whose erase count is N1 or more. In the next Step 3, L2 erased blocks of the non-volatile memory devices NVM0 to NVM3 whose erase count is N2 or less are selected.
Step4では、Step2で選択された不揮発性メモリ装置NVM0~NVM3のL1個のブロック内の有効ページのデータPDATAを、順に読み出す。図11で説明したように、データPDATAはデータDATAと、冗長データRdataから構成される。冗長データRdataには、データ反転フラグIVF、バウンダリフラグBDF、ECCコードECC1、ECC2が含まれている。
In Step 4, the valid page data PDATA in the L1 blocks of the nonvolatile memory devices NVM0 to NVM3 selected in Step 2 are sequentially read. As described with reference to FIG. 11, the data PDATA is composed of data DATA and redundant data Rdata. The redundant data Rdata includes a data inversion flag IVF, a boundary flag BDF, and ECC codes ECC1 and ECC2.
具体的には、情報処理回路MNGRは、調停回路ARBを介して読み出しキュー回路RDQ0~RDQ3へ読み出し命令RDgcと物理アドレスPAD10を転送する。なお、この読み出し命令RDgcは上位装置CPU_CPの読み出し要求以外から発生する読み出し命令であることを示す。
Specifically, the information processing circuit MNGR transfers the read instruction RDgc and the physical address PAD10 to the read queue circuits RDQ0 to RDQ3 via the arbitration circuit ARB. Note that this read command RDgc is a read command generated from other than a read request of the host device CPU_CP.
メモリ制御回路(NVCT0~NVCT3)は、読み出しキュー回路RDQ0~RDQ3から読み出し命令RDgcを読み出し、この読み出し命令RDgcに対応した読み出し命令RD10と、物理アドレスPAD10を不揮発性メモリ装置(NVM0~3)へ転送する。読み出し命令RD10は、バウンダリフラグBDと、データDATA0およびECCコードECC1、ECC2を読み出す命令である(コマンドの一覧については、後に図26で説明する)。
The memory control circuits (NVCT0 to NVCT3) read the read instruction RDgc from the read queue circuits RDQ0 to RDQ3, and transfer the read instruction RD10 corresponding to the read instruction RDgc and the physical address PAD10 to the nonvolatile memory devices (NVM0 to 3) To do. The read command RD10 is a command for reading the boundary flag BD, data DATA0, and ECC codes ECC1 and ECC2 (a list of commands will be described later with reference to FIG. 26).
不揮発性メモリ装置(NVM0~3)は、読み出し命令RD10と、物理アドレスPAD10によって、物理アドレスPAD10に対応したデータDATA10と、データDATA10の反転フラグIVFとECCコードECC1、バウンダリフラグBDと、バウンダリフラグBDのECCコードECC2をメモリ制御回路(NVCT0~NVCT3)へ転送する。
The non-volatile memory devices (NVM0 to NVM3) use the read command RD10 and the physical address PAD10, the data DATA10 corresponding to the physical address PAD10, the inversion flag IVF of the data DATA10, the ECC code ECC1, the boundary flag BD, and the boundary flag BD. The ECC code ECC2 is transferred to the memory control circuit (NVCT0 to NVCT3).
Step5では、メモリ制御回路NVCTは、ECCコードECC1を利用して、データDATA10および反転フラグIVFにエラーがあるかをチェックする。また、ECCコードECC2を利用して、バウンダリフラグBDにエラーがあるかをチェックする。これらにエラーがあれば訂正を行い、読み出しキュー回路(バッファ)RDQ0~RDQ3へデータDATA10、反転フラグIVF、バウンダリフラグBD、ECCコードECC1およびECCコードECC2を転送する。
In Step 5, the memory control circuit NVCT uses the ECC code ECC1 to check whether there is an error in the data DATA10 and the inversion flag IVF. Also, using the ECC code ECC2, it is checked whether there is an error in the boundary flag BD. If there is an error in these, correction is performed, and data DATA10, inversion flag IVF, boundary flag BD, ECC code ECC1, and ECC code ECC2 are transferred to read queue circuits (buffers) RDQ0 to RDQ3.
また、情報処理回路MNGRは、読み出し命令RDgcによって読み出し、読み出しキュー回路RDQ0~RDQ3へ保存されているデータDATA10、反転フラグIVF、バウンダリフラグBD、ECCコードECC1およびECCコードECC2に対しては、NVMロウデータ有効情報ROWDV情報の値を“0”(=有効)とし、これらの情報の値を変えずに、NVMロウデータ有効情報ROWDV情報とともに、バッファBUF0内のコピー領域CAREAへ転送する。
Further, the information processing circuit MNGR reads the data by the read command RDgc and stores the NDATA low for the data DATA10, the inversion flag IVF, the boundary flag BD, the ECC code ECC1, and the ECC code ECC2 stored in the read queue circuits RDQ0 to RDQ3. The value of the data valid information ROWDV information is set to “0” (= valid), and the data value is transferred to the copy area CAREA in the buffer BUF0 together with the NVM row data valid information ROWDV information without changing the values of these information.
次のStep6では、Step2で選択された不揮発性メモリ装置NVM0~NVM3のL1個のブロック内の有効ページのデータPDATAの全てがバッファBUF0へ転送されたかをチェックする。転送が完了していない場合は、Step7を実行し、転送が完了した場合はStep8を実行する。
In the next Step 6, it is checked whether all the valid page data PDATA in the L1 blocks of the nonvolatile memory devices NVM0 to NVM3 selected in Step 2 have been transferred to the buffer BUF0. If the transfer has not been completed, Step 7 is executed. If the transfer has been completed, Step 8 is executed.
Step7では、バッファBUF0のコピー領域CAREAが不揮発性メモリ装置NVMから読み出したデータで満たされているかをチェックする。満たされていれば、Step8を実行し、満たされていなければ、Step4を実行する。
In Step 7, it is checked whether the copy area CAREA of the buffer BUF0 is filled with the data read from the nonvolatile memory device NVM. If it is satisfied, Step 8 is executed, and if not satisfied, Step 4 is executed.
Step8では、情報処理回路MNGRは、コピー領域CAREA内のStep3で選択された消去済ブロック内の物理アドレスPAD10と、バッファBUF0のコピー領域CAREAへ格納された、反転フラグINVFと、バウンダリフラグBDと、データDATA10、ECCコードECC1、ECC2、プログラム命令PRGgcを、書込みキュー回路WTQ0~WTQ3へ転送する。
In Step 8, the information processing circuit MNGR, the physical address PAD10 in the erased block selected in Step 3 in the copy area CAREA, the inversion flag INVF, the boundary flag BD stored in the copy area CARARE of the buffer BUF0, Data DATA10, ECC codes ECC1, ECC2, and program instruction PRGgc are transferred to write queue circuits WTQ0 to WTQ3.
次に、メモリ制御回路NVCTは、書込みキュー回路WTQ0~WTQ3へ格納されている反転フラグINVFと、バウンダリフラグBDと、DATA10、ECCコードECC1、ECC2を読み出し、不揮発性メモリ装置NVM0~NVM3へ、プログラム命令PRG01と、物理アドレスPAD100と、反転フラグINVFと、バウンダリフラグBDと、データDATA10、ECCコードECC1、ECC2を転送する。プログラム命令PRG01は、反転フラグINVFと、バウンダリフラグBDと、データDATA10、ECCコードECC1、ECC2を不揮発性メモリ装置NVM0~NVM3へ書込む命令である。プログラム命令PRG01はバウンダリフラグBDをメモリに書込むため、不揮発性メモリ装置NVM0~NVM3は、ガーベージコレクション処理にバウンダリフラグBDを再利用することができる。
Next, the memory control circuit NVCT reads the inversion flag INVF, the boundary flag BD, DATA10, and the ECC codes ECC1 and ECC2 stored in the write queue circuits WTQ0 to WTQ3, and programs the nonvolatile memory devices NVM0 to NVM3. The instruction PRG01, physical address PAD100, inversion flag INVF, boundary flag BD, data DATA10, and ECC codes ECC1 and ECC2 are transferred. Program instruction PRG01 is an instruction for writing inversion flag INVF, boundary flag BD, data DATA10, and ECC codes ECC1 and ECC2 to nonvolatile memory devices NVM0 to NVM3. Since the program instruction PRG01 writes the boundary flag BD into the memory, the nonvolatile memory devices NVM0 to NVM3 can reuse the boundary flag BD for garbage collection processing.
不揮発性メモリ装置NVM0~NVM3は、プログラム命令PRG01により、内部のメモリセルへ、反転フラグINVFと、バウンダリフラグBDと、DATA10、ECCコードECC1、ECC2を書込む。
Nonvolatile memory devices NVM0 to NVM3 write inversion flag INVF, boundary flag BD, DATA10, and ECC codes ECC1 and ECC2 to internal memory cells by program instruction PRG01.
次のStep9では、Step2で選択された不揮発性メモリ装置NVM0~NVM3のL1個のブロック内の有効ページのデータPDATAの全てが、不揮発性メモリ装置へ転送されたかをチェックする。データPDATAの全てが不揮発性メモリ装置NVM0~NVM3へ転送された場合は、Step10を実行し、転送されていない場合は、Step4を実行する。Step10では、Step2で選択された書込み済ブロックを消去する。
In the next Step 9, it is checked whether all the valid page data PDATA in the L1 blocks of the nonvolatile memory devices NVM0 to NVM3 selected in Step 2 have been transferred to the nonvolatile memory device. If all of the data PDATA has been transferred to the nonvolatile memory devices NVM0 to NVM3, Step 10 is executed, and if not, Step 4 is executed. In Step 10, the written block selected in Step 2 is erased.
書込み済ブロック消去の際に、図10で説明した様に、同時にLバイト分のチェインメモリアレイ内のメモリセルを低抵抗にできる場合には、図11で示したブロックサイズが64KBのブロックに対し、(64/L)×1024回に分けた、時分割の消去動作が必要となる。
When erasing a written block, as described with reference to FIG. 10, if the memory cells in the chain memory array for L bytes can be made low resistance at the same time, the block size shown in FIG. , (64 / L) × 1024 times-divided erase operations are required.
次のStep11では、消去動作中に、ホストからの優先的な読み出し要求が発生した場合は、情報処理回路MNGRは、調停回路ARBを介して読み出しキュー回路RDQ0~RDQ3へ優先読み出し命令RDpriと物理アドレスPAD20を転送する。
In the next Step 11, if a priority read request from the host occurs during the erase operation, the information processing circuit MNGR sends the priority read instruction RDpri and physical address to the read queue circuits RDQ0 to RDQ3 via the arbitration circuit ARB. Transfer PAD20.
メモリ制御装置(NVCT0~NVCT3)は、読み出しキュー回路RDQ0~RDQ3から優先読み出し命令RDpriと物理アドレスPAD50を読み出し、物理アドレスPAD50が、現在、消去動作中の不揮発性メモリ装置(NVM0~3)内の物理アドレスであれば、消去動作の一時中断命令Erase_pauseを、消去動作中の不揮発性メモリ装置(NVM0~3)へ転送する。消去動作中の不揮発性メモリ装置は、消去動作の一時中断命令Erase_pauseを受け取ったら、現在消去中の、Lバイト分のチェインメモリアレイへの消去動作を完了し、消去動作を一時中断する。この消去動作を一時中断するまでの、最大時間はt10とする。
The memory control devices (NVCT0 to NVCT3) read the priority read instruction RDpri and the physical address PAD50 from the read queue circuits RDQ0 to RDQ3, and the physical address PAD50 is in the nonvolatile memory device (NVM0 to 3) that is currently performing the erase operation. If it is a physical address, the erase operation temporary interruption command Erase_pause is transferred to the nonvolatile memory devices (NVM0 to NVM3) that are performing the erase operation. When the nonvolatile memory device in the erasing operation receives the erase operation temporary interruption command Erase_pause, the non-volatile memory device completes the erasing operation to the chain memory array for L bytes currently being erased, and temporarily suspends the erasing operation. The maximum time until the erasing operation is temporarily interrupted is t10.
その後、t10期間が経過した後、メモリ制御装置(NVCT0~NVCT3)は読み出し命令RD01と物理アドレスPAD50を不揮発性メモリ装置(NVM0~3)へ転送する。不揮発性メモリ装置(NVM0~3)は、物理アドレスPAD50のデータDATA50、反転フラグIVFおよびECCコードECC1をメモリ制御装置へ出力し、さらに、メモリ制御装置によって読み出しキュー回路RDQ0~RDQ3へ転送される。
Thereafter, after the elapse of the t10 period, the memory control devices (NVCT0 to NVCT3) transfer the read command RD01 and the physical address PAD50 to the nonvolatile memory devices (NVM0 to NVM3). The nonvolatile memory devices (NVM0 to NVM3) output the data DATA50 of the physical address PAD50, the inversion flag IVF, and the ECC code ECC1 to the memory control device, and further transfer them to the read queue circuits RDQ0 to RDQ3 by the memory control device.
つぎに、メモリ制御装置(NVCT0~NVCT3)は、消去動作の再開命令Erase_restartを、消去動作を一時中断している不揮発性メモリ装置(NVM0~3)へ転送する。消去動作を一時中断している不揮発性メモリ装置は、次の、Lバイト分のチェインメモリアレイへの消去動作を再開する。
Next, the memory control devices (NVCT0 to NVCT3) transfer the erase operation restart command Erase_restart to the nonvolatile memory devices (NVM0 to 3) that have temporarily suspended the erase operation. The nonvolatile memory device that has temporarily suspended the erase operation resumes the next erase operation to the chain memory array for L bytes.
次に、メモリ制御装置NVCTは、ECCコードECC1を利用して、データDATA50および反転フラグIVFにエラーがあるかをチェックし、エラーがあれば訂正を行い、読み出しキュー回路RDQ0~RDQ3へデータDATA50および反転フラグIVFを転送する。次に、情報処理回路MNGRは反転フラグIVF値が0かどうかをチェックする。反転フラグIVF値が0であれば、データDATA50の各ビットを反転させ、データDATA50Rを生成し、インターフェース回路NVM_IFを通じて上位装置CPU_CPへ転送する。
Next, the memory controller NVCT uses the ECC code ECC1 to check whether there is an error in the data DATA50 and the inversion flag IVF. If there is an error, the memory controller NVCT corrects the error and sends the data DATA50 and the read queue circuit RDQ0 to RDQ3. Transfer the inversion flag IVF. Next, the information processing circuit MNGR checks whether the inversion flag IVF value is zero. If the inversion flag IVF value is 0, each bit of the data DATA50 is inverted, data DATA50R is generated, and transferred to the host device CPU_CP through the interface circuit NVM_IF.
Step12では、Step2で選択された全ての書込み済ブロックが消去されたかをチェックする。もし、Step2で選択された全ての書込み済ブロックが消去された場合は、Step13を行う。もし、Step2で選択された全ての書込み済ブロックが消去されていない場合は、Step10を行う。
In Step 12, it is checked whether all written blocks selected in Step 2 have been erased. If all the written blocks selected in Step 2 are erased, Step 13 is performed. If all the written blocks selected in Step 2 are not erased, Step 10 is performed.
Step13では、消去済ブロック数がB個より多いかどうかをチェックする。消去済ブロック数がB個より多い場合はStep14を行い、それ以外は、Step2を行う。
In Step 13, it is checked whether the number of erased blocks is greater than B. If the number of erased blocks is greater than B, Step 14 is performed, otherwise Step 2 is performed.
Step14では、情報処理回路MNGRは、メモリ装置M2に格納されている論物アドレス変換テーブルLPTBLと、物論アドレス変換テーブルPLTBLと、ブロック毎の消去回数テーブルERSTBL、消去ブロック数テーブルERSTBL1を更新し、終了する(Step15)
以上説明した様に、本実施例では、反転フラグIVFやバウンダリフラグBDを不揮発性メモリ装置NVMへ格納しておく。これにより、これを読み出しバッファBUF0およびBUF1へ格納した際は、図18のデータビット反転動作や、図3のStep3、図14のStep31、および図18のStep32での一連のバウンダリ検出動作を再実行する必要が無くなる。このため、ガーベージコレクション動作や、スタティックウエアレベリング動作時のデータコピー動作を高速化できる。 In Step 14, the information processing circuit MNGR updates the logical / physical address conversion table LPTBL, the physical address conversion table PLTBL, the erase count table ERSTBL for each block, and the erase block count table ERSTBL1 stored in the memory device M2. Finish (Step 15)
As described above, in this embodiment, the inversion flag IVF and the boundary flag BD are stored in the nonvolatile memory device NVM. Thus, when this is stored in the read buffers BUF0 and BUF1, the data bit inversion operation in FIG. 18 and the series of boundary detection operations inStep 3 in FIG. 3, Step 31 in FIG. 14, and Step 32 in FIG. 18 are re-executed. There is no need to do. Therefore, the speed of the garbage collection operation and the data copy operation during the static wear leveling operation can be increased.
以上説明した様に、本実施例では、反転フラグIVFやバウンダリフラグBDを不揮発性メモリ装置NVMへ格納しておく。これにより、これを読み出しバッファBUF0およびBUF1へ格納した際は、図18のデータビット反転動作や、図3のStep3、図14のStep31、および図18のStep32での一連のバウンダリ検出動作を再実行する必要が無くなる。このため、ガーベージコレクション動作や、スタティックウエアレベリング動作時のデータコピー動作を高速化できる。 In Step 14, the information processing circuit MNGR updates the logical / physical address conversion table LPTBL, the physical address conversion table PLTBL, the erase count table ERSTBL for each block, and the erase block count table ERSTBL1 stored in the memory device M2. Finish (Step 15)
As described above, in this embodiment, the inversion flag IVF and the boundary flag BD are stored in the nonvolatile memory device NVM. Thus, when this is stored in the read buffers BUF0 and BUF1, the data bit inversion operation in FIG. 18 and the series of boundary detection operations in
また、このバッファBUF0のコピー領域ACOPYへ格納したデータを、不揮発性メモリ装置NVMへ転送する際は、すでに、反転フラグIVF、バウンダリフラグBD、ECCコードECC1、ECC2は準備されているので、情報処理回路MNGRによる図4で示すバウンダリ処理や、図19で示すデータビット反転処理を実行する必要が無く、さらに、メモリ制御回路NVCTにて、ECCコードECC1、ECC2を生成する必要がなく、不揮発性メモリ装置NVMへのデータ転送を高速に実行できる。
In addition, when the data stored in the copy area ACOPY of the buffer BUF0 is transferred to the nonvolatile memory device NVM, the inversion flag IVF, the boundary flag BD, and the ECC codes ECC1 and ECC2 are already prepared. There is no need to execute the boundary processing shown in FIG. 4 by the circuit MNGR and the data bit inversion processing shown in FIG. 19, and it is not necessary to generate the ECC codes ECC1 and ECC2 in the memory control circuit NVCT. Data transfer to the device NVM can be performed at high speed.
さらに、消去動作の一時中断命令Erase_pauseにより、ブロックの消去動作中に、ホストからの読み出し命令を優先的に実行できるため、ホストからの読み出しを高速化できる。また、消去動作の再開命令Erase_restartにより、次の、Lバイト分のチェインメモリアレイへの消去動作を再開することができるため、同じLバイト分のチェインメモリアレイへ重複して消去動作を行う必要がなく、無駄な消去動作が発生させずに、ホストからの読み出しを高速化できる。
Furthermore, since the read command from the host can be preferentially executed during the erase operation of the block by the temporary interrupt command Erase_pause of the erase operation, the read from the host can be accelerated. Further, since the erase operation to the next L bytes of the chain memory array can be resumed by the erase operation restart instruction Erase_restart, it is necessary to perform the erase operation redundantly on the same L bytes of the chain memory array. In addition, reading from the host can be speeded up without causing unnecessary erasing operation.
なお、後述のように、Erase_pause、Erase_restartは、メモリ制御回路NVCT0~3で使用可能な図26に示す種々のコマンドに含まれ、図27のように各コマンドの有効無効を設定することにより、各種のシステムに対応が可能である。
As will be described later, Erase_pause and Erase_restart are included in various commands shown in FIG. 26 that can be used in the memory control circuits NVCT0 to NVCT3. Various settings can be made by setting the validity of each command as shown in FIG. It is possible to support this system.
以下、実施例1~3を採用したシステムに適用するのに好適な、上位装置CPU_CPからの読み出し要求の処理について説明する。システム構成は、図1、図2、図7の構成と同様である。
Hereinafter, processing of a read request from the host device CPU_CP, which is suitable for application to a system employing the first to third embodiments, will be described. The system configuration is the same as that shown in FIGS.
図25は、上位装置CPU_CPからの読み出し要求が、メモリモジュールNVMD0へ入力した際の、メモリモジュールNVMD0の読み出し動作の一例である。
FIG. 25 is an example of a read operation of the memory module NVMD0 when a read request from the host device CPU_CP is input to the memory module NVMD0.
Step1で、図1の上位装置CPU_CPから論理アドレスLAD、データ読み出し命令RD、セクタカウントSECなどが含まれる読み出し要求RQが、制御回路NVM-CTLのインターフェース回路NVM-IFを通じて、図2の情報処理回路MNGRへ入力される。要求を受けた情報処理回路MNGRは、先ず、上位装置CPU_CPからのアクセスが読み出し要求RQかをチェックし、そのアクセスが読み出し要求RQである場合、Step2を行う。
In Step 1, the read request RQ including the logical address LAD, the data read command RD, the sector count SEC, etc. is sent from the host device CPU_CP of FIG. 1 through the interface circuit NVM-IF of the control circuit NVM-CTL. Input to MNGR. The information processing circuit MNGR that has received the request first checks whether the access from the higher-level device CPU_CP is a read request RQ. If the access is the read request RQ, Step 2 is performed.
Step2では、情報処理回路MNGRは、論理アドレスLAD、データ読み出し命令RD、セクタカウントSECなどを、アドレス/コマンドバッファADCBUFへ格納する。
In Step 2, the information processing circuit MNGR stores the logical address LAD, the data read command RD, the sector count SEC, etc. in the address / command buffer ADCBUF.
Step3では、情報処理回路MANAGERは、論理アドレス値LAD0、データ読み出し命令RDおよびセクタカウントSEC1を解読し、メモリ装置M2へ保存されているアドレス変換テーブルLPTBL内のアドレスLAD0番地に格納されている物理アドレス値CPAD0と、この物理アドレス値CPAD0に対応した有効フラグCVF値を読み出す。
In Step 3, the information processing circuit MANAGER decodes the logical address value LAD0, the data read instruction RD, and the sector count SEC1, and stores the physical address stored in the address LAD0 in the address conversion table LPTBL stored in the memory device M2. The value CPAD0 and the valid flag CVF value corresponding to the physical address value CPAD0 are read.
Step4では、情報処理回路MANAGERは、読み出した有効フラグCVF値が1であるかどうかをチェックする。有効フラグCVF値が0の場合は、論理アドレスLAD0番地には物理アドレスCPADが割り当てられていないことを示し、不揮発性メモリ装置NVMからデータを読み出すことができないため、情報処理回路MANAGERはエラーが発生したことを、インターフェース回路NVM_IFを通じて上位装置CPU_CPへ伝える(Step10)。もし、有効フラグCVF値が1(有効)の場合は、Step5を行う。
In Step 4, the information processing circuit MANAGER checks whether or not the read valid flag CVF value is 1. When the valid flag CVF value is 0, it indicates that the physical address CPAD is not assigned to the logical address LAD0, and data cannot be read from the non-volatile memory device NVM. This is transmitted to the host device CPU_CP through the interface circuit NVM_IF (Step 10). If the valid flag CVF value is 1 (valid), Step 5 is performed.
Step5では、論理アドレスLAD0番地に物理アドレスCPAD0番地が対応している場合、情報処理回路MNGRは、調停回路ARBを介して読み出しキュー回路RDQ0~RDQ3へ読み出し命令RDhtと物理アドレス値CPAD0を転送する。また、この読み出し命令RDhtは、上位装置CPU_CPからの読み出し要求RQによる読み出し命令であることを示す。
In Step 5, when the physical address CPAD0 corresponds to the logical address LAD0, the information processing circuit MNGR transfers the read instruction RDht and the physical address value CPAD0 to the read queue circuits RDQ0 to RDQ3 via the arbitration circuit ARB. Further, this read command RDht indicates that it is a read command in response to a read request RQ from the host device CPU_CP.
図26は、情報処理回路(MNGR)が、メモリ制御回路(NVCT0~NVCT3)を介して、不揮発性メモリ装置NVMに発行する、NVMコマンドの機能の一覧を示す表である。コマンドには、実施例1~4で使用したErase_pause、Erase_restart、PRG01、PRG10の他、以下で説明するRD01、RD10などが定義される。本明細書では図26に示すコマンドを引用して説明している。例えば、本実施例では、バウンダリフラグを利用して書込み、バウンダリフラグをメモリセルに書込む書込み命令PRG01、バウンダリフラグを利用して書込み、バウンダリフラグをメモリセルに書き込まない書込み命令PRG10、バウンダリフラグを使用しない従来の書込み命令PRG00をサポート可能とする。
FIG. 26 is a table showing a list of NVM command functions issued by the information processing circuit (MNGR) to the nonvolatile memory device NVM via the memory control circuits (NVCT0 to NVCT3). In addition to Erase_pause, Erase_restart, PRG01, and PRG10 used in the first to fourth embodiments, RD01 and RD10 described below are defined as commands. In this specification, the commands shown in FIG. 26 are cited and described. For example, in this embodiment, writing using the boundary flag, writing command PRG01 that writes the boundary flag to the memory cell, writing using the boundary flag, writing command PRG10 that does not write the boundary flag to the memory cell, and boundary flag The conventional write command PRG00 that is not used can be supported.
また、読み出し命令もバウンダリフラグBDを読み出すRD10等と、読み出さないRD01等を選択可能である。例えば、上位装置CPU_CPからの通常のデータ読み出しであれば、バウンダリフラグBDは必要ないので、RD00またはRD01を使用すれば読み出し時間が短縮できる。一方、書込みを前提としたガーベージコレクション時の読み出しでは、バウンダリフラグBDが必要なため、RD10またはRD22を使用する。
Also, for the read command, RD10 or the like for reading the boundary flag BD and RD01 or the like for not reading can be selected. For example, since the boundary flag BD is not necessary for normal data reading from the host device CPU_CP, the reading time can be shortened by using RD00 or RD01. On the other hand, since the boundary flag BD is necessary for reading at the time of garbage collection assuming writing, RD10 or RD22 is used.
図27は、図26のNVMコマンドのモードを切り替えるために、図7のレジスタSPREGに格納される設定データの例である。この設定は、図26のコマンドSet SPREGで行う。
FIG. 27 is an example of setting data stored in the register SPREG in FIG. 7 in order to switch the mode of the NVM command in FIG. This setting is performed by the command Set SPREG in FIG.
メモリ制御回路(NVCT0~NVCT3)は、読み出しキュー回路RDQ0~RDQ3から読み出し命令RDhtを読み出し、この読み出し命令RDhtが上位装置CPU_CPからの読み出し要求RQによる読み出し命令であることを認識し、読み出し命令RD01、物理アドレスCPAD0を不揮発性メモリ装置(NVM0~3)へ転送する。図26に示すように、読み出し命令RD01は、バウンダリフラグは読みださず、データDATA、反転フラグIVFおよびECCコードECC1のみを読み出す命令である。
The memory control circuit (NVCT0 to NVCT3) reads the read command RDht from the read queue circuits RDQ0 to RDQ3, recognizes that the read command RDht is a read command based on the read request RQ from the host device CPU_CP, and reads the read command RD01, The physical address CPAD0 is transferred to the nonvolatile memory devices (NVM0 to NVM3). As shown in FIG. 26, the read instruction RD01 is an instruction for reading only the data DATA, the inversion flag IVF, and the ECC code ECC1 without reading the boundary flag.
不揮発性メモリ装置(NVM0~3)は、読み出し命令RD01と、物理アドレスCPAD0によって、物理アドレスCPAD0に対応したデータDATA0と、データDATA0に対応した、反転フラグIVFとECC1をメモリ制御回路(NVCT0~NVCT3)へ転送する。
The non-volatile memory device (NVM0 to NVM3) uses the read command RD01 and the physical address CPAD0 to send data DATA0 corresponding to the physical address CPAD0 and the inversion flag IVF and ECC1 corresponding to the data DATA0 to the memory control circuit (NVCT0 to NVCT3). ).
Step6では、メモリ制御回路NVCTは、ECCコードECC1を利用して、データDATA0および反転フラグIVFにエラーがあるかをチェックし、エラーがあれば訂正を行い、読み出しキュー回路RDQ0~RDQ3へデータDATA0および反転フラグIVFを転送する。
In Step 6, the memory control circuit NVCT uses the ECC code ECC1 to check whether there is an error in the data DATA0 and the inversion flag IVF. If there is an error, the memory control circuit NVCT corrects the error and sends data DATA0 and RDQ3 to the read queue circuit RDQ0 Transfer the inversion flag IVF.
Step7では、情報処理回路MNGRは反転フラグIVF値が0かどうかをチェックする。反転フラグIVF値が0であれば、データDATAの各ビットを反転させ、データDATA_Rを生成し(Step8)、インターフェース回路NVM_IFを通じて上位装置CPU_CPへ転送する(Step9)。
In Step 7, the information processing circuit MNGR checks whether the inversion flag IVF value is 0. If the inversion flag IVF value is 0, each bit of the data DATA is inverted to generate data DATA_R (Step 8) and transferred to the host device CPU_CP through the interface circuit NVM_IF (Step 9).
この様に、上位装置CPU_CPからの読み出し要求に対しては、読み出し命令RD01を利用し、不揮発性メモリ装置(NVM0~3)から、データDATA、反転フラグIVFおよびECCコードECC1のみを読み出す。このため、バウンダリフラグは読みだす必要は無いため、高速に読み出しが可能となる。
In this way, in response to a read request from the host device CPU_CP, only the data DATA, the inversion flag IVF, and the ECC code ECC1 are read from the nonvolatile memory device (NVM0 to NVM3) using the read command RD01. For this reason, it is not necessary to read the boundary flag, so that it can be read at high speed.
本実施例では、不揮発性メモリ装置NVM0~NVM3は、上位装置からの読み出し専用の命令RD01と、データとともに全フラグを読み出す読み出し命令RD10をサポートする。これにより、制御回路(コントローラ)NVM-CTLは、不揮発性メモリ装置NVM0~NVM3へ、上位装置からの読み出し要求に対しては、読み出し命令RD01を発行し、ガーベージコレクションやスタティックウエアレベリング動作時などの情報処理回路MNGR自身からの読み出し要求に対しては、読み出し命令RD10を発行できるため、要求元に合わせた最適な制御が可能となる。
In this embodiment, the nonvolatile memory devices NVM0 to NVM3 support a read-only command RD01 from the host device and a read command RD10 that reads all flags together with data. As a result, the control circuit (controller) NVM-CTL issues a read instruction RD01 to the non-volatile memory devices NVM0 to NVM3 in response to a read request from the host device, during garbage collection or static wear leveling operation, etc. In response to a read request from the information processing circuit MNGR itself, a read command RD10 can be issued, so that optimum control according to the request source is possible.
(まとめ)
以上に説明した各実施の形態によって得られる主な効果は以下の通りである。 (Summary)
The main effects obtained by the respective embodiments described above are as follows.
以上に説明した各実施の形態によって得られる主な効果は以下の通りである。 (Summary)
The main effects obtained by the respective embodiments described above are as follows.
第1に、書込みデータに対するバウンダリフラグBDを生成し、データを書込むために必要な内部のXアドレスと、Yアドレスと、ZアドレスへこのバウンダリフラグBDを対応付けることで、“0”データビットを一度に書込むことができる内部アドレス範囲を特定し、書込みができるため、書込み回数は減少し、書込み時間は短縮され、メモリモジュールの消費電力を低下させ、書込み速度を向上できる。
First, by generating a boundary flag BD for the write data and associating the boundary flag BD with the internal X address, Y address, and Z address necessary for writing the data, the “0” data bit is set. Since the internal address range that can be written at one time can be specified and written, the number of times of writing is reduced, the writing time is shortened, the power consumption of the memory module is reduced, and the writing speed can be improved.
第2に、書込みデータに対するバウンダリフラグBD値0の総数を求め、このバウンダリフラグBD値0の総数が、チャネル間で均一になるように、書込みデータをチャネルへ割り当てることで、不揮発性メモリの最大書込み時間を短縮でき、メモリモジュールの書込み速度を向上できる。
Second, the total number of boundary flag BD values 0 for the write data is obtained, and by assigning the write data to the channels so that the total number of boundary flag BD values 0 is uniform among the channels, The writing time can be shortened and the writing speed of the memory module can be improved.
第3に、ビット反転処理を施した書込みデータに対して、バウンダリフラグBDを生成することにより、バウンダリフラグBD値0の数を大幅に削減でき、不揮発性メモリの書込み時間を短縮でき、メモリモジュールの書込み速度を向上できる。
Third, by generating the boundary flag BD for the write data that has undergone bit inversion processing, the number of boundary flag BD values 0 can be greatly reduced, the writing time of the nonvolatile memory can be shortened, and the memory module Can improve the writing speed.
以上、本発明者によってなされた発明を実施の形態に基づき具体的に説明したが、本発明は前記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。例えば、上記した実施の形態は、本発明を分かり易く説明するために詳細に説明したものであり、必ずしも説明した全ての構成を備えるものに限定されるものではない。また、ある実施の形態の構成の一部を他の実施の形態の構成に置き換えることが可能であり、また、ある実施の形態の構成に他の実施の形態の構成を加えることも可能である。また、各実施の形態の構成の一部について、他の構成の追加・削除・置換をすることが可能である。また、実施の形態においては、主に相変化メモリを代表として説明を行ったが、ReRAM等を含めた抵抗変化型のメモリであれば、同様に適用して同様の効果が得られる。
As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, the above-described embodiment has been described in detail for easy understanding of the present invention, and is not necessarily limited to one having all the configurations described. Further, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. . Further, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment. In the embodiments, the phase change memory has been mainly described as a representative, but a resistance change type memory including a ReRAM or the like can be similarly applied to obtain the same effect.
また、実施例において、複数のメモリセルが半導体基板に対して高さ方向に順に積層して配置される3次元構造のメモリを代表として説明を行ったが、半導体基板に対して高さ方向に1つのメモリセルが配置される2次元構造のメモリにおいても同様に適用して同様の効果が得られる。
In the embodiment, the description has been given by taking as an example a memory having a three-dimensional structure in which a plurality of memory cells are sequentially stacked in the height direction with respect to the semiconductor substrate. The same effect can be obtained by applying the same to a two-dimensional memory in which one memory cell is arranged.
種々のメモリを用いた記憶装置分野に利用可能である。
It can be used in the field of storage devices using various memories.
CPU_CP…上位装置、NMV-CTL…制御回路、MNGR…情報処理回路、NVM0~3…不揮発性メモリ装置、NVMD0…メモリモジュール、NVCT0~NVCT3…メモリ制御回路
CPU_CP: Host device, NMV-CTL ... Control circuit, MNGR ... Information processing circuit, NVM0-3 ... Nonvolatile memory device, NVMD0 ... Memory module, NVCT0-NVCT3 ... Memory control circuit
Claims (15)
- 情報処理回路を具備し、メモリを制御するメモリの制御装置であって、
前記情報処理回路は、前記メモリへの書込みデータをmビット毎に分けた各データ単位に対して、バウンダリフラグを設け、
前記バウンダリフラグは、前記書込みデータの中で、特定の値のビットの数が閾値を超えない最大値になるような、前記データ単位の連続する範囲を示す、
ことを特徴とするメモリの制御装置。 A memory control device that includes an information processing circuit and controls a memory,
The information processing circuit is provided with a boundary flag for each data unit obtained by dividing write data into the memory every m bits,
The boundary flag indicates a continuous range of the data unit such that the number of bits of a specific value in the write data is a maximum value not exceeding a threshold value.
A memory control device. - 請求項1に記載のメモリの制御装置において、
さらにメモリ制御回路を具備し、
前記情報処理回路は、
前記メモリ制御回路を介して、前記バウンダリフラグを有効にする書込み命令と、前記書込みデータと、前記バウンダリフラグとを発行する、
ことを特徴とするメモリの制御装置。 The memory control device according to claim 1,
Furthermore, it has a memory control circuit,
The information processing circuit includes:
Issuing a write command to enable the boundary flag, the write data, and the boundary flag through the memory control circuit,
A memory control device. - 請求項2に記載のメモリの制御装置において、
前記情報処理回路は、
前記書込みデータと、前記バウンダリフラグに対するエラーコレクションコードを生成し、前記メモリ制御回路を介して、前記バウンダリフラグを有効にする書込み命令と、前記バウンダリフラグと、前記書込みデータと、前記エラーコレクションコードと、を発行する、
ことを特徴とするメモリの制御装置。 The memory control device according to claim 2,
The information processing circuit includes:
The write data, an error correction code for the boundary flag is generated, and the write command for enabling the boundary flag via the memory control circuit, the boundary flag, the write data, and the error correction code, , Issue,
A memory control device. - 請求項1に記載のメモリの制御装置において、
前記情報処理回路は、
前記データ単位が、前記書込みデータの中で、前記特定の値のビットの数が前記閾値を超えない最大値になるような、前記データ単位の連続する範囲の境界のデータ単位であれば、前記バウンダリフラグの値を第1の値に設定し、
前記書込みデータの中で、前記特定の値のビットの数が前記閾値を超えない最大値になるような、前記データ単位の連続する範囲に含まれているデータ単位であれば、前記バウンダリフラグの値を第2の値に設定する、
ことを特徴とするメモリの制御装置。 The memory control device according to claim 1,
The information processing circuit includes:
If the data unit is a data unit at the boundary of a continuous range of the data units such that the number of bits of the specific value in the write data is a maximum value not exceeding the threshold, Set the value of the boundary flag to the first value,
In the write data, if the data unit is included in a continuous range of the data unit such that the number of bits of the specific value is the maximum value not exceeding the threshold, the boundary flag Set the value to the second value,
A memory control device. - 請求項4に記載のメモリの制御装置において、
前記情報処理回路は、前記バウンダリフラグの第1の値の数を計測する、
ことを特徴とするメモリの制御装置。 The memory control device according to claim 4,
The information processing circuit measures the number of first values of the boundary flag;
A memory control device. - 請求項1に記載のメモリの制御装置において
前記情報処理回路は、前記各データ単位に対し、必要に応じてビット反転し、前記書込みデータからビット反転データを生成し、ビット反転した場合は、ビット反転フラグを生成し、
前記データ単位または前記ビット反転したデータ単位に対して、バウンダリフラグを設け、
前記バウンダリフラグは、前記書込みデータの中で、特定の値のビットの数がmビットを超えない最大値になるような、前記データ単位または前記ビット反転したデータ単位の連続する範囲を示す、
ことを特徴とするメモリの制御装置。 2. The memory control device according to claim 1, wherein the information processing circuit performs bit inversion as necessary for each data unit, generates bit inversion data from the write data, Generate a reverse flag,
A boundary flag is provided for the data unit or the bit-inverted data unit,
The boundary flag indicates a continuous range of the data unit or the bit-inverted data unit such that the number of bits of a specific value is a maximum value not exceeding m bits in the write data.
A memory control device. - 請求項6に記載のメモリの制御装置において、
前記情報処理回路は、前記書込みデータと、前記バウンダリフラグと、前記ビット反転フラグに対するエラーコレクションコードを生成し、前記メモリ制御回路を介して、前記バウンダリフラグを有効にする書込み命令と、前記ビット反転フラグと、前記バウンダリフラグと、前記書込みデータと、前記エラーコレクションコードと、を発行する、
ことを特徴とするメモリの制御装置。 The memory control device according to claim 6.
The information processing circuit generates an error correction code for the write data, the boundary flag, and the bit inversion flag, and enables the boundary flag through the memory control circuit, and the bit inversion Issuing a flag, the boundary flag, the write data, and the error collection code;
A memory control device. - 請求項5に記載のメモリの制御装置において、
前記半導体装置は複数のチャネルを具備し、
前記情報処理回路は、
チャネル間にて前記書込みデータに対するバウンダリフラグの第1の値の数を平準化するように、前記書込みデータを前記複数のチャネルへ割り当て、該複数のチャネルから、前記書込みデータを発行する、
ことを特徴とするメモリの制御装置。 The memory control device according to claim 5,
The semiconductor device comprises a plurality of channels,
The information processing circuit includes:
Allocating the write data to the plurality of channels so as to equalize the number of first values of boundary flags for the write data between the channels, and issuing the write data from the plurality of channels;
A memory control device. - 請求項1に記載のメモリの制御装置において、
前記閾値はmビットであり、
前記情報処理回路は、前記mの値をプログラム可能である、
ことを特徴とするメモリの制御装置。 The memory control device according to claim 1,
The threshold is m bits;
The information processing circuit can program the value of m.
A memory control device. - 不揮発性メモリと、前記不揮発性メモリへ書込みを行う制御回路と、を有する記憶装置において、
前記制御回路は、
前記不揮発性メモリへの書込みデータをmビット毎に分けた、それぞれのデータ単位m1~mn(ただし、nは自然数)に対して、バウンダリフラグを設け、
前記バウンダリフラグは、前記書込みデータの中で、特定の値のビットの数が閾値を超えない最大値になる、前記データ単位の連続する範囲を示し、
前記データ単位の連続する範囲mx~my(ただし、n≧y≧x≧1)の中で、特定の値のビットの数が閾値を超えない場合には、
前記データ単位mxおよびmyの少なくとも一つに対する前記バウンダリフラグを第1の値とし、それ以外のデータ単位に対する前記バウンダリフラグを第2の値とする、
ことを特徴とする記憶装置。 In a storage device having a nonvolatile memory and a control circuit for writing to the nonvolatile memory,
The control circuit includes:
A boundary flag is provided for each of the data units m1 to mn (where n is a natural number), in which the write data to the nonvolatile memory is divided every m bits,
The boundary flag indicates a continuous range of the data unit in which the number of bits of a specific value is a maximum value not exceeding a threshold value in the write data,
If the number of bits of a specific value does not exceed the threshold value within the continuous range mx to my (where n ≧ y ≧ x ≧ 1) of the data unit,
The boundary flag for at least one of the data units mx and my is a first value, and the boundary flag for the other data units is a second value.
A storage device. - 請求項10に記載の記憶装置において、
前記制御回路は、
前記バウンダリフラグと、前記書込みデータとを、前記不揮発性メモリ内部のアドレスへ対応付け、
前記書込みデータを前記不揮発性メモリのメモリセルへ書込む、
ことを特徴とする記憶装置。 The storage device according to claim 10.
The control circuit includes:
Associating the boundary flag and the write data with an address in the nonvolatile memory;
Writing the write data into the memory cell of the nonvolatile memory;
A storage device. - 請求項11に記載の記憶装置において、
前記制御回路は、
前記データ単位myに対する前記バウンダリフラグを第1の値とし、
mビット毎に分けた前記不揮発性メモリ内部の連続したアドレスに対して、前記データ単位のバウンダリフラグを連続的に割り当て、前記バウンダリフラグ値が前記第1の値となるまでの連続した前記データ単位を、前記不揮発性メモリに一括で書込む、
ことを特徴とする記憶装置。 The storage device according to claim 11.
The control circuit includes:
The boundary flag for the data unit my is a first value,
Boundary flag of the data unit is continuously assigned to continuous addresses in the nonvolatile memory divided every m bits, and the continuous data unit until the boundary flag value becomes the first value. Are collectively written in the nonvolatile memory,
A storage device. - 請求項10に記載の記憶装置において、
前記不揮発性メモリに前記書込みデータを書込むための、複数のチャネルを具備し、
前記制御回路は、
前記書込みデータ中の前記バウンダリフラグの第1の値の数を計測し、
前記複数のチャネルに割り当てられる、前記書込みデータに対するバウンダリフラグの前記第1の値の数を平準化するように、前記書込みデータを前記複数のチャネルへ割り当て、
前記複数のチャネルから、前記書込みデータを、前記不揮発性メモリへ転送する、
ことを特徴とする記憶装置。 The storage device according to claim 10.
Comprising a plurality of channels for writing the write data to the nonvolatile memory;
The control circuit includes:
Measuring the number of first values of the boundary flag in the write data;
Allocating the write data to the plurality of channels to level the number of first values of boundary flags for the write data assigned to the plurality of channels;
Transferring the write data from the plurality of channels to the nonvolatile memory;
A storage device. - 請求項10に記載の記憶装置において、
前記閾値の値はmビットである、
ことを特徴とする記憶装置。 The storage device according to claim 10.
The threshold value is m bits;
A storage device. - 少なくとも2つの状態に遷移可能なメモリセルを複数備え、前記メモリセルの状態を遷移させることでデータを書込むメモリに対するデータの書込み方法であって、
前記データを前記メモリに書込む際に、前記入力されたデータをmビットのデータ単位に分け、前記データを書込むために前記メモリセルの状態を遷移させる必要のあるデータのビット数が、閾値以下の最大値をとる範囲の連続する前記データ単位を一括して書込む、
ことを特徴とするメモリの書込み方法。 A method of writing data to a memory, comprising a plurality of memory cells capable of transitioning to at least two states and writing data by transitioning the state of the memory cells,
When the data is written to the memory, the input data is divided into m-bit data units, and the number of data bits that need to change the state of the memory cell to write the data is a threshold value. Write the consecutive data units in a range that takes the following maximum values in a batch,
A method for writing to a memory.
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