WO2017017842A1

WO2017017842A1 - Memory control device, storage device, and memory write method

Info

Publication number: WO2017017842A1
Application number: PCT/JP2015/071667
Authority: WO
Inventors: 三浦　誓士; 洋内垣内
Original assignee: 株式会社日立製作所
Priority date: 2015-07-30
Filing date: 2015-07-30
Publication date: 2017-02-02

Abstract

Disclosed is a method of writing data to memory which comprises a plurality of memory cells which are capable of being made to transition into at least two states, said method writing data by causing the transition of the states of the memory cells. When writing the data to the memory, inputted data is divided into data units of m bits, and the data units which are contiguous in a range in which the number of bits of data for which the transition of the memory cell state is necessary to write the data takes a maximum which is less than or equal to a threshold is written in a single operation.

Description

Memory control device, storage device, and memory writing method

The present invention relates to a storage device, and more particularly to a storage device including a nonvolatile memory device.

Recently, a phase change memory using a chalcogenite material as a recording material has been actively studied as a nonvolatile memory device. A phase change memory is a type of resistance change memory that stores information by utilizing the fact that recording materials between electrodes have different resistance states.

In the phase change memory, information is stored by utilizing the fact that the resistance value of a phase change material such as Ge ₂ Sb ₂ Te ₅ is different between an amorphous state and a crystalline state. In the amorphous state, the resistance is high (high resistance state), and in the crystal state, the resistance is low (low resistance state). Therefore, reading of information from the phase change memory is realized by applying a potential difference to both ends of the element, measuring the current flowing through the element, and determining the high resistance state / low resistance state of the element.

In the phase change memory, the data is rewritten by changing the electric resistance of the phase change film formed of the phase change material to a different state by Joule heat generated by current.

FIG. 28 is a diagram showing the relationship between the pulse width and temperature necessary for the phase change of the resistive memory element using the phase change material. In the figure, the vertical axis represents temperature and the horizontal axis represents time. When the storage information “0” is written in the storage element, as shown in FIG. 28, a reset pulse is applied so that a large current is passed to heat the storage element to the melting point Ta or higher of the chalcogenide material and then rapidly cool. . In this case, by shortening the cooling time t1 (for example, by setting to about 1 ns), the chalcogenide material becomes a high resistance amorphous state. On the other hand, when the memory information “1” is written, the memory element is kept in a temperature range lower than the melting point Ta but higher than the crystallization temperature Tx (same or higher than the glass transition temperature). A set pulse is applied for a long time so that a sufficient current flows. Thereby, the chalcogenide material is in a low-resistance polycrystalline state.

Patent Document 1 discloses that in a resistance change type memory such as a phase change memory, M-byte data stored in a buffer is written in n-byte (M> n) units in a time-sharing manner. .

In Patent Document 2, in the writing method of the resistance change type memory such as ReRAM, when the number of bits of a specific value exceeds the reference value in the data to be written, the data is inverted and the data is transferred to the nonvolatile memory. It is shown that data is transferred and written to a resistance change type memory.

Further, in Patent Document 3, in the resistance change memory writing method, when the number of bit data of “1” is larger than the number of bit data of “0”, each bit of the write data is inverted and the data is inverted. It is shown that the data is transferred to the nonvolatile memory and written to the nonvolatile memory.

JP 2012-1119018 A JP 2013-239142 A JP 2013-80537 A

Prior to the present application, the present inventors examined a control method of the resistance change type memory. In general, the power consumption during writing to the resistance change memory increases as the number of bits to be rewritten increases. In other words, there is a limit to the number of bits that can be rewritten at one time due to the limitation on the maximum power consumption of the resistance change type memory. In the writing method to the resistance change type memory shown in

Patent Documents

2 and 3, when the number of bits of a specific value exceeds the reference value in the data to be written, the data is inverted, and the nonvolatile memory By writing to, the number of bits to be rewritten can be reduced, and the power consumption at the time of writing can be reduced.

However, it has been found that the write speed cannot be improved because the number of selections of the internal address of the resistance change type memory to be selected during the write operation, that is, the write count cannot be reduced.

The present invention has been made in view of the above problems. A first object of the present invention is to provide a semiconductor device that realizes high performance and low power.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.
One aspect of the present invention is a memory control device that includes an information processing circuit and controls a memory. This information processing circuit provides a boundary flag for each data unit obtained by dividing write data into the memory every m bits. The boundary flag indicates a continuous range of data units in which the number of bits having a specific value in the write data becomes a maximum value that does not exceed the threshold value.

Another aspect of the present invention is a storage device including a nonvolatile memory and a control circuit that performs writing to the nonvolatile memory. The control circuit provides a boundary flag for each of the data units m1 to mn (where n is a natural number) obtained by dividing write data to the nonvolatile memory for each m bits. The boundary flag indicates a continuous range of data units in which the number of bits having a specific value in the write data is a maximum value that does not exceed the threshold value. For at least one of the data units mx and my if the number of bits of a specific value does not exceed the threshold within the continuous range of data units mx to my (where n ≧ y ≧ x ≧ 1) The boundary flag is set to a first value, and the boundary flag for other data units is set to a second value.

Still another aspect of the present invention is a method for writing data to a memory that includes a plurality of memory cells that can transition to at least two states and writes data by transitioning the state of the memory cells. When writing data to the memory, the input data is divided into m-bit data units, and the number of data bits that need to change the state of the memory cell in order to write the data has a maximum value less than or equal to the threshold value. Write consecutive data units in a range.

Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

That is, a high-performance and low-power semiconductor device including a nonvolatile memory can be provided.

It is a block diagram which shows the example of schematic structure of the information processing system by one Example of this invention. FIG. 2 is a block diagram illustrating a configuration example of a control circuit NMV-CTL in FIG. 1. It is a flowchart which shows an example of the write-in operation | movement of the memory module of an Example. It is a flowchart which shows an example of the allocation method of the boundary flag BD with respect to the write data of an Example. It is a schematic diagram which shows an example of allocation of the boundary flag BD with respect to the write data of an Example. It is a table | surface figure which shows an example of the data stored in a buffer, and boundary flag BD. FIG. 3 is a block diagram showing a configuration example of nonvolatile memory devices NMV0 to 31 in FIG. FIG. 8 is a circuit diagram illustrating a configuration example of the chain memory array in FIG. 7. FIG. 9 is an explanatory diagram illustrating an operation example of the chain memory array of FIG. 8. FIG. 9 is an explanatory diagram illustrating another operation example of the chain memory array of FIG. 8. It is a schematic diagram which shows an example of the block configuration of the memory array of a non-volatile memory device. 3 is a flowchart illustrating an example of an operation of an address range determination circuit FADCTL in the nonvolatile memory device according to the embodiment. It is a schematic diagram which shows an example of allocation of the boundary flag BD with respect to the address in the non-volatile memory device of an Example. It is a flowchart which shows an example of the write-in operation | movement of the memory module of an Example. It is a flowchart which shows an example of operation | movement of Step31 of FIG. It is a table | surface figure which shows an example of the data stored in a buffer, and boundary flag BD. It is a schematic diagram which shows an example of the allocation method of the boundary flag BD with respect to the write data of an Example. It is a flowchart which shows an example of the write-in operation | movement of the memory module of an Example. It is a flowchart which shows an example of the data inversion process of an Example. It is a schematic diagram which shows an example of the allocation method of the boundary flag BD with respect to the write data of an Example. It is a table | surface figure which shows an example of the data stored in a buffer, and boundary flag BD. It is a conceptual diagram which shows an example of the shortening effect of the write time by an Example. It is a conceptual diagram which shows an example of the shortening effect of the write time by an Example. 3 is a flowchart of a data copy operation performed by an information processing circuit MNGR in FIG. 2 during a garbage collection operation according to an embodiment. 10 is a flowchart of an example of a read operation of the memory module NVMD0 when a read request from the host device CPU_CP is input to the memory module NVMD0. FIG. 10 is a table showing a list of NVM command functions that the information processing circuit MNGR controls the nonvolatile memory device NVM via the memory control circuits (NVCT0 to NVCT3). It is a table | surface figure which shows ON / OFF of the function of a NVM command which controls the non-volatile memory device NVM. It is a graph which shows the relationship between pulse width required for the phase change of a resistive memory element using a phase change material, and temperature.

In the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. Unless otherwise specified, they are not irrelevant to each other, and one is in the relationship of some or all of the other, modification, application, detailed explanation, supplementary explanation, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

Furthermore, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified or apparently indispensable in principle. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numbers and the like (including the number, numerical value, quantity, range, etc.).

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same or related reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

In the embodiment, the circuit elements constituting each block are not particularly limited, but are formed on a single semiconductor substrate such as single crystal silicon by a known integrated circuit technology such as a CMOS (complementary MOS transistor). In addition, as a memory cell described in the embodiment, a resistive memory element such as a phase change memory or a ReRAM (Resistive Random Access Memory) is used.

The semiconductor device of the present embodiment shown below includes a nonvolatile memory including a plurality of memory cells and a control circuit that accesses the nonvolatile memory. The control circuit generates the boundary flag BD for each m bits of the write data, and then transfers the write data and the boundary flag BD to the nonvolatile memory. The nonvolatile memory associates the internal address with the boundary flag BD, and simultaneously selects and writes a plurality of consecutive addresses included up to the upper limit of the number of “0” data bits that can be rewritten at one time.

Specifically, for example, in the erase state, all data bits are “1”, and data writing is performed by rewriting “1” to “0” data bits. This physically corresponds to, for example, changing the state of the memory cell by a thermal action caused by an electric current. The number of memory cells whose states can be changed at a time is limited by the amount of current that can be supplied by the circuit. However, if as many memory cells as possible can be rewritten to “0” within the limits, writing can be performed at high speed. It becomes. Ideally, the number of times of writing “0” data bits is reduced by recording up to the upper limit of the number of “0” data bits that can be rewritten at one time. Thereby, the writing time and the number of address selections can be reduced, the data transfer speed of the semiconductor device can be improved, and the power consumption can be reduced. The configuration will be specifically described below.

FIG. 1 is a block diagram showing a schematic configuration example of a memory module and an information processing system according to an embodiment of the present invention. The information processing system illustrated in FIG. 1 includes a host device (for example, a processor that is an information processing device) CPU_CP and a memory module NVMD0. The host device CPU_CP is a host controller that manages data stored in the memory module NVMD0 with a logical address LAD in units of 512 bytes, although not particularly limited. The host device CPU_CP reads / writes data from / to this memory module NVMD0 through the interface signal HDH_IF. The memory module NVMD0 is not particularly limited, but corresponds to, for example, SSD (Solid State Drive).

There are a serial interface signal system, a parallel interface signal system, an optical interface signal system, etc. as signal systems for connecting the host device CPU_CP and the memory module NVMD0, and all systems can be used. There are common clock methods, source synchronous clock methods, embedded clock methods that embed clock information in data signals, etc., and all clock methods can be used to operate the host device CPU_CP and memory module NVMD0. . In this embodiment, a serial interface signal system and an embedded clock system are used as an example, and the operation will be described below.

From the host device CPU_CP, a read request RQ, a write request, etc., embedded with clock information and converted into serial data, are input to the memory module NVMD0 through the interface signal HDH_IF. The read request RQ includes a logical address LAD, a data read command RD, a sector count SEC, and the like. The write request includes a logical address LAD, a data write command WRT, a sector count SEC, write data DATA, and the like.

The memory module NVMD0 includes memory devices M0, M1, and M2, nonvolatile memory devices NVM0 to NVM3, and a control circuit (controller) NVM-CTL that controls these memory devices.

Non-volatile memory devices NVM0 to NVM3 have, for example, the same configuration and performance. These memory devices NVM0 to NVM3 include NAND flash memory, NOR flash memory, phase change memory PCM, resistance change memory ReRAM, spin transfer magnetization reversal memory STT-MRAM, ferroelectric memory, etc. Either memory can be used.

Memory devices M0 and M1 are buffers BUF0 and BUF1 for temporarily storing data, and each has a write area WAREA and a copy area CAREA. The write area WAREA is an area for storing write data from the host, and the copy area CAREA is an area used for data movement between the nonvolatile memory devices NVM0 to NVM3 at the time of garbage collection or static wear leveling. In addition, the memory device M2 has a logic that performs correspondence between the logical address LAD from the host device CPU_CP managed by the control circuit NVM-CTL and the physical addresses PAD of the nonvolatile memory devices NVM0 to NVM3 in the memory module NVMD0. A physical address conversion table LPTBL, a physical logical address conversion table PLTBL, an erase count table ERSTBL for each block, and an address map ADMAP are stored.

The control circuit NVM-CTL selects the physical address PAD and writes data so that the number of erases for each block of the nonvolatile memory devices NVM0 to NVM3 is leveled. After the data writing is completed, the control circuit NVM-CTL updates the address conversion table LPTBL.

When the control circuit NVM-CTL reads data from the nonvolatile memory devices NVM0 to NVM3, the control circuit NVM-CTL refers to the address conversion table LPTBL, determines the physical address PAD for the logical address LAD, and determines the physical address. Read data stored in PAD.

The host device CPU_CP reads and executes data, OS, and application programs from the memory module NVMD0. The execution result is written into the memory module NVMD0 by the host device CPU_CP.

FIG. 2 is a block diagram of the control circuit NVM-CTL in FIG. The control circuit NVM-CTL includes an interface circuit NVM_IF, an address / command buffer ADCBUF, a map register MAPREG, an arbitration circuit ARB, an information processing circuit MNGR, and memory control circuits RAMC and NVCT0 to NVCT3.

The memory control circuit RAMC directly controls the memory devices M0 to M2 in FIG. 1, and the memory control circuits NVCT0 to NVCT3 directly control the nonvolatile memory devices NVM0 to NVM3 in FIG. The memory control circuits NVCT0 to NVCT3 include queue circuits WTQ0 to WTQ3 and RDQ0 to RDQ for writing and reading, respectively.

The address / command buffer ADCBUF temporarily stores the logical address LAD, the data read command RD, and the data write command WT input from the host device CPU_CP to the control circuit NVM-CTL.

In the map register MAPREG, an address map ADDMAP is stored, and correspondence between the X address, Y address and Z address in the nonvolatile memory devices NVM0 to NVM3 for each block size is shown.

In the physical address register Next 格納 PAD, the selected physical address PAD is stored so that the number of erases for each block of the nonvolatile memory devices NVM0 to NVM3 is equalized, and is used when data is written.

FIG. 3 shows an example of a write operation to the buffer BUF0 and the non-volatile memory devices NVM0 to NVM3 of the memory module NVMD0 of this embodiment in response to a write request WQ from the host device CPU_CP.

Writing is started when a write request WQ is input from the host device CPU_CP to the information processing circuit MNGR through the interface circuit NVM_IF of the control circuit NVM_CTL. The write request WQ includes a logical address LAD, a data write command WRT, a sector count SEC, write data DATA (for example, 8 KB = 8192 bits), and the like.

The information processing circuit MNGR that has received the write request WQ first checks whether the access from the host device CPU_CP is the write request WQ (Step 1). If the access is a write request WQ, Step 2 is performed. If it is not the write request WQ, it waits for access from the host device CPU_CP again. In Step 2, the information processing circuit MNGR checks the following conditions.

Condition: “The buffer BUF0 is a buffer to be written to the nonvolatile memory devices NVM0 to NVM3, and the buffer BUF0 has a free space for storing data” or “the buffer BUF1 is a nonvolatile memory device NVM0 to NVM3. BUF1 has no free space, and buffer BUF0 has free space to store data. ''
If this condition is satisfied, Step 3 is executed, and if not satisfied, Step 5 is executed.

In Step 3, the information processing circuit MNGR is configured to write the data m (i = 0, 1, 2, ..., M / m) for each m bits obtained by dividing the write data DATA (8 KB = 8192 bits) into m bits. M is a write data amount (bit), which is 8 KB in this embodiment), and associates a 1 or 0 value of the boundary flag BDi. Through a series of processes in Step 3, the i-th boundary flag BDi value is assigned to the i-th data mi obtained by dividing the write data DATA every m bits.

The detailed operation of Step 3 will be described with reference to FIG. First, at the start of execution of Step 3, i = 0 is set at START, and in the next Step 300, write data DATA (8 KB = 8192 bits) is divided into m bits, and “0” in i-th m-bit data mi “Calculate the number of bits (SUMi). The m bit is set to a value that does not exceed the number of bits of “0” data that can be written at once by the nonvolatile memory devices NVM0 to NVM3. In this embodiment, the nonvolatile memory devices NVM0 to NVM3 can write at a time “ The number of bits of 0 ”data was used.

In the next Step 301, the total number of “0” bits is calculated (SUM0). In the next Step 302, it is checked whether the total number SUM0 of “0” bits is smaller than a predetermined threshold s (here, s = m). If the total number SUM0 of “0” bits is smaller than m, Step 303 is executed, otherwise Step 304 is executed. In Step 303, the boundary flag BD is set to 1, and then Step 310 is executed.

In Step 304, after Step 303 is finished, it is checked whether the total number SUM0 of “0” bits is equal to m. If the total number SUM0 of “0” bits is equal to m, Step 303 is executed, otherwise Step 306 is executed. In Step 305, the boundary flag BD is set to 0, and then Step 309 is executed.

In Step 306, after confirming that the total number SUM0 of “0” bits is larger than m, BDi-1 is set to 0 in Step 307. After Step 307 is completed, a value obtained by subtracting 1 from the current i value in Step 308 is set as the i value, and Step 309 is executed. In Step 309, the total number SUM0 of “0” bits is set to zero. In Step 310, a value obtained by adding 1 to the current i value is set as an i value, and in subsequent Step 311, it is checked whether or not the i value is equal to or larger than a value obtained by dividing M (= 8 KB = 8192 bits) by m. If the i value is equal to or greater than the value obtained by dividing M by m, the series of processing ends, and otherwise, Step 300 is executed.

As shown in FIG. 4, the i-th boundary flag BD value is assigned to the i-th data mi divided into m bits in the write data DATA by a series of processes in Step 3.

For example, if the boundary flag BDi value of mi + 3 is 0 in mi to mi + 3 consecutive from the i-th data mi and 1 otherwise, m is included in the data of mi to mi + 3. It indicates that there is no “0” data bit exceeding the bit. Therefore, by writing the data from mi to mi + 3 to the addresses in the non-volatile memory devices NVM0 to NVM3, the “0” data bits included in the data from mi to mi + 3 can be written at once. Can do. That is, the number of BDi values of 0 is the number of times of writing “0” data bits. The smaller the number of BDi values of 0, the smaller the number of times of writing “0” data bits and the shorter the write time. be able to.

Also, the information processing circuit MNGR can program m values of m bits. The m value of m bits corresponds to the maximum number of data bits that can be written at one time in the nonvolatile memory devices NVM0 to NVM3, and the maximum number of data bits differs in various nonvolatile memory devices. There is a case. Therefore, the information processing circuit MNGR can change the m value in accordance with the nonvolatile memory device to be used, and can configure an appropriate memory module NVMD0. Note that the threshold values s and m are not necessarily the same, but if m is the maximum value of writable data bits as described above, m ≧ s is required, and s = m This is preferable from the viewpoint of writing speed.

FIG. 5 is a diagram showing the association of the boundary flag BDi with the write data DATA. FIG. 5 shows a state immediately after Step 3 of FIG. 3 described in detail in FIG. 4 is executed. The write data DATA (8KB = 8192 bits) is divided into m bits, and the boundary flag BDi is associated with each data mi (i = 0, 1, 2, ..., M / m) in m bits. Show. The write data DATA is divided into D0 [0] to D0 [7], each having 1024 bits of data. In the figure, white circles indicate “1” bits of write data DATA, and black circles indicate “0” bits.

D0 [0] is divided into data m0 to m255, and boundary flags BD0 to 255 are assigned to each. D0 [1] is divided into data m256 to m511, and boundary flags BD256 to 511 are assigned to the data m256 to m511, respectively. D0 [2] is divided into data m512 to m767, and boundary flags BD512 to 767 are assigned to the respective data. D0 [3] is divided into data m768 to m1023, and boundary flags BD768 to 1023 are assigned to the respective data. D0 [4] is divided into data m1024 to m1279, and boundary flags BD1024 to 1279 are assigned to the data m1024 to m1279, respectively. D0 [5] is divided into data m1280 to m1535, to which boundary flags BD1280 to 1535 are assigned, respectively. D0 [6] is divided into data m1536 to m1791, and boundary flags BD1536 to 1791 are assigned to the respective data. D0 [7] is divided into data m1792 to m2047, and boundary flags BD1792 to 2047 are assigned to them. Among these boundary flags BD0 to 2047, there are 1365 boundary flags BD having a zero value.

Referring back to FIG. After Step 3 ends, in Step 4, write data DATA and the boundary flag BDi value assigned to each data mi divided into m bits in write data DATA are written to buffer BUF0.

FIG. 6 is a table showing an example of the data stored in the buffer and the boundary flag BD. FIG. 6A1 shows the write data DATAD0 to D7 stored in the buffer BUF0 in Step 4 of FIG. 3 and the boundary flags D0_BD to D7_BD corresponding to these data. Each of the write data D0 to D7 has a size of 8192 bytes, and each of the boundary flags D0_BD to D7_BD has a size of 256 bytes.

BDV is a flag indicating whether the boundary flag is valid / invalid. For example, “0” indicates valid and “1” indicates invalid. Valid / invalid can be switched, for example, by selecting a write command PRG00 and PRG01 or PRG10 shown in FIG. 26, which will be described later, and giving an instruction from the information processing circuit MNGR via the memory control circuit NVCT. When BDV is valid, the boundary flag BD is written to the memory, and when it is invalid, the boundary flag BD is not written to the memory. If it is disabled, writing becomes faster and memory capacity can be saved. On the other hand, once enabled, the boundary flag BD once calculated can be reused for garbage collection or the like.

FIG. 6 (A2) shows allocation to the four channels CH0 to CH3 for writing each write data to the nonvolatile memory devices NVM0 to NVM3. Here, four channels are assigned to data in order (by rotation).

Returning to FIG. 3, in Step 5, the information processing circuit MNGR checks the following conditions.

Condition: “Buffer BUF0 is a buffer to be written to nonvolatile memory devices NVM0 to NVM3, and buffer BUF0 is filled with write data.”
If this condition is satisfied, Step 6 is executed, and if not satisfied, Step 1 is executed. Step 1 to Step 5 are repeated until the buffer BUF0 is filled with the write data.

In Step 6, the information processing circuit MNGR transfers the write data stored in the buffer BUF0 to the nonvolatile memory devices NVM0 to NVM3 and performs writing.

Specifically, in this write operation, the information processing circuit MNGR reads the physical address PAD stored in the physical address register Next PAD, and further corresponds to the write data DATA stored in the buffer BUF0. The boundary flag BD is read and transferred to the memory control circuits NVCT0 to NVCT3 through the arbitration circuit ARB together with the write command WRT.

The memory control circuit NVCT0 generates ECC related to the write data DATA and the boundary flag BD corresponding to the write data DATA, converts the physical address PAD into the row address and the column address of the nonvolatile memory device NVCT0, and program instruction PRG01 (or PRG10 ), The row address and the column address, the boundary flag BD, and the write data DATA and ECC are transferred to the nonvolatile memory device NVM0. This program instruction PRG01 is an instruction for the non-volatile memory device NVM0 to write to its own internal memory cell using the boundary flag BD. See FIG. 26 for a list of instructions. In FIG. 26, PRG01 that uses the boundary flag BD and the boundary flag BD itself writes to the memory cell and PRG10 that uses the boundary flag BD but does not write to the memory cell are supported. Therefore, it may be selected as appropriate.

When the nonvolatile memory device NVM0 receives the program instruction PRG01, the row address and the column address, the boundary flag BD, and the write data DATA and ECC, the address range determination circuit FADCTL in the nonvolatile memory device NVM0 generates a row address signal. Using the column address signal and the boundary flag BD, the boundary flag BD value is associated with the internal X address, Y address, and Z address necessary for writing the write data DATA.

Furthermore, the combination of the internal X address, Y address, and Z address corresponding to the boundary flag BD value 0, that is, all of the boundary addresses BADxyz are transferred to the control circuit CTLOG.

Through this series of processing in Step 6, the i-th boundary flag BDi value assigned to the i-th data mi divided into m bits in the write data DATA is changed to the write data DATA. Corresponding to the internal X address, Y address, and Z address necessary for writing.

For example, if the X address is x0, the Z address is z0, and the boundary flag BDi value of yi + 3 is 0 in the consecutive i-th Y addresses yi to yi + 3, 1 otherwise, Y This indicates that there is no “0” data bit exceeding m bits in the data of the addresses yi to yi + 3. Therefore, “0” data bits within the range of Y addresses yi to yi + 3 can be written at a time. That is, the number of BDi values of 0 is the number of times of writing “0” data bits. The smaller the number of BDi values of 0, the smaller the number of times of writing “0” data bits and the shorter the write time. be able to.

In the next Step 7, it is checked whether all the data in the buffer BUF0 has been written to the nonvolatile memory devices NVM0 to NVM0. If not, Step 6 is performed. When all the data in the buffer BUF0 is written to the nonvolatile memory devices NVM0 to NVM3, Step 8 is performed.

In Step 8, the information processing circuit MNGR updates the address conversion table LPTBL stored in the memory device M2 and the erase count table ERSTBL for each block. In the next Step 9, the buffer BUF1 is a buffer to be written to the nonvolatile memory devices NVM0 to NVM3.

The information processing circuit MNGR can perform a write operation to the buffer BUF1 when performing Step 6 to Step 9 in the buffer BUF0. Further, the information processing circuit MNGR erases a new physical address PAD for writing the data stored in the buffer BUF0 after Step 9 is completed to the physical address register NextPAD for each of the nonvolatile memory devices NVM0 to NVM3. Select and save so that the number of times is leveled.

In addition, the write operation to the buffer BUF1 and the write operation from the buffer BUF1 to the nonvolatile memory devices NVM0 to NVM3 are the same operation as the buffer BUF0. That is, BUF0 and BUF1 in FIG. 3 are switched and processed.

As described above, “0” data bits are written at once by associating the boundary flag BDi value with the internal X address, Y address, and Z address necessary for writing the write data DATA. Since the internal address range in which data can be written can be specified and written, the number of times of writing “0” data bits is reduced, and the writing time can be shortened. Furthermore, since the write operation from the buffer BUF0 to the nonvolatile memory devices NVM0 to NVM3, the write operation to the buffer BUF1, and the storage of a new physical address in the physical address register NextPAD can be performed simultaneously, the writing speed can be improved.

FIG. 7 is a block diagram showing a configuration example of the nonvolatile memory devices NMV0 to NMV31 in FIG. Here, as an example, a phase change nonvolatile memory (phase change memory) is used. The nonvolatile memory device includes a clock generation circuit SYMD, a status register STREG, an erase size designation register NVREG, an address / command interface circuit ADCMDIF, an IO buffer IOBUF, a control circuit CTLOG, a temperature sensor THMO, a data control circuit DATCTL, and memory banks BK0 to Equipped with BK3.

Each of the memory banks BK0 to BK3 includes a memory array ARYx (x = 0 to m), a read / write control block SWBx (x = 0 to m) provided corresponding to each memory array, and various peripheral circuits for controlling them. Is provided. Among these various peripheral circuits are row address latch RADLT, column address latch CADLT, row decoder ROWDEC, column decoder COLDEC, chain selection address latch CHLT, chain decoder CHDEC, data selection circuit DSW1, data buffers DBUF0 and DBUF1, address range A determination circuit FADCTL and a register SPREG are included.

Each memory array ARYx includes a plurality of chain memory arrays CY arranged at intersections of a plurality of word lines WL0 to WLk and a plurality of bit lines BL0_x to BLi_x, and a plurality of bit lines BL0_x to BLi_x (x = 0 to m). A bit line selection circuit BSWx that selects either one and connects to the data line DTx is provided. Each read / write control block SWBx has a sense amplifier SAx (x = 0 to m) and write driver WDRx (x = 0 to m) connected to the data line DTx (x = 0 to m), A write data verification circuit WVx (x = 0 to m) is used for verifying data. In addition, if the interface for operating the nonvolatile memory device shown in FIG. 7 employs a memory interface such as a NAND flash memory interface or a DRAM interface, the compatibility of the interface with the conventional system can be maintained, which is convenient. A good nonvolatile memory device can be provided.

Furthermore, the block size of the nonvolatile memory device shown in FIG. 7 is not physically fixed, and can be easily changed as a control management unit by the control circuit NVM-CTL. For this reason, the performance and reliability of the information processing system can be improved by analyzing the characteristics of access to the memory module NVMD of the host device CPU_CP and dynamically optimizing the block size of the nonvolatile memory device.

FIG. 8 is a circuit diagram showing a configuration example of the chain memory array in FIG. As shown in FIG. 8, each chain memory array CY has a configuration in which a plurality of phase change memory cells CL0 to CLn are connected in series. One end of the memory cell CL is connected to the word line WL via the chain selection transistor Tch2, and the other end is connected to the bit line BL via the chain selection transistors Tch0 and Tch1. Although not shown, the plurality of phase change memory cells CL0 to CLn are sequentially stacked in the height direction with respect to the semiconductor substrate and connected in series to each other. Each phase change memory cell CL includes a variable resistance storage element R and a memory cell selection transistor Tc1 connected in parallel thereto. The memory element R is made of, for example, a chalcogenide material.

In the example of FIG. 8, two chain memory arrays CY share the chain selection transistor Tch2, and the chain selection transistors Tch0, 1, 2 in each chain memory array CY are connected by the chain memory array selection lines SL0, SL1, SL2. Are controlled, and thereby one of the chain memory arrays is selected. The memory cell selection lines LY0 to LYn are connected to the gate electrodes of the corresponding phase change memory cells. The memory cell selection lines LY control the memory cell selection transistors Tc1 in the phase change memory cells CL0 to CLn, Thus, each phase change memory cell is appropriately selected. The chain memory array selection lines SL0, SL1, SL2 and the memory cell selection lines LY0 to LYn are appropriately driven as the chain control line CH via the chain selection address latch CHLT and the chain decoder CHDEC in FIG.

Returning to FIG. 7, the operation of the nonvolatile memory device will be described. First, the control circuit CTLOG receives a control signal CTL via the address / command interface circuit ADCMDIF. The control signal CTL is not particularly limited. For example, the command latch enable signal (CLE), the chip enable signal (CEB), the address latch signal (ALE), the write enable signal (WEB), the read enable signal (REB), A ready busy signal (RBB) is included.

In the read operation, a read command, a row address signal, and a column address signal input in synchronization with the clock signal CLK from the input / output signal IO are taken in by a combination of these control signals CTL.

The control circuit CTLOG appropriately generates internal X address, Y address and Z address, and transmits them to the row address latch RADLT, the column address latch CADLT and the chain selection address latch CHLT, respectively.

The row decoder ROWDEC receives the output of the row address latch RADLT and selects the word lines WL0 to WLk, and the column decoder COLDEC receives the output of the column address latch CADLT and receives the bit lines BL0_x to BLi_x (x = 0 to m). Make a selection. The chain decoder CHDEC receives the output of the chain selection address latch CHLT and selects the chain control line CH. When a read command is input, data is read from the chain memory array CY selected by the combination of the word line, the bit line, and the chain control line, via the bit line selection circuits BSW0 to BSWm. The read data is amplified by the sense amplifiers SA0 to SAm and transmitted to the data buffer DBUF0 (or DBUF1) via the data selection circuit DSW1. Data on the data buffer DBUF0 (or DBUF1) is sequentially transmitted to the input / output signal IO via the data control circuit DATCTL and the IO buffer IOBUF.

In the write operation, a write command, a row address signal, a column address signal, a boundary flag BD, and write data DATA, which are input in synchronization with the clock signal CLK from the input / output signal IO, are captured by a combination of these control signals CTL.

When a write command is input, the address range determination circuit FADCTL uses the row address signal, the column address signal, and the boundary flag BD, and uses the internal X address, Y address, and Z necessary for writing the write data DATA. Associate a boundary flag BD value with the address. Further, the combination of the internal X address, Y address, and Z address corresponding to the boundary flag BD value 0, that is, all of the boundary addresses BADxyz are transferred to the control circuit CTLOG. This indicates a continuous address range in which 0 data of m bits or less can be written at a time.

The control circuit CTLOG transmits the X address, Y address, and Z address of the boundary address BADxyz to the row address latch RADLT, the column address latch CADLT, and the chain selection address latch CHLT, respectively.

The row decoder ROWDEC receives the output of the row address latch RADLT and selects the word lines WL0 to WLk, and the column decoder COLDEC receives the output of the column address latch CADLT and receives the bit lines BL0_x to BLi_x (x = 0 to m). Make a selection. The chain decoder CHDEC receives the output of the chain selection address latch CHLT and selects the chain control line CH.

When a write command is input, a data signal is transmitted to the input / output signal IO following the address signal described above, and the data signal is input to the data buffer DBUF0 (or DBUF1) via the data control circuit DATCTL. The The data signal on the data buffer DBUF0 (or DBUF1) is selected by the combination of the word lines, bit lines, and chain control lines described above via the data selection circuit DSW1, write drivers WDR0 to WDRm, and bit line selection circuits BSW0 to BSWm. Is written in the chain memory array CY. At this time, the write data verification circuits WV0 to WVm verify whether or not the write level has reached a sufficient level while appropriately reading the written data through the sense amplifiers SA0 to SAm. The write operation is performed again using the write drivers WDR0 to WDRm until it reaches.

As described above, the smaller the number of boundary flag BD values is, the smaller the number of selections of the X address, Y address, and Z address is. Therefore, the number of data writes is reduced, and the program time can be shortened.

FIG. 9 is an explanatory diagram showing an operation example of the chain memory array of FIG. With reference to FIG. 9, the operation when the variable resistance memory element R0 in the phase change memory cell CL0 in the chain memory array CY1 is set to high resistance or low resistance will be described as an example. Only the chain memory array selection line SL1 is activated (SL0 = Low, SL1 = High, SL2 = High) by the chain decoder CHDEC in FIG. 7, and the chain selection transistors Tch1 and Tch2 are turned on. Subsequently, only the memory cell selection line LY0 is deactivated (LY0 = Low, LY1 to LYn = High), the memory cell selection transistor Tcl0 of the phase change memory cell CL0 is cut off, and the remaining memory cells CL1 to CLn The memory cell selection transistors Tcl1 to Tcln are turned on.

Next, when the word line WL0 becomes High and then the bit line BL0 becomes Low, the current I0 is changed from the word line WL0 to the chain selection transistor Tch2, the variable resistance storage element R0, the memory cell selection transistors Tcl1 to Tcln, and the chain selection. It flows to the bit line BL0 via the transistor Tch1. By controlling the current I0 in the form of the Reset current pulse shown in FIG. 28, the variable resistance memory element R0 has a high resistance. Further, the current I0 is controlled in the form of the Set current pulse shown in FIG. 28, so that the variable resistance memory element R0 has a low resistance. Data “1” and “0” are distinguished by the difference in resistance values of the variable resistance memory elements R0 to Rn.

Further, as shown in FIG. 7, the writing speed can be improved by passing the current I0 to the plurality of bit lines BL0_0 to BL0_m.

Although not particularly limited, data “1” is recorded when the variable resistance memory element becomes low resistance, and data “0” is recorded when it becomes high resistance.

In addition, when reading the data recorded in the variable resistance memory element R0, a current is applied through the same path as the data writing so that the resistance value of the variable resistance memory element R0 does not change. In this case, a voltage value corresponding to the resistance value of the variable resistance memory element R0 is detected by a sense amplifier (SA0 in FIG. 7 in this example), and data “0” and “1” are determined.

In addition, as shown in FIG. 7, a current is applied through a path similar to that for data writing to the extent that the resistance value of the variable resistance memory element R0 does not change through the plurality of bit lines BL0_0 to BL0_m. In this example, data “0” and “1” are determined in SA0 to SAm in FIG. 7, and the reading speed can be improved.

FIG. 10 is an explanatory diagram showing another example of the operation of the chain memory array of FIG. The operation when all the variable resistance memory elements R0 to Rn in the one-chain memory array CY1 are collectively reduced in resistance will be described with reference to FIG. Only the chain memory array selection line SL1 is activated (SL0 = Low, SL1 = High, SL2 = High) by the chain decoder CHDEC in FIG. 7, and the chain selection transistors Tch1 and Tch2 are turned on. Subsequently, the memory cell selection lines LY0 to LYn are activated (LY0 to LYn = High), and the memory cell selection transistors Tcl0 to Tcln of the memory cells CL0 to CLn are turned on. Next, when the word line WL0 becomes High and then the bit line BL0 becomes Low, the current I2 is changed from the word line WL0 through the chain selection transistor Tch2, the memory cell selection transistors Tcl0 to Tcln, and the chain selection transistor Tch1. Flow to line BL0. Joule heat due to the current I2 is conducted to the variable resistance memory elements R0 to Rn, and the variable resistance memory elements R0 to Rn collectively have a low resistance. This current I2 is controlled to a value that allows the variable resistance memory elements R0 to Rn to be collectively reduced in resistance.

As described above, if necessary, the memory cells in the plurality of chain memory arrays can be made low resistance at the same time, and the erase data rate can be improved.

Referring to FIG. 11, the block configuration of the memory array ARY of the nonvolatile memory device will be described. FIG. 11A shows an example of a block configuration of the memory array of the nonvolatile memory device NMV constructed by the control circuit NVM-CTL using the address map ADMAP information, and an example of the block configuration when the block size is 64 KB. It is.

One block is composed of a chain memory array of 8 (X direction: X0 to 7) × (32 × 288) (Y direction: Y0 to 287) × 8 (Z direction: Z0 to 7), and its size is It is 73728 bytes (= 8 (X direction) × (32 × 288) (Y direction) × 8 (Z direction)). A large number of these blocks are arranged to constitute a memory array of the nonvolatile memory shown in FIG. The display method of the chain memory array CY is the same as that in FIG.

The size of the data area DATA-AREA is 65536 bytes (= 8 (X direction) × (32 × 256) (Y direction) × 8 (Z direction)), and the size of the management area MG-AREA is 8192 bytes (= 8 ( X direction) × (32 × 32) (Y direction) × 8 (Z direction)).

In the data area DATA-AREA and the management area MG-ARE, data DATA and redundant data Rdata shown in FIG. 11B are stored, respectively.

FIG. 11B shows an example of the configuration of data PDATA written from the control circuit NVM-CTL to the nonvolatile memory devices NVM0 to NVM31. Data PDATA is composed of data DATA (8192 bytes) and redundant data Rdata (1024 bytes). The redundant data Rdata includes a data inversion flag IVF, a boundary flag BDF, ECC codes ECC1 and ECC2, a spare area RSV, and the like. This format is supported by the command PRG01 in FIG.

The data inversion flag IVF indicates whether the data DATA written by the control circuit NVM-CTL to the non-volatile memory device (NVM10 to NVM17) is data obtained by inverting each bit of the original write data. When 1 is written to the data inversion flag IVF, it indicates that the data has been written without inverting each bit of the original data. When 0 is written, each bit of the original main data is inverted. Indicates that the data has been written. An example using the data inversion flag will be described in detail in the third embodiment.

The boundary flag BD is flag information generated in Step 3 of FIG. 3 by the control circuit NVM-CTL, and each m-bit data mi (i = 0,1) obtained by dividing the write data DATA into m bits. , 2, ..., M / m).

The ECC code ECC1 is data necessary for detecting and correcting the error of the data DATA and the data inversion flag IVF, and the ECC code ECC2 is data necessary for detecting and correcting the error of the boundary flag BDF. These ECC codes are generated by the control circuit NVM-CTL when the control circuit NVM-CTL writes the data DATA to the non-volatile memory device (NVM0 to NVM3). Bad block information BADBLK indicates whether data DATA written to a nonvolatile memory device (NVM0 to NVM3) is available.

Although not particularly limited, when 1 is written to the bad block information BADBLK, the data DATA is usable, and when 0 is written, the data DATA is not usable. The bad block information BADBLK is 1 when error correction by ECC is possible, and the bad block information BADBLK is 0 when error correction is impossible. The spare area RSV exists as an area where the control circuit NVM-CTL can be freely defined.

FIG. 11C shows another example of the configuration of data PDATA written from the control circuit NVM-CTL to the nonvolatile memory devices NVM0 to NVM31. A difference from FIG. 11B is that the redundant data Rdata does not include the boundary flag BDF and the ECC code ECC2. This format is supported by the command PRG10 of FIG.

That is, in this data PDATA configuration, the data DATA, the data inversion flag IVF, the boundary flag BDF, and the ECC code ECC1 are transferred from the control circuit NVM-CTL to the nonvolatile memory devices NVM0 to NVM31. Since the boundary flag BDF and the ECC code ECC2 are not written in the devices NVM0 to NVM31, the capacity of the nonvolatile memory device NVM can be effectively increased.

FIG. 12 shows the operation of the address range determination circuit FADCTL in the nonvolatile memory device NVM0 in Step 6 of FIG.

In Step 601, when the nonvolatile memory device NVM0 receives the program instruction PRG01 (or PRG10), the row address and column address, the boundary flag BD, and the write data DATA, in Step 602, the nonvolatile memory device NVM0 The address range determination circuit FADCTL uses the row address signal, the column address signal, and the boundary flags BD0 to 2047, and each of the boundary flags BD0 to 2047, the internal X address necessary for writing the write data DATA, and Y Associate the address with the Z address.

In Step 603, the combination of the internal X address, Y address and Z address corresponding to the boundary flag BD value 0, that is, all of the boundary addresses BADxyz are transferred to the control circuit CTLOG. The control circuit CTLOG writes to the memory array while associating the boundary address BADxyz with m0 to m2047 in the write data DATA.

FIG. 13 shows the correspondence between the boundary flags BD0 to 2047 and the internal X address, Y address, and Z address immediately after executing Step 602 in FIG. The correspondence between the internal X address and Y address and the boundary flags BD0 to 2047 when the write data DATA is written to the internal Z address Z0 is shown.

Boundary flags BD0-255 and data m0-255 are assigned to Y addresses Y0-Y255 in X address X0. Boundary flags BD256 to 511 and data m256 to 511 are assigned to Y addresses Y0 to Y255 in X address X1, respectively. Boundary flags BD512 to 767 and data m512 to 767 are assigned to Y addresses Y0 to Y255 in X address X2. Boundary flags BD768 to 1023 and data m768 to 1023 are assigned to Y addresses Y0 to Y255 in X address X3, respectively. Boundary flags BD1024 to 1279 and data m1024 to 1279 are assigned to Y addresses Y0 to Y255 in X address X4, respectively. Boundary flags BD1280 to 1535 and data m1280 to 1535 are assigned to Y addresses Y0 to Y255 in X address X5. Boundary flags BD1536 to 1791 and data m1536 to 1791 are assigned to Y addresses Y0 to Y255 in X address X6, respectively. Boundary flags BD1792 to 2047 and data m1792 to 2047 are assigned to Y addresses Y0 to Y255 in X address X7, respectively. Among these boundary flags BD0 to 2047, there are 1365 boundary flags BD having a zero value.

When the Z address is Z0 and the X address is X0, the value of the boundary flag BD2 of the Y address Y2 is 1, and the value of the boundary flag BD3 of the Y address Y3 is 0. Therefore, the data to be written to the Y addresses Y2 to Y3 In m2 to m3, there is no “0” data bit exceeding 32 bits. Therefore, data m2 to m3 within the range of Y addresses Y2 to Y3 can be written at a time. In this way, for example, by writing collectively “0” data bits in a range not exceeding 32 bits, the energy for changing the state of the memory cell is suppressed to a predetermined level or less, and depending on the power supply and circuit scale of the device. Data can be written at high speed within a limited range of write capability (for example, the maximum value of the write current). For specific writing, the memory cell structure described with reference to FIGS. 7 to 10 can be used.

For example, if the number of BDi values of 0 is 1365, the number of times “0” data bits are written is 1365 times. When the present embodiment is not used, the number of times of writing is 2048, so that the number of times of writing can be reduced by 683 times according to the present embodiment. The smaller the number of 0 of the boundary flag BD value, the smaller the number of times of writing “0” data bits, and the write time can be shortened. In this embodiment, the boundary flag is added to the data unit at the end of the continuous m-bit data unit in which the included “0” data bits do not exceed 32 bits. The first data unit may be used. In addition, the boundary flag BD value of 0 may be arbitrarily set to other values such as 1.

In the second embodiment, an example will be described in which the number of boundary flags is counted and equally allocated to the channels to the nonvolatile memory devices NVM0 to NVM3.

FIG. 14 shows another example of the write operation to the buffer BUF0 of the memory module NVMD0 and the nonvolatile memory devices NVM0 to NVM3 in response to the write request WQ from the host device CPU_CP in FIG. The system configuration is the same as that shown in FIGS.

In the operation of FIG. 14, only Step 3 and Step 6 of the operation described in FIG. 3 are changed to the operations of Step 31 and Step 61, and the other operations are the same as those in FIG.

Step 31 will be explained. In Step 31, the boundary flag is set for each mi data (i = 0, 1, 2, ..., M / m) divided into m bits in the write data DATA (8KB = 8192 bits)

Associate

1 or 0 value of BDi. Further, the total number SUMF0 of 0 values of the boundary flag BDi is obtained.

FIG. 15 shows the detailed operation of Step31. First, at the start of execution of Step 31, i = 0, SUM0 = 0, SUMF = 0, and in the next Step330, write data DATA (8KB = 8192 bits) is divided into m bits and the i-th m The number of “0” bits in the bit data mi is calculated (SUMi). The m bits represent the number of bits of “0” data that can be written at once by the nonvolatile memory devices NVM0 to NVM3.

In the next Step 331, the total number of “0” bits is calculated (SUM0). In the next Step 332, it is checked whether the total number SUM0 of “0” bits is smaller than m. If the total number SUM0 of “0” bits is smaller than m, Step 333 is executed, otherwise Step 334 is executed. In Step 333, the boundary flag BDFi is set to 1, and then Step 342 is executed.

In Step 334, after Step 333 is completed, it is checked whether the total number SUM0 of “0” bits is equal to m. If the total number SUM0 of “0” bits is equal to m, Step 333 is executed, otherwise Step 337 is executed. In step 335, the boundary flag BDFi is set to 0. After that, in step 336, the number of the boundary flag BDFi value 0 is increased by 1, so 1 is added to the total number SUMF0 of the boundary flag BDFi value 0. Thereafter, Step 341 is executed.

In Step 337, after confirming that the total number SUM0 of “0” bits is larger than m, BDFi-1 is set to 0 in Step 338. Thereafter, in Step 339, since the number of boundary flag BDFi values 0 is increased by 1, 1 is added to the total number SUMF0 of boundary flag BDFi values 0. Thereafter, in Step 340, a value obtained by subtracting 1 from the current i value is set as the i value, and then Step 341 is executed.

In Step 341, the total number SUM0 of “0” bits is set to 0. In Step 342, a value obtained by adding 1 to the current i value is set as the i value, and in subsequent Step 343, it is checked whether or not the i value is equal to or larger than a value obtained by dividing M (= 8 KB = 8192 bits) by m. If the i value is equal to or greater than the value obtained by dividing M (= 8 KB = 8192 bits) by m, the series of processing ends (END), otherwise, Step 330 is executed.

The boundary flag BDFi value and the total number SUMF0 of the boundary flag BDFi value 0 are written to the buffer BUF0 in the next Step 4.

Through this series of processing in Step 31, the write data DATA (8KB = 8192 bits) is divided into m bits for the i-th data mi,
Each i-th boundary flag BDFi value is assigned (i = 0, 1, 2,..., M / m). As in the first embodiment, by using the boundary flag BDFi, it is possible to know a continuous data range that does not include “0” data bits exceeding m bits. By writing data bits in this data range at a time, the number of times of writing can be reduced and the writing time can be shortened.

Referring back to FIG. After Step31 is completed, in Step4, write data DATA and the boundary flag BDi value assigned to each data mi divided into m bits in the write data DATA, and 0 value of the boundary flag BDi Total number SUMF0 is written to buffer BUF0.

FIG. 16 is a table showing an example of the data stored in the buffer and the boundary flag BD. In FIG. 16C1, after Step 31 of FIG. 14 is completed, the write data DATA D0 to D7 stored in the buffer BUF0 or the buffer BUF1 in Step 4 and the boundary flags D0_BD to D7_BD corresponding to these data and the boundary flag are displayed. Valid / invalid flags D0_BDV to D7_BDV (all valid in this example) and the total number BDSUM0 of 0 values in the boundary flags D0_BD to D7_BD. Compared to the example of FIG. 6, information BDSUM0 of the total number of 0 values is added.

Referring back to FIG. 14, Step 61 will be described. In Step 61, first, in order to shorten the maximum write time of the data D0 to D7 in the buffer BUF0 to the nonvolatile memory devices NVM0 to NVM3, the data D0 to D7 are set so that the total number BDSUM0 of each becomes as uniform as possible. Is assigned (channel assignment for shortening the write time), and then these data D0 to D7 are written to the nonvolatile memory devices NVM0 to NVM3 (writing to NVM).

First, write time reduction channel assignment will be described. The information processing circuit MNGR has the total number BDSUM0 (1300, 1600, 950, 800, 1050, 1200, 700, 500) of the zero values of the boundary flags D0_BD to D7_BD corresponding to the write data DATA D0 to D7 stored in the buffer BUF0. ).

Next, with these total number BDSUM0, rank from 1 to 8 in descending order. Furthermore, in these ranks, write data D1 and D7 corresponding to

ranks

1 and 8 are assigned to channel CH0, write data D0 and D6 corresponding to

ranks

2 and 7 are assigned to channel CH1, and writes corresponding to

ranks

3 and 6 are assigned. Data D5 and D3 are assigned to channel CH2, and write data D4 and D2 corresponding to

ranks

4 and 5 are assigned to channel CH3. FIG. 16C2 shows the correspondence between the rank BDRank corresponding to the write data D1 to D7 and the assigned channel CH.

Next, writing to NVM in Step 61 of FIG. 14 will be described with reference to FIG. 1 and FIG. 16 (C2). The information processing circuit MNGR reads the write data D1 and the boundary flag D1_BD, the data D7 and the boundary flag D7_BD assigned to the channel CH0 stored in the buffer BUF0, and the physical address PAD0 of the nonvolatile memory device NVM0 from the physical address register NextPAD , PAD1 is read and transferred to the memory control circuit NVCT0.

Next, write data D0 and boundary flag D0_BD, data D6 and boundary flag D6_BD assigned to channel CH1 are read, physical addresses PAD2 and PAD3 of nonvolatile memory device NVM1 are read from physical address register NextPAD, and memory control circuit NVCT1 Forward to.

Next, write data D5 and boundary flag D5_BD, data D3 and boundary flag D3_BD assigned to channel CH2 are read, physical addresses PAD4 and PAD5 of nonvolatile memory device NVM2 are read from physical address register NextPAD, and memory control circuit NVCT2 Forward to.

Next, write data D4 and boundary flag D4_BD, data D2 and boundary flag D2_BD assigned to channel CH3 are read, physical addresses PAD6 and PAD7 of nonvolatile memory device NVM3 are read from physical address register NextPAD, and memory control circuit NVCT3 Forward to.

The memory control circuit NVCT0 generates an error correction code ECC1 related to the write data D1 and the boundary flag D1_BD, converts the physical address PAD0 into the row address 1 and the column address 1 of the nonvolatile memory device NVM0, and generates the program instruction PRG01 and the row address. 1 and column address 1, boundary flag D1_BD, write data D1 and ECC1 are transferred to nonvolatile memory device NVM0.

Next, the memory control circuit NVCT0 generates an error correction code ECC7 related to the data D7 and the boundary flag D7_BD, converts the physical address PAD1 into the row address 7 and the column address 7 of the nonvolatile memory device NVM0, and generates a program instruction PRG01 and a row Address 7, column address 7, boundary flag D7_BD, and write data D7 and ECC7 are transferred to nonvolatile memory device NVM0.

The memory control circuit NVCT1 generates an error correction code ECC0 related to the write data D0 boundary flag D0_BD, converts the physical address PAD2 into the row address 0 and the column address 0 of the nonvolatile memory device NVM1, and generates the program instruction PRG01 and the row address 0. The column address 0, the boundary flag D0_BD, the write data D0, and ECC0 are transferred to the nonvolatile memory device NVM1.

Next, the memory control circuit NVCT0 generates an error correction code ECC6 related to the data D6 and the boundary flag D6_BD, converts the physical address PAD3 into the row address 6 and the column address 6 of the nonvolatile memory device NVM1, and sets the program instruction PRG01 and the row Address 6, column address 6, boundary flag D7_BD, and write data D6 and ECC6 are transferred to nonvolatile memory device NVM1.

The memory control circuit NVCT2 generates an error correction code ECC5 related to the write data D5 boundary flag D5_BD, converts the physical address PAD4 into the row address 5 and the column address 5 of the nonvolatile memory device NVM2, and generates the program instruction PRG01 and the row address 5 The column address 5, the boundary flag D5_BD, the write data D5 and ECC5 are transferred to the nonvolatile memory device NVM2.

Next, the memory control circuit NVCT2 generates an error correction code ECC3 related to the data D3 and the boundary flag D3_BD, converts the physical address PAD5 into the row address 3 and the column address 3 of the nonvolatile memory device NVM2, and sets the program instruction PRG01 and the row Address 3 and column address 3, boundary flag D3_BD, and write data D3 and ECC3 are transferred to nonvolatile memory device NVM2.

The memory control circuit NVCT3 generates an error correction code ECC4 related to the write data D4 boundary flag D4_BD, converts the physical address PAD6 into the row address 4 and the column address 4 of the nonvolatile memory device NVM3, and generates the program instruction PRG01 and the row address 4 The column address 4, the boundary flag D4_BD, the write data D4, and ECC4 are transferred to the nonvolatile memory device NVM3.

Next, the memory control circuit NVCT3 generates an error correction code ECC2 related to the data D2 and the boundary flag D2_BD, converts the physical address PAD7 into the row address 7 and the column address 7 of the nonvolatile memory device NVM3, the program instruction PRG01, and the row Address 7 and column address 7, boundary flag D2_BD, and write data D2 and ECC2 are transferred to nonvolatile memory device NVM3. The subsequent operations of the non-volatile memory devices NVM0 to NVM3 in Step 61 are the same as in Step 6 of FIG. 3. FIG. 17 shows that the address range determination circuit FADCTL in the non-volatile memory device NVM0 is in Step 61 of FIG. The correspondence between the boundary flags BD0 to 2047 by the processing performed and the internal X address, Y address, and Z address is shown. The correspondence between the internal X address and Y address and the boundary flags BD0 to 2047 when the internal Z address writes the write data DATA to Z0 is shown. The correspondence method between the internal X address and Y address and the boundary flags BD0 to 2047 is the same as in FIG. Further, among the boundary flags BD0 to 2047, the number of boundary flags BD having a zero value is reduced to 688 = 86 × 8.

When the Z address is Z0 and the X address is X0, the value of the boundary flag BD0 of the Y address Y0 is 1, the value of the boundary flag BD1 of the Y address Y1 is 1, and the value of the boundary flag BD2 of the Y address Y2 is 0 This indicates that there is no “0” data bit exceeding 32 bits in the data m0 to m2 to be written to the Y addresses Y0 to Y2. Therefore, data m0 to m2 within the range of Y addresses Y0 to Y2 can be written to the memory cells at a time. As described above, by collectively writing “0” data bits in a range not exceeding 32 bits, the energy for changing the state of the memory cell is suppressed to a predetermined level or less, and is restricted by the power supply of the device and the circuit scale. It is possible to write at high speed within the range of writing ability.

FIG. 16B2 shows a state in which channels are assigned in order to the data D0 to D7 without performing write time reduction channel assignment, and FIG. 16B3 shows the total number SUM_BDC for each channel at that time. Indicates.

Write data D0 and D4 are assigned to channel CH0, write data D1 and D5 are assigned to channel CH1, write data D2 and D6 are assigned to channel CH2, and write data D3 and D7 are assigned to channel CH3. At this time, the total number SUM_BDC of the channel CH0 is 2350, the total number SUM_BDC of the channel CH1 is 2800, the total number SUM_BDC of the channel CH2 is 1650, and the total number SUM_BDC of the channel CH3 is 1300. 2800 which is the total number SUM_BDC of the channel CH1 is the maximum number of times of writing to the nonvolatile memory device NVM, and this is the maximum write time.

On the other hand, FIG. 16 (C2) shows the channel assignment for the data D0 to D7 when the write time reduction channel assignment is performed, and FIG. 16 (C3) shows the total number SUM_BDC for each channel at that time.

At this time, the total number SUM_BDC of the channel CH0 is 2100, the total number SUM_BDC of the channel CH1 is 2000, the total number SUM_BDC of the channel CH2 is 2000, and the total number SUM_BDC of the channel CH3 is 2000.

When the write time reduction channel assignment is performed, the maximum value of the total number SUM_BDC is 2100, which is about 700 lower than the case where the write time reduction channel assignment is not performed.

In this way, the maximum number of writes to the nonvolatile memory device NVM, that is, the maximum write time can be shortened by reducing the maximum value of the total number SUM_BDC by channel assignment for write time reduction. As a result, the update timing of the address conversion table LPTBL and the erase count table ERSTBL for each block can be advanced, so that high-speed writing is possible.

A third embodiment in which data bit inversion processing is performed will be described with reference to FIGS.

FIG. 18 shows another example of the write operation to the buffer BUF0 of the memory module NVMD0 and the nonvolatile memory devices NVM0 to NVM3 in response to the write request WQ from the host device CPU_CP in FIG. In the operation of FIG. 18, only Step 31 of the operation described in FIG. 14 is changed to the operation of Step 32, and other operations are the same as those in FIG.

In Step 32, first, data bit inversion processing is performed as necessary on the write data DATA, and then the same operation as Step 31 described in FIG. 14 is performed.

Referring to FIG. 19, the data bit inversion process in Step 32 will be described. The information processing circuit MNGR first sets i = 0 at START at the start of execution of Step 32, and in the next Step 350, the write data DATA (8 KB = 8192 bits) is divided into m bits, and the i-th m-bit data. The number ZBCi of “0” bits in mi is measured.

In the next Step 351, the “0” bit number ZBCi in the m bit data mi is compared with the “1” bit number (m−ZBCi). When the number of “0” bits ZBCi is larger than the number of “1” bits, the m-bit data mi is bit-inverted (Step 352), and the bit inversion flag IVFi is set to 0 (Step 353). When the number of “0” bits ZBCi is equal to or less than the number of “1” bits, the m-bit data mi is not bit-inverted, and the bit inversion flag IVFi is set to 1 (Step 354).

In the next Step 355, the value obtained by adding 1 to the current i value is used as the i value, and in the subsequent Step 356, it is checked whether the i value is equal to or larger than the value obtained by dividing M (= 8 KB = 8192 bits) by m. If the i value is equal to or greater than the value obtained by dividing M by m, the series of processing is terminated, otherwise Step 350 is executed.

The subsequent operation is the same as Step 31 described in FIG. Since the number of bits of the “0” data in the write data DATA can be reduced to half or less by the data bit inversion process, the total number SUMF0 of 0 values of the boundary flag BD for the write data DATA obtained by the subsequent process can be reduced. . That is, by the data bit inversion process, the number of times of writing to the nonvolatile memory devices NVM0 to NVM3 is reduced, and the writing time can be shortened.

Referring back to FIG. 18, after Step 32 is completed, in Step 4, the write data DATA, the boundary flag BD corresponding to these data, the bit inversion flag IVF, and the total number BDSUM0 of the boundary flag BD0 values are written into the buffer BUF0.

FIG. 20 is a diagram showing the correspondence of the boundary flag BDi to each m-bit data mi (i = 0, 1, 2,..., M / m) divided into m bits in the write data DATA. is there. When the number of 0 data bits in the write data DATA is 5440 × 8 bits, which is 2/3, the data bit inversion processing of FIG. 19 is executed, and the state immediately after Step 32 of FIG. 18 is executed is shown. The correspondence method between the write data DATA and the data mi is the same as in FIG.

Data bit inversion reduces the number of 0 data bits in write data DATA to 1/3 of 2752 x 8 bits. As a result, the number of 0 of boundary flag BD is also (2752/32) x 8 = 688 Can be reduced. Thus, as a result of executing the data bit inversion processing of FIG. 19, the number of 0 of the BD value is 688, and the number of times of writing “0” data bits is 688 times. If the present embodiment is not used, the number of times of writing is 2048, so the number of times of writing can be reduced by 1360 times according to the present embodiment. The smaller the number of 0 of the boundary flag BD value, the smaller the number of times of writing “0” data bits, and the write time can be shortened.

FIG. 21 is a table showing an example of the data stored in the buffer and the boundary flag BD, which corresponds to FIG. 6 and FIG. 16, but is an example in which a data bit inversion process is further applied thereto.

In FIG. 21C1, after performing the data bit inversion processing in Step 32 of FIG. 18, the write data DATA D0 to D7 stored in the buffer BUF0 in Step 4 and the boundary flags D0_BD to D7_BD corresponding to these data are stored. Boundary flag valid / invalid flags D0_BDV to D7_BDV (all valid in this example), bit inversion flags D0_IVF to D7_IVF, and the total number of zero values BDSUM0 in the boundary flags D0_BD to D7_BD.

The total number BDSUM0 of 0 values of the boundary flags D0_BD to D7_BD corresponding to the write data DATA D0 to D7 is 710, 420, 950, 800, 960, 810, 700, and 500, respectively.

On the other hand, FIG. 16C1 shows the total number of BDSUM0 values when the data bit inversion process is not performed. Compared with these values, the value of the total number BDSUM0 is obtained by performing the data bit inversion process. Can be greatly reduced.

FIG. 21 (B2) shows the channel assignment for data D0 to D7 when the write time reduction channel assignment is not performed, and FIG. 21 (B3) shows the total number SUM_BDC for each channel at that time.

Write data D0 and D4 are assigned to channel CH0, write data D1 and D5 are assigned to channel CH1, write data D2 and D6 are assigned to channel CH2, and write data D3 and D7 are assigned to channel CH3.

At this time, the total number SUM_BDC of the channel CH0 is 1670, the total number SUM_BDC of the channel CH1 is 1230, the total number SUM_BDC of the channel CH2 is 1650, and the total number SUM_BDC of the channel CH3 is 1300. The total number SUM_BDC of channel CH0 1670 is the maximum number of times of writing to the nonvolatile memory device NVM, and this is the maximum write time.

On the other hand, FIG. 21 (C2) shows the conventional channel assignment for data D0 to D7 when the write time reduction channel assignment is performed in Step 61 in FIG. 18, and FIG. Indicates the total number SUM_BDC for each channel. At this time, the total number SUM_BDC of the channel CH0 is 1380, the total number SUM_BDC of the channel CH1 is 1450, the total number SUM_BDC of the channel CH2 is 1510, and the total number SUM_BDC of the channel CH3 is 1510.

When the write time reduction channel assignment is performed, the maximum value of the total number SUM_BDC is 1510, which is reduced by about 160 compared with the case where the write time reduction channel assignment is not performed. In this way, by reducing the maximum value of the total number SUM_BDC by channel assignment for shortening the write time, the maximum number of writes to the nonvolatile memory device NVM, that is, the maximum write time can be shortened. As a result, the update timing of the address conversion table LPTBL and the erase count table ERSTBL for each block can be advanced, so that high-speed writing is possible.

Referring to FIG. 22, the effect of shortening the writing time according to the present embodiment will be described. FIG. 22A shows the writing time of data D0 to D7 in the memory module NVMD0 when this embodiment is not used. FIG. 22B shows the writing time of the data D0 to D7 in the memory module NVMD0 in the control using the “boundary flag BD” of the present embodiment. FIG. 22C shows the writing time of the data D0 to D7 in the memory module NVMD0 in the control using the “boundary flag BD” and “channel allocation” of the present embodiment.

22A corresponds to a conventional example, FIG. 22B corresponds to an example using the control shown in FIG. 6 or 16B, and FIG. 22C corresponds to FIG. This corresponds to an example using the control shown.

In FIG. 22A, the maximum number of writes to channel CH0 (nonvolatile memory device NVM0) is 4096. In FIG. 22B, the number of times of writing to each channel is reduced and the writing time is shortened by the control using the “boundary flag BD” of the present embodiment. Further, in FIG. 22C, the maximum write count of the channel CH1 is reduced and the write time is shortened by the control using the “boundary flag BD” and “channel allocation” of the present embodiment.

FIG. 23A shows the write time of data D0 to D7 in the memory module NVMD0 when this embodiment is not used, and FIG. 23B shows the “bit inversion processing” and “boundary” of this embodiment. FIG. 23C shows the write time of the data D0 to D7 in the memory module NVMD0 under the control using the flag BD. FIG. 23C shows the “bit inversion process”, the “boundary flag BD” of this embodiment, The write time of data D0 to D7 in the memory module NVMD0 in the control using “channel allocation” is shown.

FIG. 23A corresponds to a conventional example, FIG. 23B corresponds to an example using the control shown in FIG. 21B, and FIG. 23C shows the control shown in FIG. Corresponds to an example using.

In FIG. 23A, the maximum number of writes to channel CH0 (nonvolatile memory device NVM0) is 4096. In FIG. 23B, the number of times of writing to each channel is greatly reduced and the writing time is shortened by the control using the “bit inversion processing” and the “boundary flag BD” of the present embodiment. Further, in FIG. 23C, the maximum number of times of writing to the channel CH0 is reduced by the control using the “bit inversion processing”, the “boundary flag BD”, and the “channel allocation” of the present embodiment, and the writing time is reduced. Shortened.

Hereinafter, a garbage collection process suitable for application to a system employing the first to third embodiments will be described. The system configuration is the same as that shown in FIGS.

FIG. 24 shows a data copy operation performed by the information processing circuit MNGR in FIG. 2 during the garbage collection operation of this embodiment. Although not limited, in this example, the garbage collection process is started from the point when Step 7 in FIG. 14 ends (Step 0). Garbage collection itself is a well-known technique, but in the following, features specific to this embodiment will be mainly described.

The information processing circuit MNGR reads the number of erased blocks of the memory module NVMD0 stored in the storage device M2 from the nonvolatile memory devices NVM0 to NVM3, and compares the number of erased blocks with a specified value B (Step 1). If the number of erased blocks is B or less, Step 2 is executed, otherwise Step 15 (end) is executed.

In Step 2, the information processing circuit MNGR selects L1 written blocks of the non-volatile memory devices NVM0 to NVM3 whose erase count is N1 or more. In the next Step 3, L2 erased blocks of the non-volatile memory devices NVM0 to NVM3 whose erase count is N2 or less are selected.

In Step 4, the valid page data PDATA in the L1 blocks of the nonvolatile memory devices NVM0 to NVM3 selected in Step 2 are sequentially read. As described with reference to FIG. 11, the data PDATA is composed of data DATA and redundant data Rdata. The redundant data Rdata includes a data inversion flag IVF, a boundary flag BDF, and ECC codes ECC1 and ECC2.

Specifically, the information processing circuit MNGR transfers the read instruction RDgc and the physical address PAD10 to the read queue circuits RDQ0 to RDQ3 via the arbitration circuit ARB. Note that this read command RDgc is a read command generated from other than a read request of the host device CPU_CP.

The memory control circuits (NVCT0 to NVCT3) read the read instruction RDgc from the read queue circuits RDQ0 to RDQ3, and transfer the read instruction RD10 corresponding to the read instruction RDgc and the physical address PAD10 to the nonvolatile memory devices (NVM0 to 3) To do. The read command RD10 is a command for reading the boundary flag BD, data DATA0, and ECC codes ECC1 and ECC2 (a list of commands will be described later with reference to FIG. 26).

The non-volatile memory devices (NVM0 to NVM3) use the read command RD10 and the physical address PAD10, the data DATA10 corresponding to the physical address PAD10, the inversion flag IVF of the data DATA10, the ECC code ECC1, the boundary flag BD, and the boundary flag BD. The ECC code ECC2 is transferred to the memory control circuit (NVCT0 to NVCT3).

In Step 5, the memory control circuit NVCT uses the ECC code ECC1 to check whether there is an error in the data DATA10 and the inversion flag IVF. Also, using the ECC code ECC2, it is checked whether there is an error in the boundary flag BD. If there is an error in these, correction is performed, and data DATA10, inversion flag IVF, boundary flag BD, ECC code ECC1, and ECC code ECC2 are transferred to read queue circuits (buffers) RDQ0 to RDQ3.

Further, the information processing circuit MNGR reads the data by the read command RDgc and stores the NDATA low for the data DATA10, the inversion flag IVF, the boundary flag BD, the ECC code ECC1, and the ECC code ECC2 stored in the read queue circuits RDQ0 to RDQ3. The value of the data valid information ROWDV information is set to “0” (= valid), and the data value is transferred to the copy area CAREA in the buffer BUF0 together with the NVM row data valid information ROWDV information without changing the values of these information.

In the next Step 6, it is checked whether all the valid page data PDATA in the L1 blocks of the nonvolatile memory devices NVM0 to NVM3 selected in Step 2 have been transferred to the buffer BUF0. If the transfer has not been completed, Step 7 is executed. If the transfer has been completed, Step 8 is executed.

In Step 7, it is checked whether the copy area CAREA of the buffer BUF0 is filled with the data read from the nonvolatile memory device NVM. If it is satisfied, Step 8 is executed, and if not satisfied, Step 4 is executed.

In Step 8, the information processing circuit MNGR, the physical address PAD10 in the erased block selected in Step 3 in the copy area CAREA, the inversion flag INVF, the boundary flag BD stored in the copy area CARARE of the buffer BUF0, Data DATA10, ECC codes ECC1, ECC2, and program instruction PRGgc are transferred to write queue circuits WTQ0 to WTQ3.

Next, the memory control circuit NVCT reads the inversion flag INVF, the boundary flag BD, DATA10, and the ECC codes ECC1 and ECC2 stored in the write queue circuits WTQ0 to WTQ3, and programs the nonvolatile memory devices NVM0 to NVM3. The instruction PRG01, physical address PAD100, inversion flag INVF, boundary flag BD, data DATA10, and ECC codes ECC1 and ECC2 are transferred. Program instruction PRG01 is an instruction for writing inversion flag INVF, boundary flag BD, data DATA10, and ECC codes ECC1 and ECC2 to nonvolatile memory devices NVM0 to NVM3. Since the program instruction PRG01 writes the boundary flag BD into the memory, the nonvolatile memory devices NVM0 to NVM3 can reuse the boundary flag BD for garbage collection processing.

Nonvolatile memory devices NVM0 to NVM3 write inversion flag INVF, boundary flag BD, DATA10, and ECC codes ECC1 and ECC2 to internal memory cells by program instruction PRG01.

In the next Step 9, it is checked whether all the valid page data PDATA in the L1 blocks of the nonvolatile memory devices NVM0 to NVM3 selected in Step 2 have been transferred to the nonvolatile memory device. If all of the data PDATA has been transferred to the nonvolatile memory devices NVM0 to NVM3, Step 10 is executed, and if not, Step 4 is executed. In Step 10, the written block selected in Step 2 is erased.

When erasing a written block, as described with reference to FIG. 10, if the memory cells in the chain memory array for L bytes can be made low resistance at the same time, the block size shown in FIG. , (64 / L) × 1024 times-divided erase operations are required.

In the next Step 11, if a priority read request from the host occurs during the erase operation, the information processing circuit MNGR sends the priority read instruction RDpri and physical address to the read queue circuits RDQ0 to RDQ3 via the arbitration circuit ARB. Transfer PAD20.

The memory control devices (NVCT0 to NVCT3) read the priority read instruction RDpri and the physical address PAD50 from the read queue circuits RDQ0 to RDQ3, and the physical address PAD50 is in the nonvolatile memory device (NVM0 to 3) that is currently performing the erase operation. If it is a physical address, the erase operation temporary interruption command Erase_pause is transferred to the nonvolatile memory devices (NVM0 to NVM3) that are performing the erase operation. When the nonvolatile memory device in the erasing operation receives the erase operation temporary interruption command Erase_pause, the non-volatile memory device completes the erasing operation to the chain memory array for L bytes currently being erased, and temporarily suspends the erasing operation. The maximum time until the erasing operation is temporarily interrupted is t10.

Thereafter, after the elapse of the t10 period, the memory control devices (NVCT0 to NVCT3) transfer the read command RD01 and the physical address PAD50 to the nonvolatile memory devices (NVM0 to NVM3). The nonvolatile memory devices (NVM0 to NVM3) output the data DATA50 of the physical address PAD50, the inversion flag IVF, and the ECC code ECC1 to the memory control device, and further transfer them to the read queue circuits RDQ0 to RDQ3 by the memory control device.

Next, the memory control devices (NVCT0 to NVCT3) transfer the erase operation restart command Erase_restart to the nonvolatile memory devices (NVM0 to 3) that have temporarily suspended the erase operation. The nonvolatile memory device that has temporarily suspended the erase operation resumes the next erase operation to the chain memory array for L bytes.

Next, the memory controller NVCT uses the ECC code ECC1 to check whether there is an error in the data DATA50 and the inversion flag IVF. If there is an error, the memory controller NVCT corrects the error and sends the data DATA50 and the read queue circuit RDQ0 to RDQ3. Transfer the inversion flag IVF. Next, the information processing circuit MNGR checks whether the inversion flag IVF value is zero. If the inversion flag IVF value is 0, each bit of the data DATA50 is inverted, data DATA50R is generated, and transferred to the host device CPU_CP through the interface circuit NVM_IF.

In Step 12, it is checked whether all written blocks selected in Step 2 have been erased. If all the written blocks selected in Step 2 are erased, Step 13 is performed. If all the written blocks selected in Step 2 are not erased, Step 10 is performed.

In Step 13, it is checked whether the number of erased blocks is greater than B. If the number of erased blocks is greater than B, Step 14 is performed, otherwise Step 2 is performed.

In Step 14, the information processing circuit MNGR updates the logical / physical address conversion table LPTBL, the physical address conversion table PLTBL, the erase count table ERSTBL for each block, and the erase block count table ERSTBL1 stored in the memory device M2. Finish (Step 15)
As described above, in this embodiment, the inversion flag IVF and the boundary flag BD are stored in the nonvolatile memory device NVM. Thus, when this is stored in the read buffers BUF0 and BUF1, the data bit inversion operation in FIG. 18 and the series of boundary detection operations in Step 3 in FIG. 3, Step 31 in FIG. 14, and Step 32 in FIG. 18 are re-executed. There is no need to do. Therefore, the speed of the garbage collection operation and the data copy operation during the static wear leveling operation can be increased.

In addition, when the data stored in the copy area ACOPY of the buffer BUF0 is transferred to the nonvolatile memory device NVM, the inversion flag IVF, the boundary flag BD, and the ECC codes ECC1 and ECC2 are already prepared. There is no need to execute the boundary processing shown in FIG. 4 by the circuit MNGR and the data bit inversion processing shown in FIG. 19, and it is not necessary to generate the ECC codes ECC1 and ECC2 in the memory control circuit NVCT. Data transfer to the device NVM can be performed at high speed.

Furthermore, since the read command from the host can be preferentially executed during the erase operation of the block by the temporary interrupt command Erase_pause of the erase operation, the read from the host can be accelerated. Further, since the erase operation to the next L bytes of the chain memory array can be resumed by the erase operation restart instruction Erase_restart, it is necessary to perform the erase operation redundantly on the same L bytes of the chain memory array. In addition, reading from the host can be speeded up without causing unnecessary erasing operation.

As will be described later, Erase_pause and Erase_restart are included in various commands shown in FIG. 26 that can be used in the memory control circuits NVCT0 to NVCT3. Various settings can be made by setting the validity of each command as shown in FIG. It is possible to support this system.

Hereinafter, processing of a read request from the host device CPU_CP, which is suitable for application to a system employing the first to third embodiments, will be described. The system configuration is the same as that shown in FIGS.

FIG. 25 is an example of a read operation of the memory module NVMD0 when a read request from the host device CPU_CP is input to the memory module NVMD0.

In Step 1, the read request RQ including the logical address LAD, the data read command RD, the sector count SEC, etc. is sent from the host device CPU_CP of FIG. 1 through the interface circuit NVM-IF of the control circuit NVM-CTL. Input to MNGR. The information processing circuit MNGR that has received the request first checks whether the access from the higher-level device CPU_CP is a read request RQ. If the access is the read request RQ, Step 2 is performed.

In Step 2, the information processing circuit MNGR stores the logical address LAD, the data read command RD, the sector count SEC, etc. in the address / command buffer ADCBUF.

In Step 3, the information processing circuit MANAGER decodes the logical address value LAD0, the data read instruction RD, and the sector count SEC1, and stores the physical address stored in the address LAD0 in the address conversion table LPTBL stored in the memory device M2. The value CPAD0 and the valid flag CVF value corresponding to the physical address value CPAD0 are read.

In Step 4, the information processing circuit MANAGER checks whether or not the read valid flag CVF value is 1. When the valid flag CVF value is 0, it indicates that the physical address CPAD is not assigned to the logical address LAD0, and data cannot be read from the non-volatile memory device NVM. This is transmitted to the host device CPU_CP through the interface circuit NVM_IF (Step 10). If the valid flag CVF value is 1 (valid), Step 5 is performed.

In Step 5, when the physical address CPAD0 corresponds to the logical address LAD0, the information processing circuit MNGR transfers the read instruction RDht and the physical address value CPAD0 to the read queue circuits RDQ0 to RDQ3 via the arbitration circuit ARB. Further, this read command RDht indicates that it is a read command in response to a read request RQ from the host device CPU_CP.

FIG. 26 is a table showing a list of NVM command functions issued by the information processing circuit (MNGR) to the nonvolatile memory device NVM via the memory control circuits (NVCT0 to NVCT3). In addition to Erase_pause, Erase_restart, PRG01, and PRG10 used in the first to fourth embodiments, RD01 and RD10 described below are defined as commands. In this specification, the commands shown in FIG. 26 are cited and described. For example, in this embodiment, writing using the boundary flag, writing command PRG01 that writes the boundary flag to the memory cell, writing using the boundary flag, writing command PRG10 that does not write the boundary flag to the memory cell, and boundary flag The conventional write command PRG00 that is not used can be supported.

Also, for the read command, RD10 or the like for reading the boundary flag BD and RD01 or the like for not reading can be selected. For example, since the boundary flag BD is not necessary for normal data reading from the host device CPU_CP, the reading time can be shortened by using RD00 or RD01. On the other hand, since the boundary flag BD is necessary for reading at the time of garbage collection assuming writing, RD10 or RD22 is used.

FIG. 27 is an example of setting data stored in the register SPREG in FIG. 7 in order to switch the mode of the NVM command in FIG. This setting is performed by the command Set SPREG in FIG.

The memory control circuit (NVCT0 to NVCT3) reads the read command RDht from the read queue circuits RDQ0 to RDQ3, recognizes that the read command RDht is a read command based on the read request RQ from the host device CPU_CP, and reads the read command RD01, The physical address CPAD0 is transferred to the nonvolatile memory devices (NVM0 to NVM3). As shown in FIG. 26, the read instruction RD01 is an instruction for reading only the data DATA, the inversion flag IVF, and the ECC code ECC1 without reading the boundary flag.

The non-volatile memory device (NVM0 to NVM3) uses the read command RD01 and the physical address CPAD0 to send data DATA0 corresponding to the physical address CPAD0 and the inversion flag IVF and ECC1 corresponding to the data DATA0 to the memory control circuit (NVCT0 to NVCT3). ).

In Step 6, the memory control circuit NVCT uses the ECC code ECC1 to check whether there is an error in the data DATA0 and the inversion flag IVF. If there is an error, the memory control circuit NVCT corrects the error and sends data DATA0 and RDQ3 to the read queue circuit RDQ0 Transfer the inversion flag IVF.

In Step 7, the information processing circuit MNGR checks whether the inversion flag IVF value is 0. If the inversion flag IVF value is 0, each bit of the data DATA is inverted to generate data DATA_R (Step 8) and transferred to the host device CPU_CP through the interface circuit NVM_IF (Step 9).

In this way, in response to a read request from the host device CPU_CP, only the data DATA, the inversion flag IVF, and the ECC code ECC1 are read from the nonvolatile memory device (NVM0 to NVM3) using the read command RD01. For this reason, it is not necessary to read the boundary flag, so that it can be read at high speed.

In this embodiment, the nonvolatile memory devices NVM0 to NVM3 support a read-only command RD01 from the host device and a read command RD10 that reads all flags together with data. As a result, the control circuit (controller) NVM-CTL issues a read instruction RD01 to the non-volatile memory devices NVM0 to NVM3 in response to a read request from the host device, during garbage collection or static wear leveling operation, etc. In response to a read request from the information processing circuit MNGR itself, a read command RD10 can be issued, so that optimum control according to the request source is possible.

(Summary)
The main effects obtained by the respective embodiments described above are as follows.

First, by generating a boundary flag BD for the write data and associating the boundary flag BD with the internal X address, Y address, and Z address necessary for writing the data, the “0” data bit is set. Since the internal address range that can be written at one time can be specified and written, the number of times of writing is reduced, the writing time is shortened, the power consumption of the memory module is reduced, and the writing speed can be improved.

Second, the total number of boundary flag BD values 0 for the write data is obtained, and by assigning the write data to the channels so that the total number of boundary flag BD values 0 is uniform among the channels, The writing time can be shortened and the writing speed of the memory module can be improved.

Third, by generating the boundary flag BD for the write data that has undergone bit inversion processing, the number of boundary flag BD values 0 can be greatly reduced, the writing time of the nonvolatile memory can be shortened, and the memory module Can improve the writing speed.

As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, the above-described embodiment has been described in detail for easy understanding of the present invention, and is not necessarily limited to one having all the configurations described. Further, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. . Further, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment. In the embodiments, the phase change memory has been mainly described as a representative, but a resistance change type memory including a ReRAM or the like can be similarly applied to obtain the same effect.

In the embodiment, the description has been given by taking as an example a memory having a three-dimensional structure in which a plurality of memory cells are sequentially stacked in the height direction with respect to the semiconductor substrate. The same effect can be obtained by applying the same to a two-dimensional memory in which one memory cell is arranged.

It can be used in the field of storage devices using various memories.

CPU_CP: Host device, NMV-CTL ... Control circuit, MNGR ... Information processing circuit, NVM0-3 ... Nonvolatile memory device, NVMD0 ... Memory module, NVCT0-NVCT3 ... Memory control circuit

Claims

A memory control device that includes an information processing circuit and controls a memory,
The information processing circuit is provided with a boundary flag for each data unit obtained by dividing write data into the memory every m bits,
The boundary flag indicates a continuous range of the data unit such that the number of bits of a specific value in the write data is a maximum value not exceeding a threshold value.
A memory control device.
The memory control device according to claim 1,
Furthermore, it has a memory control circuit,
The information processing circuit includes:
Issuing a write command to enable the boundary flag, the write data, and the boundary flag through the memory control circuit,
A memory control device.
The memory control device according to claim 2,
The information processing circuit includes:
The write data, an error correction code for the boundary flag is generated, and the write command for enabling the boundary flag via the memory control circuit, the boundary flag, the write data, and the error correction code, , Issue,
A memory control device.
The memory control device according to claim 1,
The information processing circuit includes:
If the data unit is a data unit at the boundary of a continuous range of the data units such that the number of bits of the specific value in the write data is a maximum value not exceeding the threshold, Set the value of the boundary flag to the first value,
In the write data, if the data unit is included in a continuous range of the data unit such that the number of bits of the specific value is the maximum value not exceeding the threshold, the boundary flag Set the value to the second value,
A memory control device.
The memory control device according to claim 4,
The information processing circuit measures the number of first values of the boundary flag;
A memory control device.
2. The memory control device according to claim 1, wherein the information processing circuit performs bit inversion as necessary for each data unit, generates bit inversion data from the write data, Generate a reverse flag,
A boundary flag is provided for the data unit or the bit-inverted data unit,
The boundary flag indicates a continuous range of the data unit or the bit-inverted data unit such that the number of bits of a specific value is a maximum value not exceeding m bits in the write data.
A memory control device.
The memory control device according to claim 6.
The information processing circuit generates an error correction code for the write data, the boundary flag, and the bit inversion flag, and enables the boundary flag through the memory control circuit, and the bit inversion Issuing a flag, the boundary flag, the write data, and the error collection code;
A memory control device.
The memory control device according to claim 5,
The semiconductor device comprises a plurality of channels,
The information processing circuit includes:
Allocating the write data to the plurality of channels so as to equalize the number of first values of boundary flags for the write data between the channels, and issuing the write data from the plurality of channels;
A memory control device.
The memory control device according to claim 1,
The threshold is m bits;
The information processing circuit can program the value of m.
A memory control device.
In a storage device having a nonvolatile memory and a control circuit for writing to the nonvolatile memory,
The control circuit includes:
A boundary flag is provided for each of the data units m1 to mn (where n is a natural number), in which the write data to the nonvolatile memory is divided every m bits,
The boundary flag indicates a continuous range of the data unit in which the number of bits of a specific value is a maximum value not exceeding a threshold value in the write data,
If the number of bits of a specific value does not exceed the threshold value within the continuous range mx to my (where n ≧ y ≧ x ≧ 1) of the data unit,
The boundary flag for at least one of the data units mx and my is a first value, and the boundary flag for the other data units is a second value.
A storage device.
The storage device according to claim 10.
The control circuit includes:
Associating the boundary flag and the write data with an address in the nonvolatile memory;
Writing the write data into the memory cell of the nonvolatile memory;
A storage device.
The storage device according to claim 11.
The control circuit includes:
The boundary flag for the data unit my is a first value,
Boundary flag of the data unit is continuously assigned to continuous addresses in the nonvolatile memory divided every m bits, and the continuous data unit until the boundary flag value becomes the first value. Are collectively written in the nonvolatile memory,
A storage device.
The storage device according to claim 10.
Comprising a plurality of channels for writing the write data to the nonvolatile memory;
The control circuit includes:
Measuring the number of first values of the boundary flag in the write data;
Allocating the write data to the plurality of channels to level the number of first values of boundary flags for the write data assigned to the plurality of channels;
Transferring the write data from the plurality of channels to the nonvolatile memory;
A storage device.
The storage device according to claim 10.
The threshold value is m bits;
A storage device.
A method of writing data to a memory, comprising a plurality of memory cells capable of transitioning to at least two states and writing data by transitioning the state of the memory cells,
When the data is written to the memory, the input data is divided into m-bit data units, and the number of data bits that need to change the state of the memory cell to write the data is a threshold value. Write the consecutive data units in a range that takes the following maximum values in a batch,
A method for writing to a memory.