JP6145227B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device provided with a nonvolatile memory device.

  In recent years, a phase change memory using a chalcogenite material as a recording material has been actively studied as a nonvolatile memory device. A phase change memory is a type of resistance change memory that stores information by utilizing the fact that recording materials between electrodes have different resistance states.

In the phase change memory, information is stored by utilizing the fact that the resistance value of a phase change material such as Ge ₂ Sb ₂ Te ₅ is different between an amorphous state and a crystalline state. In the amorphous state, the resistance is high (high resistance state), and in the crystal state, the resistance is low (low resistance state). Therefore, reading of information from the phase change memory is realized by applying a potential difference to both ends of the element, measuring the current flowing through the element, and determining the high resistance state / low resistance state of the element.

  In the phase change memory, data is rewritten by changing the electrical resistance of the phase change film formed of the phase change material to a different state by Joule heat generated by current.

  FIG. 14 is a diagram showing the relationship between the pulse width and temperature required for the phase change of the resistive memory element using the phase change material. In the figure, the vertical axis represents temperature and the horizontal axis represents time. When the storage information “0” is written in the storage element, as shown in FIG. 14, a reset pulse is applied so that a large current is passed to heat the storage element to the melting point Ta or higher of the chalcogenide material and then rapidly cool. In this case, by shortening the cooling time t1 (for example, by setting to about 1 ns), the chalcogenide material becomes a high resistance amorphous state. On the contrary, when the memory information “1” is written, it is sufficient to keep the memory element in a temperature region lower than the melting point Ta but higher than the crystallization temperature Tx (same or higher than the glass transition temperature). A set pulse is applied for a long time so that a proper current flows. Thereby, the chalcogenide material is in a low-resistance polycrystalline state.

  In this phase change memory, when the resistance element structure is reduced, the current required for the state change of the phase change film is reduced. For this reason, the phase change memory is suitable for miniaturization in principle, and has been actively researched. Patent Document 1 and Patent Document 2 disclose a nonvolatile memory having a three-dimensional structure.

  Patent Document 1 discloses a configuration in which memory cells each including a variable resistance element and a transistor connected in parallel thereto are connected in series in the stacking direction. Patent Document 2 shows a configuration in which memory cells each including a variable resistance element and a diode connected in series to the variable resistance element are connected in series with a conductive wire interposed in the stacking direction. In this configuration, for example, by applying a potential difference between the conductive line between two memory cells and the two conductive lines outside the two memory cells, the two memory cells can be collectively processed. Thus, the write operation is performed.

  Patent Document 3 discloses that when data is written to the phase change memory, the data is read again to verify whether the writing is successful. If the read data is different from the written data, the data is written again. Patent Document 3 discloses a writing method in which this operation is repeated until writing is successful.

International Publication No. 2011/0774545 JP 2011-142186 A JP 2008-084518 A

  Prior to the present application, the present inventors have studied a method for controlling a resistance variable nonvolatile memory. As described in FIG. 14, in the phase change memory, data is rewritten by changing the electric resistance of the phase change film to a different state by Joule heat generated by current. The reset operation, that is, the operation of changing the phase change film to the high resistance amorphous state is performed by flowing a large current for a short time to dissolve the phase change material, and then rapidly decreasing and rapidly cooling the current. On the other hand, the set operation, that is, the operation of changing the phase change film to a low resistance crystal state is performed by flowing a current sufficient for maintaining the phase change material at the crystallization temperature for a long time.

  This means that in the phase change memory, the reset operation can be performed at high speed, but the set operation is slower than that. In addition, Joule heat generated when a write operation is performed on a certain memory cell affects the crystal state of the surrounding memory cell, and the resistance value of the surrounding memory cell may fluctuate, possibly causing data loss. is there. In particular, the setting operation to the memory cell, that is, the operation to change to the low resistance crystal state, flows a current sufficient to maintain the phase change material at the crystallization temperature for a long time. May have a significant impact on

  Further, if the microfabrication technology of the phase change memory is advanced with the aim of reducing the cost, there is a possibility that the influence of the setting operation to the memory cell on the crystal state of the peripheral memory cell becomes larger.

  The present invention has been made in view of the above problems. SUMMARY OF THE INVENTION A first object of the present invention is to provide a semiconductor device capable of improving the speed of setting memory cells per unit time (higher erase data rate). A second object of the present invention is to provide a semiconductor device capable of simultaneously reducing the cost while suppressing a decrease in reliability due to thermal disturbance in the set operation. That is, it is an object to provide a semiconductor device including a nonvolatile memory with high reliability and low cost.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  That is, the semiconductor device includes a nonvolatile memory unit including a plurality of memory cells, a control circuit that allocates a physical address to a logical address input from the outside, and accesses the nonvolatile memory unit according to the allocated physical address; It has.

  Here, the nonvolatile memory unit includes intersections of the plurality of first signal lines, the plurality of second signal lines intersecting with the plurality of first signal lines, and the plurality of first signal lines and the plurality of second signal lines. And a plurality of memory cell groups arranged in the. Further, each of the memory cell groups includes first to Nth (N is an integer of 2 or more) memory cells, and memory cell selection lines for selecting the first to Nth memory cells, respectively. .

  The control circuit includes a plurality of memory cell groups included in the non-volatile memory unit, the first region including the plurality of memory cell groups arranged adjacent to each other, and one side of the outer periphery of the first region. The first logic level is written collectively to each of the arranged second region and the plurality of memory cell groups included in the first region, and to the memory cell group included in the second region. Therefore, writing to the first logic level is not performed.

  The control circuit performs a first operation on the first data and the second data input from the outside of the semiconductor device, generates third data, and the size of the third data is equal to or larger than the size of the second region. The data is written to the first area, the second data and the third data are not written to the first area, the second operation is performed on the first data and the third data held in the first area, and the second data is Generate.

  In one embodiment, the first logic level is a memory cell set state.

  As a result, the set operation (erase operation) can be performed simultaneously on the memory cell groups adjacent to each other, so that the throughput of the set operation, that is, the erase data rate can be improved. In addition, when performing a set operation collectively, the second area functions as a heat shielding area, prevents the influence of thermal disturbance on other memory cell groups, and prevents data loss in other memory cell groups. Is possible. Further, since the second data input from the outside of the semiconductor device is not written to the first area, a data amount larger than the amount of data that can be physically held in the first area is larger than the size of the second area. The second region can function as a heat shielding region, but the cost of the semiconductor device can be reduced.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  That is, a semiconductor device including a nonvolatile memory with high reliability and low cost can be provided.

1 is a block diagram illustrating a schematic configuration example of an information processing system to which a semiconductor device according to an embodiment of the present invention is applied. It is a block diagram which shows the structural example of the control circuit in FIG. FIG. 2 is a block diagram illustrating a configuration example of a nonvolatile memory device in FIG. 1. FIG. 3B is a circuit diagram showing a configuration example of the chain memory array in FIG. 3A. FIG. 3C is an explanatory diagram showing an operation example of the chain memory array of FIG. 3B. It is explanatory drawing which shows another operation example of the chain memory array of FIG. 3B. It is explanatory drawing which shows another operation example of the chain memory array of FIG. 3B. It is explanatory drawing which shows another operation example of the chain memory array of FIG. 3B. It is a figure which shows an example of the block configuration of the memory array of the non-volatile memory in FIG. 3A. It is a figure which shows an example of the write-in operation which the control circuit of FIG. 1 performs. It is a figure which shows an example of the write data stored in the random access memory of FIG. It is a figure which shows an example of the write data stored in the random access memory of FIG. It is a figure which shows an example of the block structure information stored in the random access memory of FIG. It is a figure which shows the structural example of the address conversion table stored in the random access memory of FIG. FIG. 2 is a diagram illustrating an example of a physical position of a physical address in a physical block in the nonvolatile memory device of FIG. 1. It is a figure which shows the structural example of the address conversion table stored in the random access memory of FIG. FIG. 2 is a diagram illustrating an example of a physical position of a physical address in a physical block in the nonvolatile memory device of FIG. 1. It is a figure which shows the structural example of the address conversion table stored in the random access memory of FIG. FIG. 2 is a diagram illustrating an example of a physical position of a physical address in a physical block in the nonvolatile memory device of FIG. 1. It is an example of the operation code ARITH_CODE for restoring data stored in the random access memory RAM. It is an example of the data restoration method using the operation code ARITH_CODE shown in FIG. 12A stored in the random access memory RAM. It is an example of the data restoration method using the operation code ARITH_CODE shown in FIG. 12A stored in the random access memory RAM. It is a figure which shows an example of the reading which the control circuit of FIG. 1 performs. It is a figure which shows the relationship between pulse width and temperature required for the phase change of the resistive memory element using a phase change material.

  In the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. Unless otherwise specified, they are not irrelevant to each other, and one is in the relationship of some or all of the other, modification, application, detailed explanation, supplementary explanation, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Furthermore, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numbers and the like (including the number, numerical value, quantity, range, etc.).

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same or related reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  The circuit elements constituting each block in the embodiment are not particularly limited, but are formed on a single semiconductor substrate such as single crystal silicon by a known integrated circuit technology such as CMOS (complementary MOS transistor). In addition, as a memory cell described in the embodiment, a resistive memory element such as a phase change memory or a ReRAM (Resistive Random Access Memory) is used.

<Outline of information processing system>
FIG. 1 is a block diagram showing a schematic configuration example of an information processing system to which a semiconductor device according to an embodiment of the present invention is applied. The information processing system shown in FIG. 1 includes an information processing device (processor) CPU_CP and a memory module (semiconductor device) NVMMD0. The information processing device CPU_CP is a host controller that manages data stored in the memory module NVMMD0 with a logical address (LAD) of a minimum of 8192 bytes, although not particularly limited. The information processing device CPU_CP reads and writes data from and to the memory module NVMMD0 through the interface signal HDH_IF. The memory module NVMMD0 is not particularly limited, but corresponds to, for example, an SSD (Solid State Drive).

  Signal systems for connecting the information processing device CPU_CP and the memory module (semiconductor device) NVMMD0 include a serial interface signal system, a parallel interface signal system, and an optical interface signal system. Needless to say, all methods can be used. As a clock system for operating the information processing device CPU_CP and the memory module NVMMD0, there are a common clock system and a source synchronous clock system using a reference clock signal REF_CLK, an embedded clock system in which clock information is embedded in a data signal, and the like. Needless to say, all clock systems can be used. In this embodiment, the serial interface signal system and the embedded clock system are used as an example, and the operation will be described below.

  From the information processing device CPU_CP, a read request (RQ), a write request (WQ) or the like in which clock information is embedded and converted into serial data is input to the memory module NVMMD0 through the interface signal HDH_IF. The read request (RQ) includes a logical address (LAD), a data read command (RD), a sector count (SEC), and the like, and the write request (WQ) includes a logical address (LAD) and a data write command (WRT). ), Sector count (SEC), write data (WDATA), and the like.

  The memory module (semiconductor device) NVMMD0 includes a nonvolatile memory device, NVM10 to NVM17, a random access memory RAM, and a control circuit MDLCT0 that controls the nonvolatile memory device and the random access memory. The nonvolatile memory devices NVM10 to NVM17 have, for example, the same configuration and performance.

  The non-volatile memory device NVM10 stores data, an OS, an application program, block configuration information (BLKCFG), and further stores a boot program for the information processing device CPU_CP and the like in .about.NVM17.

  The random access memory RAM has an address conversion table (LPTBL) that stores the physical address (PAD) of the nonvolatile memory device assigned to the logical address (LAD), and the physical address (PAD) of the nonvolatile memory device. In addition, a defective physical address table BADPADTBL storing information indicating whether or not a defective physical address cannot write data, an erase count table ERSTBL storing the erase count value of a physical block in which a plurality of physical addresses PAD are collected, and the like are stored.

  The random access memory RAM is not particularly limited, but is a DRAM or the like, for example.

  Immediately after the power is turned on, the memory module NVMMD0 performs an initialization operation (so-called power-on reset) of the internal nonvolatile memory devices NVM10 to NVM17, the random access memory RAM, and the control circuit MDLCT0. Further, the memory module NVMMD0 also initializes the internal nonvolatile memory devices NVM10 to NVM17, the random access memory RAM, and the control circuit MDLCT0 when receiving the reset signal RSTSIG from the information processing device CPU_CP.

  FIG. 2 is a block diagram illustrating a configuration example of the control circuit in FIG. The control circuit MDLCT0 illustrated in FIG. 2 includes an interface circuit HOST_IF, buffers BUF0 to BUF3, an address buffer ADDBUF, an arbitration circuit ARB, an information processing circuit MNGER, and memory control circuits RAMC, NVCT0, NVCT10 to NVCT7. . The memory control circuit RAMC directly controls the random access memory RAM of FIG. 1, and the NVCT10 to NVCT17 directly control the nonvolatile memory devices NVM10 to NVM17 of FIG. Buffers BUF0 to BUF3 temporarily store write data and read data of nonvolatile memory devices NVM10 to NVM17. The address buffer ADDBUF temporarily stores an address LAD input from the information processing device (processor) CPU_CP to the control circuit MDLCT0.

  Write physical address table NXPTBL, which is a table that stores physical addresses to be assigned to the logical address when a write command with a logical address is received from the information processing device CPU_CP, and is not particularly limited. This is realized by a register or the like. Note that the block configuration information (BLKCFG) and the boot program are arranged in the control circuit MDLCT0, for example, directly connected to the information processing circuit MNGER in FIG. 2 in order to speed up the initial setting of the memory module NVMMD0. Is also possible.

  3A is a block diagram illustrating a configuration example of the nonvolatile memory device in FIG. 1, and FIG. 3B is a circuit diagram illustrating a configuration example of the chain memory array in FIG. 3A. The non-volatile memory device shown in FIG. 3A corresponds to each of the non-volatile memory devices NVM10 to NVM17 of FIG. 1, and here, as an example, a phase change type non-volatile memory (phase change memory) is used. Yes. The nonvolatile memory device includes a clock generation circuit SYMD, a status register STREG, an erase size designation register NVREG, an address / command interface circuit ADCMDIF, an IO buffer IOBUF, a control circuit CTLOG, a temperature sensor THMO, a data control circuit DATCTL, and memory banks BK0 to BK0. BK3 is provided.

  Each of the memory banks BK0 to BK3 includes a memory array ARYx (x = 0 to m), a read / write control block SWBx (x = 0 to m) provided corresponding to each memory array, and various peripheral circuits for controlling them. Is provided. The various peripheral circuits include a row address latch RADLT, a column address latch CADLT, a row decoder ROWDEC, a column decoder COLDEC, a chain selection address latch CHLT, a chain decoder CHDEC, a data selection circuit DSW1, and data buffers DBUF0 and DBUF1. .

  Each memory array ARYx (x = 0 to m) includes a plurality of chain memory arrays CY arranged at intersections of a plurality of word lines WL0 to WLk and a plurality of bit lines BL0_x to BLi_x, and a plurality of bit lines BL0_x to BLi_x ( a bit line selection circuit BSWx that selects any one of x = 0 to m) and connects to the data line DTx. Each read / write control block SWBx (x = 0 to m) includes a sense amplifier SAx (x = 0 to m) and a write driver WDRx (x = 0 to m) connected to the data line DTx (x = 0 to m). , And a write data verification circuit WVx (x = 0 to m) for verifying data using these during a write operation. Further, if the interface for operating the nonvolatile memory device shown in FIG. 3A is a memory interface such as a NAND flash memory interface or a DRAM interface, the interface compatibility with the conventional system can be maintained, which is convenient. A good nonvolatile memory device can be provided.

  As shown in FIG. 3B, each chain memory array CY has a configuration in which a plurality of phase change memory cells CL0 to CLn are connected in series, one end of which is connected to a word line WL via a chain selection transistor Tch2. The other end is connected to the bit line BL via chain selection transistors Tch0 and Tch1. Although not shown, the plurality of phase change memory cells CL0 to CLn are sequentially stacked in the height direction with respect to the semiconductor substrate and are connected in series. Each phase change memory cell CL includes a variable resistance type storage element R and a memory cell selection transistor Tcl connected in parallel thereto. The memory element R is made of, for example, a chalcogenide material.

  In the example of FIG. 3B, two chain memory arrays CY share the chain selection transistor Tch2, and the chain memory transistors Tch0, 1, and 2 in each chain memory array are connected by the chain memory array selection lines SL0, SL1, and SL2. Each is controlled, and one of the chain memory arrays is thereby selected. The memory cell selection lines LY (LY0 to LYn) are connected to the gate electrodes of the corresponding phase change memory cells. The memory cell selection lines LY cause the memory cell selection transistors Tcl in the phase change memory cells CL0 to CLn to be respectively connected. And each phase change memory cell is appropriately selected. The chain memory array selection lines SL0, SL1, and SL2 and the memory cell selection lines LY0 to LYn are appropriately driven as the chain control line CH via the chain selection address latch CHLT and the chain decoder CHDEC in FIG. 3A.

  Next, the operation of the nonvolatile memory device of FIG. 3A will be briefly described. In FIG. 3A, first, the control circuit CTLOG receives the control signal CTL via the address / command interface circuit ADCMDIF. The control signal CTL is not particularly limited. For example, the command latch enable signal (CLE), the chip enable signal (CEB), the address latch signal (ALE), the write enable signal (WEB), the read enable signal (REB), A write instruction or a read instruction is issued by a combination of these including a ready busy signal (RBB). The control circuit CTLOG receives the input / output signal IO through the IO buffer IOBUF together with the control signal CTL. The input / output signal IO includes an address signal, and the control circuit CTLOG extracts a row address and a column address from the address signal. The control circuit CTLOG appropriately generates an internal address based on the row address, the column address, and a predetermined write / read unit, and transmits the internal address to the row address latch RADLT, the column address latch CADLT, and the chain selection address latch CHLT, respectively. To do.

  The row decoder ROWDEC receives the output of the row address latch RADLT and selects the word lines WL0 to WLk, and the column decoder COLDEC receives the output of the column address latch CALLT and receives bit lines BL0_x to BLi_x (x = 0 to m). Make a selection. The chain decoder CHDEC receives the output of the chain selection address latch CHLT and selects the chain control line CH. When a read command is input by the control signal CTL, data is read from the chain memory array CY selected by the combination of the word line, bit line, and chain control line described above via the bit line selection circuits BSW0 to BSWm. The read data is amplified by the sense amplifiers SA0 to SAm and transmitted to the data buffer DBUF0 (or DBUF1) via the data selection circuit DSW1. The data on the data buffer DBUF0 (or DBUF1) is sequentially transmitted to the input / output signal IO via the data control circuit DATCTL and the IO buffer IOBUF.

  On the other hand, when a write command is input by the control signal CTL, a data signal is transmitted to the input / output signal IO following the address signal described above, and the data signal is transmitted to the data buffer DBUF0 ( Or it is input to DBUF1). A data signal on the data buffer DBUF0 (or DBUF1) is selected by a combination of the above-described word line, bit line, and chain control line via the data selection circuit DSW1, the write drivers WDR0 to WDRm, and the bit line selection circuits BSW0 to BSWm. Is written to the chain memory array CY. At this time, the write data verification circuits WV0 to WVm verify whether or not the write level has reached a sufficient level while appropriately reading the written data through the sense amplifiers SA0 to SAm. The write operation is performed again using the write drivers WDR0 to WDRm until it reaches.

  FIG. 4 is an explanatory diagram showing an operation example of the chain memory array of FIG. 3B. With reference to FIG. 4, for example, an operation when the variable resistance memory element R0 in the phase change memory cell CL0 in the chain memory array CY1 is set to a high resistance or a low resistance will be described. Only the chain memory array selection line SL1 is activated (SL0 = Low, SL1 = High, SL2 = High) by the chain decoder CHDEC, and the chain selection transistors Tch1 and Tch2 are turned on. Subsequently, only the memory cell selection line LY0 is deactivated (LY0 = Low, LY1 to LYn = High), the memory cell selection transistor Tcl0 of the phase change memory cell CL0 is cut off, and the remaining memory cells CL1 to CLn. The memory cell selection transistors Tcl1 to Tcln are turned on.

  Next, when the word line WL0 becomes High and then the bit line BL0 becomes Low, the current I0 is changed from the word line WL0 to the chain selection transistor Tch2, the variable resistance memory element R0, the memory cell selection transistors Tcl1 to Tcln, and the chain selection. It flows to the bit line BL0 via the transistor Tch1. By controlling the current I0 in the form of the Reset current pulse shown in FIG. 14, the variable resistance memory element R0 has a high resistance. Further, the current I0 is controlled in the form of the Set current pulse shown in FIG. 14, so that the variable resistance memory element R0 has a low resistance. Data “1” and “0” are distinguished by the difference in resistance values of the variable resistance memory elements R0 to Rn.

  In addition, as shown in FIG. 3A, the writing speed can be improved by flowing the current I0 to the plurality of bit lines BL0_0 and BL0_1 to BL0_m.

  Although not particularly limited, it is assumed that data “1” is recorded when the variable resistance memory element becomes low resistance, and data “0” is recorded when the variable resistance memory element becomes high resistance.

  Note that when data recorded in the variable resistance memory element R0 is read, a current is applied through a path similar to that for data writing to the extent that the resistance value of the variable resistance memory element R0 does not change. In this case, a voltage value corresponding to the resistance value of the variable resistance storage element R0 is detected by a sense amplifier (SA0 in FIG. 3A in this example), and data “0” and “1” are determined.

  Further, as shown in FIG. 3A, a plurality of senses can be obtained by applying a current through a path similar to that of data writing to the extent that the resistance value of the variable resistance memory element R0 does not change through the plurality of bit lines BL0_0 and BL0_1 to BL0_m. Data “0” and “1” are determined by the amplifier (SA0 to SAm in FIG. 3A in this example), and the reading speed can be improved.

  5A, FIG. 5B, and FIG. 5C are explanatory diagrams showing another operation example of the chain memory array of FIG. 3B. First, using FIG. 5A, the operation when all the variable resistance memory elements R0 to Rn in the one-chain memory array CY1 are collectively reduced in resistance will be described. Only the chain memory array selection line SL1 is activated (SL0 = Low, SL1 = High, SL2 = High) by the chain decoder CHDEC, and the chain selection transistors Tch1 and Tch2 are turned on. Subsequently, the memory cell selection lines LY0 to LYn are deactivated (LY0 to LYn = Low), and the memory cell selection transistors Tcl0 to Tcln of the memory cells CL0 to CLn are cut off. Next, when the word line WL0 becomes High and then the bit line BL0 becomes Low, the current I1 passes from the word line WL0 via the chain selection transistor Tch2, the variable resistance memory elements R0 to Rn, and the chain selection transistor Tch1. It flows to the bit line BL0. By controlling the current I1 in the form of the Set current pulse shown in FIG. 14, the variable resistance memory elements R0 to Rn collectively have a low resistance.

  Next, using FIG. 5B, an operation when all the variable resistance memory elements R0 to Rn in the one-chain memory array CY1 are collectively reduced in resistance will be described. Only the chain memory array selection line SL1 is activated (SL0 = Low, SL1 = High, SL2 = High) by the chain decoder CHDEC, and the chain selection transistors Tch1 and Tch2 are turned on. Subsequently, the memory cell selection lines LY0 to LYn are activated (LY0 to LYn = High), and the memory cell selection transistors Tcl0 to Tcln of the memory cells CL0 to CLn are turned on. Next, when the word line WL0 becomes High and then the bit line BL0 becomes Low, the current I2 is a bit from the word line WL0 via the chain selection transistor Tch2, the memory cell selection transistors Tcl0 to Tcln, and the chain selection transistor Tch1. Flow to line BL0. Joule heat due to the current I2 is conducted to the variable resistance memory elements R0 to Rn, and the variable resistance memory elements R0 to Rn collectively have a low resistance. The current I2 is controlled to such a value that the variable resistance memory elements R0 to Rn can collectively reduce the resistance.

  Next, with reference to FIG. 5C, the operation when all the variable resistance memory elements R0 to Rn in the chain memory arrays CY0 and CY1 are collectively reduced in resistance will be described. The chain decoder CHDEC activates the chain memory array selection lines SL0 and SL1 (SL0, SL1 = High, SL2 = High), and the chain selection transistors Tch0, Tch1, and Tch2 of both the chain memory arrays CY0 and CY1 are turned on. . Subsequently, the memory cell selection lines LY0 to LYn are activated (LY0 to LYn = High), and the memory cell selection transistors Tcl0 to Tcln of the memory cells CL0 to CLn of both the chain memory arrays CY0 and CY1 are turned on. Next, when the word line WL0 becomes High and then the bit line BL0 becomes Low, the current I3 changes from the word line WL0 to the chain selection transistor Tch2, the memory cell selection transistors Tcl0 to Tcln of both the chain memory arrays CY0 and CY1, and the chain. It flows to the bit line BL0 via the selection transistors Tch0 and Tch1. The Joule heat generated by the current I3 is conducted to the variable resistance memory elements R0 to Rn of both the chain memory arrays CY0 and CY1, and the variable resistance memory elements R0 to Rn collectively have a low resistance. The value of the current I3 is controlled to such a value that the variable resistance memory elements R0 to Rn of both the chain memory arrays CY0 and CY1 are collectively reduced in resistance.

  As described above, if necessary, the memory cells in the plurality of chain memory arrays can be simultaneously reduced in resistance, and the erase data rate can be improved.

  FIG. 6 is an example of a block configuration of a memory array to be constructed by the control circuit MDLCT0 using the block configuration information (BLKCFG) of FIG. 9, and the block information BLKINFO is included in the block configuration information (BLKCFG) of FIG. Is an example of a block configuration of a memory array when erasure unit information ERSINFO is 1 and thermal buffer area information WALINFO is 1.

  When the block information BLKINFO of FIG. 9 is 1, one block is a chain memory array of 9 (X direction: X-BLK) × 9216 (Y direction: Y-BLK) × 8 (Z direction: Z-BLK). The size is 82944 bytes (= 9 (X direction) × 9216 (Y direction) × 8 (Z direction)).

Further, the erase unit information ERSINFO in FIG. 9 indicates a memory array region in which the resistance is reduced collectively when the memory cells in one block are reduced in resistance. When the erase unit information ERSINFO is 1, the memory array of 8 (X direction: XERS) × 72 (Y direction: YERS) × 8 (Z direction: ZERS) has a low resistance at a time, and the erase data size is 576 bytes. (= 9 (X direction) × 72 (Y direction) × 8 (Z direction)).
Further, the thermal buffer area information WALINFO in FIG. 9 indicates a memory array area as the thermal buffer area WALL. When the thermal buffer area information WALINFO is 1, a memory array for only one row in the X direction, that is, a memory array of 1 (X direction: XWAL) × 9216 (Y direction) × 8 (Z direction) is used as the thermal buffer area WALL. It is set and indicates that its size is 9216 bytes (= 1 (X direction) × 9216 (Y direction) × 8 (Z direction)).

  The nonvolatile memory device includes blocks BLK0 to BLKkn + n-1, and an example of the arrangement of the chain memory array CYL and the chain memory array CYH of the memory array ARY in each block is shown. In these drawings, the chain memory array CYL is indicated by white circles, and the chain memory array CYH is indicated by circles filled with dots. In the following drawings, the chain memory array CYL and the chain memory array CYH use the same display method.

  In FIG. 6, since the case where the block information BLKINFO of FIG. 9 is 1 is used, one block is composed of a chain memory array of 9 (X direction) × 9216 (Y direction), and its size is 82944. Byte (= 9 (X direction) × 9216 (Y direction) × 8 (Z direction)). A large number of these blocks are arranged to constitute a memory array of the nonvolatile memory shown in FIG. 3A.

  The write area WT-AREA in one block is the same as the erase area, and is an area in which a plurality of chain memory arrays CYL are physically gathered.

  The size of the write area WT-AREA is 73728 bytes (= 8 (X direction) × 9216 (Y direction) × 8 (Z direction)).

  The size of the data area DATA-AREA in the write area WT-AREA is 65536 bytes (= 8 (X direction) × 8192 (Y direction) × 8 (Z direction)), and the management area MG− in the write area WT-AREA. The size of AREA is 8192 bytes (= 8 (X direction) × 1024 (Y direction) × 8 (Z direction)).

  The data size of one logical address LAD is 8192 bytes, and the information processing circuit MNGER generates an ECC code for the data DATA, and sends the data DATA to the write area WT-AREA in the block of the memory array of the nonvolatile memory. Write ECC code.

Also, since one physical address is allocated an 8192-byte data area DATA-AREA for writing data DATA of one logical address LAD and a 1024-byte management area MG-AREA for writing an ECC code for the data DATA, etc.
In a 73728-byte write area WT-AREA, physical address data for eight logical addresses LAD is stored.

  The thermal buffer area WALL is an area in which a plurality of chain memory arrays CYH arranged outside the write area WT-AREA are physically gathered.

In FIG. 6, the heat buffer area information WALINFO of FIG.
The size of the thermal buffer area WALL is 9216 bytes (= 1 (X direction) × 9216 (Y direction) × 8 (Z direction)).

  In FIG. 6, since the case where the erase unit information ERSINFO of FIG. 9 is 1, the size of the chain memory array CYL to be erased at one time is 576 bytes (= 8 (X direction) × 72 (Y direction) × 8. (Z direction)).

  First, the data of all the memory cells included in all the chain memory arrays CYL in the write area WT-AREA (= erasure area) is “1” (Set state: low resistance state). That is, the data is erased all at once, and then only “0” data (reset state: high resistance state) is written for each physical address PAD. For example, when the write area WT-AREA size is 73728 bytes and the batch erase data size by one erase operation is 576 bytes, 128 erase operations are sequentially performed in the direction parallel to the Y direction, and the write area The data of all memory cells of WT-AREA is “1” (Set state: low resistance state).

  Since the erasing operation is not performed on the thermal buffer area WALL, the influence of the reliability deterioration due to the thermal disturbance when the erasing operation is performed on the writing area is not exerted on the adjacent block. Further, “0” data (Reset state: high resistance state) is not written in the thermal buffer region WALL.

As described above, by disposing the chain memory array CYH as the thermal buffer area WALL around the write area (= erasure area), it is possible to prevent a decrease in reliability due to thermal disturbance.
In addition, since no data is stored in the thermal buffer area WALL, data of eight physical addresses can be stored in one block.

  The block configuration information BLKCFG shown in FIG. 9 will be described in detail. The information processing circuit MNGER in the control circuit MDLCT0 uses this block configuration information (BLKCFG) to determine the block configuration of the nonvolatile memory.

  In the operation immediately after power-on, the information processing circuit MNGER reads the block configuration information BLKCFG stored in the nonvolatile memory devices NVM10 to NVM17 through the arbitration circuit ARB and the nonvolatile memory devices NVM10 to NVM17, and the block configuration register Store in BLKCFFGREG.

  Further, the information processing circuit MNGER includes desired block information BLKINFO, erasure unit information ERSINFO, and the like in accordance with the reliability, cost, and performance required by the information processing system in the block configuration information BLKCFG stored in the block configuration register BLKCFREG. The thermal buffer area information WALINFO is read to determine the block configuration of the volatile memory.

  Furthermore, the block configuration information BLKCFG is programmable, and the block configuration information BLKCFG can be changed in accordance with the reliability, cost, and performance required in various information processing systems.

  When the block information BLKINFO is 1, one block is configured by a chain memory array of 9 (X direction: X-BLK) × 9216 (Y direction: Y-BLK) × 8 (Z direction: Z-BLK). The size is 82944 bytes (= 9 (X direction) × 9216 (Y direction) × 8 (Z direction)).

  When the block information BLKINFO is 2, one block is composed of a chain memory array of 17 (X direction: X-BLK) × 9216 (Y direction: Y-BLK) × 8 (Z direction: Z-BLK). The size is 156672 bytes (= 17 (X direction) × 9216 (Y direction) × 8 (Z direction)).

  When the block information BLKINFO is 3, one block is configured by a chain memory array of 33 (X direction: X-BLK) × 9216 (Y direction: Y-BLK) × 8 (Z direction: Z-BLK). The size is 304128 bytes (= 33 (X direction) × 9216 (Y direction) × 8 (Z direction)).

  When the erase unit information ERSINFO is 1, the memory array of 8 (X direction: XERS) × 72 (Y direction: YERS) × 8 (Z direction: ZERS) has a low resistance at a time, and the erase data size is 576 bytes. (= 8 (X direction) × 72 (Y direction) × 8 (Z direction)).

  When the erase unit information ERSINFO is 1, the memory array of 16 (X direction: XERS) × 72 (Y direction: YERS) × 8 (Z direction: ZERS) has a low resistance at a time, and its erase data size is 1152 bytes. (= 16 (X direction) × 72 (Y direction) × 8 (Z direction)).

When the erase unit information ERSINFO is 1, the memory array of 32 (X direction: XERS) × 72 (Y direction: YERS) × 8 (Z direction: ZERS) has a low resistance at a time, and the erase data size is 2304 bytes. (= 32 (X direction) × 72 (Y direction) × 8 (Z direction)) In the case where the thermal buffer area information WALINFO is 1, a memory array for only one row in the X direction in one block, That is, a memory array of 1 (X direction: XWAL) × 9216 (Y direction) × 8 (Z direction) is set as the thermal buffer area WALL, and its size is 9216 bytes (= 1 (X direction) × 9216 (Y direction). × 8 (Z direction)).

  In the case where the thermal buffer area information WALINFO is 2, in one block, only two rows in the X direction, that is, 2 (X direction: XWAL) × 9216 (Y direction) × 8 (Z direction) memory The array is set as a thermal buffer area WALL, and its size is 18432 bytes (= 2 (X direction) × 9216 (Y direction) × 8 (Z direction)).

  In the case where the thermal buffer area information WALINFO is 2, in one block, the memory array for only three rows in the X direction, that is, the memory of 3 (X direction: XWAL) × 9216 (Y direction) × 8 (Z direction) The array is set as the thermal buffer area WALL, and its size is 27648 bytes (= 3 (X direction) × 9216 (Y direction) × 8 (Z direction)).

  In the block configuration when the block information BLKINFO is 1 and the combination of the thermal buffer area information WALINFO is 1, the thermal buffer area WALL is set for one line in the X direction to prevent thermal disturbance between adjacent blocks. Is done. In addition, since there is a 9216-byte thermal buffer area WALL in the 82944-byte block, the area for 73728 bytes becomes the write area WT-AREA, and the ratio of the write area of one block becomes 88.9%.

  In order to reduce the influence of thermal disturbance and improve reliability compared to the above block configuration, it is preferable to select a combination of block information BLKINFO of 1 and thermal buffer area information WALINFO of 2. In this case, the thermal buffer area WALL for two rows is set in the X direction between adjacent blocks, and the influence of thermal disturbance can be further reduced.

  Further, in order to realize a block configuration with a lower cost than the block configuration in the case where the combination of the block information BLKINFO of 1 and the thermal buffer area information WALINFO of 1 is selected, the block information BLKINFO is 2 and the thermal buffer area information WALINFO of It is better to select a combination of 1. In this case, since there is a 9216-byte thermal buffer area WALL in the 156672-byte block, 147456 bytes are the write area WT-AREA, and the ratio of the write area of one block is 94.1%.

  As described above, the specification of the nonvolatile memory to be used can be changed by the block configuration information BLKCFG to flexibly cope with the specifications required by the memory module NVMMD0 and the information processing system.

  In FIG. 6, the thermal buffer area WALL is an area for preventing a decrease in reliability due to thermal disturbance, and among the capacity of 92944 bytes of one block, the capacity of 9216 bytes of the thermal buffer area WALL is an area where data is not written. Data of eight physical addresses can be stored in the block, that is, one physical address can correspond to eight logical addresses in one block.

  In the block configuration shown in FIG. 6, the data for the capacity of the thermal buffer area WALL is restored and the capacity of one block is changed while maintaining the thermal buffer area WALL for high reliability by using FIGS. First, a writing method capable of effectively handling nine logical addresses in one block will be described. By this method, one block can effectively correspond to data of nine logical addresses LAD while preventing reliability degradation due to thermal disturbance by the thermal buffer area WALL, and a highly reliable, large capacity and low cost memory. A module (semiconductor device) NVMMD0 can be realized.

  In the block configuration shown in FIG. 6, the size of one physical address is 9216 bytes, and one block is 82944 bytes (= 9216 bytes × 9). That is, data of nine physical addresses can be effectively stored in one block.

  Further, the thermal buffer area information WALINFO in FIG. 9 indicates a memory array area as the thermal buffer area WALL. When the thermal buffer area information WALINFO is 1, a memory array for only one row in the X direction, that is, a memory array of 1 (X direction: XWAL) × 9216 (Y direction) × 8 (Z direction) is used as the thermal buffer area WALL. It is set and indicates that its size is 9216 bytes (= 1 (X direction) × 9216 (Y direction) × 8 (Z direction)).

  FIG. 7 shows a flow of a writing method that can effectively handle nine logical addresses in one block. First, FIG. 7 will be described.

  First, a write request to the logical addresses LAD0 to LAD8 and write data (8192 bytes / logical address) to the logical addresses LAD0 to LAD8 are sequentially generated from the information processing device (processor) CPU_CP to the control circuit MDLCT0.

  The information processing circuit MNGER sequentially writes data for 8192 bytes corresponding to each of the nine logical addresses LAD to the random access memory RAM through the memory control circuit RAMC (FIG. 7: Step 1).

  Next, the information processing circuit MNGER checks whether one block of data (8192 bytes × 9 LAD) has been written to the random access memory RAM (FIG. 7: Step 2). If one block of data has been written If not, Step 1 of FIG. 7 is performed. If data for one block has been written, Step 3 in FIG. 7 is performed.

  In Step 3 of FIG. 7, the data written in the random access memory RAM is read, and the data of the logical address whose all data bits of 8192 bytes are “1” is searched.

  In the next Step 4, it is checked whether the data size in which all data bits are “1” is 8192 bytes or more obtained by subtracting 1024 bytes of the spare area from the physical size 9216 bytes of the thermal buffer area WALL in one block. To do.

  In the block configuration of FIG. 6, the physical size of the thermal buffer area WALL in one block is 9216 bytes.

  If all data bits are “1”, it is checked whether the size of the data is N bytes (8192 bytes) or more. If it is N bytes or more, Step 9 is performed, and if it is less than N bytes, Step 5 is performed.

  In Step 9, the control circuit MDLCT0 assigns eight logical addresses LAD other than the logical address LAD in which all data bits of 8192 bytes are “1” to the physical address PAD of the write area WT-AREA of the nonvolatile memory.

  Further, the control circuit MDLCT0 stores all 1 flag A1FLG corresponding to the logical address LAD in which all data bits of 8192 bytes are “1” in the random access memory RAM, and all data bits of 8192 bytes are stored. The all-one flag A1FLG corresponding to the logical address LAD that is “1” is set to 1 (described in FIG. 10A).

  Next, in Step 10, data corresponding to eight logical addresses LAD other than the logical address LAD in which all data bits of 8192 bytes are “1” is written to the write area WT-AREA of the nonvolatile memory. In the next Setp11, the address conversion table (LPTBL) stored in the random access memory RAM is updated.

  Thus, since the data of the logical address LAD in which all data bits of 8192 bytes are “1” can be represented by “all 1 flag A1FLG = 1”, it is necessary to allocate to the write area WT-AREA of the nonvolatile memory. There is no.

  Therefore, the thermal buffer area WALL prevents the deterioration of reliability due to thermal disturbance, and the capacity of one block of 82944 bytes can correspond to the data corresponding to nine logical addresses LAD, and is a highly reliable, large capacity and low cost memory. A module (semiconductor device) NVMMD0 can be realized.

  In Step 5, all “1” data is generated such that all data bits of 8192 bytes are “1” by performing an operation on the data of the logical address LADX written in the random access memory RAM.

  Further, a data restoration method of the target logical address LADX is generated from the calculation method that generated all “1” data.

  In the next Step 6, it is checked whether the size of the data generated in Step 5 is N bytes (8192 bytes) or more.

  If the size of the data in which all data bits of the generated data are “1” is N bytes (8192 bytes) or more, Step 9 is performed, and if it is less than N bytes, Step 7 is performed.

  In Step 9, the logical address LADX that has been subjected to the operation is assigned to the physical address DPAD of the random access memory RAM, and a data restoration method corresponding to the logical address LADX obtained in Step 5 is stored in this physical address DPAD. Further, a logical address LAD other than the logical address LADX is assigned to the physical address PAD in the write area WT-AREA of the nonvolatile memory.

  Further, the calculation method for generating all “1” data and the method for restoring data corresponding to the logical address LADX obtained in Step 5 may be stored in the nonvolatile memory.

  By storing the calculation method and the restoration method in the nonvolatile memory, even if a sudden power interruption occurs, data is not lost, so that a highly reliable memory module can be provided.

  Thus, since the data of the logical address LADX that has been subjected to the operation can be restored by the restoration method stored in the physical address DPAD of the random access memory RAM, there is no need to assign it to the write area WT-AREA of the nonvolatile memory. Therefore, the thermal buffer area WALL prevents the deterioration of reliability due to thermal disturbance, and the capacity of one block of 82944 bytes can effectively correspond to the physical address data for nine logical addresses LAD. A low-cost memory module (semiconductor device) NVMMD0 can be realized.

  In Step 7, it is checked whether all “1” data in which all data bits of 8192 bytes are “1” is found or the block size for generation exceeds the maximum value BM.

  If the block size exceeds the maximum value BM, Step 12 is performed, and if not, Step 8 is performed.

  In Step 12, all “1” data in which all data bits of 8192 bytes are “1” in the data of the logical address LAD written to the random access memory RAM could not be found or generated. Thus, a logical address is assigned only to the physical address PAD of the write area WT-AREA of the nonvolatile memory.

  In Step 8, in order to make it easy to find or generate all “1” data in which all data bits of 8192 bytes are “1”, the block size is increased, and then Step 1 is executed again.

  The N bytes shown in Step 4 and Step 6 are programmable, indicate the data size of a logical address not assigned to the write area WT-AREA of the nonvolatile memory, and can be applied to a defective physical address in addition to the thermal buffer area WALL.

  FIG. 8A shows write data corresponding to logical addresses LAD0 to LAD8 written to the random access memory RAM.

  In FIG. 8A, Queue indicates a queue number, LAD indicates a logical address, DATA indicates write data (8192 bytes) corresponding to the logical address, and QVLD indicates whether the data of the queue number is valid or invalid. When QVLD is 1, it indicates valid, and when it is 0, it indicates invalid.

  Each of the logical addresses LAD0 to LAD8 corresponds to data Data0 to Data8, and the contents are indicated in hexadecimal notation for every 8 bytes in order from the 8191st byte to the 0th byte. For example, the data Data0 of the logical address LAD0 is 0001_0002_0003_0004... 0005_0006_0007_0008. The data Data4 of the logical address LAD4 has all the bits of 8192 bytes “1”, and the data Data7 of the logical address LAD7 has all the bits of 8192 bytes “0”.

    FIG. 10A shows an address conversion table (LPTBL) updated after the data shown in FIG. 8A is written to the nonvolatile memory.

  FIG. 10B shows to which physical address of the nonvolatile memory the data shown in FIG. 8A has been written.

  FIG. 10A will be described. The all 1 flag A1FLG is information indicating whether all data bits of the logical address LAD are “1”. When the all 1 flag A1FLG is 1, it indicates that all data bits of the logical address LAD are “1”, and other than that, it indicates that all data bits of the logical address LAD are not “1”.

  Used indicates that the data of the logical address LAD has been written to the physical address PAD of the write area WT-AREA of the non-volatile memory, or the restoration method for restoring the data of the logical address LAD is the write area WT-AREA. This is information indicating whether data has been written to the physical address PAD.

  When Used is 1, it indicates that the data of the logical address LAD has been written to the physical address PAD of the write area WT-AREA of the nonvolatile memory.

  When Used is other than 1, it indicates that the data of the logical address LAD is not written to the physical address PAD of the write area WT-AREA of the nonvolatile memory.

  RESTORE is information indicating whether restoration processing is required for the data of the logical address LAD. When RESTORE is 1, it indicates that the data at the logical address LAD needs to be restored, and when RESTORE is other than 1, it indicates that the data at the logical address LAD does not need to be restored.

  REFDEV is information indicating in which memory the data restoration method is stored. When REFDEV = 1, the data restoration method is stored in the random access memory RAM, and when REFDEV = 1, the data restoration method is stored in the nonvolatile memory.

  VLD is information indicating whether the correspondence between the logical address LAD and the physical address PAD of the nonvolatile memory or the physical address physical address DPAD of the random access memory RAM is valid or invalid. When VLD = 0, it indicates that the correspondence between the logical address LAD and the physical address PAD or the physical address DPAD is invalid.

  When VLD = 1, the correspondence between the logical address LAD and the physical address PAD or the physical address DPAD is valid, and the data of the logical address LAD is the latest data and is not used for data restoration of other logical addresses LAD. Indicates.

  When VLD = 2, the correspondence between the logical address LAD and the physical address PAD or the physical address DPAD is valid, and the data of the logical address LAD is the latest data and is used for data restoration of other logical addresses LAD. Indicates.

  When VLD = 3, the correspondence between the logical address LAD and the physical address PAD or the physical address DPAD is valid, and the data of the logical address LAD is old data but is used for data restoration of other logical addresses LAD. It shows that.

  RESLAD is information indicating which logical address LAD the data of the logical address LAD is used for.

  PAD / DPAD indicates the physical address of the nonvolatile memory or the physical address of the random access memory RAM.

  Since all 1 flag A1FLG of logical address LAD4 in FIG. 10A is 1 and USED is 0, all bits of data of logical address LAD4 are “1”, and this data is physical address PAD of write area WT-AREA of the nonvolatile memory. Indicates that it has not been written to.

  Also, since the all 1 flag A1FLG of the logical addresses LAD0, 1, 2, 3, 5, 6, 7, and 8 in FIG. 10A is 0 and USED is 1, these logical addresses LAD0, 1, 2, 3, 5, 6 , 7 and 8 indicate that data has been written to the physical addresses PAD 18, 19, 20, 21, 22, 23, 24, 25 of the write area WT-AREA of the nonvolatile memory.

  The information processing circuit MNGER reads all 1 flag A1FLG = 1 and RESTORE = 1 with respect to the logical address LAD4, thereby generating data in which all bits of 8192 bytes are set to “1”, and the data Data4 of the logical address LAD4 is generated. Can be restored.

  FIG. 10B will be described. FIG. 10B shows a block of a chain memory array including physical addresses PAD18, 19, 20, 21, 22, 23, 24, and 25, and data Data0, 1, 2, 3, and 5 of FIG. 8A written to these physical addresses. , 6, 7 and 8 are shown.

  The area in the block corresponding to the physical addresses PAD18 to 25 is the 0th to 7th chain memory arrays in the X direction and the 0th to 9215th chain memory arrays in the Y direction, and the data size of each physical address is 9216 bytes (= 1) (X direction) × 9216 (Y direction) × 8 (Z direction)).

  The physical addresses PAD18 to 21 store the data Data0 to Data3 of the logical address LAD0 and the ECC codes ECC0 to ECC3 of the data Data0 to Data3, respectively. The physical addresses PAD22 to 25 store the data Data5 to Data8 of the logical address LAD5 and the ECC codes ECC5 to ECC8 of the data Data5 to Data8, respectively.

  Data Data4 of logical address LAD4 is not written to the nonvolatile memory.

  As described above, the information processing circuit MNGER can quickly restore the data corresponding to the capacity of the thermal buffer area WALL by reading the all 1 flag A1FLG = 1 for the logical address LAD. While preventing deterioration in reliability due to disturbance, the capacity of one block of 82944 bytes can correspond to physical address data for nine logical addresses LAD, and a large-capacity and low-cost memory module (semiconductor device) NVMMD0 can be realized. .

  FIG. 8B shows write data corresponding to the logical addresses LAD9 to LAD17 written to the random access memory RAM.

  8B, Queue indicates a queue number, LAD indicates a logical address, DATA indicates write data (8192 bytes) corresponding to the logical address, and QVLD indicates whether the data of the queue number is valid or invalid. When QVLD is 1, it indicates valid, and when it is 0, it indicates invalid.

  Each of the logical addresses LAD9 to LAD17 corresponds to data Data9 to Data17, and the contents thereof are shown in hexadecimal notation for every 8 bytes in order from the 8191st byte to the 0th byte. For example, the data Data9 of the logical address LAD9 is FFFF_FFFF_FFFF_FFFF... FFFF_FFFF_FFFF — 1023, all bits of the data from the 8191st byte to the 4th byte are “1”, and the data from the 3rd byte to the 0th byte is 16 The decimal number is 1023.

  The data Data10 of the logical address LAD10 is 0000 — 0000 — 0000 — 0000... 0000 — 0000 — 0000_E478, all bits of data from the 8191st byte to the 4th byte are “0”, and the data from the 3rd byte to the 0th byte is 16 It is E478 in decimal.

  Further, in the data Data17 of the logical address LAD17, all bits of data from the 8191st byte to the 1st byte are “0”, and the data up to the 0th byte is 1 in hexadecimal.

  FIG. 11A shows an address conversion table (LPTBL) updated after the data shown in FIG. 8B is written to the nonvolatile memory.

  FIG. 11B shows to which physical address of the nonvolatile memory the data shown in FIG. 8B has been written.

  Since the all 1 flag A1FLG of the logical address LAD9 in FIG. 11A is 0, USED is 0, RESTOR is 1, PAD / DPAD is 128, REFDEV is 1, and VLD is 1, the data of the logical address LAD9 is nonvolatile memory. Indicates that data is not written to the physical address PAD of the write area WT-AREA. Further, it is necessary to restore the data of the logical address LAD9. Further, since the all 1 flag A1FLG is 0, it can be seen that the restoring method is stored in the physical address DPAD128 of the random access memory RAM. Also, since the logical address LAD10 is 0 for all 1 flag A1FLG, 1 for USED, 0 for RESTORE, 0 for PAD / DPAD, 2 for VLD, 0 for REFDEV, and 9 for RESLAD, It can be seen that the data is written to the physical address PAD0 in the write area WT-AREA of the nonvolatile memory. Further, it can be seen that the data of the logical address LAD10 is used for data restoration of the logical address LAD9.

  FIG. 11A shows a case where data of another logical address is used for data restoration of the logical address LAD9. However, for data restoration, a plurality of logical addresses other than the logical address for data to be restored are used. Data may be used. By using the data of a plurality of logical addresses for data restoration, it becomes easy to restore data more than the capacity of the thermal buffer area WALL.

  Further, since the USED of each of the logical addresses LAD11, 12, 13, 14, 15, 16, 17 is 1 and PAD / DPAD0, 1, 2, 3, 4, 5, 6, 7, the logical addresses LAD11, 12 , 13, 14, 15, 16, and 17 indicate that data has been written to the physical addresses PAD0, 1, 2, 3, 4, 5, 6, and 7 in the write area WT-AREA of the nonvolatile memory. .

  Further, a method for restoring data of the logical address LAD9 may be stored in a nonvolatile memory. By storing this restoration method in a non-volatile memory, data is not erased, so that it is possible to cope with sudden power interruption and to provide a highly reliable memory module.

  FIG. 11B will be described. FIG. 11B shows a block of the chain memory array including the physical addresses PAD0 to 7 and the data Data10 to 17 of FIG. 8B written to these physical addresses.

  The area in the block corresponding to the physical addresses PAD0 to 7 is the 0th to 7th chain memory arrays in the X direction and the 0th to 9215th chain memory arrays in the Y direction, and the data size of each physical address is 9216 bytes (= 1) (X direction) × 9216 (Y direction) × 8 (Z direction)).

  The physical addresses PAD0 to 7 store data Data10 to Data17 of the logical addresses LAD10 to 17, and respective ECC codes ECC10 to ECC17. Data Data9 of logical address LAD9 is not written to the nonvolatile memory.

  As described above, even if the data bits of the logical address LAD are not all “1”, the data at the logical address other than the logical address for the data to be restored is used for the data restoration. Since data corresponding to the capacity of the buffer area WALL can be restored, the thermal buffer area WALL prevents the deterioration of reliability due to thermal disturbance, and the capacity of one block of 82944 bytes corresponds to data of physical addresses for nine logical addresses LAD. Therefore, a large-capacity and low-cost memory module (semiconductor device) NVMMD0 can be realized.

  FIG. 11C shows another example of the address conversion table (LPTBL) updated after the data shown in FIG. 8B is written to the nonvolatile memory.

  FIG. 11D is another example showing to which physical address of the nonvolatile memory the data shown in FIG. 8B has been written.

  Each value of the address translation table (LPTBL) relating to the logical addresses LAD9 to 16 in FIG. 11C is the same as that in FIG. 11A. An address conversion table (LPTBL) relating to the logical address LAD17 will be described.

  Since all 1 flag A1FLG is 0, USED is 0, RESTROR is 1, PAD / DPAD is 129, REFDEV is 1, and VLD is 1, the data of logical address LAD17 is stored in the write area WT-AREA of the nonvolatile memory. This indicates that data has not been written to the physical address PAD.

Further, it is necessary to restore the data of the logical address LAD17. Furthermore, since the all 1 flag A1FLG is 0, it can be seen that the restoring method is stored in the physical address DPAD129 of the random access memory RAM.
Since the logical addresses LAD10, 11, 12, 13, 14, 15, and 16 have a USED of 1 and PAD / DPAD0, 1, 2, 3, 4, 5, and 6, respectively, the logical addresses LAD10, 11, 12 , 13, 14, 15, and 16 indicate that data has been written to the physical addresses PAD0, 1, 2, 3, 4, 5, and 6 in the write area WT-AREA of the nonvolatile memory.

  Further, the data restoring method of the logical addresses LAD9 and 17 may be stored in the nonvolatile memory. By storing this restoration method in a non-volatile memory, data is not erased, so that it is possible to cope with sudden power interruption and to provide a highly reliable memory module.

  FIG. 11D will be described. FIG. 11D shows a block of the chain memory array including the physical addresses PAD0 to 7 and the data Data10 to 16 of FIG. 8B written to these physical addresses.

  The area in the block corresponding to the physical addresses PAD0 to 7 is the 0th to 7th chain memory arrays in the X direction and the 0th to 9215th chain memory arrays in the Y direction, and the data size of each physical address is 9216 bytes (= 1) (X direction) × 9216 (Y direction) × 8 (Z direction)).

  The physical addresses PAD0 to 6 store the data Data10 to Data16 of the logical addresses LAD10 to 16 and the respective ECC codes ECC10 to ECC16.

  Further, when reading data stored in the physical address PAD7, since the number of bits causing an error is large, the physical address PAD7 is registered in the defective physical address table BADPADTBL as a defective physical address to which data cannot be written.

  Data Data9 of logical address LAD9 and data Data17 of logical address LAD17 are not written to the nonvolatile memory.

  As described above, the data bits of the logical address LAD are not all “1”, and the data restoration is performed without using the data of the logical address other than the logical address for the data to be restored, that is, The data can be restored at high speed without reading the data stored in the physical address PAD.

  Furthermore, since the data corresponding to the capacity of the defective physical address as well as the thermal buffer area WALL can be restored, the capacity of 92944 bytes of one block corresponds to nine logical addresses LAD while preventing the reliability deterioration due to the thermal disturbance and the defective physical address. A memory module (semiconductor device) NVMMD0 that can deal with data of a physical address and has a large capacity and low cost can be realized.

  FIG. 12A shows an operation code ARITH_CODE prepared for restoring data stored in the random access memory RAM.

  FIG. 12B shows a data restoration method using the operation code ARITH_CODE shown in FIG. 12A.

  First, FIG. 12A will be described.

  The operation code ARITH_CODE includes a 4-bit instruction code ICODE, a 2-bit target data type UDT, a 1-bit priority operation presence / absence PRI, and a 1-bit operation end EFLAG.

  The instruction code ICODE can prepare 16 types of operations. In FIG. 12, 12 types of operations are prepared, and the rest can be added as necessary.

  When the target data type UDT is 10, it indicates that the data used for the data restoration calculation is stored in the physical address PAD of the nonvolatile memory. When the target data type UDT is 11, the data used for the data restoration calculation is adjusted. Data ADJ_DATA is used, and 00 or 01 indicates that the above data is not used for data restoration calculation.

  When the presence / absence of the priority calculation PRI is 0, the current calculation is preferentially executed, and when it is 1, the subsequent calculation is preferentially executed.

  When the calculation end EFLAG is 0, the calculation is continued, and when it is 1, all the calculations are ended.

  FIG. 12B will be described.

  FIG. 12B shows a method of restoring the data Data9 of the logical address LAD9 generated in Step 5 of the flow of the writing method shown in FIG. 7 using the data shown in FIG. 8B.

  In Step 5 of FIG. 7, first, an operation method for generating all “1” data is obtained, and further, a restoration method for the data Data9 of the logical address LAD9 is obtained.

  The calculation method when all “1” data is generated using the data Data9 of the logical address LAD9, the data Data10 of the LAD10, and the adjustment data ADJ_DATA0B68 is as follows.

(Formula 1) ―――― ALL1 = LAD9 (Data9) + LAD10 (Data10) + ADJ_DATA (0B64)
Further, when a method for restoring the data Data9 of the target logical address LAD9 is obtained from the calculation method for generating all “1” data,
(Formula 2) ―――― LAD9 (Data9) = (ALL1−ADJ_DATA (0B64)) − LAD10 (Data10)
It becomes.

  FIG. 12B shows (Formula 2). This (Formula 2) is stored in the physical address 128 of the random access memory RAM in Step 9 of FIG. 7, and is updated in Step 11 of FIG. (LPTBL) is the address conversion table (LPTBL) shown in FIG. 11A. At this time, the data Data10 of the logical address LAD10 is stored in the physical address PAD0 as shown in FIG. 11A.

  FIG. 12C will be described. FIG. 12C shows a method for restoring the data Data17 of the logical address LAD17 generated in Step 5 of the flow of the writing method shown in FIG. 7 using the data shown in FIG. 8B.

  In Step 5 of FIG. 7, first, an arithmetic method for generating all “1” data is obtained, and further, a restoration method for the data Data17 of the logical address LAD17 is obtained.

  The operation method when all “1” data is generated using the data Data17 of the logical address LAD17 and the adjustment data ADJ_DATA0001 is as follows.

(Equation 3) ----- ALL1 = bit inversion {LAD17 (Data17)} + ADJ_DATA (0001)
Further, when a method for restoring the data Data17 of the target logical address LAD17 is obtained from the calculation method that generated all “1” data,
(Formula 4) ―――― LAD17 (Data17) = Bit inversion {(ALL1 −
ADJ_DATA (0001))}
It becomes.

  FIG. 12C shows (Formula 4). This (Formula 4) is stored in the physical address 129 of the random access memory RAM at Step 9 in FIG. 7, and is updated at Step 11 in FIG. (LPTBL) is the address conversion table (LPTBL) shown in FIG. 11C.

  A method for reading data of the logical address LAD4 performed by the control circuit MDLCT0 will be described with reference to FIGS. 13, 10A, and 10B. First, the information processing device (processor) CPU_CP issues a read request to the logical address LAD4 to the control circuit MDLCT0 (FIG. 13: Step 1).

Next, the control circuit MDLCT0 reads the A1FLG value, USED value, RESTORE value, PAD / DPAD value, and VLD value corresponding to the logical address LAD4 from the address conversion table (LPTBL) in FIG. 10A (FIG. 13: Step 2). Each value is checked (FIG. 13: Step 3). Since A1FLG value = 1, USED value = 0, RESTORE value = 1, and VLD value = 1, all the bits of the data of logical address LAD4 are 1, and are written to the physical address PAD in the nonvolatile memory You can see that it is not.
Therefore, the control circuit MDLCT0 generates ALL1 data in which all bits of 8192 bytes are set to “1”, restores the data Data4 of the logical address LAD4, and outputs the data of ALL1 to the information processing device (processor) CPU_CP. (FIG. 13: Step 4). At this time, since the control circuit MDLCT0 does not need to access the non-volatile memory, it can transfer data to the information processing device (processor) CPU_CP at high speed and with low power.

  Next, a method for reading data of the logical address LAD1 performed by the control circuit MDLCT0 will be described with reference to FIGS. 13, 10A, and 10B.

  First, a read request to the logical address LAD1 is generated from the information processing device (processor) CPU_CP to the control circuit MDLCT0 (FIG. 13: Step 1).

Next, the control circuit MDLCT0 reads the A1FLG value, USED value, RESTORE value, PAD / DPAD value, VLD value, REFDEV value, and RESLAD value corresponding to the logical address LAD1 from the address conversion table (LPTBL) in FIG. 13: Step 2), each value is checked (FIG. 13: Step 3). Since A1FLG value = 0, USED value = 0, RESTORE value = 0, PAD / DPAD value = 19, VLD value = 1, REFDEV value = 0,
The control circuit MDLCT0 reads the data Data1 and the ECC code ECC1 from the physical address PAD19 of the nonvolatile memory, and performs an error check. If an error is detected, error correction is performed using the ECC code, and data Data1 is restored (FIG. 13: Step 5).
In the next Step 6, the control circuit MDLCT0 checks whether the RESTORE value is 1. Since the RESTORE value is 0, the control circuit MDLCT0 transfers the data Data1 read from the physical address PAD19 of the nonvolatile memory to the information processing device (processor) CPU_CP (Step 8).

  Next, a method for reading data of the logical address LAD9 performed by the control circuit MDLCT0 will be described with reference to FIGS. 13, 11A, and 11B.

  First, the information processing device (processor) CPU_CP issues a read request to the logical address LAD9 to the control circuit MDLCT0 (FIG. 13: Step 1).

  Next, the control circuit MDLCT0 reads the A1FLG value, USED value, RESTORE value, PAD / DPAD value, VLD value, REFDEV value, and RESLAD value corresponding to the logical address LAD9 from the address conversion table (LPTBL) of FIG. 11A ( FIG. 13: Step 2), each value is checked (FIG. 13: Step 3). Since A1FLG value = 0, USED value = 0, RESTORE value = 1, PAD / DPAD value = 128, VLD value = 1, and REFDEV value = 1, the data of logical address LAD9 is ALL1 data in which all bits are 1. However, it is not written in the physical address in the non-volatile memory, and it can be seen that the data restoration arithmetic expression of the logical address LAD9 is stored in the physical address DPAD128 of the random access memory RAM.

  Next, the control circuit MDLCT0 reads data from the physical address DPAD128 of the random access memory RAM (FIG. 13: Step 5). In the next Step 6, it is checked whether or not the RESTORE value is 1. Since the RESTORE value is 1, Step 7 is executed.

  At Step 7, the data restoration arithmetic expression of the logical address LAD9 stored in the physical address DPAD128 of the random access memory RAM shown in FIG. 12B is read, and the data of the logical address LAD9 is read according to the data restoration arithmetic expression (Equation 2). To restore.

  Specifically, a difference SUB1 between the ALL1 data in which all bits of 8192 bytes are 1 and the adjustment data ADJ_DATA (0B64) is obtained. Next, a difference SUB2 between the difference SUB1 and the data stored in the physical address PAD10 is obtained, and this SUB2 is transferred to the information processing device (processor) CPU_CP (Step 8).

  In this manner, even if the data bits of the logical address LAD are not all “1” by the restoration operation formula, the data of the logical address LAD9 can be restored from the data of the other logical address LAD10. Thus, while preventing reliability degradation due to thermal disturbance, one block capacity 82944 bytes can store physical addresses for nine logical addresses LAD, can reduce wasteful capacity, and low-cost memory module (semiconductor device) NVMMD0 realizable.

  Next, a method for reading data of the logical address LAD17 performed by the control circuit MDLCT0 will be described with reference to FIGS. 13, 11C, and 11D.

  First, a read request to the logical address LAD17 is generated from the information processing device (processor) CPU_CP to the control circuit MDLCT0 (FIG. 13: Step 1).

  Next, the control circuit MDLCT0 reads the A1FLG value, the USED value, the RESTORE value, the PAD / DPAD value, the VLD value, the REFDEV value, and the RESLAD value corresponding to the logical address LAD17 from the address conversion table (LPTBL) in FIG. 11A ( FIG. 13: Step 2), each value is checked (FIG. 13: Step 3). Since A1FLG value = 0, USED value = 0, RESTORE value = 1, PAD / DPAD value = 129, VLD value = 1, and REFDEV value = 1, the data of logical address LAD17 is ALL1 data in which all bits are 1. However, it is not written in the physical address in the non-volatile memory, and it can be seen that the data restoration arithmetic expression of the logical address LAD17 is stored in the physical address DPAD129 of the random access memory RAM.

  Next, the control circuit MDLCT0 reads data from the physical address DPAD129 of the random access memory RAM (FIG. 13: Step 5). In the next Step 6, it is checked whether or not the RESTORE value is 1. Since the RESTORE value is 1, Step 7 is executed.

  At Step 7, the data restoration arithmetic expression of the logical address LAD17 stored in the physical address DPAD129 of the random access memory RAM shown in FIG. 12C is read, and the data of the logical address LAD17 is read according to this data restoration arithmetic expression (Formula 4). To restore.

  Specifically, the difference SUB3 between the ALL1 data in which all the bits of 8192 bytes are 1 and the adjustment data ADJ_DATA (0001) is obtained. Next, INVD3 obtained by bit-inverting the data of the difference SUB3 is obtained, and this INVD3 is transferred to the information processing device (processor) CPU_CP (Step 8).

  As described above, even if the data of the logical address LAD17 is not all “1” data, the logical address other than the logical address corresponding to the data to be restored is restored. The data can be restored at high speed without using the data of the data, that is, without reading the data stored in the physical address PAD, and the thermal buffer area WALL prevents the deterioration of the reliability due to the thermal disturbance. The capacity 82944 bytes can store physical addresses for nine logical addresses LAD, can reduce useless capacity, and can realize a low-cost memory module (semiconductor device) NVMMD0.

(Summary)
The main effects obtained by the respective embodiments described above are as follows.

  First, the memory cells in the plurality of chain memory arrays CY can be made low resistance at the same time, and the erase data rate can be improved.

  Second, after erasing the chain memory array CY, data “0” is simultaneously written into the memory cells in the plurality of chain memory arrays CY, so that the writing speed can be improved.

  Third, since data can be read from the memory cells in the plurality of chain memory arrays CY at the same time, the reading speed can be improved.

  Fourth, after all the states in the set state and the reset state are collectively written (after erasure) to all the memory cells in the chain memory array CY, the other state is set to a specific memory. By using a method for writing to a cell, a stable write operation can be realized.

  Fifth, the existence of the memory array CYH between the write areas WT-AREA provides a highly reliable memory module that can write and hold data in the write area WT-AREA with high reliability without affecting thermal disturbance. it can.

  Sixth, the first data input from the outside of the semiconductor device and the first calculation are performed to generate the second data. Since the second data is not written to the write area WT-AREA, the memory array CYH is present. Thus, it is possible to handle data larger than the amount of data that can be physically held in the write area WT-AREA, and to provide a low-cost and highly reliable memory module.

  Seventh, the first data input from the outside of the semiconductor device and the first calculation are performed to generate the second data. Since the second data is not written to the write area WT-AREA, a defective physical address is present. Thus, it is possible to handle data larger than the amount of data that can be physically held in the write area WT-AREA, and to provide a low-cost and highly reliable memory module.

  Eighth, how to arrange the memory array CYH can be programmed into the initial setting area in the non-volatile memory device, and flexible according to the level of function, performance and reliability required of the memory module NVMMD0 It can correspond to.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, the above-described embodiment has been described in detail for easy understanding of the present invention, and is not necessarily limited to one having all the configurations described. Further, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. . In addition, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment. In the embodiments, the phase change memory has been mainly described as a representative, but a resistance change type memory including a ReRAM or the like can be similarly applied to obtain the same effect.

  In the embodiment, the description has been given by taking as an example a memory having a three-dimensional structure in which a plurality of memory cells are sequentially stacked in the height direction with respect to the semiconductor substrate. The same effect can be obtained by applying the same to a two-dimensional memory in which one memory cell is arranged.

  ADCMDIF ... Address / command interface circuit, ARB ... Arbitration circuit, ARY ... Memory array, BK ... Memory bank, BL ... Bit line, BSW ... Bit line selection circuit, BUF ... Buffer, CADLT ... Column address latch, CH ... Chain control line , CHDEC ... chain decoder, CHLT ... chain selection address latch, CL ... phase change memory cell, COLDEC ... column decoder, PAD ... physical address, CPAD ... physical address, CPU_CP ... information processing device (processor), CPVLD ... valid flag, CTLOG ... Control circuit, CY ... Chain memory array, DATCTL ... Data control circuit, DBUF ... Data buffer, DSW ... Data selection circuit, DT ... Data line, ENUM ... Entry number, HDH_IF ... Interface Signal, HOST_IF ... interface circuit, IOBUF ... IO buffer, LAD ... logical address, LRNG ... logical address area, LPTBL ... address conversion table, LY ... memory cell selection line, LYC ... layer number, LYN ... data write layer information, MAPREG ... Map register, MDLCT ... Control circuit, MNERC ... Minimum erase count, MNGER ... Information processing circuit, MNIPAD ... Invalid physical offset address, MNVPAD ... Valid physical offset address, MXERC ... Maximum erase count, MXIPAD ... Invalid physical offset address, MXVPAD ... Valid Physical offset address, NVCT ... Memory control circuit, NVM ... Non-volatile memory device, NVMMD ... Memory module, NVREG ... Erase size designation register, NXLYC ... Ear number, NXPAD ... write physical address, NXPADTBL ... write physical address table, NXPERC ... erase count, NXPTBL ... write physical address table, NXPVLD ... valid flag, PSEGTBL ... physical segment table, PAD ... physical address, PADTBL ... physical address table, PERC: Erase count, PPAD: Physical offset address, PRNG: Physical address area, PVLD: Valid flag, R: Memory element, RADLT: Row address latch, RAM: Random access memory, RAMC: Memory control circuit, REF_CLK: Reference clock signal REG: Register, ROWDEC: Row decoder, RSTSIG: Reset signal, SA: Sense amplifier, SGAD: Physical segment address, SL: Chain memo Rear array selection line, STREG ... status register, SWB ... read / write control block, SYMD ... clock generation circuit, Tch ... chain selection transistor, Tcl ... memory cell selection transistor, THMO ... temperature sensor, TNIPA ... total number of invalid physical addresses, TNVPA ... valid physical Total number of addresses, WDR: write driver, WL: word line, WV: write data verification circuit.

Claims (12)

A non-volatile memory unit;
A control circuit that assigns a physical address to an input logical address and accesses the physical address of the nonvolatile memory unit;
The nonvolatile memory unit is
A first signal line;
A second signal line intersecting the first signal line;
A memory cell group disposed at an intersection of the first signal line and the second signal line;
Have
Each of the memory cell groups is
N memory cells (N is an integer of 1 or more);
N memory cell selection lines for selecting the N memory cells, respectively.
The control circuit includes:
A memory cell group arranged adjacent to each other is defined as a first region, and M (N is an integer of 1 to N) in the N memory cells in each of the memory cell groups in the first region. For the first logic level,
After writing the first logic level to the first area, write a second logic level different from the first logic level to the memory cells included in the first area;
Performing a first calculation method on the first data corresponding to the first logical address input to the control circuit to generate second data;
2. A semiconductor device according to claim 1, wherein a physical address in the first area for the first data corresponding to the first logical address is not assigned. The semiconductor device according to claim 1,
The control circuit uses the first calculation method,
A semiconductor device that generates the method for restoring the first data. The semiconductor device according to claim 2,
The semiconductor device includes a random access memory unit,
The control circuit stores the restoration method in a random access memory. The semiconductor device according to claim 2,
The semiconductor device detects information indicating that the first data corresponding to the first logical address needs to be restored, and restores the first data. The semiconductor device according to claim 4 ,
The semiconductor device includes a random access memory unit,
Information indicating that the restoration process is necessary is stored in the random access memory unit. The semiconductor device according to claim 1,
2. A semiconductor device according to claim 1, wherein a group of memory cells arranged adjacent to the outer periphery of the first region is a second region, and the first logic level is not written to the second region. A non-volatile memory unit;
A control circuit that assigns a physical address to an input logical address and accesses the physical address of the nonvolatile memory unit;
The nonvolatile memory unit is
A first signal line;
A second signal line intersecting the first signal line;
A memory cell group disposed at an intersection of the first signal line and the second signal line,
Each of the memory cell groups is
N memory cells (N is an integer of 1 or more);
N memory cell selection lines for selecting the N memory cells, respectively.
The control circuit includes:
A memory cell group arranged adjacent to each other is defined as a first region, and M (N is an integer of 1 to N) in the N memory cells in each of the memory cell groups in the first region. For the first logic level,
After writing the first logic level to the first area, write a second logic level different from the first logic level to the memory cells included in the first area;
Performing a second operation method on the first data for the first logical address and the second data for the second logical address input to the control circuit, and generating third data;
Assigning a first physical address in a first area for the first data to the first logical address, and writing the second logical level in the first data;
2. A semiconductor device according to claim 1, wherein a physical address in the first area for the second data corresponding to the second logical address is not allocated. The semiconductor device according to claim 7 ,
The control circuit uses the second calculation method,
A semiconductor device that generates the method for restoring the first data. The semiconductor device according to claim 8 ,
The semiconductor device includes a random access memory unit,
The control circuit stores the restoration method in a random access memory. A non-volatile memory unit;
A control circuit that assigns a physical address to an input logical address and accesses the physical address of the nonvolatile memory unit;
The nonvolatile memory unit is
A first signal line;
A second signal line intersecting the first signal line;
A memory cell group disposed at an intersection of the first signal line and the second signal line,
Each of the memory cell groups is
N memory cells (N is an integer of 1 or more);
N memory cell selection lines for selecting the N memory cells, respectively.
The control circuit includes:
A memory cell group arranged adjacent to each other is defined as a first region, and M (N is an integer of 1 to N) in the N memory cells in each of the memory cell groups in the first region. For the first logic level,
After writing the first logic level to the first area, write a second logic level different from the first logic level to the memory cells included in the first area;
The control circuit outputs all 1 flag information indicating that the third data is all 1 if all the third data for the third logical address input to the control circuit is the first logic level. Level,
A semiconductor device, wherein a physical address in the first area for the third data for the third logical address is not allocated. The semiconductor device according to claim 10 .
The semiconductor device includes a random access memory unit,
The all-one flag information is stored in the random access memory unit. The semiconductor device according to claim 10 .
When the data read request for the third logical address is input, the control circuit accesses the nonvolatile memory unit if the all-one flag information for the third logical address is the first logical level. Rather, all the data for the third logical address is set to the first logical level and output.

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