WO2017013799A1

WO2017013799A1 - Computer and control method for controlling computer

Info

Publication number: WO2017013799A1
Application number: PCT/JP2015/071014
Authority: WO
Inventors: 静香二宮; 厚浦山; 正文大桃; 輝昌上畑
Original assignee: 株式会社日立製作所
Priority date: 2015-07-23
Filing date: 2015-07-23
Publication date: 2017-01-26

Abstract

This computer includes: a multi-core processor having multiple processor cores; a memory; and firmware. The processor cores include: an execution mode for switching between a first mode in which an application or an operating system is executed and a second mode in which processing is executed by the firmware in response to a predetermined interrupt; and a power-saving function for setting one of a power-saving-enabled mode in which the power consumption of the processor cores is reduced and a power-saving-disabled mode in which the processor cores are caused to operate at or higher than a rated power thereof. Upon receipt of the predetermined interrupt to the processor cores, core processors to be operated in the power-saving-disabled mode are selected from among the multiple processor cores, and the selected processor cores are caused to transit to the second mode in order to cause the processing by the firmware to be executed.

Description

Computer and computer control method

The present invention relates to execution of firmware in a computer equipped with a multi-core CPU.

A multi-core CPU is a CPU including a plurality of CPU cores or logical CPUs internally although it is apparently one CPU package. The multi-core CPU improves performance in an environment where parallel processing is executed. In most computer systems used in the field of workstations and servers that require high performance, multi-core CPUs are employed. In recent years, multi-core CPUs are also used in general personal computers.

In general-purpose computer systems, an OS (Operating System) is introduced in order to perform a variety of processes in the computer system, and a mode in which a large number of tasks are switched on the OS is widely known. Computers equipped with a plurality of multi-core CPUs use, for example, Microsoft Windows, Linux, UNIX, or the like as an SMP (symmetric multiprocessing) OS.

A computer system equipped with a multi-core CPU adopting the Intel architecture (x86) has an execution mode called SMM (system management mode) in addition to a mode for executing an application or OS. The SMM provides an environment that can be used only by firmware such as BIOS, and provides an independent environment that cannot be accessed from a user program including an OS.

The SMM executes predetermined processing in an area dedicated to SMM set in advance in a memory space, triggered by a hardware interrupt having the highest priority called SMI (system management interrupt) (for example, Patent Document 2). 3).

Events that cause SMI include hardware failure detection such as whether or not the computer system memory can be corrected, and whether or not the platform can be corrected. When SMI occurs, the execution mode of the multi-core CPU transitions to SMM, and control shifts from the OS to the SMI handler on the firmware. As an example of SMM processing, the firmware acquires register values of all CPU cores, register values of devices connected to the computer, and transfers them to an external storage device. When the transfer is completed, the firmware returns from the SMM, and the OS processing is resumed (for example, Patent Document 3).

JP 2002-99436 A Special table 2010-535384 gazette International Publication No. 2012/114463

The latest Intel CPU supports an advanced power saving function (for example, Patent Document 1). In the ACPI (Advanced Configuration and Power Interface), which is a standard for power management, “C state” is defined as an index representing the power saving state of the CPU. A C state having a high power saving effect is called a deep C state. It takes a delay of several ms to return the CPU operation mode from the deep C state to the C0 state, which is a normal operation, and the deep C state with higher power saving effect takes longer time to return to the C0 state.

For example, INTEL Haswell-EX CPU supports C0, C1, C3, and C6 as the C state of the logical CPU, C0, C1, C3, and C6 as the C state of the physical CPU core, and C in the CPU package. C0, C2, C3, and C6 are supported as states. The C state becomes a state with higher power saving effect as the number after “C” increases. For example, the C state number increases as the operation clock decreases, and the C state number increases as the supply voltage decreases. A power saving state having a large C state number is defined as a deep C state.

The logical CPU that has received the SMI shifts to a special execution mode called SMM, and executes the SMI processing set in advance by the system firmware.

In the SMI process of the system firmware, all logical CPUs are first waited and a logical CPU to be executed on behalf of subsequent processes is selected. The waiting of the logical CPU is to wait until the SMI is notified to all the logical CPUs, and the logical CPU in the power saving state such as the sleep state transitions (or returns) to the C0 state which is the operating state. When all the logical CPUs transition to the C0 state, the waiting is completed, and a logical CPU to be executed on behalf of subsequent processing is selected. A logical CPU executed on behalf of subsequent processing is referred to as BSP (Boot Strap Processor).

In a computer system having an SMP configuration equipped with a plurality of multi-core CPUs having a power saving function, the C state of each CPU is likely to be non-uniform depending on the operating status. For this reason, when the SMI occurs, the logic CPU in the power saving state other than the C0 state has a different time for returning from the deep C state to the C0 state, and the logic CPU in the power saving state other than the C0 state is different from the logic CPU in the power saving state other than the C0 state. In the CPU, variations occur in the time to reach the SMI waiting process.

For this reason, in the computer system having the conventional multi-core CPU, the time until the start of BSP selection in SMI processing is delayed by the arrival time of waiting for the logical CPU returning from the deep C state, and the OS interruption time also increases. There was a problem.

The present invention is a computer including a multi-core processor having a plurality of processor cores, a memory, and firmware. The processor core performs processing of firmware by a first mode for executing an application or OS, and a predetermined interrupt. One of an execution mode for switching to a second mode for executing the power saving, a power saving effective mode for reducing the power consumption of the processor core, and a power saving invalid mode for operating the processor core at a rating or above the rating. And when the predetermined interrupt is received, the processor core selects a processor core that operates in a power saving invalid mode from the plurality of processor cores, and the selected processor core To the second mode to execute the firmware process. Make.

According to the present invention, in a computer equipped with a multi-core processor, even when the power saving state of the processor core (logical CPU) is not uniform, the processor core in which the power saving state is invalid is selected and the second mode (SMM) is selected. To move to. As a result, there is no need to wait for a return from the deep C state, which has a high power saving effect, and the influence of delay can be eliminated. Thereby, it is possible to suppress an increase in the time during which the execution of the OS is interrupted due to the occurrence of a predetermined interrupt such as SMI.

1 is a block diagram illustrating an example of a computer system according to a first embodiment of this invention. FIG. It is a time chart which shows a 1st Example of this invention and shows an example of SMI processing from SMI generation | occurrence | production to the end of SMI processing. It is a figure which shows 1st Example of this invention and shows an example of a C state table. It is a flowchart figure which shows a 1st Example of this invention and shows an example of SMI processing from SMI generation | occurrence | production to the end of SMI processing. It is a figure which shows the 2nd Example of this invention and shows an example of CPU power consumption register | resistor. It is a figure which shows the 2nd Example of this invention and shows an example of a power consumption-C state table. It is a flowchart which shows the 2nd Example of this invention and shows SMI processing from SMI generation | occurrence | production performed by logic CPU to the completion | finish of SMI processing. 3 shows a third embodiment of the present invention and is a BIOS setup screen image. FIG.

Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an example of a computer system of the present invention.

1, the computer system is a computer such as a server computer or a personal computer, and one or more blades 100-0 to 100-n and a management module 210 are accommodated in the chassis 200. In this embodiment, an example having a plurality of blades 100-0 to 100-n is shown. In the following, the generic name of the blade is represented by a symbol “100” in which “−” and subsequent characters are omitted. The same applies to the reference numerals of other components.

Each blade 100 is connected to the management module 210. The management module 210 is connected to the management terminal 300 via the network 350. The management module 210 manages each blade 100 according to a command from the management terminal 300. The management terminal 300 includes a display device and an input device (not shown), and can set the BIOS 60 and the like via the management module 210 and the BMC 50.

The blade 100 includes one or more CPU packages 10-0 to 10-i including a plurality of logical CPUs 11-1 to 11-j, a memory 20 connected to each CPU package 10, and a peripheral I / O control chip. PCH (Platform Controller Hub) 30, FPGA (Field Programmable Gate Array) 40 that executes specific arithmetic processing, and BMC (Baseboard Management Controller 50) that is connected to the management module 210 and manages each blade 100. BIOS (Basic Input / Output System) 60 is included. The blades 100-0 to 100-n have the same configuration.

In the first embodiment, an example in which a plurality of logical CPUs 11 are accommodated in the CPU package 10 is shown, but a CPU socket may be used instead of the CPU package 10. The logical CPU may be a CPU that can be recognized by the OS, and may be a physical CPU core. In the first embodiment, the CPU package 10 shows a homogeneous configuration including a plurality of logical CPUs 11, but may be a heterogeneous configuration including a processor such as a GPU. The logical CPU 11 and the package 10 of the first embodiment include the power saving function as described in the conventional example.

For example, as in the conventional example, the logical CPU 11 supports C0, C1, C3, and C6 as power saving states (C state), and the CPU package 10 supports C0, C2, C3, and C6 as C states. An example is shown. The logical CPU 11 may have a logical configuration in which resources of a physical CPU core (not shown) are allocated. In this case, the physical CPU core supports C0, C1, C3, and C6.

Here, among the C states in the power saving state, the C0 state indicates a state in which the power saving is invalid, for example, a state in which the logical CPU 11 operates at a predetermined frequency and a predetermined voltage.

In each blade 100, a hypervisor, an OS, and the like loaded in the memory 20 are executed. Further, an I / O device (not shown) such as a network interface can be connected to the PCH 30.

The logical CPU 11 and the CPU package 10 of the first embodiment support SMM as in the conventional example. That is, when an SMI (system management interrupt) occurs in the CPU package 10, the SMI is notified to all the logical CPUs 11, and a predetermined process is executed in an area dedicated to SMM set in the memory 20 in advance.

FIG. 2 is a time chart showing an outline of SMI processing from the generation of SMI 400 to the end of SMM 410 in the computer system of the present invention. The process of FIG. 2 is a process performed by one CPU package 10 when an SMI occurs. When each logical CPU 11 in the CPU package 10 receives the SMI, the logical CPU 11 calls an SMI handler preset in the BIOS 60 that is firmware, and executes the processing of FIG.

In the first embodiment, it is assumed that the SMI 400 is generated from the management module 210, the memory 20, the PCH 30, or the CPU package 10. In the description of FIG. 2, the logical CPU 11 in the C0 state is represented by the logical CPU group 11A, and the logical CPU 11 in the power saving state other than the C0 state is represented by the logical CPU group 11B. Also, any one of C0 to Cx is set as the C state of each logical CPU 11.

First, when the SMI 400 is generated, the logical CPU group 11A in the C0 state executes SMM waiting for the C0 state CPU (S111). That is, the logical CPU group 11A in the C0 state activates an SMI handler preset in the BIOS 60 and performs a waiting process.

When the waiting process is completed in step S111, one logical CPU 11 that executes the SMI process as a representative is selected from the logical CPU group 11A in the C0 state as a BSP (Boot Strap Processor) (S112). In this selection, for example, among the plurality of C0 state logical CPU groups 11A, the logical CPU 11 that first acquires a predetermined semaphore is determined as the BSP.

In step S113, the BSP performs runtime SMI processing (for example, failure processing). When the SMI process ends, the BSP notifies the S0 end 410 to the logical CPU group 11A in the C0 state and the logical CPU group 11B other than the C0 state.

The

logical CPU groups

11A and 11B that have received the SMM end 410 return to the processing mode (for example, OS processing) before the occurrence of SMI.

In the process of FIG. 2, first, an SMI 400 is generated at time T0. The SMI 400 is notified to the logical CPU group 11A in the C0 state and the logical CPU group 11B in the power saving state, respectively.

In the C0 state logical CPU group 11A, a waiting process for the C0 state logical CPU is started (S111). In the logical CPU group 11B in the power saving state, a delay occurs from the power saving state to the transition to the C0 state.

Therefore, the logical CPU group 11A in the C0 state completes the waiting process at time T1 and can proceed to BSP selection (S112). However, the logical CPU group 11B in the power saving state waits after the transition of the C0 state is completed. Therefore, the waiting process is not completed until time T2.

In the first embodiment, when the SMI 400 is notified to the CPU package 10, the BSP is selected only from the logical CPU group 11A in the C0 state by excluding the logical CPU group 11B in the power saving state. The SMI process (S113) can be completed at time 420 until time T3 without waiting for all the logical CPU groups 11B to transition to the C0 state.

As described above, in the computer system equipped with the multi-core CPU package 10 having the power saving function, even when the power saving states of the plurality of logical CPUs 11 are not uniform, the selection targets of the BSP depending on the respective power saving states of the logical CPUs 11. The logical CPU 11 that is a (candidate) can be controlled.

Thereby, it is possible to eliminate the influence of the delay when the logical CPU 11 returns from the deep C state having a high power saving effect on the SMI processing time of the system firmware such as the BIOS 60. Thereby, it is possible to avoid an increase in the time during which the execution of the OS is interrupted due to the occurrence of SMI.

In particular, in the logic CPU 11 in the deep C state such as the sleep state, since it takes a long time to transition to the C0 state, the interruption time of the OS is increased in the conventional example, but it is saved as in the present invention. By excluding the logical CPU group 11B in the power state from the selection targets (candidates) of the BSP, the OS interruption time during the SMI processing can be shortened.

3A and 3B show details of the processing of FIG. In this example, a logical CPU group 11A that is always operated in the C0 state is determined in advance, and during SMI processing, a BSP is selected from the logical CPU group 11A and SMI processing is executed.

FIG. 3A is a diagram showing an example of the C state table 21 in which the relationship between the APIC ID of the logical CPU 11 and the C state is set. FIG. 3B is a flowchart showing the SMI process from the SMI generation to the end of the SMI process performed by each logical CPU 11.

First, the C state table 21 in FIG. 3A is set in a predetermined area of the memory 20 when the blade 100 is started. When the BMC 50 activates the blade 100, the specific logical CPU 11 does not transition to the deep C state and always operates in the C0 state during the POST (Power On SelfTest) 500 period of the BIOS (Basic Input / Output System) 60. Hardware is set, and the C state table 21 is set in a predetermined area of the memory 20 so that the OS running on the logical CPU 11 cannot transition to the deep C state.

The C state table 21 includes APIC 211 that stores an ID of an APIC (Advanced Programmable Interrupt Controller) as an identifier (CPU number) for identifying the logical CPU 11 and information on whether or not to fix the C state of the logical CPU 11. The C state setting 212 to be stored is included in one entry.

In the C state setting 212, the logical CPU 11 that is always operated in the C0 state is set to “C0 fixed”. The other logical CPUs 11 are set to “variable from C0 to Cx” and can transition to the deep C state.

The BIOS 60 is set to “C0 fixed” that always operates at least one logical CPU 11 in the C0 state at the time of startup. The logical CPU 11 that always operates in the C0 state can be selected from the CPU packages 10 connected to the PCH 30 that is physically superior in communication with the BMC 50. Here, the CPU package 10 having superior communication is, for example, the CPU package 10 having the shortest wiring length from the BMC 50. Further, at least one logical CPU 11 may always be operated in the C0 state for each of the CPU packages 10-0 to 10-i.

Next, SMI processing performed by each logical CPU 11 will be described with reference to FIG. 3B.

When the SMI 400 is generated and the BSP is selected in the SMI process, the logical CPU 11 refers to the C state table 21 and acquires the C state setting 212 corresponding to the APIC 211 of the logical CPU 11. The logical CPU 11 determines whether or not it is a BSP selection target (candidate) depending on whether or not the C state setting 212 is “fixed C0” (S402). This determination is made a BSP selection target if the C state setting 212 is “C0 fixed”.

If the logical CPU 11 is a BSP selection target, the process proceeds to step S403 to set a BSP candidate semaphore. The BSP candidate semaphore can be realized, for example, by setting a flag for each APIC ID in a predetermined area of the memory 20. On the other hand, if the logical CPU 11 is not a BSP selection target, the process advances to step S408 to shift to BSP processing completion waiting.

Next, in step S404, the logical CPU 11 determines whether all the logical CPUs 11 to be selected by the BSP have set BSP candidate semaphores and have completed check-in. If the BSP candidate semaphore has been set for all selection targets, the logical CPU 11 determines that the check-in of all BSP selection target logical CPUs 11 has been completed and proceeds to step S405. That is, if all the BSP candidate semaphores corresponding to the APIC ID in which the C state setting 212 is set to “C0 fixed” in the C state table 21 are set, the process proceeds to step S405.

In step S405, the BSP is determined from the logical CPUs 11 to be selected by the BSP. For example, as a method of determining the BSP from the selection target, one logical CPU 11 is selected as the BSP from the number with the smallest APIC ID. The logical CPU 11 not selected as the BSP proceeds to step S408 and shifts to a BSP process completion wait.

The selected BSP proceeds to step S406 and executes a predetermined SMI process as described above. When the SMI process is completed, the BSP issues a notification of completion of the SMI process to the logical CPU 11 in the wait state, and the logical CPU 11 in the BSP wait state ends the wait state (S407).

Through the above processing, one logical CPU 11 is selected as the BSP from the logical CPU group 11A set to “C0 fixed” in the C state table 21 and executes the SMI processing. In the package 10, there is no need to wait for the deep C state logical CPU group 11B to transition to the C0 state. Further, among the logical CPUs 11 in the C0 state, the logical CPUs 11 that are not selected as the BSP are prohibited from SMI processing and wait for the completion of the SMI processing by the BSP.

As described above, in the computer system equipped with the multi-core CPU package 10 having the power saving function, even when the power saving states of the plurality of logical CPUs 11 are not uniform, the selection targets of the BSP depending on the respective power saving states of the logical CPUs 11. The logical CPU 11 can be controlled.

In particular, when the logical CPU group 11B in the power saving state is in the deep C state such as the sleep state, it takes a long time to shift to the C0 state. Therefore, in the conventional example, the interruption time of the OS also increases. However, the OS interruption time during the SMI processing can be shortened by excluding the logical CPU group 11B in the power saving state from the selection targets of the BSP as in the present invention.

4A to 4C show Example 2 of the present invention. In the first embodiment, an example in which the logical CPU 11 always operating in the C0 state is fixed in the C state table 21 is shown. In the second embodiment, the C state of the CPU package 10 unit is determined based on the power consumption, the CPU package 10 in the C0 state is dynamically selected, and the BSP is selected from the logical CPU 11 of the selected CPU package 10. An example is shown.

FIG. 4A is a diagram illustrating an example of the CPU power consumption register 41 according to the second embodiment. The second embodiment shows an example in which the power consumption of the CPU packages 10-0 to 10-i is measured by the FPGA 40. The FPGA 40 connected to each CPU package 10 acquires the values of various sensors mounted on the CPU package 10, calculates the power consumption for each CPU package 10, and sets it in the CPU power consumption register 41. Note that the calculation of the power consumption of the CPU package 10 may be a well-known or publicly known method, and therefore will not be described in detail here.

The CPU power consumption register 41 is set in a predetermined address space accessible from each logical CPU 11. The CPU power consumption register 41 includes a package ID 411 that stores an identifier of the CPU package 10 and a power consumption 412 that stores a calculation (or measurement) result of power consumption of the CPU package 10 in one entry.

The FPGA 40 can calculate new power consumption and update the CPU power consumption register 41 when values of various sensors of the CPU package 10 change. Alternatively, even when the FPGA (power consumption calculation device) 40 acquires values of various sensors of the CPU package 10 every time a predetermined period is reached, calculates power consumption, and updates the value of the CPU power consumption register 41. Good. In the above description, the package ID 411 is used as the identifier of the CPU package 10, but a socket ID can also be used.

FIG. 4B is a diagram illustrating an example of the power consumption-C state table 42 according to the second embodiment. The power consumption-C state table 42 is a table that is set in a predetermined area of the memory 20 by firmware such as the BIOS 60 when the blade 100 is activated, and identifies the C state from the power consumption.

The power consumption-C state table 42 may be installed on an area of the memory 20 that can be read from firmware such as the BIOS 60.

The power consumption-C state table 42 includes a C state 422 and power consumption 421 corresponding to the C state in one entry. In the illustrated example, the C state is the C0 state if the power consumption of the CPU package 10 is 100 W or more, and the C state is the C1 state if the power consumption of the CPU package 10 is less than 100 W and 90 W or more. .

FIG. 4C is a flowchart showing the SMI process from the SMI generation to the end of the SMI process performed by each logical CPU 11.

When the SMI 400 is generated and the BSP is selected in the SMI process, the logical CPU 11 accesses the CPU power consumption register 41 of the FPGA 40 and acquires the power consumption 412 of the package ID 411 to which the logical CPU 11 belongs (S501). As the package ID 411, the package ID included in the APIC ID can be used.

Next, the logical CPU 11 refers to the power consumption-C state table 42 and acquires the C state of the CPU package corresponding to the acquired power consumption (S502). Then, the logical CPU 11 determines whether or not it is a BSP selection target (candidate) depending on whether or not the C state of the acquired CPU package 10 is “C0” (S503).

If the C state of the CPU package 10 is “C0”, the logical CPU 11 determines that one of the logical CPUs 11 of the CPU package 10 is a BSP selection target, and proceeds to step S504.

On the other hand, if the C state of the CPU package is other than “C0”, the logical CPU 11 determines that the CPU package 10 is not a BSP selection target and proceeds to step S509.

In step S504, since any one of the logical CPUs 11 of the CPU package 10 is a BSP selection target, a BSP candidate semaphore is set. The BSP candidate semaphore can be realized by setting a flag for each APIC ID belonging to the package ID 411 of the C0 state in a predetermined area of the memory 20 by the logical CPU 11 that performs processing, for example, as in the first embodiment. Can do.

Next, in step S505, the logical CPU 11 determines whether all the logical CPUs 11 to be selected by the BSP have set BSP candidate semaphores and check-in is completed. If the BSP candidate semaphore has been set for all selection targets, the logical CPU 11 determines that the check-in of all BSP selection target logical CPUs 11 has been completed, and proceeds to step S506. That is, if all the BSP candidate semaphores corresponding to the APIC ID for which the C state is determined to be C0 are set, the process proceeds to step S506.

In step S506, the BSP is determined from the logical CPUs 11 to be selected by the BSP. For example, as in the first embodiment, as a method for determining the BSP from the selection target, the number with the smallest APIC ID is selected. The logical CPU 11 that is not selected as the BSP proceeds to step S509 and shifts to a BSP process completion wait.

The selected BSP proceeds to step S507 and executes a predetermined SMI process as in the first embodiment. When the SMI process is completed, the BSP issues a notification of completion of the SMI process to the logical CPU 11 in the wait state, and the logical CPU 11 in the BSP wait state ends the wait state (S508).

With the above processing, the C state of the CPU package 10 is specified by the power consumption-C state table 42 from the power consumption of each CPU package 10 calculated by the FPGA 40, so that the logical CPU 11 in the CPU package 10 in the C0 state is BSP. It becomes possible to specify as a candidate. This eliminates the need to fix the logical CPU 11 operating in the C0 state in advance, and allows the CPU package 10 to be selected by the BSP to be dynamically changed.

In the second embodiment, since all the logical CPUs 11 can enable the power saving function, the power consumption of the computer system can be reduced.

In the process of FIG. 4C, when the CPU package 10 in the C0 state does not exist, the processes of steps S504 to S506 may be performed with all the logical CPUs 11 as BSP selection targets. In the second embodiment, the power consumption corresponding to each of the C states 422 is set in advance in the power consumption-C state table 42. However, the present invention is not limited to this.

For example, in correspondence with the comparison in step S503, only the power consumption of the C0 state in which power saving is invalid may be held in the power consumption-C state table 42. Then, the logical CPU 11 acquires the power consumption of the CPU package 10 from the CPU power consumption register 41, and selects the CPU package 10 whose power consumption corresponds to the C0 state of the power consumption-C state table 42 as a BSP selection target. .

FIG. 5 is a screen image showing an example 3 of the BIOS 60 according to the third embodiment of the present invention. The third embodiment shows an example in which the SMI process is selected when setting up the BIOS 60 of the blade 100 via the management module 210 and the BMC 50 from the management terminal 300 shown in the first embodiment.

The setup screen 310 of the BIOS 60 selects one of the “Performance” mode and the “Power Saving” mode 320 when selecting a BSP in the SMM SMI process.

Here, the “Performance” mode shows an example using the C state table 21 shown in the first embodiment. On the other hand, the “Power Saving” mode shows an example in which the CPU power consumption register 41 and the power consumption-C state table 42 of the FPGA 40 of the second embodiment are used.

In the third embodiment, when the SMI 400 occurs, the operator of the management terminal 300 selects one of the processing of the first embodiment and the processing of the second embodiment on the setup screen 310 of the BIOS 60. For example, the first embodiment is set as the default value of the BIOS 60.

As a feature of the first embodiment, since any one of the logical CPUs 11 is always set in the C0 state, the power saving effect can be reduced, but the time during which the execution of the OS is interrupted due to the occurrence of SMI is the second embodiment. It may be shorter than Therefore, the BSP selection process of the first embodiment is set to the first execution core selection mode in which the performance of the computer system is emphasized.

On the other hand, as a feature of the second embodiment, when the CPU package 10 in the C0 state is not provided, the time during which the execution of the OS is interrupted when the SMI is generated is not shortened as compared with the first embodiment. Thus, a high power saving effect can be obtained. Therefore, the second embodiment is set as a second execution core selection mode that suppresses the power consumption of the computer system.

According to the third embodiment, the mode for selecting the BSP can be switched between performance-oriented and power-saving-oriented according to the operation policy of the computer system, etc., and a multi-core CPU having a power-saving function It is possible to flexibly operate a computer system including

In the first to third embodiments, the BIOS 60 is used as the firmware of the blade 100. However, UEFI (Unified Extensible Firmware Interface) may be used.

In the first to third embodiments, an example is shown in which a multi-core CPU having a power saving function and transitioning to SMM in response to SMI is used. However, the present invention is not limited to this. For example, it may be a multi-core processor having a plurality of processor cores, each processor core having a power saving function capable of transitioning to a power saving mode, and executing firmware processing with a predetermined interrupt. When a predetermined interrupt is received, one of the plurality of processor cores only needs to execute firmware processing. The power saving function may be any function that reduces at least one of the processor core clock and the processor core drive voltage.

In addition, although an example in which the C state is used as an index indicating the usage state of the power saving function is shown, the present invention is not limited to this. For example, the power saving valid mode for reducing the power consumption of the processor core may be set to a state other than the C0 state, and the power saving invalid mode for operating the processor core at the rated value or higher than the rated value. Note that operating the processor core above the rating means, for example, that when the power consumption of the processor core in the power saving effective mode is low, the clock of the processor core in the power saving invalid mode is set to a predetermined ratio (for example, 20 %) To increase the processing capacity.

In the first to third embodiments, an example in which the multi-core CPU switches between the mode in which the application or OS is executed and the SMM (System Maintenance Mode) that executes the processing of the BIOS 60 with a predetermined interrupt has been shown. It is not limited. For example, the multi-core CPU only has to have a first mode for executing an application or OS and a second mode for executing firmware processing with a predetermined interrupt, and the two execution modes can be switched.

In the second embodiment, the power consumption is calculated by the FPGA 40 connected to the plurality of CPU packages 10 and set in the CPU power consumption register 41 to provide the power consumption to each logical CPU 11. It is not limited to. Any power consumption calculation device that is connected to a plurality of CPU packages 10 to calculate the power consumption of each CPU package 10 and sets the power consumption of the calculation result in a register accessible from each logical CPU 11 may be used.

In addition, this invention is not limited to the above-mentioned Example, Various modifications are included. For example, the above-described embodiments are described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the configurations described. Further, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. In addition, any of the additions, deletions, or substitutions of other configurations can be applied to a part of the configuration of each embodiment, either alone or in combination.

In addition, each of the above-described configurations, functions, processing units, processing means, and the like may be realized by hardware by designing a part or all of them with, for example, an integrated circuit. In addition, each of the above-described configurations, functions, and the like may be realized by software by the processor interpreting and executing a program that realizes each function. Information such as programs, tables, and files that realize each function can be stored in a memory, a hard disk, a recording device such as an SSD (Solid State Drive), or a recording medium such as an IC card, an SD card, or a DVD.

Also, the control lines and information lines indicate what is considered necessary for the explanation, and not all the control lines and information lines on the product are necessarily shown. Actually, it may be considered that almost all the components are connected to each other.

Claims

A computer including a multi-core processor having a plurality of processor cores, a memory, and firmware,
The processor core is
An execution mode for switching between a first mode for executing an application or an OS and a second mode for executing firmware processing by a predetermined interrupt;
A power saving function for setting one of a power saving effective mode for reducing the power consumption of the processor core and a power saving invalid mode for operating the processor core at a rating or above a rating; and
The processor core is
When the predetermined interrupt is received, a processor core that operates in the power saving invalid mode is selected from the plurality of processor cores, and the firmware process is executed by changing the selected processor core to the second mode. A computer characterized by letting
The computer according to claim 1,
A computer in which a processor core that operates in a power saving invalid mode is determined in advance among the plurality of processor cores.
The computer according to claim 1,
A plurality of the multi-core processors, connected to the multi-core processor to calculate the power consumption for each multi-core processor and set the power consumption in a register accessible from the multi-core processor;
Information that is set in the memory and that predetermines power consumption corresponding to at least the power saving invalid mode;
The processor core is
When the predetermined interrupt is received, the power consumption for each multi-core processor is obtained from the register of the power consumption arithmetic device, the multi-core processor in the power saving invalid mode is specified by referring to the information with the power consumption, A computer characterized by selecting a processor core of the identified multi-core processor.
The computer according to claim 1,
The processor core is
When the predetermined interrupt is received, one processor core operating in the power saving invalid mode is selected from the plurality of processor cores, and the selected processor core is shifted to the second mode to perform the processing of the firmware. A computer that is executed and that is not selected among processor cores operating in the power saving invalid mode prohibits the processing of the firmware.
The computer according to claim 1,
A plurality of the multi-core processors, connected to the multi-core processor to calculate the power consumption for each multi-core processor and set the power consumption in a register accessible from the multi-core processor;
Information that is set in the memory and that predetermines power consumption corresponding to at least the power saving invalid mode;
The firmware is
One of a first execution core selection mode that places importance on the performance of a computer and a second execution core selection mode that suppresses power consumption of the computer when selecting a processor core to be shifted to the second mode. Set one side,
The first execution core selection mode is:
The firmware determines in advance a processor core that operates in a power saving invalid mode among the plurality of processor cores,
The second execution core selection mode is:
When the processor core accepts the predetermined interrupt, the power consumption for each multi-core processor is acquired from the register of the power consumption arithmetic device, and the information is referred to by the power consumption, and the multi-core processor in the power saving invalid mode And a processor core of the identified multi-core processor is selected.
A computer control method including a multi-core processor having a plurality of processor cores, a memory, and firmware,
The processor core sets a power saving effective mode for reducing power consumption of the processor core and a power saving invalid mode for operating the processor core at a rating or above a rating, and a first step;
The processor core operates in a first mode for executing an application or OS;
The processor core includes a third step of transitioning to a second mode in which processing of the firmware is executed when a predetermined interrupt is received;
The third step includes
Selecting a processor core operating in a power saving invalid mode from the plurality of processor cores, causing the selected processor core to transition to the second mode and executing the processing of the firmware; Control method.
The computer control method according to claim 6, comprising:
A computer control method, wherein a processor core operating in a power saving invalid mode is determined in advance among the plurality of processor cores.
The computer control method according to claim 6, comprising:
The third step includes
Power consumption for each multi-core processor is calculated from the register of the power consumption calculation device connected to a plurality of multi-core processors to calculate power consumption for each multi-core processor and set the power consumption in a register accessible from the multi-core processor Obtaining the multi-core processor in the power saving invalid mode with reference to information that is set in the memory and predetermined power consumption corresponding to at least the power saving invalid mode is set, and the processor core of the identified multi-core processor is determined A computer control method characterized by selecting.
The computer control method according to claim 6, comprising:
The third step includes
Selecting one processor core operating in the power saving invalid mode from the plurality of processor cores, causing the selected processor core to transition to the second mode and executing the processing of the firmware; A computer control method, wherein the processor cores that are not selected among processor cores that operate in the system prohibit the processing of the firmware.
The computer control method according to claim 6, comprising:
The firmware is
One of a first execution core selection mode that places importance on the performance of a computer and a second execution core selection mode that suppresses power consumption of the computer when selecting a processor core to be shifted to the second mode. Further comprising setting one,
The third step includes
In the first execution core selection mode, a processor core that operates in the power saving invalid mode among the plurality of processor cores is determined in advance, and a processor core that operates in the power saving invalid mode is selected, and the selected processor Causing the core to transition to the second mode to execute the firmware process;
In the second execution core selection mode,
Power consumption for each multi-core processor is calculated from the register of the power consumption calculation device connected to a plurality of multi-core processors to calculate power consumption for each multi-core processor and set the power consumption in a register accessible from the multi-core processor Obtaining the multi-core processor in the power saving invalid mode with reference to information that is set in the memory and predetermined power consumption corresponding to at least the power saving invalid mode is set, and the processor core of the identified multi-core processor is determined A computer control method comprising: selecting, causing the selected processor core to transition to the second mode, and executing the processing of the firmware.