WO2017009996A1 - Dispositif de traitement d'informations, procédé de traitement d'informations et programme - Google Patents

Dispositif de traitement d'informations, procédé de traitement d'informations et programme Download PDF

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Publication number
WO2017009996A1
WO2017009996A1 PCT/JP2015/070395 JP2015070395W WO2017009996A1 WO 2017009996 A1 WO2017009996 A1 WO 2017009996A1 JP 2015070395 W JP2015070395 W JP 2015070395W WO 2017009996 A1 WO2017009996 A1 WO 2017009996A1
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Prior art keywords
instruction table
instruction
exception
entries
exception condition
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PCT/JP2015/070395
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English (en)
Japanese (ja)
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勝己 奥田
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三菱電機株式会社
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Priority to PCT/JP2015/070395 priority Critical patent/WO2017009996A1/fr
Priority to JP2017528252A priority patent/JP6529588B2/ja
Publication of WO2017009996A1 publication Critical patent/WO2017009996A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines

Definitions

  • the present invention relates to an information processing apparatus, an information processing method, and a program, and more particularly, to an information processing apparatus, an information processing method, and a program that divide an instruction table to create a decoding tree.
  • the instruction set simulator or disassembler includes an instruction decoder as part of the component.
  • the instruction decoder is a software component that receives a machine language program and identifies instructions included in the machine language program.
  • a CPU Central Processing Unit
  • the instruction opcode is a bit group that holds a fixed value of 0 or 1 in the instruction bit string. Since the CPU instruction has a unique operation code, the instruction decoder refers to the operation code to identify the instruction.
  • the instruction opcode differs depending on the ISA (Instruction Set Architecture). Therefore, in order to obtain an instruction set simulator or disassembler corresponding to a plurality of ISAs, it is necessary to develop an instruction decoding process for each ISA.
  • the instruction table has an entry for each instruction, and each entry has an instruction identifier and opcode information.
  • the instruction decoder decodes the instruction by retrieving an entry having an operation code that matches the input bit string from the instruction table.
  • the instruction table search time increases in proportion to the number of entries in the instruction table, that is, the number of ISA instructions. For this reason, there has been a problem that the processing efficiency of instruction decoding is poor.
  • the conventional technique generates a decoding tree from the instruction table and uses the decoding tree instead of the instruction table to reduce the processing time.
  • the decoder searches the decoding tree instead of the linear search of the instruction table. In general, the average tree search time is shorter than the average time required for the linear table search.
  • the conventional method has a problem that it cannot cope with an instruction set having an exceptional condition.
  • the conventional method cannot create a tree when the operation codes of two or more instructions match one instruction bit string.
  • the reason why two or more instruction opcodes match one instruction bit string is that an instruction set generally includes instructions with exception conditions.
  • the instruction bit string I is not the instruction x as long as the instruction bit string I satisfies the exception condition of the instruction x even if the instruction bit string I matches the operation code of the instruction x.
  • the conventional tree creation method has a problem that it cannot be applied to an instruction set in which an exception condition exists.
  • an object of the present invention is to be able to generate a decoding tree even for an instruction set in which an exceptional condition exists.
  • An information processing apparatus includes an instruction table dividing unit that divides an instruction table including a plurality of entries having operation code information for specifying an instruction identifier and an instruction identifier corresponding to a bit string, and the instruction table A tree creating unit that creates a decoding tree for identifying the instruction identifier corresponding to the bit string from the instruction table divided by the dividing unit, and the instruction table dividing unit includes a plurality of entries in the plurality of entries.
  • the instruction table is A first instruction comprising an entry whose opcode information matches one of the one or more exception conditions And Buru, characterized by dividing the second instruction table of entries the opcode information in any of the one or more exception conditions do not match, the.
  • An information processing method includes a process of dividing an instruction table including a plurality of entries having operation code information for specifying an instruction identifier and an instruction identifier corresponding to a bit string, and the divided instruction table Generating a decoding tree for specifying the instruction identifier corresponding to the bit string, and at least one of the plurality of entries includes one or more exception conditions
  • the instruction table is converted into the one or more exception conditions.
  • a first instruction table comprising entries whose opcode information matches any of the above, and the one or more exception conditions To both characterized by divided into a second instruction table of entries the opcode information does not match.
  • a program includes an instruction table dividing unit that divides an instruction table including a plurality of entries having operation code information for specifying an instruction identifier and an instruction identifier corresponding to a bit string, and the instruction A program that functions as a tree creating unit that creates a decoding tree for identifying the instruction identifier corresponding to the bit string from the instruction table divided by the table dividing unit, the instruction table dividing unit comprising:
  • at least one of the plurality of entries includes one or more exception conditions, and a mask common to all the opcode information included in the plurality of entries cannot be calculated.
  • the instruction table is set to one of the one or more exception conditions.
  • Information is a first instruction table of entries that match, characterized by dividing the second instruction table of entries the opcode information in any of the one or more exception conditions do not match, the.
  • a decoding tree can be generated even for an instruction set in which an exceptional condition exists.
  • (A)-(c) is the schematic which shows the 1st example which divides
  • (A) And (b) is the schematic (the 1) which shows the 2nd example which divides
  • (A)-(c) is the schematic (the 2) which shows the 2nd example which divides
  • (A) to (c) are schematic diagrams for explaining the effect when a decoding tree is created from an instruction table including a plurality of exception conditions.
  • (A) to (c) are schematic diagrams for explaining the effect when one instruction has a plurality of exception conditions.
  • (A)-(c) is the schematic for demonstrating the effect when several exception conditions share a part of conditions.
  • (A) to (c) are schematic diagrams for explaining the effect when an instruction table including an exception condition unnecessary for instruction table division is input. It is the schematic which shows the comparative example of the tree for decoding. It is the schematic which shows the tree for decoding in this Embodiment. It is the schematic which shows the 2nd example of the instruction table with an exception condition in this Embodiment. It is the schematic which shows the program expression of the tree for decoding in this Embodiment.
  • FIG. 1 is a block diagram schematically showing a configuration of a decoding tree creation unit 100 as an information processing apparatus according to the present embodiment.
  • the decoding tree creation unit 100 includes a tree creation unit 101 and an instruction table division unit 104.
  • the decoding tree creation unit 100 receives the input of the instruction table with exception condition 110 and outputs a decoding tree 130.
  • the tree creation unit 101 includes a node creation unit 102 and a leaf creation unit 103.
  • the information processing method according to the present embodiment is a method executed by the decoding tree creation unit 100.
  • the instruction table with exception condition 110 is an instruction table having an entry for each instruction, in other words, an instruction including a plurality of entries having an instruction identifier for identifying an instruction and opcode information for specifying an instruction identifier corresponding to a bit string. It is a table. At least one of the plurality of entries includes one or more exception conditions. The order of entries in the exception condition instruction table 110 is arbitrary. Each entry in the instruction table with exception condition 110 holds an instruction identifier, opcode information, and an exception condition set.
  • the operation code information is composed of a pair of an operation code mask and an operation code pattern, but is not limited to this.
  • the exception condition set is empty when the instruction corresponding to the entry has no exception condition.
  • the exception condition set has a plurality of elements when the instruction corresponding to the entry has a plurality of exception conditions.
  • the exception condition of entry E means that this instruction bit string does not match entry E when a part of the instruction bit string matches a specific pattern.
  • the exception condition is configured by a pair of an exception mask and an exception pattern, but is not limited to this.
  • “&” represents a logical product for each bit.
  • the decoding tree 130 is a kind of decision tree, and is used to specify an instruction identifier corresponding to a bit string.
  • the instruction decoder can specify the instruction of the input instruction bit string using the decoding tree 130.
  • the decoding tree 130 includes nodes and leaves as components, similar to a general tree.
  • a node of the decoding tree 130 has one or more children, and the children are either nodes or leaves.
  • the node has information for checking the bit group of the instruction sequence, and holds the value of the bit group and the child in association with each other. For example, the node associates a child with a combination of a mask and a bit pattern described later.
  • a child associated with a combination of a mask and a bit pattern is a node or a leaf created by an instruction table divided by this combination. Further, the leaf of the decoding tree 130 has no children.
  • a specific node and leaf holding method in this embodiment will be described together with details of the node creation processing and leaf creation processing.
  • the decoding tree creation unit 100 shown in FIG. 1 receives an instruction table having no exception condition and outputs a decoding tree by a conventional method.
  • a conventional decoding tree creation method will be described with reference to FIGS. 2 to 4, and specific examples will be described with reference to FIGS.
  • FIG. 2 is a flowchart showing a conventional decoding tree creation process.
  • an instruction table is input, and a decoding tree corresponding to the instruction table is recursively created.
  • the input instruction table has one or more entries.
  • the node creation unit 102 determines whether or not the number of entries in the input instruction table is 1 (S10). If the number of entries is 1 (Yes in S10), the process proceeds to step S11. If the number of entries is not 1 (No in S10), in other words, if there are a plurality of entries, the process proceeds to step S12. Proceed to In step S11, the leaf creation unit 103 creates a leaf. The leaf holds an instruction identifier as an attribute. The leaf creation unit 103 obtains an instruction identifier from a single entry in the instruction table simultaneously with leaf creation, and sets the obtained instruction identifier as a leaf attribute. In step S12, the node creation unit 102 creates a node of the tree with the instruction table as an input. Details of the node creation processing will be described with reference to FIG.
  • FIG. 3 is a flowchart showing a conventional node creation process.
  • the input of the node creation process is an instruction table, and the output is a node having two or more children.
  • the input command table has two or more entries.
  • the instruction table dividing unit 104 calculates a value to determine a mask (S20). For example, the instruction table dividing unit 104 calculates a value by calculating the total logical product for each bit with respect to the opcode mask of all entries in the instruction table. For example, the value obtained from the three opcode masks “0111”, “1111”, and “1101” is the total logical product “0101”. If the i-th bit is 1 in the calculated value, it means that the i-th bit of the instruction is part of the opcode for all the instructions in the input instruction table.
  • the instruction table dividing unit 104 divides the instruction table into two or more values based on the value determined from the mask determined by this value, and the tree creating unit 101 creates a tree for the divided instruction table.
  • the processing FIG. 2 recursively, the entire decoding tree is created.
  • step S21 the instruction table dividing unit 104 determines whether or not all the bits of the calculated value are “0” (S21). If all the bits are 0 (Yes in S21), the process proceeds to step S22. If any bit is 1 (No in S21), the process proceeds to step S23. In step S ⁇ b> 22, the node creation unit 102 returns a failure of creation as a result of the process because a mask that functions effectively cannot be calculated, and ends the process.
  • step S23 the node creation unit 102 allocates an output node area on the memory.
  • a node has a mask and a child node set as attributes.
  • An element of the child node set is a pair of an opcode (bit pattern) and a child node.
  • the node creating unit 102 initializes the mask attribute of the node with the mask calculated in step S20.
  • the child node set is empty when the node is created in step S23.
  • the node creation unit 102 completes the child node set by adding elements to the child node set in the subsequent processing of steps S24 to S29.
  • the instruction table dividing unit 104 creates a pattern set from the mask (S24).
  • the pattern set includes all values corresponding to the mask calculated in step S20.
  • the pattern set is a set of all bit patterns identified by the mask.
  • bit pattern an arbitrary element (bit pattern) of the pattern set P
  • the pattern set P is expressed by the following equation (1).
  • p i represents the i-th bit of the bit pattern p
  • m i represents the i-th bit of the mask m.
  • the number of elements included in the pattern set P corresponding to the mask m is 2 N. For example, when the value of the mask m is “0101”, the pattern set P has four elements “0000”, “0001”, “0100”, and “0101”.
  • Steps S25 to S29 are processes for circulating the pattern set P. In other words, the processes of steps S25 to S29 are performed for each element of the pattern set P.
  • Step S26 is a pattern matching instruction table creation process.
  • the pattern matching instruction table creation process the instruction table dividing unit 104 creates a new instruction table including only instructions that match the bit pattern being circulated. Details of the pattern matching instruction table creation processing will be described later with reference to FIG.
  • step S27 the node creation unit 102 and the leaf creation unit 103 receive the instruction table created in step S26 as input, and recursively perform the decoding tree creation process shown in FIG.
  • step S28 the node creation unit 102 adds the pair of the bit pattern being visited and the tree created in step S27 as an element of the child node set attribute of the node created in step S23.
  • the node creation unit 102 returns that the creation is successful and the output node in step S30 as a result of the processing.
  • FIG. 4 is a flowchart showing a conventional pattern matching instruction table creation process.
  • the input of the pattern matching instruction table creation process is a mask / bit pattern pair and an instruction table, and the output is a new instruction table.
  • the instruction table output here is only an entry that matches the input mask and bit pattern pair among the input instruction table entries.
  • the operation code mask of the new entry has a value obtained by masking off the bits of the mask input from the operation code mask of the original entry. For example, if the opcode mask of the original entry is “0011” and the input mask is “0001”, the opcode mask of the new entry is “0010”.
  • the instruction table dividing unit 104 secures an empty table on the memory as an instruction table to be output (hereinafter referred to as an output instruction table) (S40).
  • steps S41 to S46 are loop processing, and the instruction table dividing unit 104 circulates the input instruction table and sequentially registers entries matching the pattern in the output instruction table.
  • Step S43 is a branching process on the condition that the result of step S42 matches the pattern. If the pattern matches (Yes in S43), the process proceeds to step S44. If the pattern does not match (No in S43), steps S44 and S45 are skipped, and the process proceeds to step S46.
  • step S44 the instruction table dividing unit 104 creates a new opcode mask OM # in which the bits of the mask m input from the opcode mask OM of the instruction table entry being cycled are masked off. Specifically, the instruction table division unit 104 creates a new opcode mask OM # according to the following equation (3). OM & ⁇ M (3)
  • “&” means binary operation of logical product for each bit
  • ⁇ means inversion for each bit.
  • step S28 the instruction table dividing unit 104 adds the entry of the instruction table being visited to the entry of the output instruction table.
  • the new opcode mask OM # calculated in step S44 is used as the opcode mask of the entry to be added.
  • the instruction table 5 shown in FIG. 5 has five instructions A, B, C, D, and E as entries.
  • step S10 in FIG. 2 the node creation unit 102 determines that the number of entries in the instruction table 5 is not 1, and performs the node creation process (FIG. 3) in step S12.
  • step S20 of FIG. 3 the node creation unit 102 obtains the mask value “11000000” by calculating the logical product of the opcode masks of the instructions A to E. The resulting mask contains bits with a value of 1. Therefore, in the branch process of step S21 in FIG. 3, the process proceeds to step S23.
  • step S24 of FIG. 3 the instruction table dividing unit 104 generates four bit patterns “00000000”, “01000000”, “10000000”, and “11000000” from the mask values.
  • steps S25 to S29 in FIG. 3 the four bit patterns generated in step S24 are circulated.
  • the pattern matching instruction table created in step S26 (FIG. 4) of FIG. 3 during each bit pattern cycle is shown in FIG.
  • the pattern matching instruction table 6a shown in FIG. 6A has the instruction A that matches the bit pattern “00000000” and the mask “11000000” in the instruction table 5 of FIG. 5 as an entry.
  • the opcode mask of the entry of the instruction A is “00000000” excluding the mask “11000000” calculated in step S20 of FIG.
  • the pattern matching instruction table 6b shown in FIG. 6B has the instruction B and the instruction C that match the bit pattern “01000000” and the mask “11000000” in the instruction table 5 of FIG. 5 as entries.
  • the pattern matching instruction table 6c shown in FIG. 6C has, as entries, an instruction D and an instruction E that match the bit pattern “10000000” and the mask “1100000” in the instruction table 5 of FIG.
  • the opcode masks for instruction D and instruction E are also “00001100”, excluding the mask “11000000”.
  • step S27 the instruction tables 6a to 6c shown in FIG.
  • the number of entries is “1”, and the process proceeds to step S11.
  • step S11 a leaf corresponding to the instruction A which is the only entry in the pattern matching instruction table 6a is created.
  • the tree generation using the pattern matching instruction table 6b and the pattern matching instruction table 6c as input is the same repetition as described above.
  • FIG. 7 shows a conventional tree output by the above-described processing with the instruction table 5 shown in FIG. 5 as an input.
  • Reference numerals 7a, 7b, and 7c in FIG. 7 are nodes, and reference numerals 8a, 8b, 8c, 8d, and 8e are leaves.
  • the leaf 8a is a tree created by tree creation processing from the instruction table 6a shown in FIG.
  • the subtree having the node 7b as the root is a tree created from the instruction table 6b shown in FIG. 6B
  • the subtree having the node 7c as the root is shown in FIG. 6C. This is a tree created from the instruction table 6c.
  • the conventional method has a problem that it cannot cope with an instruction table having an exception condition.
  • a description will be given using the instruction table 111 shown in FIG. 8
  • the instruction bit string “11000000” matches the operation codes of the instruction A and the instruction B.
  • step S20 in FIG. 3 the mask calculated in step S20 in FIG. 3 is “00000000”.
  • This mask is a result of the logical product of the operation code masks “11000000”, “00000011”, and “00000011” of the instructions A, B, and C in FIG. Therefore, in the branch process of step S21 in FIG. 3, all bits of the mask become “0”, the process proceeds to step S22, and a valid mask is not calculated, so that node creation fails. Further, even if the process proceeds to step S23 in FIG. 3 as it is, a pattern set cannot be created and the process cannot be continued correctly.
  • the conventional tree creation method has a problem that it cannot be applied to an instruction table having an exception condition. Therefore, in the following, a description will be given of the present embodiment in which a decoding tree can be generated even for an instruction table in which an exception condition exists.
  • the tree creation unit 101 creates a decoding tree from the instruction table.
  • the node creation unit 102 creates a corresponding node when the instruction table includes a plurality of entries.
  • the leaf creation unit 103 creates a corresponding leaf when the instruction table includes one entry.
  • the instruction table dividing unit 104 divides the instruction table.
  • the instruction table is divided until there is one entry in the instruction table, and a corresponding node or leaf is created by the tree creation unit 101 based on the divided instruction table.
  • the instruction table division unit 104 includes one or more exception conditions in at least one of the plurality of entries included in the instruction table, and is included in the plurality of entries. If a mask common to all the operation code information cannot be calculated, the instruction table is changed to a first instruction table including an entry whose operation code information matches one or more exception conditions, and one or more The operation code information is divided into a second instruction table including entries whose opcode information does not match any exception condition.
  • the instruction table division unit 104 includes one or more exception conditions in at least one of the plurality of entries included in the instruction table, and is included in the plurality of entries.
  • a mask common to all the operation code information can be calculated, a bit pattern is selected one by one from a plurality of bit patterns that can be identified by this mask, and the selected one
  • the instruction table is divided for each bit pattern to generate a third instruction table. .
  • the processing circuit includes a processor 140 and a memory 141.
  • the processor 140 is a CPU (also referred to as a central processing unit, a processing unit, an arithmetic unit, a microprocessor, a microcomputer, or a DSP) that executes a program stored in the memory 141.
  • the memory 141 is a nonvolatile or volatile semiconductor memory such as RAM, ROM, flash memory, EPROM, or EEPROM, a magnetic disk, a flexible disk, an optical disk, a compact disk, a mini disk, or a DVD.
  • the memory 141 also stores an instruction table with exception condition 110 and a decoding tree 130.
  • FIG. 10 is a flowchart showing decoding tree creation processing in the present embodiment.
  • the same processes as those shown in FIG. 2 are denoted by the same reference numerals as those in FIG. 2.
  • the input of the decoding tree creation process shown in FIG. 10 is an instruction table 110 with an exception condition, and the output is a decoding tree 130.
  • the decoding tree creation process is premised on that the input instruction table has one or more entries.
  • step S10 the node creation unit 102 determines whether or not the number of entries in the input instruction table is 1. If the number of entries is 1 (Yes in S10), the process proceeds to step S11. If the number of entries is 2 or more (No in S10), the process proceeds to step S13.
  • step S11 the leaf creation unit 103 creates a leaf. The leaf holds an instruction identifier as an attribute. The leaf creating unit 103 associates information of the instruction table entry as an attribute with this leaf.
  • Steps S13 to S15 are processes for creating a node when the instruction table has two or more entries.
  • the node creation unit 102 performs node creation processing.
  • the node creation process creates a node using the instruction table as an input. Details of this node creation processing will be described later.
  • Step S14 is a branch process for determining whether or not the node creation has succeeded as a result of step S13. If the node has been successfully created (Yes in S14), the process in step S15 is skipped, and if the node creation has failed (No in S14), the process proceeds to step S15.
  • step S15 the node creation unit 102 receives the instruction table and performs a condition node creation process.
  • the condition node is a node newly introduced in the present embodiment. Details of the condition node and condition node creation processing will be described later.
  • FIG. 11 is a flowchart showing the node creation processing in the present embodiment.
  • the node creation process shown in FIG. 11 is the details of the process in step S13 of FIG.
  • processes similar to those of the conventional node creation process shown in FIG. 3 are denoted by the same reference numerals as those in FIG. 3.
  • the process shown in FIG. 11 is the same as the process of FIG. 3 except for the process of step S31.
  • the process in step S31 will be mainly described.
  • Step S31 is a pattern matching instruction table creation process in the present embodiment.
  • the mask is determined by calculating the total logical product of the opcode masks.
  • the mask determination method is not limited to this. The mask is arbitrary as long as the number of entries in the instruction table created in the pattern matching instruction table creation process in step S31 can be made smaller than the number of elements in the inputted instruction table.
  • FIG. 12 is a flowchart showing pattern matching instruction table creation processing in the present embodiment.
  • the pattern matching instruction table creation process shown in FIG. 12 is details of the process in step S31 of FIG.
  • the same reference numerals as those in FIG. 4 are assigned to the same processes as the conventional pattern matching instruction table creation process shown in FIG.
  • the process shown in FIG. 12 is the same as the process in FIG. 4 except for the processes in steps S47 to S49.
  • the processes in steps S47 to S49 will be mainly described.
  • the input of the pattern matching instruction table creation processing is a mask / bit pattern pair and an instruction table
  • the output is a new instruction table including only entries matching the mask / bit pattern pair.
  • a feature of the pattern matching instruction table creation process in the present embodiment is that an exception condition is used in addition to the bit pattern for determining whether or not the instruction table matches the mask and bit pattern pair.
  • Step S47 is a pattern matching confirmation process.
  • the instruction table dividing unit 104 determines whether or not the input instruction table entry matches the input mask and bit pattern pair in consideration of the exception condition. Details of the pattern matching confirmation process will be described later.
  • Step S48 is an exception condition set creation process at the time of pattern matching.
  • the instruction table dividing unit 104 newly creates a set of exception conditions in the entry of the output instruction table.
  • the input of the exception condition set creation process at the time of pattern matching is the mask and bit pattern pair input to the pattern match instruction table creation process itself, and the exception condition set of the instruction table entry in circulation.
  • the output is a new exception condition set.
  • step S49 the instruction table dividing unit 104 adds an entry of the input instruction table currently being cycled to the output instruction table.
  • the operation code mask created in step S44 and the exception condition set created in step S48 are set in the opcode mask and exception condition set of the new entry, respectively.
  • FIG. 13 is a flowchart showing the pattern matching confirmation processing in the present embodiment.
  • the pattern matching confirmation process shown in FIG. 13 is the details of the process in step S47 of FIG.
  • the pattern matching confirmation process the mask / bit pattern pair and the instruction table entry are input, and the instruction table dividing unit 104 determines whether the instruction table entry matches the mask / bit pattern pair.
  • step S50 the instruction table dividing unit 104 checks whether or not the result of step S50 matches the pattern (S51). If the result does not match the pattern (No in S51), the process proceeds to step S52. If the result matches the pattern (Yes in S51), the process proceeds to step S53. In step S52, the instruction table dividing unit 104 determines that the results do not match and ends the processing.
  • step S53 the instruction table dividing unit 104 performs an exceptional condition confirmation process.
  • the exception condition confirmation process the instruction table dividing unit 104 confirms the exception condition of the entry in the instruction table being visited.
  • the exception condition confirmation processing the mask and bit pattern pair and the exception condition set of the instruction table entry are input, and the instruction table dividing unit 104 outputs whether or not the mask and bit pattern pair satisfies the exception condition. Details of the exception condition confirmation processing will be described later.
  • step S54 the instruction table dividing unit 104 checks whether or not the result in step S53 satisfies the exception condition (S54). If the result satisfies the exception condition (Yes in S54), the process proceeds to step S55. If the result does not satisfy the exception condition (No in S54), the process proceeds to step S56. In step S55, since the exception condition is satisfied, the instruction table dividing unit 104 determines that the results do not match and ends the process. On the other hand, in step S56, since the exception condition is not satisfied, the instruction table dividing unit 104 ends the process with the result being the same.
  • FIG. 14 is a flowchart showing exception condition confirmation processing in the present embodiment.
  • the exception condition confirmation process shown in FIG. 14 is the details of the process in step S53 of FIG.
  • the input of the exception condition confirmation process is a mask and bit pattern pair and an exception condition set.
  • the instruction table dividing unit 104 confirms whether or not the input mask and bit pattern pair matches one or more exception conditions.
  • steps S61 to S65 are loops that circulate exception conditions and check whether there is an exception condition that matches the input mask and bit pattern pair. If at least one exception condition that matches the input mask and bit pattern pair is found, the result of the exception condition confirmation process is the same.
  • “&” means a logical product for each bit.
  • step S52 determines whether or not the confirmation results in step S52 are the same. If the confirmation result is a match (Yes in S63), the process proceeds to step S64. If the confirmation result is a mismatch (No in S63), step S64 is skipped and the process proceeds to step S65. .
  • step S64 the instruction table dividing unit 104 stores in the memory that the results match as a result of the exceptional condition confirmation processing. When the exceptional condition circulation process in steps S61 to S65 is completed, a match or mismatch is obtained as a result of the exception condition confirmation process.
  • FIG. 15 is a flowchart of exception condition set creation processing at the time of pattern matching in the present embodiment.
  • the exception condition set creation process at the time of pattern matching shown in FIG. 15 is the details of the process in step S48 in FIG.
  • the input in the exception condition set creation process at the time of pattern matching is a mask and bit pattern pair and an exception condition set, and the output is a new exception condition set obtained by removing invalid exception conditions from the input exception condition set. .
  • the instruction table dividing unit 104 allocates an area for output exception conditions to a memory (S70).
  • the initial value of the output exception condition is an empty set.
  • Steps S71 to S76 are a loop process that circulates exceptional conditions. In this loop processing, the instruction table dividing unit 104 adds only necessary exception conditions to the output exception condition set.
  • the instruction table division unit 104 is a process of checking whether or not the exception condition during circulation is valid for the input mask and bit pattern pair.
  • m is an input mask
  • p is an input bit pattern p
  • EM is an exception mask in an exception condition in circulation
  • EP is an exception pattern in an exception condition in circulation
  • the instruction table dividing unit 104 determines that the exceptional condition during the circulation is valid.
  • p & EM & m EP & EM & m (6)
  • “&” means a logical product for each bit.
  • step S74 the instruction table dividing unit 104 creates a new exception mask and updates the exception mask. Specifically, the instruction table division unit 104 calculates a new exception mask EM # using the exception mask EM and the input mask m, using the following equation (7). EM & ⁇ M (7) Here, “&” means logical product for each bit, and “ ⁇ ” means inversion for each bit.
  • step S75 the instruction table dividing unit 104 adds a new exception condition to the output exception condition set. This new exception condition is a pair of the exception pattern in the exception condition being visited and the exception mask created in step S74.
  • FIG. 16 is a flowchart of the condition node creation process in the present embodiment.
  • the condition node creation process shown in FIG. 16 is the details of the process in step S15 in FIG.
  • the input of the condition node creation process is an instruction table with exception conditions, and the output is a condition node.
  • the condition node has an exception condition and two children as attributes.
  • the entity of the exception condition attribute is a mask and bit pattern pair (exception mask and exception pattern pair).
  • One of the children of the condition node corresponds to the case where the bit string to be decoded satisfies the exception condition, and the other corresponds to the case where the bit string to be decoded does not satisfy the exception condition.
  • the node creation unit 102 selects one arbitrary exception condition from all the exception conditions in the instruction table (S80).
  • the node creation unit 102 checks whether or not an exception condition exists in step S80 (S81). If no exception condition exists (No in S81), the process proceeds to step S82. If an exception condition exists (Yes in S81), the process proceeds to step S83.
  • the cause when the exception condition is not found in step S81 is an error in the input instruction table. Therefore, in step S82, the node creation unit 102 notifies the user that there is an error in the input command table. For example, the node creation unit 102 displays an error screen on a display unit such as a display (not shown). Alternatively, the node creation unit 102 may notify the user that an error has occurred by voice or the like.
  • step S83 the instruction table dividing unit 104 receives the instruction table and the exception mask and exception pattern pair of the exception condition selected in step S80, and uses the pattern matching instruction table described above with reference to FIG. Execute the creation process.
  • the exception mask and exception pattern pair of the selected exception condition are used as a mask and bit pattern pair.
  • step S84 the node creation unit 102 and the leaf creation unit 103 create a tree with the instruction table created in step S83 as an input (S84).
  • the tree creation process in step S84 is as described above with reference to FIG.
  • the instruction table division unit 104 performs pattern mismatch instruction table creation processing using the instruction table and the exception mask and exception pattern pair in the exception condition selected in step S80 as inputs.
  • the exception mask and exception pattern pair in the selected exception condition is used as a mask and bit pattern pair.
  • the pattern mismatch instruction table creation process is a process for creating an instruction table including only entries that do not match an input mask and bit pattern pair. Details of the pattern mismatch instruction table creation processing will be described later.
  • the node creation unit 102 and the leaf creation unit 103 create a tree with the instruction table created in step S85 as an input (S86).
  • the tree creation procedure is as described above with reference to FIG.
  • the node creation unit 102 creates an output condition node (S87).
  • the condition attribute of the condition node is the exception condition selected in step S80.
  • the tree created in step S84 is set as a child corresponding to the case where the condition is satisfied.
  • the tree created in step S86 is set to the child corresponding to the case where the condition is not satisfied.
  • FIG. 17 shows a pattern mismatch instruction table creation process in the present embodiment.
  • the pattern mismatch instruction table creation process shown in FIG. 17 is the details of the process in step S85 in FIG.
  • the input of the pattern mismatch instruction table creation process is a mask and bit pattern pair (exception mask and exception pattern pair) and an instruction table, and the output does not match the input mask and bit pattern pair in the input instruction table.
  • This is an instruction table consisting of only instructions.
  • the instruction table dividing unit 104 secures an area for storing the output instruction table in the memory (S90).
  • the output instruction table has no entry in the initial state.
  • Steps S91 to S96 are loop processing for circulating the input instruction table.
  • the instruction table dividing unit 104 selects an entry that does not match the input mask and bit pattern pair, and adds the selected entry to the output instruction table.
  • step S92 the instruction table division unit 104 is a pattern matching confirmation process for confirming whether or not the cyclic entry matches the inputted mask and bit pattern pair. Details of the pattern matching confirmation process in step S92 are as described above with reference to FIG.
  • step S93 the instruction table dividing unit 104 confirms whether or not the circulating instruction matches the mask and bit pattern pair based on the result of step S92. If they do not match (No in S93), the process proceeds to step S94. If they match (Yes in S93), the process skips steps S94 and S95, Proceed to step S96.
  • step S94 the instruction table dividing unit 104 creates a pattern mismatch exception condition set. Details of step S94 will be described later.
  • step S95 the instruction table dividing unit 104 adds the instruction table entry in circulation to the output instruction table entry. At this time, the exception condition set created in step S94 is used as the exception condition set of the entry added to the output instruction table.
  • FIG. 18 is a flowchart showing exception condition creation processing when a pattern does not match.
  • the exception condition creation process at the time of pattern mismatch shown in FIG. 18 is the details of the process in step S94 in FIG.
  • the input of the exception condition set creation process at the time of pattern mismatch is a mask and bit pattern pair (exception mask and exception pattern pair) and an exception condition set, and the output is only from invalid exception conditions in the input exception condition set Is a new exception condition set.
  • the instruction table dividing unit 104 secures an area for storing a set of output exception conditions in the memory (S100).
  • the set of output instruction conditions is empty in the initial state.
  • Steps S101 to S105 are a loop that circulates the exceptional condition set.
  • the instruction table division unit 104 adds the exception condition being cyclic to the output exception condition set if it is invalid for the mask and bit pattern pair to which the exception condition is input for each exception condition cycle.
  • step S102 the instruction table dividing unit 104 confirms whether or not the exception condition during circulation is valid for the input mask and bit pattern pair.
  • the instruction table dividing unit 104 has the following ( 8) When the formula is satisfied, it is determined that the exceptional condition during the circulation is valid.
  • EP & m & EM p & m & EM (9)
  • “&” means a logical product for each bit.
  • step S103 the instruction table dividing unit 104 confirms whether or not the confirmation result in step S102 is valid. If the confirmation result is not valid (No in S103), in other words, if the confirmation result is invalid, the process proceeds to step S104. If the confirmation result is valid (Yes in S103), step S104 is performed. Is skipped, and the process proceeds to step S105. In skip S104, the instruction table dividing unit 104 adds the exception condition during the circulation to the output exception condition set created in step S100. When the loop processing from step S101 to step S105 is completed, the result of the exception condition set creation process at the time of pattern mismatch is obtained as the output exception condition set.
  • the instruction table with exception conditions corresponding to the instruction table 111 shown in FIG. 8 is the instruction table 112a with exception conditions shown in FIG.
  • the node creation unit 102 fails in the node creation process in step S13. Therefore, the node creation unit 102 performs the condition node creation process in step S15, in other words, the condition node creation process shown in FIG.
  • the pattern matching instruction table 112b does not include the instruction B and the instruction C. This is because in the pattern matching instruction table creation process shown in FIG. 12, the instruction table dividing unit 104 removes the instruction B and the instruction C by using the exception condition (step S47 in FIG. 12). And step S53 in FIG. In step S84 in FIG.
  • step 11 when the node creation unit 102 and the leaf creation unit 103 perform the tree creation process shown in FIG. 10 again with the pattern matching instruction table 112b as an input, the leaf creation process in step 11 is performed. To succeed. Similarly, in step S85 in FIG. 16, when the node creation unit 102 and the leaf creation unit 103 perform the tree creation process shown in FIG. 10 again with the pattern mismatch instruction table 112c as an input, the node creation in step S13 is performed. Successful processing.
  • a decoding tree can be created from an instruction table having an exception condition by having means for dividing an instruction table with an exception condition using an exception condition in the tree creation process.
  • step S20 of FIG. 11 of the present embodiment is replaced with a process different from the operation of the operation code mask.
  • the node creation unit 102 is shown in FIG. 11 via step S13. Execute node creation processing.
  • the node creation unit 102 uses “11000000” as a mask in step S20.
  • the instruction table dividing unit 104 divides the input instruction table 111 into four instruction tables.
  • 20 and 21 are schematic diagrams for explaining how the instruction table dividing unit 104 divides the input instruction table into four instruction tables.
  • the instruction table 113a shown in FIG. 20A is input, the instruction B and the instruction C match the three bit patterns “00000000”, “01000000”, and “10000000”.
  • the unit 104 includes a pattern matching instruction table 113b shown in FIG. 20B, a pattern matching instruction table 113c shown in FIG. 21A, and a pattern matching instruction table shown in FIG. 113d is created. Since only the instruction A matches the bit pattern “11000000”, the instruction table dividing unit 104 creates the pattern matching instruction table 113e shown in FIG.
  • the pattern match instruction table 113e shown in FIG. 21C does not include the instruction B and the instruction C. For this reason, the tree creation process shown in FIG. 10 is recursively performed on the pattern matching instruction tables 113b to 113e, whereby the entire tree is completed.
  • the input instruction table 112a is divided into two, a pattern match instruction table 112b and a pattern mismatch instruction table 112c, whereas FIG. In the example shown in FIG. 21, the pattern matching instruction tables 113b to 113e are divided into four. The size of the decoding tree generated from the instruction table divided as shown in FIG.
  • the present embodiment includes processing for creating a condition node in step S15 of FIG. By including the condition node creation process in this way, the present embodiment can reduce the size of the instruction decode tree to be generated.
  • a decoding tree can be generated from an instruction table having exception conditions.
  • the present embodiment has a means for excluding exception conditions when the instruction table is divided in the tree creation process, so that one instruction has a decoding tree for an instruction table having a plurality of exception conditions. Can be created.
  • the instruction table with exception condition 116a illustrated in FIG. 24A includes three entries corresponding to the instruction A, the instruction B, and the instruction C.
  • “ ⁇ ” means logical product.
  • this embodiment has a means for updating the exception condition when dividing the instruction table, thereby improving the decoding efficiency with respect to the instruction table in which a plurality of exception conditions share a part of the condition.
  • a good decoding tree can be created.
  • the node creation unit 102 executes the node creation process shown in FIG. 11 in step S13.
  • the instruction table dividing unit 104 generates the pattern matching instruction table 117b shown in FIG. 25B and the pattern matching instruction table 117c shown in FIG.
  • the mask “00000011” of the node 131a is first applied to the instruction I to obtain a pattern “00000001”.
  • the leaf 131b corresponding to the instruction B is selected.
  • a leaf is associated with an entry in the instruction table B in step S11 when creating a leaf. Therefore, after reaching the leaf 131b, the instruction decoder can check the instruction sequence I using the exceptional condition of B.
  • the instruction decoder can prevent an incorrect instruction sequence I from being erroneously determined as the instruction B.
  • this embodiment has a means for associating an exception condition with a leaf of a decoding tree, so that even when an instruction table including an exception condition unnecessary for instruction table division is input, the instruction A decoding tree in which the decoder can normally determine the instruction can be created.
  • FIG. 27 is a schematic diagram illustrating an example of a decoding tree generated in the present embodiment.
  • the decoding tree 132 shown in FIG. 27 is obtained as a result of executing the tree generation process shown in FIG. 10 with the exception condition instruction table 118 shown in FIG. 28 as an input.
  • Reference numerals 132a and 132i are nodes.
  • Reference numerals 132c, 132d, and 132e are condition nodes.
  • Reference numerals 132b, 132f, 132g, 132h, 132j, and 132k are leaves.
  • the instruction decoder identifies the instruction of the instruction bit string I by tracing from the root of the decoding tree to the leaf according to the value of the instruction bit string I.
  • the instruction decoder checks the instruction bit string I using the node 132a which is the root of the tree.
  • the mask of the node 132a is “11000000”, and when this is applied to the instruction bit string, the pattern “100000000” is obtained as a result. Since the child corresponding to the pattern “11000000” in the node 132a is the node 132c, the instruction decoder next checks the instruction bit string I using the node 132c.
  • FIG. 29 is a schematic diagram showing a program representation of a decoding tree.
  • the decoding tree 133 shown in FIG. 29 is a C language program that can be compiled by the GNU C compiler. The correspondence with each node and leaf of the decoding tree 132 shown in FIG. 27 is shown in the comments in the program. Note that binary notation prefixed with 0b is used as a numeric literal for readability of patterns and masks, but this is an extension notation of GCC.
  • the program shown in FIG. 29 is not only one of the representation forms of the decoding tree, but also the instruction decoder program itself.
  • the function Decode receives an instruction bit string i and returns an instruction identifier as a return value.

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  • General Physics & Mathematics (AREA)
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Abstract

L'invention concerne : une unité de division de table d'instructions (104) permettant de diviser une table d'instructions en une première table d'instructions comprenant des entrées pour lesquelles les informations de code de fonctionnement concordent avec une quelconque condition d'une pluralité de conditions d'exception et en une seconde table d'instructions comprenant des entrées pour lesquelles les informations de code de fonctionnement ne concordent pas avec une quelconque condition d'une pluralité de conditions d'exception lorsque la condition ou la pluralité de conditions d'exception sont incluses dans au moins une entrée d'une pluralité d'entrées dans une table d'instructions, et qu'il est impossible de calculer un masque commun à toutes les informations de code de fonctionnement incluses dans la pluralité d'entrées ; et une unité de création d'arborescence (101) permettant de créer un arbre de décodage pour spécifier des identifiants d'instructions correspondant à des chaînes de bits à partir de la table d'instructions divisée.
PCT/JP2015/070395 2015-07-16 2015-07-16 Dispositif de traitement d'informations, procédé de traitement d'informations et programme WO2017009996A1 (fr)

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Citations (2)

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JPH08235019A (ja) * 1995-02-22 1996-09-13 Matsushita Electric Ind Co Ltd 命令テーブル生成方法
US20050268289A1 (en) * 2004-05-28 2005-12-01 Samsung Electronics Co., Ltd. Method for decoding instruction in architectural simulator

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JP3167305B2 (ja) * 1989-12-28 2001-05-21 株式会社リコー 可変長符号の復号化テーブルの自動作成方法
EP1290588A2 (fr) * 2000-05-24 2003-03-12 Koninklijke Philips Electronics N.V. Ameliorations apportees a un environnement de modelisation et de simulation de conceptions d'un circuit electronique oriente objet
KR100484137B1 (ko) * 2002-02-28 2005-04-18 삼성전자주식회사 개선된 허프만 디코딩 방법 및 장치
US7219337B2 (en) * 2003-03-06 2007-05-15 Northrop Grumman Corporation Direct instructions rendering emulation computer technique
JP2005063165A (ja) * 2003-08-13 2005-03-10 Fujitsu Ltd 仮想計算機の高速エミュレータ
JP3938580B2 (ja) * 2004-12-21 2007-06-27 株式会社ソニー・コンピュータエンタテインメント 情報処理装置、情報処理方法、半導体装置、コンピュータプログラム

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JPH08235019A (ja) * 1995-02-22 1996-09-13 Matsushita Electric Ind Co Ltd 命令テーブル生成方法
US20050268289A1 (en) * 2004-05-28 2005-12-01 Samsung Electronics Co., Ltd. Method for decoding instruction in architectural simulator

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