WO2017008283A1

WO2017008283A1 - Layout structure for reducing noise generated by printed circuit board

Info

Publication number: WO2017008283A1
Application number: PCT/CN2015/084136
Authority: WO
Inventors: 杨涛
Original assignee: 华为技术有限公司
Priority date: 2015-07-15
Filing date: 2015-07-15
Publication date: 2017-01-19
Also published as: CN107852815A; CN107852815B

Abstract

A layout structure for reducing noise generated by a printed circuit board comprises: a printed circuit board (PCB) (101), a power supply signal line (102), and at least two piezoelectric elements (103). The power supply signal line is disposed on the PCB. Two adjacent piezoelectric elements of the at least two piezoelectric elements are disposed on the PCB at the same angle and connected to the power supply signal line, respectively. Therefore, noise of the printed circuit board can be effectively reduced.

Description

Layout structure for reducing noise generated by printed wiring boards

Technical field

The present invention relates to the field of printed wiring boards, and more particularly to a layout structure for reducing noise generated by a printed wiring board.

Background technique

At present, ceramic capacitors have been widely used, but when they are applied with alternating voltages (especially for large-capacity ceramic capacitors, such as those above the micro-level), the deformation of the capacitor body is caused by the piezoelectric effect. In practical applications, after the ceramic capacitor is applied with a periodic alternating voltage, the internal capacitance of the ceramic capacitor will be squeezed or stretched due to the piezoelectric effect, and transmitted to the printed circuit board (PCB) through the pad of the capacitor. The PCB will undergo periodic deformation, and the deformation of the PCB will produce sound waves, which is the appearance of noise. Therefore, how to avoid the defect of the piezoelectric effect of the ceramic capacitor and solve the noise generated further becomes an urgent problem to be solved.

In the prior art, the single-capacitor and the flexible printed circuit (FPC) are mainly arranged to reduce the single-board noise caused by the FPC deformation caused by the capacitive piezoelectric effect, for example, a single capacitor It is placed at an angle to the axis of the FPC. However, this method does not effectively reduce the noise of the printed circuit board.

Summary of the invention

Embodiments of the present invention provide a layout structure for reducing noise generated by a printed wiring board, which can effectively reduce noise of a printed wiring board.

In a first aspect, a layout structure for reducing noise generated by a printed wiring board is provided, the layout structure comprising: a printed wiring board PCB, a power signal line, and at least two piezoelectric elements;

The power signal line is disposed on the PCB;

Two of the at least two piezoelectric elements are disposed at the same angle on the PCB, and the at least two piezoelectric elements are respectively connected to the power signal line.

In conjunction with the first aspect, in a first implementation of the first aspect, the capacitance values of the at least two piezoelectric elements are the same.

In conjunction with the first implementation of the first aspect, in a second implementation of the first aspect, each of the at least two piezoelectric elements is applied when an alternating voltage is applied to the power signal line A deformation stress is generated, wherein the deformation stress includes: tension and contraction.

In conjunction with the second implementation of the first aspect, in a third implementation of the first aspect, the direction of the deformation stress is determined according to an electromotive force of each of the piezoelectric elements, and the magnitude of the deformation stress is Determined according to the alternating voltage.

In conjunction with the second implementation of the first aspect or the third implementation of the first aspect, in a fourth implementation of the first aspect, each of the at least two piezoelectric elements is under the same voltage condition Piezoelectric elements produce the same tension;

Correspondingly, each of the at least two piezoelectric elements produces the same contraction force.

With reference to the first aspect, or any one of the foregoing four implementation manners of the first aspect, in a fifth implementation manner of the first aspect, the number of the piezoelectric elements is three;

Locating the two adjacent ones of the at least two piezoelectric elements at the same angle on the PCB includes:

Two of the three piezoelectric elements are disposed on the PCB at an angle of 120 degrees, and one of the piezoelectric elements is located on one side of the power signal line, and the other two piezoelectric elements are located The other side of the power signal line.

In conjunction with the fifth implementation of the first aspect, in a sixth implementation manner of the first aspect, one end of each of the three piezoelectric elements is connected to the power signal line, and the other end Ground.

In combination with the first aspect or any one of the foregoing six implementation manners of the first aspect, at the first In a seventh implementation of the aspect, the piezoelectric element is a multilayer ceramic capacitor MLCC.

The layout structure for reducing the noise generated by the printed circuit board provided by the embodiment of the present invention includes: a printed circuit board PCB, a power signal line, and at least two piezoelectric elements; the power signal line is disposed on the PCB; Two of the at least two piezoelectric elements are disposed at the same angle on the PCB, and the at least two piezoelectric elements are respectively connected to the power signal line. Thereby, the noise of the printed wiring board can be effectively reduced.

DRAWINGS

1 is a schematic structural view of a layout for reducing noise generated by a printed circuit board according to Embodiment 1 of the present invention;

2 is a schematic view showing deformation stress generated by each capacitor in FIG. 1;

FIG. 3 is an exploded perspective view showing deformation stress generated by each capacitor in FIG. 2. FIG.

detailed description

The technical solution of the present invention will be further described in detail below through the accompanying drawings and embodiments.

The technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the drawings in the embodiments of the present invention. It is a partial embodiment of the invention, and not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.

In order to facilitate the understanding of the embodiments of the present invention, the embodiments of the present invention are not to be construed as limiting.

The layout structure for reducing the noise generated by the printed circuit board provided by the embodiment of the present invention is applied to a filter circuit of a power source, and the filtering of the power source is usually realized by a capacitance of a certain capacitance value, and a capacitance of a certain capacitance value, especially a large capacity. When the value of the capacitor (for example, the capacity above the micro-level) is applied with an alternating voltage, the piezoelectric body will be deformed due to the piezoelectric effect, which will cause noise on the PCB. The production. In order to avoid the generation of noise on the PCB, the present invention realizes the capacitance of a certain capacitance value by combining a plurality of capacitors with a small capacitance value. Preferably, the capacitances of the plurality of capacitors having a smaller capacitance value are the same, and the capacitance value is the same. The number of small capacitors can be adjusted. Here, the adjustment of the number of capacitors with a small capacitance value can be combined with the following two conditions: 1) whether the capacitance with a smaller capacitance value is already existing; 2) the piezoelectric effect of a plurality of capacitors with a small capacitance value is generated. Whether the deformation stresses can cancel each other or reach a minimum.

Of course, in practical applications, condition 1) can be used as a priority condition to be satisfied, and if condition 1) is satisfied, whether or not condition 2) is satisfied.

For example, if the capacitance of the capacitor is determined to be 60F according to the requirements of the power source to be filtered, the capacitor with a capacitance of 60F can be realized by a combination of two capacitors with a capacitance of 30F, or three capacitors. Implemented for a 20F capacitor combination. It is assumed that the capacitors of the above two kinds of capacitance can be produced in the market, that is, both division methods satisfy the condition 1), but since the deformation stress generated by the piezoelectric effect of the capacitance of 20F is canceled, the volume can be adjusted. The number of capacitors with a small value (ie, 20F) is three, that is, the capacitor with a capacitance of 60F can be realized by a combination of three 20F capacitors.

1 is a schematic structural view of a layout for reducing noise generated by a printed wiring board according to Embodiment 1 of the present invention. In FIG. 1, the layout structure includes: a printed circuit board PCB 101, a power signal line 102, and at least two piezoelectric elements. 103.

The power signal line 102 is disposed on the PCB 101;

Two of the at least two piezoelectric elements 103 are disposed at the same angle on the PCB 101, and at least two of the piezoelectric elements 103 are respectively connected to the power signal line 102.

At least two piezoelectric elements 103 are arranged on both sides of the power signal line 102. Preferably, the piezoelectric element 103 is a Multi-layer Ceramic Capacitors (MLCC); in addition, the capacitance values of the at least two piezoelectric elements 103 may be the same.

In this embodiment, the number of the piezoelectric elements 103 is three, and the piezoelectric element 103 is specifically an MLCC as an example, that is, a capacitor having a certain capacitance is realized by a combination of three capacitors having a small capacitance value. The three capacitors having a smaller capacitance are respectively the first capacitor C ₁ , the second capacitor C _{2 ,} and the third capacitor C ₃ , and the capacitances of the first capacitor C ₁ , the second capacitor C _{2 ,} and the third capacitor C ₃ are the same .

In FIG. 1 , the power signal line 102 is horizontally disposed on the PCB 101 along the axis of the abscissa axis, and the first capacitor C ₁ , the second capacitor C _{2 ,} and the third capacitor C ₃ are disposed on the PCB 101 at an angle of 120 degrees to each other, and the The three capacitors are arranged on both sides of the power signal line 102, that is, the first capacitor C ₁ is located on one side (upper side) of the power signal line 102, and the second capacitor C ₂ and the third capacitor C _{3 are} located on the power signal line 102. One side (lower side); in addition, one end of the first capacitor C ₁ is connected to the power signal line 102, the other end is grounded, one end of the second capacitor C ₂ is connected to the power signal line 102, the other end is grounded, and the third capacitor C One end of ₃ is connected to the power signal line 102 and the other end is grounded; and since the first capacitor C ₁ , the second capacitor C ₂ and the third capacitor C ₃ are both connected to the power signal line 102 , the three capacitors have the same Voltage conditions.

For the above layout structure, when an alternating voltage is applied to the power signal line 102, each of the at least two piezoelectric elements 103 generates a deformation stress, wherein the deformation stress includes: tension and contraction, here, Tension refers to the force generated by one end of each piezoelectric element connected to the power signal line 102, and the contraction force refers to the force generated by one end of each piezoelectric element to which the piezoelectric element is grounded. The direction of the deformation stress may be determined according to the electromotive force of each piezoelectric element, and the magnitude of the deformation stress may be determined according to the alternating voltage.

For example, referring to the deformation stress diagram generated by each capacitor in FIG. 1 shown in FIG. 2, when an alternating voltage is applied to the power signal line 102, a piezoelectric effect occurs in all three capacitors, thereby causing three capacitors to be Deformation stress is generated, the deformation stress of the first capacitor C ₁ is f ₁₁ and f ₁₂ , the deformation stress of the second capacitor C ₂ is f ₂₁ and f ₂₂ , and the deformation stress of the third capacitor C ₃ is f ₃₁ and f ₃₂ , wherein , f ₁₂ , f _{21 ,} and f ₃₁ are the tensions in the deformation stress generated by the three capacitors, respectively, and f ₁₁ , f _{22 ,} and f ₃₂ are the contraction forces in the deformation stress generated by the three capacitors, respectively. In Figure 2, the direction of the deformation stress of the three capacitors is related to the electromotive force (ie, the voltage direction) across the three capacitors.

Further, in FIG. 1, under the same voltage condition, each of the at least two piezoelectric elements generates the same tension; correspondingly, each of the at least two piezoelectric elements produces the same contraction force. That is, under the same voltage condition, the tensions of the different capacitances of the same capacitance are consistent, the contraction forces are consistent, or the magnitude of the deformation stress of the three capacitors is related to the magnitude of the alternating voltage applied on the power signal line 102. Therefore, f ₁₂ has the same size as f ₂₁ and f ₃₁ , and f _{11 has the} same size as f ₂₂ and f ₃₂ .

Here, it should be noted that the tension and the contraction force of the same capacitor described above are inconsistent, and it is this inconsistency that causes the deformation of the capacitor itself.

Referring to the exploded view of the deformation stress generated by each of the capacitors shown in FIG. 3, in FIG. 3, according to the principle of orthogonal decomposition of forces, the deformation stress of the three capacitors can be decomposed into the horizontal force f _x and the vertical direction. The force f _y , and f _x and f _y are calculated according to the following formula:

f _x =f ₂₁ ×cos(α)+f ₃₂ ×cos(α)-f ₂₂ ×cos(α)-f ₃₁ ×cos(α);

f _y =f ₁₁ -f ₁₂ +f ₂₁ ×sin(α)+f ₃₁ ×sin(α)-f ₂₂ ×sin(α)-f ₃₂ ×sin(α);

And since f ₁₁ =f ₂₂ =f ₃₂ , f ₁₂ =f ₂₁ =f ₃₁ , and α=30°, then

f _x =0;

f _y =f ₁₁ -f ₁₂ +0.5×f ₁₂ +0.5×f ₁₂ -0.5×f ₁₁ -0.5×f ₁₁ =0;

Thereby, the forces in both directions are offset.

It can be seen from the above that when a capacitance of a certain capacitance value (especially a capacitance of a large capacitance value) is realized by a combination of three capacitors having a small capacitance value, the deformation stress generated by the piezoelectric effect of the capacitor will become 0, that is, it can be circumvented. The ceramic capacitor has the drawback of piezoelectric effect, which can effectively reduce the noise of printed circuit boards.

Of course, in practical applications, when a capacitance of a certain capacitance cannot be realized by a combination of three capacitors having a small capacitance value, in the case where the capacitances of the capacitors having a small capacitance value are the same, the above conditions can also be used. 1) and/or condition 2) adjusting the number of capacitors having a small capacitance, such as four, five or other numbers, which are not limited in this application. It can be understood that when the number of capacitors with smaller capacitance values is adjusted to four, five or other numbers, the placement position on the PCB and the calculation method of the deformation stress thereof and the three capacitors in the first embodiment Consistently, the present invention will not be described herein.

In short, when a capacitor of a certain capacitance value is realized by a combination of a plurality of capacitors having a small capacitance value, and the adjacent two capacitors of the plurality of capacitance values are disposed at the same angle on the PCB, the ceramic capacitor can be effectively cancelled. The deformation stress generated by the piezoelectric effect can effectively reduce the noise of the printed wiring board.

A person skilled in the art should further appreciate that the elements and algorithm steps of the various examples described in connection with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both, in order to clearly illustrate hardware and software. Interchangeability, the composition and steps of the various examples have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the solution. A person skilled in the art can use different methods for implementing the described functions for each particular application, but such implementation should not be considered to be beyond the scope of the present invention.

The steps of a method or algorithm described in connection with the embodiments disclosed herein can be implemented in hardware, a software module executed by a processor, or a combination of both. The software module can be placed in random access memory (RAM), memory, read only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or technical field. Any other form of storage medium known.

The specific embodiments of the present invention have been described in detail with reference to the preferred embodiments of the present invention. All modifications, equivalent substitutions, improvements, etc., made within the spirit and scope of the invention are intended to be included within the scope of the invention.

Claims

A layout structure for reducing noise generated by a printed wiring board, wherein the layout structure comprises: a printed circuit board PCB, a power signal line, and at least two piezoelectric elements;

The power signal line is disposed on the PCB;

Two of the at least two piezoelectric elements are disposed at the same angle on the PCB, and the at least two piezoelectric elements are respectively connected to the power signal line.
The layout structure according to claim 1, wherein the at least two piezoelectric elements have the same capacitance value.
The layout structure according to claim 2, wherein each of the at least two piezoelectric elements generates a deformation stress when an alternating voltage is applied to the power signal line, wherein the deformation Stresses include: tension and contraction.
The layout structure according to claim 3, wherein the direction of the deformation stress is determined according to an electromotive force of each of the piezoelectric elements, and the magnitude of the deformation stress is determined according to the alternating voltage.
The layout structure according to claim 3 or 4, wherein each of the at least two piezoelectric elements generates the same tension under the same voltage condition;

Correspondingly, each of the at least two piezoelectric elements produces the same contraction force.
The layout structure according to any one of claims 1 to 5, wherein the number of the piezoelectric elements is three;

Locating the two adjacent ones of the at least two piezoelectric elements at the same angle on the PCB includes:

Two of the three piezoelectric elements are disposed on the PCB at an angle of 120 degrees, and one of the piezoelectric elements is located on one side of the power signal line, and the other two piezoelectric elements are located The other side of the power signal line.
The layout structure according to claim 6, wherein one end of each of the three piezoelectric elements is connected to the power signal line and the other end is grounded.
The layout structure according to any one of claims 1 to 7, wherein the piezoelectric element is a multilayer ceramic capacitor MLCC.