WO2017006437A1

WO2017006437A1 - Controller mounted on component mounting machine

Info

Publication number: WO2017006437A1
Application number: PCT/JP2015/069557
Authority: WO
Inventors: 陽祐寺西; 和弘浅田; 文則伊藤; 秀幸熊澤
Original assignee: 富士機械製造株式会社
Priority date: 2015-07-07
Filing date: 2015-07-07
Publication date: 2017-01-12
Also published as: JP6584506B2; JPWO2017006437A1

Abstract

A controller that is mounted on a component mounting machine for mounting electronic components on a circuit substrate, and that controls at least some operations of the component mounting machine, wherein: said controller is provided with a processor for executing a plurality of tasks, and a ring buffer for storing log information relating to the tasks executed by the processor; the ring buffer is divided into partial ring buffers, each of which stores log information relating to execution of one of the plurality of tasks by the processor; and the processor is configured to store log information relating to each task of the plurality of tasks in the corresponding one of the partial ring buffers on a per processing cycle basis.

Description

Controller equipped on component mounter

The technology disclosed in this specification relates to a component mounter that mounts electronic components on a circuit board, and more particularly, to a controller that is mounted on the component mounter.

Patent Document 1 (Japanese Patent Publication No. 2012-018617) discloses an electronic component mounting apparatus for mounting electronic components on a substrate. The electronic component mounting apparatus includes a control device having a ring buffer memory. The control device executes the control program and controls each part of the electronic component mounting apparatus to mount the electronic component on the board. The control device stores log data, which is execution history information of the control program, in the ring buffer memory.

Generally, in a component mounter, a processor executes a plurality of tasks and stores log information related to each of the plurality of tasks in a ring buffer. When an abnormality occurs in the component mounter, the operator diagnoses the abnormality of the component mounter from each state of a plurality of tasks using log information stored in the ring buffer. For this reason, in order to diagnose the state of the component mounter, log information regarding all tasks is preferably stored in the ring buffer. In the electronic component mounting apparatus disclosed in Patent Document 1, log information related to a plurality of tasks is stored in a single ring buffer. According to such a configuration, the log information of one task may be overwritten by the log information of another task. As a result, the log information of all tasks may not be stored in the ring buffer. In this case, there is a problem that there is a task that cannot confirm the state at the time of occurrence of the abnormality.

The controller disclosed in this specification is mounted on a component mounter that mounts electronic components on a circuit board, and controls the operation of at least a part of the component mounter. The controller includes a processor that executes a plurality of tasks and a ring buffer that stores log information related to the tasks executed by the processor. The ring buffer is divided into partial ring buffers for storing log information when the processor executes the task for each of a plurality of tasks, and the processor performs the task for each of the plurality of tasks for each processing cycle. Is stored in a partial ring buffer corresponding to the task.

In the above controller, the ring buffer that stores log information is divided into a partial ring buffer that stores log information related to the task for each of a plurality of tasks. That is, only log information related to a specific task is stored in the partial ring buffer. According to such a configuration, it is possible to prevent log information relating to one task from being overwritten by log information relating to another task. As a result, log information regarding each of the plurality of tasks is stored in the ring buffer.

It is a side view which represents typically the structure of the component mounting machine with which the controller is equipped. It is a block diagram which shows the structure of a controller. It is a figure explaining the information regarding the task preserve | saved at main RAM. It is a conceptual diagram explaining a partial ring buffer. It is a figure which shows the flowchart of the ring buffer division | segmentation process of Example 1. FIG. It is a conceptual diagram explaining the state of the partial ring buffer before and behind divided | segmented by a ring buffer division | segmentation process. FIG. 10 is a diagram illustrating a flowchart of ring buffer division processing according to the second embodiment. It is a conceptual diagram explaining the main RAM of a modification.

The technical elements described below are independent technical elements and exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing.

(Feature 1) The processor may be configured to store time information corresponding to the log information in the partial ring buffer when the log information is stored in the partial ring buffer. According to such a configuration, the operator can confirm the time when the log information is stored by confirming the time information.

(Characteristic 2) The processor calculates, for each of a plurality of tasks, the occupation ratio of the task in the total processing capacity of the processor for each predetermined setting period, and each of the plurality of tasks for each setting period. The ring buffer may be divided into partial ring buffers having a size corresponding to the occupation rate calculated for the task. According to such a configuration, the size of the partial ring buffer is determined based on the task occupancy ratio in the total processing capacity of the processor. As a result, the ring buffer can be divided into partial ring buffers having appropriate sizes.

(Feature 3) The processor calculates the information size of the log information stored in each of the plurality of partial ring buffers during the set period for each set period and sets a plurality of tasks for each set period. For each of these, a partial ring buffer having a size corresponding to a ratio between the information size calculated for the task and the information size of all the log information stored in the set period may be divided. According to such a configuration, the partial ring buffer is divided based on the information size of the log information stored in each of the plurality of partial ring buffers during a predetermined setting period. As a result, the ring buffer can be divided into partial ring buffers having appropriate sizes.

(Feature 4) A sub-memory for storing a plurality of log information may be further provided. When changing the size of any of the plurality of partial ring buffers, the processor saves log information stored in each of the plurality of partial ring buffers to the sub memory, and then saves the log information to the sub memory. After changing the size of multiple partial ring buffers and changing the size of multiple partial ring buffers, the log information saved in the sub memory is saved in each of the multiple partial ring buffers. May be. According to such a configuration, when changing the size of any partial ring buffer, the log information before the change is saved in the sub memory, and the log information saved in the sub memory after the size change is divided. Return to buffer. Thereby, the log information is appropriately rewritten before and after the size change, and the log information related to the task corresponding to the partial ring buffer can be stored in the divided partial ring buffer.

Next, the component mounter 10 equipped with the controller 40 will be described with reference to FIGS. The component mounter 10 is a device for mounting the electronic component 4 on the circuit board 2. The component mounter 10 is also referred to as a surface mounter or a chip mounter. Usually, the component mounting machine 10 is provided together with a solder printer, other component mounting machines, and a board inspection machine, and constitutes a series of mounting lines.

As shown in FIG. 1, the component mounter 10 includes a plurality of component feeders 12, a feeder holding unit 14, a mounting head 16, an imaging unit 20, and a moving device 18 that moves the mounting head 16 and the imaging unit 20. A substrate conveyor 26, an operation panel 28, and a controller 40.

Each component feeder 12 accommodates a plurality of electronic components 4. The component feeder 12 is detachably attached to the feeder holding unit 14 and supplies the electronic component 4 to the mounting head 16. The specific configuration of the component feeder 12 is not particularly limited. Each component feeder 12 is, for example, a tape feeder that accommodates a plurality of electronic components 4 on a winding tape, a tray feeder that accommodates a plurality of electronic components 4 on a tray, or a plurality of electronic components 4 in a container. Any of the bulk type feeders that accommodates the ink at random.

The moving device 18 is an example of a moving device that moves the mounting head 16 and the imaging unit 20 between the component feeder 12 and the circuit board 2. The moving device 18 of the present embodiment is an XY robot that moves the moving base 18a in the X direction and the Y direction. The moving device 18 includes a guide rail that guides the moving base 18a, a moving mechanism that moves the moving base 18a along the guide rail, and a servo motor 30 (shown in FIG. 2) that drives the moving mechanism. . The moving device 18 is disposed above the component feeder 12 and the circuit board 2. The mounting head 16 and the imaging unit 20 are attached to the moving base 18a. The mounting head 16 and the imaging unit 20 are moved above the component feeder 12 and above the circuit board 2 by the moving device 18.

The mounting head 16 includes a suction nozzle 6 that sucks the electronic component 4. The suction nozzle 6 is detachable from the mounting head 16. The suction nozzle 6 is attached to the mounting head 16 so as to be movable in the Z direction (vertical direction in the drawing). The suction nozzle 6 is configured to be moved up and down by a servo motor 30 (shown in FIG. 2) accommodated in the mounting head 16 and to suck the electronic component 4. In order to mount the electronic component 4 on the circuit board 2 by the mounting head 16, first, the suction nozzle 6 is moved downward until the lower surface (suction surface) of the suction nozzle 6 contacts the electronic component 4 accommodated in the component feeder 12. Move. Next, the electronic component 4 is sucked by the suction nozzle 6 and the suction nozzle 6 is moved upward. Next, the mounting head 16 is positioned with respect to the circuit board 2 by the moving device 18. Next, the electronic component 4 is mounted on the circuit board 2 by lowering the suction nozzle 6 toward the circuit board 2. In the present specification, the above operation by the mounting head 16 is referred to as mounting processing.

The imaging unit 20 is attached to the moving base 18a. For this reason, when the mounting head 16 moves, the imaging unit 20 also moves together. The imaging unit 20 includes a camera support unit 22 and a camera 24. The camera support unit 22 is attached to the moving base 18a. A camera 24 is attached to the camera support portion 22. The camera 24 is disposed on the side of the suction nozzle 6 (the Y direction in the drawing) and captures a side image of the suction nozzle 6. In addition, the area of the suction nozzle 6 included in the imaging area of the camera 24 can be adjusted by moving the suction nozzle 6 up and down by the mounting head 16.

The board conveyor 26 is a device that carries the circuit board 2 into the component mounter 10, positions it on the component mounter 10, and carries it out of the component mounter 10. The substrate conveyor 26 of this embodiment includes, for example, a pair of belt conveyors, a support device (not shown) that is attached to the belt conveyor and supports the circuit board 2 from below, and a servo motor 30 that drives the belt conveyor (FIG. 2). Can be configured. The operation panel 28 is an input device that receives an instruction from the worker and an interface device that displays various types of information to the worker.

As shown in FIG. 2, the controller 40 is connected to the host controller 110, the servo motor 30, and the camera 24. The controller 40 controls the plurality of servo motors 30 based on the command input from the host control device 110 and the side image input from the camera 24 and mounts the electronic component 4 on the circuit board 2.

The controller 40 includes a CPU 50, a ROM 60, a main RAM 70, and a sub RAM 80. The CPU 50 is a processor that controls the operation of the controller 40. The CPU 50 is connected to the ROM 60, the main RAM 70, and the sub RAM 80. A plurality of tasks 62 are stored in the ROM 60. The plurality of tasks 62 include a servo processing task 62 a that controls the operation (such as torque) of the servo motor 30, a camera processing task 62 b that processes a side image transmitted from the camera 24, and inputs from the host controller 110 and the camera 24. An IO processing task 62c for processing information and output information to the servo motor 30 is included. The CPU 50 mounts the electronic component 4 on the circuit board 2 by executing a plurality of tasks 62 stored in the ROM 60. Note that the occupation ratio of each of the plurality of tasks 62 occupying the entire processing capacity of the CPU 50 changes dynamically depending on the processing contents executed by the CPU 50.

The main RAM 70 includes a ring buffer. Log data 74 corresponding to the task 62 executed by the CPU 50 is stored in the ring buffer of the main RAM 70. As shown in FIG. 3, the main RAM 70 records information about log data 74 and addresses 72 (A ₁ , A ₂ ,..., A _n ) where the log data 74 is stored. The log data 74 includes log information 74a (L ₁ , L ₂ ,..., L _n ) related to the task 62, and time information 74b (T ₁ , T2,..., T _n corresponding to the log information 74a. )It is included. The CPU 50 transmits the log data 74 stored in the main RAM 70 to the host controller 110 based on a command input from the host controller 110. The operator can confirm the state of the task 62 (that is, the state of the component mounter 10) by analyzing the log data 74 transmitted to the host controller 110.

As shown in FIG. 4, the ring buffer of the main RAM 70 includes a plurality of partial ring buffers 76a for storing log data 74 when the CPU 50 executes the tasks 62a to 62c for each of the tasks 62a to 62c. It is divided into 76b and 76c. Specifically, the ring buffer of the main RAM 70 includes a first partial ring buffer 76a corresponding to the servo processing task 62a, a second partial ring buffer 76b corresponding to the camera processing task 62b, and a first partial ring buffer 76c corresponding to the IO processing task 62c. It is divided into three partial ring buffers 76c. The plurality of

partial ring buffers

76a, 76b, and 76c have the same structure except for the size. Hereinafter, when any one of the plurality of

partial ring buffers

76a, 76b, and 76c is expressed without distinction, it is expressed as “partial ring buffer 76”. The CPU 50 executes a plurality of tasks 62 for each processing cycle, and for each of the plurality of tasks 62 executed for each processing cycle, the log data 74 corresponding to the task 62 is a portion corresponding to the task 62. Save in the ring buffer 76. That is, only the log data 74 of the task 62 corresponding to the partial ring buffer 76 is stored in the partial ring buffer 76. For example, when the CPU 50 executes the servo processing task 62a, the log data 74 is stored in the partial ring buffer 76a. According to such a configuration, it is possible to prevent the log data 74 stored in the partial ring buffers 76a to 76c from being overwritten by the log data 74 corresponding to different partial ring buffers 76a to 76c. The CPU 50 transmits log data 74 stored in the main RAM 70 to the upper control device 110 based on a command from the upper control device 110. The worker confirms the state of the task 62 being executed by the component mounter 10 by analyzing the log data 74 received by the host controller 110. Since the main RAM 70 includes a plurality of partial ring buffers 76, log data 74 corresponding to each of the plurality of tasks 62a to 62c is reliably transmitted to the host control device 110. Thereby, the worker can appropriately determine the state of each of the plurality of tasks 62a to 62c.

As described above, the occupation ratio of each of the plurality of tasks 62a to 62c occupying the entire processing capacity of the CPU 50 changes dynamically. In general, a task 62 with a higher occupation rate generates more log data 74 than a task 62 with a lower occupation rate. For this reason, the size of the partial ring buffer 76 can be dynamically changed according to the occupation ratio of the task 62 in the ring buffer division processing described later. Note that the size of the partial ring buffer 76 at the start of operation of the component mounter 10 (default) is preferably set based on the occupation rate of each task in the operation start process of the component mounter 10.

The sub RAM 80 includes a ring buffer. In the ring buffer of the sub-RAM 80, log data 74 stored in the partial ring buffers 76a to 76c is temporarily stored during ring buffer division processing described later. Note that the size of the sub RAM 80 is preferably larger than the size of the main RAM 70.

Next, the ring buffer division processing executed by the CPU 50 will be described with reference to FIGS. Ring buffer division process is a process executed in the first every set period t _1. The first setting period t ₁ may be set in advance or may be configured to be input from the operation panel 28. The shorter the first setting period t ₁ , the easier it is to deal with when the occupation rate of each task changes abruptly, for example, when the component mounter 10 fails. The size of the ring buffer of the main RAM 70 is, for example, 100 Mbytes, and the sizes of the

partial ring buffers

76a, 76b, 76c before the ring buffer division processing are, for example, 20 Mbytes, 30 Mbytes, and 50 Mbytes. Further, the size of the partial ring buffers 76a to 76c before the ring buffer division processing is set as the first division size, and the size of the partial ring buffers 76a to 76c after the ring buffer division processing is set as the second division size.

First, in step S12, CPU 50, for each of a plurality of tasks 62a ~ 62c of executing the first set time period _{t 1,} to calculate the occupation ratio of each task 62a ~ 62c to the total capacity of the CPU 50. Next, in step S14, the CPU 50 sets the second divided sizes of the partial ring buffers 76a to 76c based on the occupation ratios of the tasks 62a to 62c calculated in step S12. As described above, the tasks 62a to 62c having a high occupation rate of the CPU 50 generate more log data 74 than the tasks 62a to 62c having a low occupation rate. For this reason, the CPU 50 makes the size of the partial ring buffers 76a to 76c corresponding to the tasks 62a to 62c having a high occupation ratio larger than the size of the partial ring buffers 76a to 76c corresponding to the tasks 62a to 62c having a low occupation ratio. As described above, the second division size is set. Specifically, the CPU 50 sets the second divided size of the partial ring buffer 76 by multiplying the size of the ring buffer of the main RAM 70 by the occupation rates of the tasks 62a to 62c. For example, if the occupation ratios of the

tasks

62a, 62b, and 62c are calculated as 60%, 20%, and 20%, and the size of the ring buffer of the main RAM 70 is 100 Mbytes, the

partial ring buffers

76a and 76b , 76c are set to 60 Mbytes, 20 Mbytes, and 20 Mbytes, respectively.

Next, in step S <b> 16, the CPU 50 saves the log data 74 stored in the ring buffer of the main RAM 70 in the sub RAM 80. At this time, the log data 74 stored in the partial ring buffers 76a to 76c is saved in the sub RAM 80 for each of the partial ring buffers 76a to 76c. That is, the sub RAM 80 is divided into a plurality of areas according to the tasks 62a to 62c, and the log data 74 of the task 62 corresponding to each divided area is stored. Next, in step S18, the CPU 50 divides the ring buffer of the main RAM 70 into the second division size set in step S14. Note that when the ring buffer of the main RAM 70 is divided into the second division size, the log data 74 secured in the ring buffer of the main RAM 70 is cleared.

Next, in step S20, the CPU 50 determines whether or not the second division size of the partial ring buffer 76 is equal to or larger than the first division size. If the second division size of the partial ring buffer 76 is greater than or equal to the first division size (YES in S20), the CPU 50 proceeds to step S22. In step S22, the CPU 50 re-saves the log data 74 corresponding to the partial ring buffer 76 saved in the sub RAM 80 in the partial ring buffer 76 (for example, the partial ring buffer 76a in FIG. 6). In this case, all log data 74 stored in the partial ring buffer 76 before the ring buffer division processing can be stored in the partial ring buffer 76 after changing to the second division size. On the other hand, if the second division size of the partial ring buffer 76 is smaller than the first division size (NO in S20), the CPU 50 proceeds to step S24. In step S24, the CPU 50 selectively re-saves the log data 74 corresponding to the partial ring buffer 76 saved in the sub-RAM 80 in the partial ring buffer 76 (for example, the partial ring buffer 76b, FIG. 76c). In this case, all of the log data 74 stored before the ring buffer division processing cannot be stored in the partial ring buffer 76 changed to the second division size. Specifically, the CPU 50 preferentially stores the new log data 74 of the time information 74b.

As is apparent from the above description, in the controller 40 of this embodiment, the ring buffer of the main RAM 70 is divided into a plurality of partial ring buffers 76 that store the log data 74 of the plurality of tasks 62a to 62c. . As a result, it is possible to prevent the log data 74 stored in the partial ring buffer 76 from being overwritten by the log data 74 related to the task 62 corresponding to the other partial ring buffer 76. As a result, the worker can appropriately determine the states of the plurality of tasks 62.

Further, the controller 40 executes a ring buffer division process every first setting period t ₁ . In the ring buffer dividing process, the controller 40 divides the ring buffer of the main RAM 70 according to the occupation ratio of each task 62. Thereby, it is possible to cope with a dynamic change in the occupation ratio of each task 62 occupying the entire processing capacity of the CPU 50. That is, the size of the partial ring buffer 76 can be adjusted to an appropriate size by matching the size of the partial ring buffer 76 with the dynamic change of the occupation ratio of each task 62 by the ring buffer division processing.

In addition, in the ring buffer division processing, the controller 40 saves the log data 74 in the sub RAM 80 before changing the size of the partial ring buffer 76, and the log data 74 stored in the ring buffer of the main RAM 70 before the change. Has cleared. When the size of the partial ring buffer 76 is changed without saving the log data 74 stored in the partial ring buffer 76 to the sub RAM 80, logs corresponding to a plurality of tasks 62 are stored in the partial ring buffer 76 after the size change. Data 74 may be stored. On the other hand, in the present embodiment, the log data 74 is saved in the sub RAM 80 before the size of the partial ring buffer 76 is changed. Therefore, only the log data 74 of the task 62 corresponding to the partial ring buffer 76 is changed in size. It is stored in the subsequent partial ring buffer 76. Thus, the worker can appropriately determine the states of the plurality of tasks 62 of the component mounter 10.

A component mounter 10 according to the second embodiment will be described with reference to FIG. In addition, about the structure which is common between Examples, the same code | symbol is attached | subjected and description is abbreviate | omitted. In the second embodiment, the ring buffer dividing process is different from the ring buffer dividing process of the first embodiment. Ring buffer division process of the second embodiment is the processing executed in the second every set period t _2. Note that the second set time period t ₂ can be set similarly to the first setting period t _1.

First, in step S112, CPU 50, during the second set time period _{t 2,} and calculates the information size of the log data 74 stored in each of the plurality of partial ring buffers 76a ~ 76c. Then, in step S114, CPU 50 has a ring buffer of the main RAM70 during the second set time period _{t 2} (i.e., partial ring buffers 76a ~ 76c) information size of the saved log data 74 (hereinafter, the first information size The ratio of the information size of the log data 74 stored in each of the partial ring buffers 76a to 76c is calculated. The first information size is a value obtained by adding the information sizes of the

partial ring buffers

76a, 76b, and 76c.

Next, in step S116, the CPU 50 calculates the second division size of the partial ring buffers 76a to 76c based on the information size ratio of the partial ring buffers 76a to 76c. Specifically, the CPU 50 calculates the second divided size of the partial ring buffers 76a to 76c by multiplying the size of the ring buffer of the main RAM 70 by the ratio of the partial ring buffers 76a to 76c calculated in step S114. . For example, a case will be described in which the size of the ring buffer of the main RAM 70 is 100 Mbytes and the information sizes of the

partial ring buffers

76a, 76b, and 76c are 6 Mbytes, 2 Mbytes, and 2 Mbytes, respectively. In this case, the first information size is 10 Mbytes, and the ratios of the

partial ring buffers

76a, 76b, and 76c are calculated as 60%, 20%, and 20%. Therefore, the second division sizes of the

partial ring buffers

76a, 76b, and 76c are calculated as 60 Mbytes, 20 Mbytes, and 20 Mbytes (see FIG. 6).

Next, in step S 118, the CPU 50 saves the log data 74 stored in the ring buffer of the main RAM 70 in the sub RAM 80. Next, in step S120, the CPU 50 changes the partial ring buffers 76a to 76c to the second division size set in step S116.

Next, in step S122, the CPU 50 determines for each of the partial ring buffers 76a to 76c whether or not the second divided size of the partial ring buffers 76a to 76c is equal to or larger than the first divided size. If the second division size of the partial ring buffer 76 is greater than or equal to the first division size (YES in S122), the CPU 50 proceeds to step S124. In step S124, the CPU 50 re-saves the log data 74 corresponding to the partial ring buffer 76 saved in the sub RAM 80 in the partial ring buffer 76 (for example, the partial ring buffer 76a in FIG. 6). In this case, all the log data 74 stored in the partial ring buffer 76 before the ring buffer division processing is stored in the partial ring buffer 76 after being changed to the second division size. On the other hand, when the second division size of the partial ring buffer 76 is smaller than the first division size (NO in S122), the CPU 50 proceeds to step S126. In step S126, the CPU 50 selectively re-saves the log data 74 corresponding to the partial ring buffer 76 saved in the sub RAM 80 so that the data amount corresponds to the size of the partial ring buffer 76 ( For example, the partial ring buffers 76b and 76c in FIG. Specifically, the CPU 50 preferentially stores the new log data 74 of the time information 74b.

As apparent from the above description, the controller 40 of the second embodiment, the second every set period t _2, performing a ring buffer division process. In the ring buffer division processing, the controller 40, during a second predetermined time period _{t 2,} based on the proportion of the information size of the partial ring buffers 76a ~ log data 74 stored in 76c, the size of the partial ring buffers 76a ~ 76c To change. For this reason, calculating the second division size of the partial ring buffers 76a to 76c based on the ratio of the information sizes of the partial ring buffers 76a to 76c can also dynamically change the log output amount of each task 62a to 62c. Can be matched. Thereby, the size of the partial ring buffers 76a to 76c can be adjusted to an appropriate size.

As mentioned above, although the Example which concerns on the technique disclosed by this specification was described in detail, these are only illustrations and do not limit a claim. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.

In each embodiment described above, the controller 40 includes two RAMs, a main RAM 70 and a sub RAM 80. However, the controller 40 may be composed only of the main RAM 70. In this case, as shown in FIG. 8, the main RAM 70 is divided into a program area 172, a main log area 174, and a sub log area 178. For example, when the size of the main RAM is 2 Gbytes, the size of the program area 172, the main log area 174, and the sublog area 178 is divided into 1 Gbyte, 500 Mbyte, and 500 Mbyte. In the program area 172, information regarding the processing of the tasks 62a to 62c is stored. The main log area 174 is divided into a plurality of partial ring buffers 176a to 176c, and log data 74 corresponding to each of the tasks 62a to 62a is stored. The sizes of the plurality of partial ring buffers 176 are dynamically changed by ring buffer division processing. Log data 74 stored in the main log area 174 (specifically, the partial ring buffers 176a to 176c) is temporarily stored in the sub-log area 178 during the ring buffer division processing. According to this configuration, the same effects as those of the embodiments can be obtained.

Claims

A controller that is mounted on a component mounter that mounts electronic components on a circuit board and controls the operation of at least a part of the component mounter,
A processor that performs multiple tasks;
A ring buffer for storing log information relating to the task executed by the processor,
The ring buffer is divided into a partial ring buffer for storing log information when the processor executes the task for each of the plurality of tasks.
The controller is configured to store, for each of the plurality of tasks, log information related to the task in the partial ring buffer corresponding to the task for each processing cycle.
The controller according to claim 1, wherein the processor is configured to store time information corresponding to the log information in the partial ring buffer when the log information is stored in the partial ring buffer.
The processor calculates, for each of the plurality of tasks, the occupation ratio of the task in the total processing capacity of the processor for each predetermined setting period,
3. The controller according to claim 1, wherein, for each of the plurality of tasks, the ring buffer is divided into partial ring buffers having a size corresponding to an occupation rate calculated for the task for each of the plurality of tasks.
The processor calculates an information size of the log information stored in each of the plurality of partial ring buffers during the setting period for each predetermined setting period,
For each of the plurality of tasks, a partial ring buffer having a size corresponding to the ratio between the information size calculated for the task and the information size of all log information stored in the setting period is set for each of the plurality of tasks. The controller according to claim 1, wherein the controller is divided.
A sub memory for storing the plurality of log information;
When changing the size of any of the plurality of partial ring buffers, the processor saves the log information stored in each of the plurality of partial ring buffers to the sub-memory,
After saving the log information to the sub-memory, change the size of the plurality of partial ring buffers,
The log information saved in the sub-memory after changing the size of the plurality of partial ring buffers is configured to be saved in each of the plurality of partial ring buffers. The controller according to claim 1.