WO2017004879A1 - 液晶显示处理方法、装置和设备 - Google Patents

液晶显示处理方法、装置和设备 Download PDF

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Publication number
WO2017004879A1
WO2017004879A1 PCT/CN2015/089055 CN2015089055W WO2017004879A1 WO 2017004879 A1 WO2017004879 A1 WO 2017004879A1 CN 2015089055 W CN2015089055 W CN 2015089055W WO 2017004879 A1 WO2017004879 A1 WO 2017004879A1
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WIPO (PCT)
Prior art keywords
liquid crystal
row
gate driver
crystal panel
frame picture
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PCT/CN2015/089055
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English (en)
French (fr)
Inventor
亓东欣
张钰枫
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青岛海信电器股份有限公司
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Application filed by 青岛海信电器股份有限公司 filed Critical 青岛海信电器股份有限公司
Priority to US15/018,400 priority Critical patent/US10235924B2/en
Publication of WO2017004879A1 publication Critical patent/WO2017004879A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the invention belongs to the technical field of liquid crystal display, and in particular relates to a liquid crystal display processing method, device and device.
  • LCD Liquid Crystal Display
  • TFT Thin Film Transistor
  • TFD Thin Film Diode
  • UFB Ultra Fine Bright
  • TFT type LCD is an active matrix type liquid crystal display, which is a plate capacitor composed of two layers of glass substrates sandwiching liquid crystal. The capacitor of this capacitor is charged by a TFT embedded in the lower glass plate to maintain the needs of each frame. The voltage is updated until the next frame, and the amount of power on the storage capacitor determines the content of the frame.
  • the TFT type LCD is equivalent to designing a thin film transistor at each pixel point, and a plurality of TFTs constitute a TFT liquid crystal panel.
  • FIG. 1 an equivalent circuit diagram of the liquid crystal panel, and a TFT unit composed of each TFT and a storage capacitor represents one pixel.
  • the driving system drives each row of TFTs to be turned on in turn, thereby sequentially charging the storage capacitors of the respective rows.
  • the driving system of the TFT type LCD mainly includes three parts: a signal source, a timing controller (Tcon) and a liquid crystal panel.
  • the liquid crystal panel includes a panel substrate, a source driver, and a gate driver. wherein, as shown in FIG. 1, each source driver is connected to a source of each column of TFTs, and each gate driver and each row are connected.
  • the gate of the TFT is connected.
  • Signal source for generating image signals, providing image information to Tcon; Tcon for outputting control signals and matching liquids
  • the data signals required by the crystal panel such as the data signal required by the source driver, the Clock Pulse Vertical (CPV) signal required by the gate driver, the Vertical Start (STV) signal, etc., the CPV is controlled.
  • CPV Clock Pulse Vertical
  • STV Vertical Start
  • the clock signal of each row of TFTs is turned on, and the STV is used to control the transmission of each frame of the picture.
  • 2 is a timing chart of driving of a conventional liquid crystal panel in the prior art. Assuming that the liquid crystal panel has n rows, corresponding n gate drive signals are G1, G2, ..., Gn-1 and Gn, respectively. As shown in FIG.
  • each row of driving signals corresponds to one CPV, and is outputted one by one according to the cycle order of the CPV, respectively updating the storage capacitor power of each row of liquid crystal molecules, with one level of n
  • the TFT on each row will only turn on the 1/n of the update time of the entire frame at most, and the higher the pixel of the liquid crystal panel, the more the number of rows n, the pixels of each row of the same refresh rate liquid crystal panel. The shorter the charging time of the storage capacitor is.
  • the present invention provides a liquid crystal display processing method, apparatus, and device for solving the problem of insufficient charging of each row of storage capacitors caused by an increase in pixels of the liquid crystal panel, which affects the image quality of the liquid crystal display.
  • An aspect of the invention provides a liquid crystal display processing method, including:
  • the timing controller sequentially sends N vertical start signals corresponding to the frame picture to the gate driver, so that the gate driver sequentially controls the thin film transistors of each row of the liquid crystal panel according to the N vertical start signals (Thin Film Transistor, Referred to as TFT) pre-conducting N times, the source driver pre-charges the storage capacitors of each row when the TFTs of each row are pre-conducted;
  • TFT Thi Film Transistor
  • the timing controller sends an N+1th vertical start signal corresponding to the frame picture to the gate driver before the end of the first pre-conduction of the TFT in the Mth row of the liquid crystal panel, so that the gate
  • the pole driver controls the TFTs of each row of the liquid crystal panel to be sequentially turned on according to the (N+1)th vertical start signal N+1 times, so that the source driver performs final charging on the storage capacitors of each row when the row of TFTs is turned on for the N+1th time, wherein N and M are positive integers greater than or equal to 1, and less than the total number of rows of the liquid crystal panel.
  • the method further includes:
  • the timing controller sequentially sends N scan drive output enable signals corresponding to the frame picture to the gate driver, so that the gate driver controls the liquid crystal panel according to the N scan drive output enable signals.
  • N scan drive output enable signals corresponding to the frame picture
  • the gate driver controls the liquid crystal panel according to the N scan drive output enable signals.
  • Each line of TFTs is pre-conducted for N times;
  • the method further includes:
  • the timing controller sends an N+1th scan driving output enable signal corresponding to the frame picture to the gate driver, so that the gate driver outputs an enable signal according to the (N+1)th scan driving, Controlling the time when the TFTs of the liquid crystal panel are turned on for the N+1th time.
  • the method further includes:
  • the timing controller determines a width of the N scan drive output enable signals according to a grayscale size of the frame picture
  • the method further includes:
  • the timing controller determines a width of the (N+1)th scan driving output enable signal according to a grayscale size of the frame picture.
  • the timing controller sends the N+1th vertical start signal corresponding to the frame picture to the gate driver before the end of the first pre-conduction of the TFT in the Mth row of the liquid crystal panel, including:
  • the timing controller determines the number of vertical clock pulses transmitted after transmitting the first vertical start signal
  • the timing controller sends the N+1th vertical start signal corresponding to the frame picture to the gate driver.
  • the method further includes:
  • the timing controller sends a pre-processed data signal corresponding to the frame picture to the source driver, so that the source driver pre-charges the storage capacitor of the first M rows of the liquid crystal panel according to the pre-processed data signal. .
  • the timing controller sends the N+1th STV signal to the gate driver
  • the data signal corresponding to the frame picture is also synchronized to the source driver at the same time
  • the source driver precharges the storage capacitors on the respective rows according to the data signals that are simultaneously turned on.
  • the method further includes:
  • the timing controller determines the preprocessed data signal according to a grayscale size of the frame picture.
  • M is less than 1/3 of the total number of rows of the liquid crystal panel.
  • the polarity inversion manner of the liquid crystal panel is a row polarity inversion
  • the M is an even number.
  • liquid crystal display timing control apparatus including:
  • a first transmitting module configured to sequentially send N vertical start signals corresponding to the frame picture to the gate driver, so that the gate driver sequentially controls the thin film transistors of each row of the liquid crystal panel according to the N vertical start signals ( Thin Film Transistor (TFT) is pre-conducted N times, so that the source driver pre-charges the storage capacitors of each row when the TFTs of each row are pre-conducted;
  • TFT Thin Film Transistor
  • a second sending module configured to send N+1 vertical start signals corresponding to the frame picture to the gate driver before the end of the first pre-conduction of the TFT in the Mth row of the liquid crystal panel, so that the The gate driver controls the TFTs of each row of the liquid crystal panel to be turned on for the N+1th time according to the (N+1)th vertical start signal, so that the source driver stores the rows in the N+1th turn of the TFTs of each row.
  • the capacitor is finally charged, and N and M are positive integers greater than or equal to 1, and less than the total number of rows of the liquid crystal panel.
  • the device further comprises:
  • a third sending module configured to sequentially send, to the gate driver, N scans corresponding to the frame picture Driving an output enable signal, so that the gate driver controls an output enable signal according to the N scans to control a time period in which the TFTs of the liquid crystal panel are pre-conducted N times;
  • the third transmitting module is further configured to send, to the gate driver, an N+1th scan driving output enable signal corresponding to the frame picture, so that the gate driver is driven according to the (N+1)th scan driving Outputting an enable signal to control the time when the TFTs of the liquid crystal panel are turned on for the N+1th time
  • the device further comprises:
  • a determining module configured to determine a width of the N scan driving output enable signals according to a grayscale size of the frame picture
  • the determining module is further configured to determine a width of the (N+1)th scan driving output enable signal according to a grayscale size of the frame picture.
  • the second sending module is specifically configured to:
  • the timing controller sends the N+1th vertical start signal corresponding to the frame picture to the gate driver.
  • the device further comprises:
  • a fourth sending module configured to send a pre-processed data signal corresponding to the frame picture to the source driver, so that the source driver performs a storage capacitor on the first M rows of the liquid crystal panel according to the pre-processed data signal Precharged.
  • the device further comprises:
  • the fifth sending module is configured to simultaneously synchronize the data signal corresponding to the frame picture to the source driver when the N+1th STV signal is sent to the gate driver, so that after the M+1th line and the M+1 line When each row of TFTs is pre-conducted, the source driver precharges the storage capacitors on the respective rows according to the data signals that are simultaneously turned on.
  • the determining module is further configured by the timing controller to determine the pre-processed data signal according to a grayscale size of the frame picture.
  • M is less than 1/3 of the total number of rows of the liquid crystal panel.
  • the polarity inversion manner of the liquid crystal panel is a row polarity inversion
  • the M is an even number.
  • a further aspect of the present invention provides a liquid crystal display device including: a processor, a memory, a gate driver, a source driver, and a thin film transistor (TFT) and a storage capacitor of each row of the liquid crystal panel;
  • a processor a memory
  • a gate driver a gate driver
  • a source driver a source driver
  • TFT thin film transistor
  • a processor configured to execute the program in the memory, sequentially send N vertical start signals corresponding to the frame picture to the gate driver, and before the end of the first pre-conduction of the TFT in the Mth row of the liquid crystal panel,
  • the gate driver sends the N+1th vertical start signal corresponding to the frame picture;
  • the gate driver is configured to sequentially control TFTs of each row of the liquid crystal panel to be turned on N times according to the N vertical start signals; and control TFTs of each row of the liquid crystal panel according to the N+1 vertical start signal Turn on the N+1th time in turn;
  • the source driver is configured to perform final charging of the storage capacitors of each row when the rows of TFTs are turned on for the N+1th turn, and pre-charge the storage capacitors of the rows when the TFTs of each row are pre-conducted, wherein N And M is a positive integer greater than or equal to 1, and less than the total number of rows of the liquid crystal panel.
  • the timing controller first sends N STV signals corresponding to the frame picture to the gate driver, and the gate driver sequentially controls according to the N STV signals.
  • the TFTs of each row of the liquid crystal panel are pre-conducted N times, and then the N+1th STV signal of the frame picture is sent to the gate driver before the end of the first pre-conduction of the Mth row, and the gate driver is based on the N+1th
  • the STV signals sequentially control the TFTs of each row of the liquid crystal panel to be turned on for the N+1th time, so that the source driver finally charges the storage capacitors of the respective rows according to the data signals corresponding to the frame picture, and simultaneously pre-conducts the rows of the TFTs.
  • the storage capacitor is pre-charged.
  • the liquid crystal display processing method charges the storage capacitors of all the rows in the screen at least twice before displaying the image on one frame, thereby prolonging the charging time of the storage capacitors of each row of the liquid crystal panel, thereby causing each row to be stored.
  • the power at both ends of the capacitor is as large as possible to meet the needs of the frame display, which improves the picture quality of the liquid crystal display.
  • 1 is an equivalent circuit diagram of a liquid crystal panel
  • FIG. 2 is a driving timing diagram of a conventional liquid crystal panel in the prior art
  • FIG. 3 is a schematic flowchart of a liquid crystal display processing method according to Embodiment 1 of the present invention.
  • FIG. 4 is a timing chart of driving a liquid crystal panel according to an embodiment of the present invention.
  • FIG. 5 is a schematic flowchart diagram of another liquid crystal display processing method according to Embodiment 2 of the present invention.
  • FIG. 6 is a schematic flowchart diagram of still another liquid crystal display processing method according to Embodiment 3 of the present invention.
  • Figure 7 is an equivalent circuit diagram of a pixel
  • FIG. 8 is a diagram showing the polarity inversion patterns of the liquid crystal panel
  • FIG. 9 is a schematic flowchart diagram of still another liquid crystal display processing method according to Embodiment 4 of the present invention.
  • FIG. 10 is a schematic structural diagram of a liquid crystal display timing control apparatus according to Embodiment 5 of the present invention.
  • FIG. 11 is a schematic structural diagram of another liquid crystal display timing control apparatus according to Embodiment 6 of the present invention.
  • FIG. 12 is a schematic structural diagram of still another liquid crystal display timing control apparatus according to Embodiment 7 of the present invention.
  • FIG. 13 is a schematic structural diagram of a liquid crystal display device according to Embodiment 8 of the present invention.
  • the charging time of each row of the storage capacitor of the liquid crystal panel becomes shorter.
  • the storage capacitor of each row has a problem of insufficient charging. Will seriously affect the picture quality of the liquid crystal display, which is mainly because the voltage across the storage capacitor at each pixel determines the flip angle of the liquid crystal molecules.
  • the present invention mainly proposes a liquid crystal display processing method, apparatus and device from the perspective of how to increase the voltage across the storage capacitor at each pixel point.
  • FIG. 3 is a schematic flowchart diagram of a liquid crystal display processing method according to Embodiment 1 of the present invention. As shown in FIG. 3, the liquid crystal display processing method includes:
  • the timing controller sequentially sends N vertical start signals (STV) corresponding to the frame picture to the gate driver, so that the gate driver sequentially controls the liquid crystal panel according to the N vertical start signals.
  • N vertical start signals STV
  • Thin film transistors (TFTs) of each row are pre-conducted N times, so that the source driver precharges the storage capacitors of each row when the rows of TFTs are pre-conducted.
  • the timing controller sends an N+1th vertical start signal corresponding to the frame picture to the gate driver before the end of the first pre-conduction of the TFT in the Mth row of the liquid crystal panel, so that the The gate driver controls the TFTs of each row of the liquid crystal panel to be turned on for the N+1th time according to the N+1 vertical start signal, so that the source driver is turned on for each row when the row of TFTs is turned on for the N+1th.
  • the storage capacitor is subjected to final charging, wherein N and M are greater than or equal to 1, and are less than a positive integer of the total number of rows of the liquid crystal panel.
  • the execution body of the liquid crystal display processing method is a timing controller (Tcon).
  • the timing controller is respectively connected to the signal source and the liquid crystal panel, and the timing controller is configured to generate a control signal and a data signal required by the liquid crystal panel according to the image information provided by the signal source, such as providing the source driver with the required source driver latch ( Latch signal for source driver (TP) signal and output data inversion signal for sorce driver (POL) signal, wherein TP controls the latching and output of each row of data information, for example, TP signal high power Normally, one line of data is latched into the line memory.
  • TP source driver latch
  • POL data inversion signal for sorce driver
  • the gate driver after receiving the STV signal, the gate driver starts to control the TFTs of each row of the liquid crystal panel to be turned on sequentially, and under the control of the N+1 STV signals, the TFTs of each row are controlled to be turned on and N+1. Second, wherein the N+1th conduction period of each row of TFTs is performed simultaneously.
  • the source driver may receive the data signal sent by the Tcon, or may not receive the data signal sent by the Tcon, and the data signal received by the source driver may be framed.
  • the actual data signal of the surface may also be a pre-processed data signal determined by the Tcon according to the grayscale size of the frame picture, or may be the number of times that the Tcon is combined with each row of TFTs during each frame period, and the number of times of conduction is turned on.
  • the preprocessed data signal determined by the time and actual data signals.
  • the timing controller in this embodiment sends N+1 STV signals to the gate driver before each frame of the screen is displayed, so that for each frame of the screen, the gate driver controls the TFTs of each row of the liquid crystal panel to be at least N+1.
  • This allows the source driver to charge at least N+1 times for each row of storage capacitors.
  • the source driver when the TFTs of each row are turned on for the first time, the source driver precharges the storage capacitors of the respective rows, and when the TFTs of the respective rows are turned on for the N+1th time, the source driver finally charges the storage capacitors of the respective rows. Thereby the frame picture is displayed.
  • the source driver can supplement or correct the amount of power on the storage capacitor during final charging.
  • the amount of power on the storage capacitor of the pixel is greater than the amount of power required by the current frame of the pixel, and then the amount of charge on the storage capacitor of the pixel can pass through the source during final charging.
  • the driver is released so that the amount of power on the storage capacitor of the pixel eventually meets the requirements of the current frame display.
  • the storage capacitor of a certain pixel of the liquid crystal panel is precharged, the amount of electricity is less than the amount of power required by the current frame picture, and then the source driver continues to charge the storage capacitor of the pixel at the final charging. Thereby, the amount of power on the storage capacitor of the pixel point satisfies the requirement of the current frame picture display.
  • the driving mode of the conventional liquid crystal panel provided in FIG. 2 is specifically as follows: when a frame of picture starts transmitting, the timing controller sends an STV signal to the gate driver, and the gate driver receives After the STV signal, that is, when the first CPV signal comes high, a high level signal G1 is output to the TFT of the first row of the liquid crystal panel, and the TFT of the first row is controlled to be turned on, so that the source driver is on the first line.
  • the storage capacitor of each pixel is charged.
  • the gate driver When the second CPV signal comes high, the gate driver outputs a high level signal G2 to the TFT of the second row of the liquid crystal panel to control the TFT of the second row to be turned on, and Turning G1 output to the TFT of the first row to a low level, turning off the TFT of the first row, so that the source driver charges the storage capacitor of each pixel of the second row, and so on, row by row for each row of the liquid crystal panel The storage capacitor is charged. According to the above analysis, each line of TFTs is turned on. It is related to the total number of rows of the liquid crystal panel.
  • the on-time of each row of TFTs is 1/(N*f), which increases with the number of rows of the liquid crystal panel.
  • the on-time of each row of TFTs is reduced.
  • the shorter the on-time of the TFT the shorter the charging time of the source driver through the TFT, and the amount of charge on the storage capacitor. The lower the charge, the problem of insufficient charging.
  • the timing controller in this embodiment sends N times STV signals to the gate driver before each frame of the screen is displayed, and N is greater than 1, as shown in FIG. 4 below.
  • N is greater than 1, as shown in FIG. 4 below.
  • FIG. 4 is a timing diagram of driving a liquid crystal panel according to an embodiment of the present invention. It is assumed that the liquid crystal panel has m rows, and corresponding to m gate drive signals are G1, G2, ..., Gn-1, Gn, Gn+1, ..., Gm, respectively. Specifically, for each frame picture, the timing controller first sends an STV signal STV1 to the gate driver, and then, after the gate driver receives the STV1, that is, when the first CPV signal comes high, the liquid crystal is directed to the liquid crystal.
  • the TFT in the first row of the panel outputs a high-level signal G1, which controls the TFT of the first row to be pre-conducted.
  • the gate driver When the second CPV signal comes high, the gate driver outputs a high voltage to the TFT of the second row of the liquid crystal panel.
  • the level signal G2 controls the TFT of the second row to be pre-conducted, and changes the G1 outputted to the TFT of the first row to a low level, turns off the TFT of the first row, and so on, and the gate driver controls each row of the liquid crystal panel.
  • the TFTs are pre-conducted row by row, and the source driver precharges the storage capacitors of the respective rows when the rows of TFTs are pre-conducted.
  • the timing controller sends a second STV signal STV2 to the gate driver.
  • Tcon also synchronizes the data signal corresponding to the frame picture to the source driver, when the M+1 CPV signal arrives, the gate driver under the control of STV1 and STV2 simultaneously goes to the M+1 line of the liquid crystal panel.
  • the TFT of the first row outputs two high-level signals GM and G1, and controls the TFT of the M+1th row and the first row to be turned on at the same time, and turns the GM outputted to the TFT of the Mth row to a low level, Turn off the TFT of the Mth row.
  • the source driver can finally charge the storage capacitor of the first row according to the received data signal, thereby storing the pixels at the first row. The voltage across the capacitor satisfies the display requirement of the frame picture, and displays the content corresponding to the frame picture.
  • the source driver pre-charges the storage capacitor of the M+1 line by using the data signal of the first line; at the M+2
  • the gate driver outputs two high-level signals GM+2 and G2 to the TFTs of the M+2 row and the second row of the liquid crystal panel under the control of STV1 and STV2, and controls the M+2 row.
  • the source driver can finally charge the storage capacitor of each pixel in the second row according to the received data signal, so that the second line displays the content of the frame picture, and the source driver uses the second line.
  • the data signal precharges the storage capacitor of the M+2 row, and so on, until the source driver completes the final charging of the storage capacitors of all the rows of the liquid crystal panel according to the data signal corresponding to the frame picture, and at the same time, the liquid crystal panel M Pre-charging the storage capacitors of +1 row and all subsequent rows, thus completing Display processing of the picture frame. Since the Tcon control charges the storage capacitors of each row of the liquid crystal panel twice, the charging time of each row of storage capacitors is prolonged, so that the power at both ends of each row of storage capacitors satisfies the requirements of the frame display.
  • the source driver precharges the storage capacitors on the respective rows according to the actual data signals that are simultaneously turned on.
  • the precharge voltage of the M+1th row is the final charging voltage of the first row
  • the charging voltage of the M+2th row is the final charging voltage of the second row and the like.
  • the Tcon may send a data signal to the source driver or may not send the data signal. Accordingly, before the Mth row, the storage capacitors of all rows may be precharged. It may or may not be pre-charged.
  • the pre-processing data signal corresponding to the frame picture may be sent by the timing controller to the source driver after the S30 is performed.
  • the source driver pre-charges the storage capacitors of the first M rows of the liquid crystal panel N times according to the pre-processed data signal.
  • the preprocessed data signal may be the same signal as the data signal corresponding to the frame picture, or may be a different data signal.
  • the TFT itself has parasitic capacitance, there is a parasitic capacitance connected in parallel with the storage capacitor, so when the storage capacitor is charged, the parasitic capacitance in parallel with it is also It will also be charged, i.e., in the various embodiments of the present invention, the parasitic capacitance is also charged at least twice while charging the storage capacitor at least twice.
  • the timing controller first sends N STV signals corresponding to the frame picture to the gate driver, and the gate driver sequentially controls the rows of the liquid crystal panel according to the N STV signals.
  • the TFT is pre-conducted N times, and the source driver pre-charges the storage capacitors of each row when the TFTs of each row are pre-conducted, and sends the frame to the gate driver before the end of the first pre-conduction of the TFTs in the Mth row.
  • the N+1th STV signal the gate driver sequentially controls the TFTs of each row of the liquid crystal panel to be turned on for the N+1th time according to the N+1th STV signal, so that the source driver according to the data signal corresponding to the frame picture
  • the storage capacitors of the respective rows are finally charged.
  • the liquid crystal display processing method performs at least two charging processes on the storage capacitors of all the rows in the screen before the display of one frame of the screen, thereby prolonging the charging time of the storage capacitors of the rows of the liquid crystal panel, thereby The power at both ends of the storage capacitors of each row is made to meet the requirements of the frame display as much as possible, thereby improving the picture quality of the liquid crystal display.
  • the Tcon controls the charging time of the storage capacitors of the respective rows of the liquid crystal panel by controlling the TFTs of the respective rows of the liquid crystal panel to be at least twice, and in actual use, the storage capacitors of the respective rows are performed.
  • the power storage capacity of each row can be further accurately controlled, and the amount of power on the storage capacitor can be controlled by controlling each row of TFTs.
  • FIG. 5 is a schematic flow chart of another liquid crystal display processing method according to Embodiment 2 of the present invention. As shown in FIG. 5, on the basis of the above-mentioned FIG. 3, after the S30, the liquid crystal display processing method provided by the present embodiment further includes:
  • the timing controller sequentially sends N scan driving output enable signals corresponding to the frame screen to the gate driver, so that the gate driver outputs an enable signal according to the N scan driving outputs,
  • the thin film transistors of each row of the liquid crystal panel are pre-conducted for N times.
  • the liquid crystal display processing method provided by the embodiment further includes:
  • the timing controller sends an N+1th scan driving output enable signal corresponding to the frame picture to the gate driver, so that the gate driver is enabled according to the (N+1)th scan driving output. a signal that controls the time of the N+1th turn-on of the thin film transistor of each row of the liquid crystal panel.
  • the Tcon after transmitting N STV signals to the gate driver, the Tcon sends N OE signals to the gate driver. If the widths of the N OE signals are the same, only one N can be sent to the gate driver. OE signal; or, Tcon can also send an OE signal to the gate driver every time it sends an STV signal to the gate driver. This embodiment does not limit this.
  • the OE signal width corresponding to different STV signals may be the same or different for each frame of the picture, and the OE signal width corresponding to each row of TFTs may be the same or different during each STV signal period. This embodiment does not limit this.
  • the Tcon after transmitting the STV signal to the gate driver, the Tcon sends an OE signal to the gate driver, so that the gate driver controls the TFT of each row to be turned on.
  • Each on-time of the TFT of the row is controlled according to the corresponding OE signal, thereby controlling the charging time of the storage capacitor of each row by the source driver, so that the amount of charge on the storage capacitors of each row satisfies the requirement of the frame display as much as possible.
  • the Tcon in order to further control the charging time of the storage capacitor each time, for the same STV signal, can also send different OE signals to the gate driver according to different rows, so that the same STV signal period is different.
  • the on-time of the TFTs of the rows is different, that is, the charging times of the storage capacitors of different rows are different.
  • the timing controller first sends N STV signals corresponding to the frame picture to the gate driver, and the gate driver sequentially controls the rows of the liquid crystal panel according to the N STV signals.
  • the TFT is pre-conducted N times, and the source driver pre-charges the storage capacitors of each row when the TFTs of each row are pre-conducted, and sends the frame picture to the gate driver before the end of the first pre-conduction of the Mth row.
  • the N+1th STV signal the gate driver sequentially controls the TFTs of each row of the liquid crystal panel to be turned on for the N+1th time according to the N+1th STV signal, so that the source driver pairs each row according to the data signal corresponding to the frame picture.
  • the storage capacitor is used for final charging.
  • the liquid crystal display processing method performs at least twice the storage capacitance of all the rows in the screen before displaying on one frame of the screen.
  • the charging process prolongs the charging time of the storage capacitors of each row of the liquid crystal panel, so that the power at both ends of each row of storage capacitors satisfies the requirements of the frame display as much as possible, thereby improving the image quality of the liquid crystal display.
  • the total charging time of the storage capacitors of the source drivers for each row is controlled, so that the power at both ends of the storage capacitors of each row is more accurate, thereby further improving the image quality of the liquid crystal display.
  • the grayscale size of the picture is set to the width of the OE signal described above, and another liquid crystal display processing method provided by the present invention will be described below with reference to FIG.
  • FIG. 6 is a schematic flowchart diagram of still another liquid crystal display processing method according to Embodiment 3 of the present invention. As shown in FIG. 6, on the basis of FIG. 5, before the above S32, the liquid crystal display processing method further includes:
  • the timing controller determines a width of the N scan driving output enable signals according to a grayscale size of the frame picture.
  • the liquid crystal display processing method further comprises:
  • the timing controller determines a width of the (N+1)th scan driving output enable signal according to a grayscale size of the frame picture.
  • the Tcon can determine the final amount of power required on each pixel storage capacitor of the liquid crystal panel, so that the storage capacitor of each pixel is precharged by appropriately setting the width of each OE signal. After the final charging is completed, the amount of power on the storage capacitor is as close as possible to the amount of power required for the frame display.
  • Tcon determines the width of the OE signal according to the grayscale size of the current frame picture, and achieves precise control of the amount of power on the storage capacitor of each pixel point, thereby further improving the image quality of the liquid crystal display.
  • the number of TFTs per row of the liquid crystal panel is K
  • the number of TFTs that the gate driver controls to turn on is K when each CPV arrives, and after the Tcon sends the STV2 signal to the gate driver.
  • the number of TFTs that the gate driver controls to turn on is 2K.
  • the same source driving signal is used in each of the 2K TFTs that are turned on, that is, each column of TFTs charges the respective storage capacitors using the same voltage, and the present embodiment
  • the timing of the output signal of the source driver is similar to that of the gate driver, the frequency of the CPV signal changes sequentially after receiving the STV signal, and in order to ensure the final display effect of the frame picture, the TFTs of each row are When finally turned on, the data signal added by the source driver to the storage capacitor of each row needs to be the actual data signal corresponding to the frame picture. Then, after the timing controller outputs the N+1th STV signal, the gate driver outputs again.
  • the charging voltage applied to the source of the TFT by the source driver is the voltage corresponding to the frame of the first row.
  • the voltage of the frame of the first row is performed on the first storage capacitor.
  • the storage capacitors that are simultaneously turned on with the first row of TFTs are also precharged.
  • the storage capacitors of the rows in which the TFTs are simultaneously turned on have the same charging polarity.
  • the TFTs of the first row and the Lth row are simultaneously turned on, and the storage capacitors at the pixels of the first row and the Lth row are required to have the same polarity in the same frame.
  • the following is an example of an equivalent circuit of one pixel.
  • Fig. 7 is an equivalent circuit diagram of a pixel. Assuming that the voltage of the upper plate of the storage capacitor in FIG. 7 is higher than that of the common electrode plate, the liquid crystal molecules indicating the pixel point are turned upside down, and the “+” indicates that the voltage of the upper plate of the storage capacitor is lower than that of the common electrode plate. The liquid crystal indicating the pixel is turned down, and is indicated by "-".
  • the voltage of the storage capacitor is positive and negative, and the liquid crystal molecules of the pixel point are flipped downward, and if the next charging is completed, the storage capacitor is discharged.
  • the voltage on the upper side becomes negative and positive, indicating that the polarity of the second charge is opposite to the first time.
  • the voltage of 1V controls the liquid crystal molecules to flip at an angle of 10 degrees (°), such as the first charge
  • the voltage on the storage capacitor is -2V.
  • the liquid crystal molecules of the pixel point are flipped down by 20°.
  • the voltage on the storage capacitor is +3V, then the charging on the storage capacitor after the end of the two charging ends.
  • the voltage is +1V, and finally the liquid crystal molecules at the pixel point are turned up by 10°. Compared with the first charge, the final flip direction of the liquid crystal molecules is not changed, and the flip angle is smaller than that after the first charge. It can be seen from the above analysis that if the charging polarity of the storage capacitor is different when the TFT is turned on twice before and after, the two charging may not increase the deflection of the liquid crystal of the pixel, but lower the reversal of the liquid crystal molecule. Therefore, the picture quality is worse.
  • the charging polarity of the storage capacitors of each row of the liquid crystal panel is related to the polarity inversion mode of the liquid crystal panel.
  • the polarity inversion mode of the liquid crystal panel mainly includes frame polarity inversion, row polarity inversion, column polarity inversion, and dot polarity inversion as shown in FIG. Fig. 8 is a view showing the polarity inversion of the liquid crystal panel. In the figure, "+" and "-" are used to indicate the two flipping directions of the liquid crystal molecules at the pixel or the two charging voltage polarities of the storage capacitor. As can be seen from Fig.
  • the Mth row can be any other than the first row on the liquid crystal panel.
  • One row, and for the liquid crystal panel of the row polarity inversion mode, the M row can be any even row on the liquid crystal panel, and the storage capacitors of the rows in which the TFTs are simultaneously turned on have the same charging polarity.
  • the timing controller can be implemented in various ways when determining the Mth row. For example, a timer can be used, because the conduction time of each row of TFTs can be known. Then, after the first STV signal is sent, the Tcon can start the timer when the first CPV signal is output at a high level.
  • the transmission can be triggered.
  • N STV signals since the turn-on timing of each row of TFTs is related to the CPV signal, the Tcon can also use a counter to assist in determining the timing of transmitting the N+1th STV signal.
  • the counter is taken as an example to detail the scheme. description.
  • FIG. 9 is a schematic flow chart of still another liquid crystal display processing method according to Embodiment 4 of the present invention. As shown in FIG. 9, based on the foregoing FIG. 7, the foregoing S31 includes:
  • the timing controller determines the number of vertical clock pulses transmitted after transmitting the first vertical start signal.
  • the timing controller sends the N+1th vertical start signal corresponding to the frame picture to the gate driver.
  • the counter can be started to start recording the number of transmitted CPV signals.
  • the Tcon can send the second STV signal to the gate driver.
  • the gate driver simultaneously goes to the TFT of the fifth row and the first The TFT of the row outputs a high level drive signal, thereby making the TFT and the first row of the 5th row The TFTs are simultaneously turned on, and then the source drivers of the respective columns are precharged to the storage capacitors of the fifth row, and finally charged to the storage capacitors of the first row.
  • M may be 2, 3, 4, or the like. If the selected M is 2, the Tcon sends a second STV signal to the gate driver before the end of the TFT pre-conduction of the first row, so that when the next CPV arrives, the gate driver simultaneously goes to the second row of TFTs and the first row.
  • the TFT outputs a high-level driving signal, and controls the second-row TFT and the first-row TFT to be turned on, thereby pre-charging the storage capacitor of the second row, and finally charging the storage capacitor of the first row, and so on, and completing the pair
  • the entire storage panel of the entire LCD panel is charged twice.
  • the polarity inversion mode of the liquid crystal panel is the row polarity inversion, the inversion directions of the liquid crystal molecules in each row on the liquid crystal panel are the same, then The purpose of charging the storage capacitor and increasing the voltage across the storage capacitor is to ensure that M is even.
  • the Tcon sends a second STV signal to the gate driver, so that when the next CPV arrives, the gate driver simultaneously
  • the gate driver In the third row, the fifth row or the seventh row, any one of the TFTs and the first row of TFTs outputs a high-level driving signal, and controls any one row of TFTs and the first row of TFTs of the third row, the fifth row or the seventh row, and the like.
  • the capacitor is charged twice.
  • the M line preferably selects a line that is closer to the first line, for example, M is 2.
  • the liquid crystal display processing method provided in this embodiment performs at least two charging processes on the storage capacitors of all the rows in the screen before the display of one frame of the screen, thereby prolonging the charging time of the storage capacitors of the rows of the liquid crystal panel, thereby making the storage capacitors of the respective rows
  • the power at both ends is as large as possible to meet the needs of the frame display, which improves the picture quality of the liquid crystal display.
  • the image quality of the liquid crystal display is improved, and the display effect between the frame images is not affected.
  • FIG. 10 is a schematic structural diagram of a liquid crystal display timing control apparatus according to Embodiment 5 of the present invention. As shown in FIG. 10, the liquid crystal display timing control apparatus 100 includes a first transmitting module 101 and a second transmitting module 102.
  • the first sending module 101 is configured to sequentially send N vertical start signals corresponding to the frame picture to the gate driver, so that the gate driver sequentially controls the thin films of the liquid crystal panels according to the N vertical start signals.
  • a transistor Thin Film Transistor, TFT for short
  • TFT Thin Film Transistor
  • the second sending module 102 is configured to send N+1 vertical start signals corresponding to the frame picture to the gate driver before the end of the first pre-conduction of the TFT in the Mth row of the liquid crystal panel, so that the The gate driver controls the TFTs of each row of the liquid crystal panel to be turned on for the N+1th time according to the (N+1)th vertical start signal, so that the source driver stores the rows in the N+1th turn of the TFTs of each row.
  • the capacitor is subjected to final charging, wherein N and M are greater than or equal to 1, and are less than a positive integer of the total number of rows of the liquid crystal panel.
  • the liquid crystal display timing control device in this embodiment includes Tcon.
  • the liquid crystal display timing control device is respectively connected with the signal source and the liquid crystal panel, and the Tcon in the liquid crystal display timing control device is used for generating the control signal and the data signal required by the liquid crystal panel according to the image information provided by the signal source, for example, providing the source driver
  • the required TP signal and POL signal provide the required CPV signal, STV signal, etc. for the gate driver.
  • the gate driver after receiving the STV signal, the gate driver starts to control the TFTs of each row of the liquid crystal panel to be turned on sequentially, and controls the TFTs of each row under the control of N+1 STV signals.
  • the loop is turned on for N+1 times, wherein the N+1th turn-on period of each row of TFTs is performed simultaneously.
  • the source driver may receive the data signal sent by the Tcon, or may not receive the data signal sent by the Tcon, and the data signal received by the source driver may be the actual data signal of the frame picture.
  • It may also be a preprocessed data signal determined by the Tcon according to the grayscale size of the frame picture, or may be determined by the Tcon combined with each row of TFTs during each frame period, the number of times of conduction, each conduction time, and the actual data signal. Preprocessed data signals.
  • the timing controller in this embodiment sends N+1 STV signals to the gate driver before each frame of the screen is displayed, so that for each frame of the screen, the gate driver controls the TFTs of each row of the liquid crystal panel to be at least N+1.
  • This allows the source driver to charge at least N+1 times for each row of storage capacitors.
  • the source driver when the TFTs of each row are turned on N times before, the source driver precharges the storage capacitors of the respective rows, and when the TFTs of the respective rows are turned on for the N+1th time, the source driver performs final charging on the storage capacitors of the respective rows. , so that the frame picture is displayed.
  • the source driver can supplement or correct the amount of power on the storage capacitor during final charging.
  • the amount of power on the storage capacitor of the pixel is greater than the amount of power required by the current frame of the pixel, and then the amount of charge on the storage capacitor of the pixel can pass through the source during final charging.
  • the driver is released so that the amount of power on the storage capacitor of the pixel eventually meets the requirements of the current frame display.
  • the storage capacitor of a certain pixel of the liquid crystal panel is precharged, the amount of electricity is less than the amount of power required by the current frame picture, and then the source driver continues to charge the storage capacitor of the pixel at the final charging. Thereby, the amount of power on the storage capacitor of the pixel point satisfies the requirement of the current frame picture display.
  • the liquid crystal display timing control device for each frame picture, the timing controller first sends N STV signals corresponding to the frame picture to the gate driver, and the gate driver sequentially controls the liquid crystal panel according to the N STV signals.
  • the TFTs of each row are pre-conducted N times, and the N+1th STV signal of the frame picture is sent to the gate driver before the end of the first pre-conduction of the Mth row, and the gate driver is based on the N+1th STV signal. , sequentially controlling the TFTs of each row of the liquid crystal panel to be turned on for the N+1th time, so that the source driver finally charges the storage capacitors of the respective rows according to the data signals corresponding to the frame picture.
  • the liquid crystal display processing method extends the storage capacitor of all the rows in the screen at least twice before the display of one frame of the screen, thereby prolonging the liquid crystal panel The charging time of the storage capacitors of each row, so that the power at both ends of each row of storage capacitors meets the requirements of the frame picture display as much as possible, thereby improving the picture quality of the liquid crystal display.
  • the Tcon controls the charging time of the storage capacitors of the respective rows of the liquid crystal panel by controlling the TFTs of the respective rows of the liquid crystal panel to be at least twice, and in actual use, the storage capacitors of the respective rows are performed.
  • the power storage capacity of each row can be further accurately controlled, and the amount of power on the storage capacitor can be controlled by controlling each row of TFTs.
  • FIG. 11 is a schematic structural diagram of another liquid crystal display timing control apparatus according to Embodiment 6 of the present invention.
  • the apparatus further includes: a third transmitting module 103.
  • the third sending module 103 is configured to sequentially send N scan driving output enable signals corresponding to the frame screen to the gate driver, so that the gate driver outputs an enable signal according to the N scan driving outputs.
  • the thin film transistors of each row of the liquid crystal panel are pre-conducted for N times; and are further configured to send an N+1th scan driving output enable signal corresponding to the frame picture to the gate driver, so that the gate driver is configured according to The (N+1)th scan driving output enable signal controls the time of the N+1th turn-on of the thin film transistor of each row of the liquid crystal panel
  • the liquid crystal display timing control device for each frame picture, the timing controller first sends N STV signals corresponding to the frame picture to the gate driver, and the gate driver sequentially controls the liquid crystal panel according to the N STV signals.
  • the TFTs of each row are pre-conducted N times, and then the N+1th STV signal of the frame picture is sent to the gate driver before the end of the first pre-conduction of the Mth line, and the gate drive
  • the TFTs of the liquid crystal panel are sequentially controlled to be turned on for the N+1th time, so that the source driver finally charges the storage capacitors of the respective rows according to the data signals corresponding to the frame picture, and simultaneously
  • the storage capacitors of the rows of the TFT pre-conduction are pre-charged.
  • the liquid crystal display processing method extends the storage capacitors of the rows of the liquid crystal panel by charging the storage capacitors of all the rows in the screen at least twice before displaying the image on one frame.
  • the charging time is such that the power at both ends of each row of storage capacitors satisfies the requirements of the frame display as much as possible, thereby improving the picture quality of the liquid crystal display.
  • the total charging time of the storage capacitors of the source drivers for each row is controlled, so that the power at both ends of the storage capacitors of each row is more accurate, thereby further improving the image quality of the liquid crystal display.
  • the source driver charges the storage capacitors of the respective rows, so that the power on the storage capacitors of each row satisfies the frame picture requirement, and the OE signal can also be used.
  • the width is set according to the grayscale size of each frame of the screen, and another liquid crystal display timing control apparatus provided by the present invention will be described below with reference to FIG.
  • FIG. 12 is a schematic structural diagram of still another liquid crystal display timing control apparatus according to Embodiment 7 of the present invention. As shown in FIG. 12, on the basis of FIG. 11, the apparatus further includes: a determining module 104.
  • the determining module 104 is configured to determine a width of the N scan driving output enable signals according to a grayscale size of the frame picture; the determining module 104 is further configured to determine, according to a grayscale size of the frame picture, The width of the N+1th scan drive output enable signal.
  • the liquid crystal display timing control device can determine the final required amount of power on each pixel storage capacitor of the liquid crystal panel according to the grayscale size of the current frame picture, so that the storage capacitance of each pixel point is determined by appropriately setting the width of the OE signal. After pre-charging and final charging, the amount of power on the storage capacitor is as close as possible to the amount of power required for the frame display.
  • the source driver performs the storage capacitors on the respective rows according to the actual data signals that are simultaneously turned on.
  • Precharge for example, the precharge voltage of the M+1th row is the final charging voltage of the first row, and the charging voltage of the M+2th row is the final charging voltage of the second row and the like.
  • the Tcon may or may not send a data signal to the source driver. Accordingly, the storage capacitors of all rows before the Mth line may be precharged or may not be precharged.
  • the liquid crystal display timing control apparatus further includes: a fourth sending module 105, configured to send the preprocessed data corresponding to the frame picture to the source driver, in order to make the storage capacitors of all the rows are charged at least twice. And a signal, wherein the source driver pre-charges the storage capacitors of the first M rows of the liquid crystal panel N times according to the pre-processed data signal.
  • the preprocessed data signal may be the same signal as the data signal corresponding to the frame picture, or may be a different data signal.
  • the liquid crystal display timing control device further includes: a fifth transmitting module, configured to simultaneously synchronize the data signal corresponding to the frame picture to the source driver when transmitting the N+1th STV signal to the gate driver, so as to enable
  • a fifth transmitting module configured to simultaneously synchronize the data signal corresponding to the frame picture to the source driver when transmitting the N+1th STV signal to the gate driver, so as to enable
  • the source driver precharges the storage capacitors on the respective rows according to the data signals that are simultaneously turned on.
  • the liquid crystal display timing control device determines the width of the OE signal according to the grayscale size of the current frame picture, and realizes precise control of the electric quantity on the storage capacitor of each pixel point, thereby further improving the image quality of the liquid crystal display.
  • the second sending module is specifically configured to:
  • the timing controller sends the N+1th vertical start signal corresponding to the frame picture to the gate driver.
  • the counter can be started to start recording the number of transmitted CPV signals.
  • the Tcon can send the second STV signal to the gate driver.
  • the gate driver simultaneously goes to the TFT of the fifth row and the first The TFT of the row outputs a high-level driving signal, so that the TFT of the fifth row and the TFT of the first row are simultaneously turned on, and then the source drivers of the respective columns are respectively pre-processed to the storage capacitor of the fifth row. Charge and final charge the storage capacitor on the 1st line.
  • M may be 2, 3, 4, or the like. If the selected M is 2, the Tcon sends a second STV signal to the gate driver before the end of the TFT pre-conduction of the first row, so that when the next CPV arrives, the gate driver simultaneously goes to the second row of TFTs and the first row.
  • the TFT outputs a high-level driving signal, and controls the second-row TFT and the first-row TFT to be turned on, thereby pre-charging the storage capacitor of the second row, and finally charging the storage capacitor of the first row, and so on, and completing the pair
  • the entire storage panel of the entire LCD panel is charged twice.
  • the polarity inversion mode of the liquid crystal panel is the row polarity inversion, the inversion directions of the liquid crystal molecules in each row on the liquid crystal panel are the same, then The purpose of charging the storage capacitor and increasing the voltage across the storage capacitor is to ensure that M is even.
  • the Tcon sends a second STV signal to the gate driver, so that when the next CPV arrives, the gate driver simultaneously
  • the gate driver In the third row, the fifth row or the seventh row, any one of the TFTs and the first row of TFTs outputs a high-level driving signal, and controls any one row of TFTs and the first row of TFTs of the third row, the fifth row or the seventh row, and the like.
  • the capacitor is charged twice.
  • the Mth line preferably selects a line closer to the first line, for example, M is 2.
  • the liquid crystal display timing control device performs at least two charging processes on the storage capacitors of all the rows in the screen before the display of one frame of the screen, thereby prolonging the charging time of the storage capacitors of the rows of the liquid crystal panel, thereby causing each row to be stored.
  • the power at both ends of the capacitor is as large as possible to meet the needs of the frame display, which improves the picture quality of the liquid crystal display.
  • the image quality of the liquid crystal display is improved, and the display effect between the frame images is not affected.
  • FIG. 13 is a schematic structural diagram of a liquid crystal display device according to Embodiment 8 of the present invention.
  • the liquid crystal display device 130 includes a processor 131, a memory 132, a gate driver 133, a source driver 134, a thin film transistor (TFT) 135 of each row of the liquid crystal panel, and a liquid crystal panel.
  • Storage capacitor 136 is a schematic structural diagram of a liquid crystal display device according to Embodiment 8 of the present invention.
  • the liquid crystal display device 130 includes a processor 131, a memory 132, a gate driver 133, a source driver 134, a thin film transistor (TFT) 135 of each row of the liquid crystal panel, and a liquid crystal panel.
  • Storage capacitor 136 storage capacitor 136.
  • the memory 132 is configured to store a program
  • the processor 131 is configured to execute the program in the memory 132, and sequentially send N vertical start signals corresponding to the frame picture to the gate driver 133, and before the end of the first pre-conduction of the TFT in the Mth row of the liquid crystal panel,
  • the gate driver 133 sends an N+1th vertical start signal corresponding to the frame picture;
  • the gate driver 133 is configured to sequentially control the TFTs 135 of each row of the liquid crystal panel to be pre-conducted N times according to the N vertical start signals; and control the TFTs 135 of each row of the liquid crystal panel according to the (N+1)th vertical start signal. Turn on the N+1th time in turn;
  • the source driver 134 is configured to perform final charging of the storage capacitors 136 of each row when the rows of TFTs 135 are turned on for the N+1th time, and pre-charge the storage capacitors 136 of the rows when the rows of TFTs 135 are pre-conducted.
  • N and M are positive integers greater than or equal to 1, and less than the total number of rows of the liquid crystal panel.
  • the program stored in the memory includes frame picture information to be displayed, and generates a vertical start signal related program corresponding to the frame picture, a program for generating a clock signal, and data information required for the source driver to charge each line of storage capacitors. Wait.
  • the processor When the liquid crystal display device is used, the processor generates an image signal, a vertical start signal transmitted to the gate driver, a data signal transmitted to the source driver, and the like by executing a program in the memory.
  • the gate driver sequentially controls the TFTs of the liquid crystal panel to be turned on under the control of the vertical start signal sent by the processor, so that the source driver charges the storage capacitors of the liquid crystal display panels at least twice when the TFT is turned on.
  • the detailed description of the liquid crystal display processing method provided in the above-mentioned first embodiment to the fourth embodiment can be referred to in the detailed description of the function and the detailed processing flow of the various parts of the structure.
  • the timing controller first sends N STV signals corresponding to the frame picture to the gate driver, and the gate driver sequentially controls the rows of the liquid crystal panel according to the N STV signals.
  • the TFT is pre-conducted N times, and then the N+1th STV signal of the frame picture is sent to the gate driver before the end of the first pre-conduction of the Mth line, and the gate driver is based on the N+1th STV signal.
  • the TFTs of each row of the liquid crystal panel are sequentially turned on for the N+1th time, so that the source driver finally charges the storage capacitors of the respective rows according to the data signals corresponding to the frame picture, and pre-prescribes the storage capacitors of the rows pre-conducted by the TFTs.
  • Charging the liquid crystal display processing method performs charging process of the storage capacitors of all the rows in the screen at least twice before the display of one frame of the screen, thereby prolonging the charging time of the storage capacitors of the respective rows of the liquid crystal panel, thereby making the storage capacitors of the respective rows of the lines
  • the power is as large as possible to meet the needs of the frame display, and the picture quality of the liquid crystal display is improved.
  • the foregoing program may be stored in a computer readable storage medium, and the program is executed when executed.
  • the foregoing steps include the steps of the foregoing method embodiments; and the foregoing storage medium includes: a medium that can store program codes, such as a ROM, a RAM, a magnetic disk, or an optical disk.

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Abstract

一种液晶显示处理方法、装置和设备，对每一帧画面，时序控制器(100)都会先向栅极驱动器(133)发送该帧画面对应的N个STV信号，栅极驱动器(133)根据N个STV信号，依次控制液晶面板各行的TFT(135)预导通N次，在第M行第一次预导通结束前，向栅极驱动器(133)发送第N+1个STV信号，栅极驱动器(133)根据第N+1个STV信号，控制液晶面板各行的TFT(135)导通第N+1次，以便使源极驱动器(134)对各行的存储电容(136)进行最终充电，同时对TFT(135)预导通的各行的存储电容(136)进行预充电，所述液晶显示处理方法通过在一帧画面显示前，对屏幕中所有行的存储电容(136)进行至少两次充电，延长了对液晶面板各行的存储电容(136)的充电时间，从而使各行存储电容(136)两端的电量尽量满足帧画面显示的需求，提高了液晶显示器的画质。

Description

液晶显示处理方法、装置和设备
本申请要求在2015年7月3日提交中国专利局、申请号为201510388769.X、发明名称为“液晶显示处理方法、装置和设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明属于液晶显示技术领域，尤其是涉及一种液晶显示处理方法、装置和设备。
背景技术
目前，液晶显示器(Liquid Crystal Display，简称LCD)广泛应用于台式电脑、手机、电视及多种办公自动化与视听设备中。LCD主要包括：薄膜晶体管(Thin Film Transistor，简称TFT)型LCD、薄膜二极管(Thin Film Diode，简称TFD)型LCD、超薄清(Ultra Fine Bright，简称UFB)型LCD等等，其中，TFT型LCD是一种有源矩阵类型的液晶显示器，是由两层玻璃基板夹住液晶组成的一个平板电容器，通过嵌入在下玻璃板上的TFT对这个电容器的存储电容充电，来维持每帧画面所需要的电压直到下一帧画面更新，存储电容上电量的大小决定了帧画面的内容。
TFT型LCD相当于在每一个像素点上设计了一个薄膜晶体管，多个TFT构成一个TFT液晶面板，如图1为液晶面板的等效电路图，每个TFT与存储电容组成的TFT单元代表一个像素点，驱动系统驱动各行TFT依次导通，从而对各行的存储电容依次充电。
TFT型LCD的驱动系统主要包括三部分：信号源、时序控制器(Time Controller，简称Tcon)和液晶面板。液晶面板，包括面板基板、源极驱动器(source Driver)和栅极驱动器(gate Driver)，其中，如图1所示，各源极驱动器与各列TFT的源极连接，各栅极驱动器与各行TFT的栅极连接。信号源，用于产生图像信号，给Tcon提供图像信息；Tcon用于输出控制信号和符合液 晶面板需要的数据信号，如源极驱动器需要的数据信号、栅极驱动器需要的垂直时钟脉冲(Clock Pulse Vertical，简称CPV)信号、垂直起始(Start Vertical，简称STV)信号等，CPV为控制每一行TFT打开的时钟信号，STV用于控制每一帧画面的传输。图2为现有技术中普通液晶面板的驱动时序图。假设液晶面板有n行，对应有n个栅极驱动信号分别为G1、G2……Gn-1和Gn。如图2所示，当帧画面的STV高电平到来时，每一行驱动信号对应一个CPV，根据CPV的周期顺序逐条输出，分别更新每一行液晶分子的存储电容电量，以一个有n条水平行的液晶面板而言，每个行上的TFT，最多仅会开启整个帧画面更新时间的1/n，液晶面板像素越高，行数n越多，则相同刷新频率液晶面板的每行像素中存储电容可充电时间越短。
随着消费者对液晶显示器的分辨率要求越来越高，即对液晶面板像素的要求越来越高，若使用相同的频率来播放视频，像素的增多就会使每一行存储电容的充电时间变短，当行数增加到一定程度时，每行的存储电容就会存在充电不足的问题，从而会严重影响液晶显示器的画质。
发明内容
本发明提供一种液晶显示处理方法、装置和设备，用于解决现有技术中，液晶面板的像素增多带来的每行存储电容充电不足，影响液晶显示器的画质的问题。
本发明一方面提供一种液晶显示处理方法，包括：
时序控制器向栅极驱动器依次发送帧画面对应的N个垂直起始信号，以使所述栅极驱动器根据所述N个垂直起始信号，依次控制液晶面板各行的薄膜晶体管(Thin Film Transistor，简称TFT)预导通N次，源极驱动器在各行TFT预导通时，对各行的存储电容进行预充电；
所述时序控制器在液晶面板第M行的TFT第一次预导通结束前，向所述栅极驱动器发送所述帧画面对应的第N+1个垂直起始信号，以使所述栅极驱动器根据所述第N+1垂直起始信号，控制液晶面板各行的TFT依次导通第 N+1次，以便源极驱动器在各行TFT第N+1次导通时，对各行的存储电容进行最终充电，其中，N和M为大于或等于1，且小于液晶面板总行数的正整数。
所述时序控制器向栅极驱动器依次发送帧画面对应的N个垂直起始信号之后，还包括：
所述时序控制器向栅极驱动器依次发送所述帧画面对应的N个扫描驱动输出使能信号，以使所述栅极驱动器根据所述N个扫描驱动输出使能信号，控制所述液晶面板各行TFT预导通N次的时间；
向所述栅极驱动器发送所述帧画面对应的第N+1个垂直起始信号之后，还包括：
所述时序控制器向栅极驱动器发送所述帧画面对应的第N+1个扫描驱动输出使能信号，以使所述栅极驱动器根据所述第N+1个扫描驱动输出使能信号，控制所述液晶面板各行TFT第N+1次导通的时间。
优选地，所述时序控制器向栅极驱动器依次发送所述帧画面对应的N个扫描驱动输出使能信号之前，还包括：
所述时序控制器根据所述帧画面的灰阶大小确定所述N个扫描驱动输出使能信号的宽度；
所述时序控制器向栅极驱动器发送所述帧画面对应的第N+1个扫描驱动输出使能信号之前，还包括：
所述时序控制器根据所述帧画面的灰阶大小确定所述第N+1个扫描驱动输出使能信号的宽度。
优选地，所述时序控制器在液晶面板第M行的TFT第一次预导通结束前，向所述栅极驱动器发送所述帧画面对应的第N+1个垂直起始信号，包括：
所述时序控制器确定在发送第一个垂直起始信号后，发送的垂直时钟脉冲的个数；
在所述垂直时钟脉冲个数为M时，所述时序控制器向所述栅极驱动器发送所述帧画面对应的第N+1个垂直起始信号。
优选地，所述时序控制器向栅极驱动器依次发送帧画面对应的N个垂直起始信号之后，还包括：
所述时序控制器向源极驱动器发送所述帧画面对应的预处理数据信号，以使所述源极驱动器根据所述预处理数据信号，对所述液晶面板前M行的存储电容进行预充电。
优选地，时序控制器向栅极驱动器发送第N+1个STV信号时，还同时向源极驱动器同步该帧画面对应的数据信号；
在第M+1行及M+1行之后的各行TFT预导通时，源极驱动器根据与其同时导通行的数据信号，对各行上的存储电容进行预充电。
优选地，所述时序控制器向源极驱动器依次发送所述帧画面对应的预处理数据信号之前，还包括：
所述时序控制器根据所述帧画面的灰阶大小确定所述预处理数据信号。
优选地，M小于所述液晶面板总行数的1/3。
优选地，所述液晶面板的极性反转方式为行极性反转；
所述M为偶数。
本发明另一方面提供一种液晶显示时序控制装置，包括：
第一发送模块，用于向栅极驱动器依次发送帧画面对应的N个垂直起始信号，以使所述栅极驱动器根据所述N个垂直起始信号，依次控制液晶面板各行的薄膜晶体管(Thin Film Transistor，简称TFT)预导通N次，以便源极驱动器在各行TFT预导通时，对各行的存储电容进行预充电；
第二发送模块，用于在液晶面板第M行的TFT第一次预导通结束前，向所述栅极驱动器发送所述帧画面对应的N+1个垂直起始信号，以使所述栅极驱动器根据所述第N+1垂直起始信号，控制液晶面板各行的TFT依次导通第N+1次，以便源极驱动器在各行TFT第N+1次导通时，对各行的存储电容进行最终充电，N和M为大于或等于1，且小于液晶面板总行数的正整数。
优选地，该装置还包括：
第三发送模块，用于向栅极驱动器依次发送所述帧画面对应的N个扫描 驱动输出使能信号，以使所述栅极驱动器根据所述N个扫描驱动输出使能信号，控制所述液晶面板各行TFT预导通N次的时间；
所述第三发送模块，还用于向栅极驱动器发送所述帧画面对应的第N+1个扫描驱动输出使能信号，以使所述栅极驱动器根据所述第N+1个扫描驱动输出使能信号，控制所述液晶面板各行TFT第N+1次导通的时间
优选地，该装置还包括：
确定模块，用于根据所述帧画面的灰阶大小确定所述N个扫描驱动输出使能信号的宽度；
所述确定模块，还用于根据所述帧画面的灰阶大小确定所述第N+1个扫描驱动输出使能信号的宽度。
优选地，所述第二发送模块，具体用于：
确定在发送第一个垂直起始信号后，发送的垂直时钟脉冲的个数；
在所述垂直时钟脉冲个数为M时，所述时序控制器向所述栅极驱动器发送所述帧画面对应的第N+1个垂直起始信号。
优选地，该装置还包括：
第四发送模块，用于向源极驱动器发送所述帧画面对应的预处理数据信号，以使所述源极驱动器根据所述预处理数据信号，对所述液晶面板前M行的存储电容进行预充电。
优选地，该装置还包括：
第五发送模块，用于向栅极驱动器发送第N+1个STV信号时，还同时向源极驱动器同步该帧画面对应的数据信号，以使在第M+1行及M+1行之后的各行TFT预导通时，源极驱动器根据与其同时导通行的数据信号，对各行上的存储电容进行预充电。
优选地，所述确定模块，还用于所述时序控制器根据所述帧画面的灰阶大小确定所述预处理数据信号。
优选地，M小于所述液晶面板总行数的1/3。
优选地，所述液晶面板的极性反转方式为行极性反转；
所述M为偶数。
本发明再一方面提供一种液晶显示设备，包括：处理器、存储器、栅极驱动器、源极驱动器、液晶面板各行的薄膜晶体管(Thin Film Transistor，简称TFT)和存储电容；
存储器，用于存储程序；
处理器，用于执行所述存储器中程序，向栅极驱动器依次发送帧画面对应的N个垂直起始信号，并在液晶面板第M行的TFT第一次预导通结束前，向所述栅极驱动器发送所述帧画面对应的第N+1个垂直起始信号；
所述栅极驱动器，用于根据所述N个垂直起始信号，依次控制液晶面板各行的TFT预导通N次；并根据所述第N+1垂直起始信号，控制液晶面板各行的TFT依次导通第N+1次；
所述源极驱动器，用于在各行TFT第N+1次导通时，对各行的存储电容进行最终充电，同时在各行TFT预导通时，对各行的存储电容进行预充电，其中，N和M为大于或等于1，且小于液晶面板总行数的正整数。
本发明提供的液晶显示处理方法、装置和设备，对每一帧画面，时序控制器都会先向栅极驱动器发送该帧画面对应的N个STV信号，栅极驱动器根据N个STV信号，依次控制液晶面板各行的TFT预导通N次，之后在第M行第一次预导通结束前，向栅极驱动器发送该帧画面的第N+1个STV信号，栅极驱动器根据第N+1个STV信号，依次控制液晶面板各行的TFT导通第N+1次，以便使源极驱动器根据该帧画面对应的数据信号对各行的存储电容进行最终充电，同时对TFT预导通的各行的存储电容进行预充电，本液晶显示处理方法通过在一帧画面显示前，对屏幕中所有行的存储电容进行至少两次充电，延长了对液晶面板各行的存储电容的充电时间，从而使各行存储电容两端的电量尽量满足帧画面显示的需求，提高了液晶显示器的画质。
附图说明
图1为液晶面板的等效电路图；
图2为现有技术中普通液晶面板的驱动时序图；
图3为本发明实施例一提供的一种液晶显示处理方法的流程示意图；
图4为本发明实施例提供的液晶面板驱动时序图；
图5为本发明实施例二提供的另一种液晶显示处理方法的流程示意图；
图6为本发明实施例三提供的又一种液晶显示处理方法的流程示意图；
图7为像素点的等效电路图；
图8为液晶面板的各极性反转方式图；
图9为本发明实施例四提供的又一种液晶显示处理方法流程示意图；
图10为本发明实施例五提供的一种液晶显示时序控制装置结构示意图；
图11为本发明实施例六提供的另一种液晶显示时序控制装置结构示意图；
图12为本发明实施例七提供的又一种液晶显示时序控制装置结构示意图；
图13为本发明实施例八提供的一种液晶显示设备结构示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。
由背景技术分析可知，随着液晶面板像素的增多就会使液晶面板每一行存储电容的充电时间变短，当行数增加到一定程度时，每行的存储电容就会存在充电不足的问题，从而会严重影响液晶显示器的画质，这主要是由于每个像素点上存储电容两端电压的大小决定了液晶分子的翻转角度，当液晶分子翻转角度达不到帧画面显示的要求时，就会使画质变差，基于此原因，本发明主要从如何增加各像素点上存储电容两端电压的角度提出一种液晶显示处理方法、装置和设备。
图3为本发明实施例一提供的一种液晶显示处理方法的流程示意图。如图3所示，该液晶显示处理方法包括：
S30，时序控制器向栅极驱动器依次发送帧画面对应的N个垂直起始信号(Start Vertical，简称STV)，以使所述栅极驱动器根据所述N个垂直起始信号，依次控制液晶面板各行的薄膜晶体管(Thin Film Transistor，简称TFT)预导通N次，以便源极驱动器在各行TFT预导通时，对各行的存储电容进行预充电。
S31，所述时序控制器在液晶面板第M行的TFT第一次预导通结束前，向所述栅极驱动器发送所述帧画面对应的第N+1个垂直起始信号，以使所述栅极驱动器根据所述第N+1垂直起始信号，控制液晶面板各行的TFT依次导通第N+1次，以便源极驱动器在各行TFT第N+1次导通时，对各行的存储电容进行最终充电，其中，N和M为大于或等于1，且小于所述液晶面板总行数的正整数。
在本实施例中，液晶显示处理方法的执行主体为时序控制器(Time Controller，简称Tcon)。时序控制器分别与信号源和液晶面板连接，时序控制器用于根据信号源提供的图像信息，生成控制信号和符合液晶面板需要的数据信号，如为源极驱动器提供需要的源极驱动器锁存(latch signal for source driver，简称TP)信号和输出数据的使能控制(polarity inversion signal for sorce driver，简称POL)信号，其中，TP控制每一行数据信息的锁存和输出，比如，TP信号高电平时，控制一行数据锁存到行存储器内，低电平时，释放一行数据，对液晶电容充电，POL用于控制液晶分子极性反转；为栅极驱动器提供需要的垂直时钟脉冲(Clock Pulse Vertical，简称CPV)信号、垂直起始(Start Vertical，简称STV)信号、扫描驱动输出使能(scan driver output enable，简称OE)信号等。
其中，本实施例中，栅极驱动器在收到STV信号后，就开始控制液晶面板各行的TFT依次导通，在N+1个STV信号的控制下，控制各行的TFT循环导通N+1次，其中，各行TFT的N+1次导通周期是交叉同时进行的。在前N个STV信号期间，源极驱动器可能接收到了Tcon发送的数据信号，也可能未收到Tcon发送的数据信号，而且，源极驱动器收到的数据信号可以是帧画 面的实际数据信号，也可以是Tcon根据所述帧画面的灰阶大小确定的预处理数据信号，或者，也可以是Tcon结合各行TFT在每帧画面期间，导通的次数、每次导通时间及实际数据信号确定的预处理数据信号。
本实施例中的时序控制器在每帧画面显示前，向栅极驱动器发送N+1个STV信号，使得对每帧画面而言，栅极驱动器控制液晶面板各行的TFT至少导通N+1次，从而使源极驱动器可以为各行的存储电容进行至少N+1次充电。其中，在各行的TFT前N次导通时，源极驱动器对各行的存储电容进行预充电，在各行的TFT第N+1次导通时，源极驱动器对各行的存储电容进行最终充电，从而使帧画面显示。最终充电时，源极驱动器可以对存储电容上的电量进行补充或矫正。举例来说，若液晶面板某个像素点的存储电容在预充电后，电量大于该像素点显示当前帧画面需要的电量，则最终充电时，该像素点的存储电容上的电量可通过源极驱动器进行释放，使得最终该像素点的存储电容上的电量满足当前帧画面显示的需求。相应的，若液晶面板某个像素点的存储电容在预充电后，电量小于该像素点显示当前帧画面需要的电量，则最终充电时，源极驱动器继续向该像素点的存储电容进行充电，从而使得该像素点的存储电容上的电量满足当前帧画面显示的需求。
为了更加直观的说明本实施例中液晶显示处理方法，下面结合本实施例提供的液晶面板驱动时序图，对本方法进行进一步的描述。首先，根据图2可知，图2中提供的现有技术中普通液晶面板的驱动方式具体为：在一帧画面开始传输时，时序控制器向栅极驱动器发送一个STV信号，栅极驱动器收到STV信号后，即在第一个CPV信号高电平到来时，向液晶面板第一行的TFT输出一个高电平信号G1，控制第一行的TFT导通，从而源极驱动器对第一行各像素点的存储电容进行充电，当第二个CPV信号高电平到来时，栅极驱动器向液晶面板第二行的TFT输出一个高电平信号G2，控制第二行的TFT导通，并且将向第一行的TFT输出的G1变为低电平，关断第一行的TFT，从而源极驱动器对第二行各像素点的存储电容进行充电，依次类推，逐行对液晶面板各行的存储电容进行充电。通过上述分析可知，每行TFT的导通时 间与液晶面板的总行数有关，假设液晶面板有N行，每帧画面的更新频率为f，则每行TFT的导通时间为1/(N*f)，随着液晶面板行数的增加，每行TFT的导通时间会减小，而由图1中的TFT单元可知，TFT导通时间越短，源极驱动器通过TFT对存储电容的充电时间就越短，存储电容上的电量就越低，从而会出现充电不足的问题。
与图2中现有技术中普通液晶面板的驱动不同的是，本实施例中的时序控制器在每帧画面显示前，向栅极驱动器发送N次STV信号，N大于1，下面结合图4，以N＝1为例，具体说明本液晶显示处理方法对各行存储电容进行充电的过程。同理，对于N大于1情形不再赘述。
图4为本发明实施例提供的液晶面板驱动时序图。假设液晶面板有m行，分别对应m个栅极驱动信号为G1、G2……Gn-1、Gn、Gn+1……Gm。具体来说，对每一帧画面，时序控制器都会首先向栅极驱动器发送一个STV信号STV1，之后，栅极驱动器接收到STV1后，即在第一个CPV信号高电平到来时，向液晶面板第一行的TFT输出一个高电平信号G1，控制第一行的TFT预导通，当第二个CPV信号高电平到来时，栅极驱动器向液晶面板第二行的TFT输出一个高电平信号G2，控制第二行的TFT预导通，并且将向第一行的TFT输出的G1变为低电平，关断第一行的TFT，依次类推，栅极驱动器控制液晶面板各行的TFT逐行预导通，源极驱动器在各行TFT预导通时，对各行的存储电容进行预充电。
假如在液晶面板的第M行TFT预导通结束前，即在栅极驱动器收到STV1之后，监测到第M个CPV信号后，时序控制器向栅极驱动器发送第二个STV信号STV2，此时，Tcon也会向源极驱动器同步该帧画面对应的数据信号，那么在第M+1个CPV信号到来时，栅极驱动器在STV1和STV2的控制下，同时向液晶面板第M+1行和第一行的TFT输出2个高电平信号GM和G1，控制第M+1行和第一行的TFT同时导通，并且将向第M行的TFT输出的GM变为低电平，关断第M行的TFT，此时，源极驱动器即可根据接收到的数据信号对第一行的存储电容进行最终充电，从而使第一行的各像素点上的存储 电容两端的电压满足帧画面的显示要求，并显示帧画面对应的内容，同时，源极驱动器利用第一行的数据信号对第M+1行的存储电容进行预充电；在第M+2个CPV信号到来时，栅极驱动器在STV1和STV2的控制下，同时向液晶面板第M+2行和第二行的TFT输出2个高电平信号GM+2和G2，控制第M+2行和第二行的TFT同时导通，并且将向第M+1行和第一行的TFT输出的GM+1和G1变为低电平，关断第M+1行和第一行的TFT，此时，源极驱动器即可根据接收到的数据信号对第二行各像素点的存储电容进行最终充电，以使第二行显示帧画面的内容，同时，源极驱动器利用第二行的数据信号对第M+2行的存储电容进行预充电，依次类推，直至源极驱动器根据与帧画面对应的数据信号完成对液晶面板所有行的存储电容的最终充电，同时，对液晶面板第M+1行及之后所有行的存储电容的预充电，从而完成了对该帧画面的显示处理。由于Tcon控制对液晶面板的各行的存储电容进行了两次充电，延长了各行存储电容的充电时间，从而使得各行存储电容两端的电量尽量满足帧画面显示的需求。
通过上述分析可知，在第M+1行及M+1行之后的各行TFT预导通时，源极驱动器都是根据与其同时导通行的实际数据信号，对各行上的存储电容进行了预充电，如第M+1行预充电电压为第一行的最终充电电压，而第M+2行的充电电压为第二行的最终充电电压等等。由于，在第N+1个STV信号到来前，Tcon可能向源极驱动器发送了数据信号，也可能未发送数据信号，相应的，在第M行之前，所有行的存储电容可能进行了预充电，也可能未进行预充电。为了尽量使所有行的存储电容都至少进行两次充电，本实施例中，可以在上述S30之后，由所述时序控制器向源极驱动器发送所述帧画面对应的预处理数据信号，以使所述源极驱动器根据所述预处理数据信号，对所述液晶面板前M行的存储电容进行N次预充电。其中，预处理数据信号可以是与帧画面对应的数据信号相同的信号，也可以是不同的数据信号。
需要说明的是，由于TFT本身有寄生电容，所以在存储电容两端有与之并联的寄生电容存在，故当对存储电容进行充电时，与之并联的寄生电容也 会同样被充电，即在本发明各个实施例中在对存储电容进行至少两次充电的同时，也对寄生电容进行了至少两次充电。
本实施例提供的液晶显示处理方法，对每一帧画面，时序控制器都会先向栅极驱动器发送该帧画面对应的N个STV信号，栅极驱动器根据N个STV信号，依次控制液晶面板各行的TFT预导通N次，源极驱动器在各行TFT预导通时，对各行的存储电容进行预充电，在第M行TFT第一次预导通结束前，向栅极驱动器发送该帧画面的第N+1个STV信号，栅极驱动器根据第N+1个STV信号，依次控制液晶面板各行的TFT导通第N+1次，以便使源极驱动器根据该帧画面对应的数据信号对各行的存储电容进行最终充电，本液晶显示处理方法通过在一帧画面显示前，对屏幕中所有行的存储电容进行至少两次充电过程，延长了对液晶面板各行的存储电容的充电时间，从而使各行存储电容两端的电量尽量满足帧画面显示的需求，提高了液晶显示器的画质。
通过上述分析可知，对每帧画面而言，Tcon通过控制液晶面板各行的TFT至少导通两次，来延长对液晶面板各行的存储电容的充电时间，在实际使用时，对各行的存储电容进行两次充电后，为了使最终各行的存储电容上的电量尽可能满足帧画面需求，可进一步对各行的存储电容上电量进行准确控制，控制存储电容上的电量可以通过控制各行TFT每次的导通时间来实现，下面结合图5对通过控制各行TFT每次的导通时间来实现控制各行的存储电容上电量的方法进行详细的描述。
图5为本发明实施例二提供的另一种液晶显示处理方法的流程示意图。如图5所示，在上述图3所示的基础上，在S30之后，本实施提供的液晶显示处理方法，还包括：
S32，所述时序控制器向栅极驱动器依次发送所述帧画面对应的N个扫描驱动输出使能信号，以使所述栅极驱动器根据所述N个扫描驱动输出使能信号，控制所述液晶面板各行的薄膜晶体管预导通N次的时间。
相应的，在S31之后，本实施提供的液晶显示处理方法，还包括：
S33，所述时序控制器向栅极驱动器发送所述帧画面对应的第N+1个扫描驱动输出使能信号，以使所述栅极驱动器根据所述第N+1个扫描驱动输出使能信号，控制所述液晶面板各行的薄膜晶体管第N+1次导通的时间。
本实施例中，Tcon在向栅极驱动器发送N个STV信号后，再向栅极驱动器发送N个OE信号，其中，若N个OE信号的宽度相同，也可以向栅极驱动器仅发送一个N个OE信号；或者，Tcon也可以每向栅极驱动器发送一个STV信号，就向栅极驱动器发送一个OE信号。本实施例对此不做限定。其中，对每帧画面而言，不同的STV信号对应的OE信号宽度可以相同也可以不同，每个STV信号期间，每行的TFT对应的OE信号宽度可以相同也可以不同。本实施例对此不做限定。
具体的，本实施例中，对每帧画面而言，Tcon在向栅极驱动器发送STV信号后，再向栅极驱动器发送OE信号，使得栅极驱动器在控制每行的TFT导通后，再根据对应的OE信号控制该行的TFT的每次导通时间，从而控制了源极驱动器对各行的存储电容每次的充电时间，使得各行的存储电容上的电量尽量满足帧画面显示的需求。
可以理解的是，为了进一步控制存储电容每次的充电时间，对同一STV信号而言，Tcon还可以根据不同的行，向栅极驱动器发送不同的OE信号，使得在同一STV信号周期内，不同行的TFT的导通时间不同，即，使不同行的存储电容的充电时间不同。
本实施例提供的液晶显示处理方法，对每一帧画面，时序控制器都会先向栅极驱动器发送该帧画面对应的N个STV信号，栅极驱动器根据N个STV信号，依次控制液晶面板各行的TFT预导通N次，源极驱动器在各行TFT预导通时，对各行的存储电容进行预充电，在第M行第一次预导通结束前，向栅极驱动器发送该帧画面的第N+1个STV信号，栅极驱动器根据第N+1个STV信号，依次控制液晶面板各行的TFT导通第N+1次，以便使源极驱动器根据该帧画面对应的数据信号对各行的存储电容进行最终充电，本液晶显示处理方法通过在一帧画面显示前，对屏幕中所有行的存储电容进行至少两次 充电过程，延长了对液晶面板各行的存储电容的充电时间，从而使各行存储电容两端的电量尽量满足帧画面显示的需求，提高了液晶显示器的画质。并且通过控制各行的TFT每次导通的时间，来控制源极驱动器对各行的存储电容的总充电时间，使各行存储电容两端的电量更加准确，进一步提高了液晶显示器的画质。
进一步地，为了更加精准的控制液晶面板各行TFT导通的时间，从而控制源极驱动器向各行的存储电容上充的电量，使各行的存储电容上的电量满足帧画面需求，还可以根据每帧画面的灰阶大小设置上述的OE信号的宽度，下面结合图6对本发明提供的又一种液晶显示处理方法进行说明。
图6为本发明实施例三提供的又一种液晶显示处理方法的流程示意图。如图6所示，在图5所示的基础上，上述S32之前，该液晶显示处理方法还包括：
S34，所述时序控制器根据所述帧画面的灰阶大小确定所述N个扫描驱动输出使能信号的宽度。
相应的，S33之前，液晶显示处理方法还包括：
S35，所述时序控制器根据所述帧画面的灰阶大小确定所述第N+1个扫描驱动输出使能信号的宽度。
具体的，Tcon根据当前帧画面的灰阶大小可以确定液晶面板各个像素点存储电容上最终需要的电量大小，从而通过合理的设置各OE信号的宽度，使得各个像素点的存储电容在预充电和最终充电结束后，存储电容上的电量与帧画面显示需要的电量尽量一致。
本实施例提供的液晶显示处理方法，Tcon根据当前帧画面的灰阶大小确定OE信号的宽度，实现了对各像素点的存储电容上的电量的精准控制，进一步提高了液晶显示器的画质。
另外，结合图1和图4可以看出，假如液晶面板每行的TFT个数为K， 对每个帧画面而言，在Tcon向栅极驱动器发送STV2信号前，每个CPV到来时，栅极驱动器控制导通的TFT的个数为K，而在Tcon向栅极驱动器发送STV2信号后，且在液晶面板的最后一行完成该帧画面的预充电前，每个CPV信号到来时，栅极驱动器控制导通的TFT的个数为2K。并且，由图1中可以看出，在每次导通的2K个TFT中，都使用相同的源极驱动信号，即每列的TFT都使用相同的电压对各自的存储电容充电，而本实施例中，由于源极驱动器输出数据信号的时机与栅极驱动器相似，都是在收到STV信号后，随CPV信号的频率依次变化，并且，为了保证帧画面最终显示的效果，各行的TFT在最终导通时，源极驱动器加在各行的存储电容上的数据信号需要是帧画面对应的实际数据信号，那么，在时序控制器输出第N+1个STV信号后，栅极驱动器再一次输出第一行TFT的驱动信号G1时，源极驱动器加载到TFT源极上的充电电压为第一行的帧画面对应的电压，此时，第一行帧画面的电压在对第一存储电容进行最终充电的同时，也对与第一行TFT同时导通行的存储电容进行预充电。
那么本实施例中，若要通过对每行的存储电容至少充电两次，来实现每行存储电容的充电量的增加，就要求TFT同时导通的行的存储电容具有相同的充电极性，举例来说，第一行和第L行的TFT同时导通，就要求第一行和第L行的像素点上的存储电容在同一帧画面时具有相同的极性。下面以一个像素点的等效电路为例进行说明。
图7为像素点的等效电路图。假设图7中存储电容的上极板的电压高于公共电极板时，表示该像素点的液晶分子向上翻转，用“+”表示，存储电容的上极板的电压低于公共电极板时，表示该像素点的液晶向下翻转，用“-”表示。
举例来说，若图7中的TFT某一次充电结束后，存储电容的电压为下正、上负，此时该像素点的液晶分子向下翻转，而若接下来一次充电结束后，存储电容上的电压变为下负上正，则说明第二次的充电极性与第一次相反。举例来说，若1V的电压控制液晶分子翻转的角度为10度(°)，比如第一充电 后，存储电容上电压为-2V，此时该像素点的液晶分子向下翻转20°，第二次充电后，存储电容上电压为+3V，那么两次充电结束后，存储电容上的充电电压为+1V，最终该像素点的液晶分子向上翻转10°，与第一次充电后相比，液晶分子最终的翻转方向不仅变了，且翻转角度较第一次充电后更小了。通过上述分析可以看出，若TFT前后两次导通时，对存储电容的充电极性不同，那么两次充电可能并不能增大该像素点液晶的偏转，反而拉低了液晶分子的反转，使得画质更差，因此，对每帧画面而言，为了实现通过至少两次充电，增加各行存储电容上的电量，必须保证TFT同时导通的行的存储电容具有相同的充电极性，对于本实施例而言，需要保证第M行的存储电容与第一行的存储电容具有相同的充电极性。
而液晶面板各行的存储电容的充电极性与液晶面板的极性反转方式相关。液晶面板的极性反转方式如图8所示主要包括帧极性反转、行极性反转、列极性反转和点极性反转。图8为液晶面板的各极性反转方式图。图中用“+”和“-”表示像素点上液晶分子的两种翻转方向或者存储电容的两种充电电压极性，由图8可以看出，对于帧极性反转方式，如果第N帧各存储电容被正电压充电，则第N+1帧各存储电容被负电压充电；对于行极性反转方式，如果第N帧各奇数行存储电容被正电压充电，各偶数行存储电容被负电压充电，则第N+1帧各奇数行存储电容被负电压充电，各偶数行存储电容被正电压充电；对于列极性反转方式，极性变换与行极性反转方式类似；对于点极性反转方式，相邻像素点的存储电容的充电电压极性相反。对图8进行分析可以得知，对于帧极性反转方式、列极性反转方式和点极性反转方式的液晶面板，第M行可以为液晶面板上除第一行之外的任意一行，而对于行极性反转方式的液晶面板，M行可以为液晶面板上的任意一个偶数行，即可满足，TFT同时导通的行的存储电容具有相同的充电极性。
需要说明的是，各存储电容两端的电压在充电后会保持一段时间，直至下一帧画面来临，而存储电容上电压保持的时间与帧画面的更新频率有关，假如帧画面更新频率为60赫兹(Hz)，则存储电容的保持时间大概为(1/60)秒 (s)＝16.6毫米(ms)，那么液晶分子在该电压的作用下，翻转保持时间也可达16.6ms，而对于高清(High-Definition简称，HD)液晶显示器而言，其分辨率为(1366*768)，假设有效行数为768，每帧画面空行为38，则每帧画面总行数为806，这样每行的充电时间为1/60/806＝20.7微秒(us)，这相对于16.6ms非常小，因此预充电带来帧画面变化对帧画面显示影响非常小，不会因为分两次充电而影响帧画面显示内容。
由上述分析可知，若通过对同一行的存储电容进行至少两次充电，实现延长各行存储电容充电时间的目的，需要根据液晶面板的极性反转方式，使第M行的液晶分子的翻转方式与第一行的液晶分子的翻转方式满足一定关系，时序控制器在确定第M行时，可以采用多种方式实现，举例来说，可以采用一个计时器，由于每行TFT的导通时间可知，那么Tcon在发送第一个STV信号后，即可在第一个CPV信号高电平输出时启动计时器，当计时时间达到M行的TFT第一次预导通时，即可触发发送第N个STV信号。或者，由于每行TFT的导通时机与CPV信号相关，那么Tcon也可以采用计数器来辅助确定发送第N+1个STV信号的时机，下面图9中以采用计数器的方式为例对本方案进行详细描述。
图9为本发明实施例四提供的又一种液晶显示处理方法流程示意图。如图9所示，在上述图7所述的基础上，上述S31包括：
S31a，所述时序控制器确定在发送所述第一个垂直起始信号后，发送的垂直时钟脉冲的个数。
S31b，在所述垂直时钟脉冲个数为M时，所述时序控制器向所述栅极驱动器发送所述帧画面对应的第N+1个垂直起始信号。
本实施例中，结合图4来说，举例来说，若M为4，则Tcon在向栅极驱动器发送第一个STV信号后，即可启动计数器，开始记录发送的CPV信号的个数，当计数器计数值为4之后，Tcon就可向栅极驱动器发送第2个STV信号，结合图4可知，在第5个CPV信号到来时，栅极驱动器会同时向第5行的TFT和第一行的TFT输出高电平驱动信号，从而使第5行的TFT和第一行 的TFT同时导通，之后各列的源极驱动器，分别向第5行的存储电容进行预充电，向第1行的存储电容进行最终充电。
另外，通过图4可以得出，假设帧画面的更新频率为f，液晶面板的总行数为L，则采用本液晶显示处理方法时，在第L行的存储电容完成最终充电时，该帧画面对应的所有行的存储电容的总充电时间大于1/f，若第M行选择的距离第一行越远，则一副帧画面对应的所有行的存储电容的总充电时间越大，而由于两幅帧画面传输的时间间隔为1/f，若前一帧画面的传输，液晶面板各行的存储电容充电时间过长，会影响下一帧画面的显示，因此本发明中M小于所述液晶面板总行数的前1/3，比如，对应HD型液晶显示器，M可以在256以内选择，选择的M越小，效果越好。
结合上述图8举例来说，对于液晶面板的反转方式为帧极性反转、点极性反转或列极性反转的液晶显示设备，M可以为2、3、4等等。若选择的M为2，则当第1行TFT预导通结束前，Tcon向栅极驱动器发送第二STV信号，从而在下一个CPV到来时，栅极驱动器同时向第二行TFT和第一行TFT输出高电平驱动信号，控制第二行TFT和第一行TFT导通，从而对第二行的存储电容进行预充电，并对第一行的存储电容进行最终充电，依次类推，完成对整个液晶面板所有行的存储电容的两次充电。
或者，由图8可以看出，若所述液晶面板的极性反转方式为行极性反转，则液晶面板上的各行，每相隔一行的液晶分子的翻转方向相同，那么为达到通过两次对存储电容的充电，增加存储电容两端电压的目的，则需保证M为偶数。即，在第2行、第4行或第6行等等任意一行的TFT预导通结束前，Tcon向栅极驱动器发送第二个STV信号，从而在下一个CPV到来时，栅极驱动器同时向第3行、第5行或第7行等等任意一行TFT和第一行TFT输出高电平驱动信号，控制第3行、第5行或第7行等等任意一行TFT和第一行TFT导通，从而对第3行、第5行或第7行等等任意一行的存储电容进行充电，并对第1行的存储电容进行最终充电，依次类推，完成对整个液晶面板所有行的存储电容的两次充电。同样的，为了尽量减小帧画面间的干扰，第 M行最好选择距离第一行较近的行，比如，M为2。
本实施例提供的液晶显示处理方法，在一帧画面显示前，对屏幕中所有行的存储电容进行至少两次充电过程，延长了对液晶面板各行的存储电容的充电时间，从而使各行存储电容两端的电量尽量满足帧画面显示的需求，提高了液晶显示器的画质。另外，通过选择距离第一行较近的行作为第M行，使得在提高液晶显示器画质的同时，不影响帧画面间的显示效果。
图10为本发明实施例五提供的一种液晶显示时序控制装置结构示意图。如图10所示，该液晶显示时序控制装置100包括：第一发送模块101和第二发送模块102。
其中，第一发送模块101用于向栅极驱动器依次发送帧画面对应的N个垂直起始信号，以使所述栅极驱动器根据所述N个垂直起始信号，依次控制液晶面板各行的薄膜晶体管(Thin Film Transistor，简称TFT)预导通N次，以便源极驱动器在各行TFT预导通时，对各行的存储电容进行预充电；
第二发送模块102用于在液晶面板第M行的TFT第一次预导通结束前，向所述栅极驱动器发送所述帧画面对应的N+1个垂直起始信号，以使所述栅极驱动器根据所述第N+1垂直起始信号，控制液晶面板各行的TFT依次导通第N+1次，以便源极驱动器在各行TFT第N+1次导通时，对各行的存储电容进行最终充电，其中，N和M为大于或等于1，且小于所述液晶面板总行数的正整数。
本实施例中的液晶显示时序控制装置中包括Tcon。液晶显示时序控制装置分别与信号源和液晶面板连接，液晶显示时序控制装置中的Tcon用于根据信号源提供的图像信息，生成控制信号和符合液晶面板需要的数据信号，如为源极驱动器提供需要的TP信号和POL信号，为栅极驱动器提供需要的CPV信号、STV信号等。
其中，本实施例中，栅极驱动器在收到STV信号后，就开始控制液晶面板各行的TFT依次导通，在N+1个STV信号的控制下，控制各行的TFT循 环导通N+1次，其中，各行TFT的N+1次导通周期是交叉同时进行的。在前N个STV信号期间，源极驱动器可能接收到了Tcon发送的数据信号，也可能未收到Tcon发送的数据信号，而且，源极驱动器收到的数据信号可以是帧画面的实际数据信号，也可以是Tcon根据所述帧画面的灰阶大小确定的预处理数据信号，或者，也可以是Tcon结合各行TFT在每帧画面期间，导通的次数、每次导通时间及实际数据信号确定的预处理数据信号。
本实施例中的时序控制器在每帧画面显示前，向栅极驱动器发送N+1个STV信号，使得对每帧画面而言，栅极驱动器控制液晶面板各行的TFT至少导通N+1次，从而使源极驱动器可以为各行的存储电容进行至少N+1次充电。其中，在各行的TFT前N次导通时，源极驱动器对各行的存储电容进行预充电，在各行的TFT第N+1次导通时，源极驱动器对各行的存储电容上进行最终充电，从而使帧画面显示。最终充电时，源极驱动器可以对存储电容上的电量进行补充或矫正。举例来说，若液晶面板某个像素点的存储电容在预充电后，电量大于该像素点显示当前帧画面需要的电量，则最终充电时，该像素点的存储电容上的电量可通过源极驱动器进行释放，使得最终该像素点的存储电容上的电量满足当前帧画面显示的需求。相应的，若液晶面板某个像素点的存储电容在预充电后，电量小于该像素点显示当前帧画面需要的电量，则最终充电时，源极驱动器继续向该像素点的存储电容进行充电，从而使得该像素点的存储电容上的电量满足当前帧画面显示的需求。
本实施例提供的液晶显示时序控制装置中各模块的功能及处理流程，可参照上述实施例一提供的液晶显示处理方法的详细描述，此处不再赘述。
本实施例提供的液晶显示时序控制装置，对每一帧画面，时序控制器都会先向栅极驱动器发送该帧画面对应的N个STV信号，栅极驱动器根据N个STV信号，依次控制液晶面板各行的TFT预导通N次，在第M行第一次预导通结束前，向栅极驱动器发送该帧画面的第N+1个STV信号，栅极驱动器根据第N+1个STV信号，依次控制液晶面板各行的TFT导通第N+1次，以便使源极驱动器根据该帧画面对应的数据信号对各行的存储电容进行最终充 电，同时对TFT预导通的各行的存储电容进行预充电，本液晶显示处理方法通过在一帧画面显示前，对屏幕中所有行的存储电容进行至少两次充电过程，延长了对液晶面板各行的存储电容的充电时间，从而使各行存储电容两端的电量尽量满足帧画面显示的需求，提高了液晶显示器的画质。
通过上述分析可知，对每帧画面而言，Tcon通过控制液晶面板各行的TFT至少导通两次，来延长对液晶面板各行的存储电容的充电时间，在实际使用时，对各行的存储电容进行两次充电后，为了使最终各行的存储电容上的电量尽可能满足帧画面需求，可进一步对各行的存储电容上电量进行准确控制，控制存储电容上的电量可以通过控制各行TFT每次的导通时间来实现，下面结合图11对通过控制各行TFT每次的导通时间来实现控制各行的存储电容上电量的方法进行详细的描述。
图11为本发明实施例六提供的另一种液晶显示时序控制装置的结构示意图。如图11所示，在图10所示的基础上，该装置，还包括：第三发送模块103。其中，第三发送模块103用于向栅极驱动器依次发送所述帧画面对应的N个扫描驱动输出使能信号，以使所述栅极驱动器根据所述N个扫描驱动输出使能信号，控制所述液晶面板各行的薄膜晶体管预导通N次的时间；还用于向栅极驱动器发送所述帧画面对应的第N+1个扫描驱动输出使能信号，以使所述栅极驱动器根据所述第N+1个扫描驱动输出使能信号，控制所述液晶面板各行的薄膜晶体管第N+1次导通的时间
本实施例提供的液晶显示时序控制装置中各模块的功能和液晶显示处理方法，可参照上述实施例二提供的液晶显示处理方法的详细描述，此处不再赘述。
本实施例提供的液晶显示时序控制装置，对每一帧画面，时序控制器都会先向栅极驱动器发送该帧画面对应的N个STV信号，栅极驱动器根据N个STV信号，依次控制液晶面板各行的TFT预导通N次，之后在第M行第一次预导通结束前，向栅极驱动器发送该帧画面的第N+1个STV信号，栅极驱 动器根据第N+1个STV信号，依次控制液晶面板各行的TFT导通第N+1次，以便使源极驱动器根据该帧画面对应的数据信号对各行的存储电容进行最终充电，同时对TFT预导通的各行的存储电容进行预充电，本液晶显示处理方法通过在一帧画面显示前，对屏幕中所有行的存储电容进行至少两次充电过程，延长了对液晶面板各行的存储电容的充电时间，从而使各行存储电容两端的电量尽量满足帧画面显示的需求，提高了液晶显示器的画质。并且通过控制各行的TFT每次导通的时间，来控制源极驱动器对各行的存储电容的总充电时间，使各行存储电容两端的电量更加准确，进一步提高了液晶显示器的画质。
进一步地，为了更加精准的控制液晶面板各行TFT导通时，源极驱动器向各行的存储电容上充的电量，使各行的存储电容上的电量满足帧画面需求，还可以将上述的OE信号的宽度根据每帧画面的灰阶大小进行设置，下面结合图12对本发明提供的又一种液晶显示时序控制装置进行说明。
图12为本发明实施例七提供的又一种液晶显示时序控制装置的结构示意图。如图12所示，在图11所示的基础上，该装置还包括：确定模块104。
其中，确定模块104用于根据所述帧画面的灰阶大小确定所述N个扫描驱动输出使能信号的宽度；所述确定模块104，还用于根据所述帧画面的灰阶大小确定所述第N+1个扫描驱动输出使能信号的宽度。
具体的，液晶显示时序控制装置根据当前帧画面的灰阶大小可以确定液晶面板各个像素点存储电容上最终需要的电量大小，从而通过合理的设置OE信号的宽度，使得各个像素点的存储电容在预充电和最终充电结束后，存储电容上的电量与帧画面显示需要的电量尽量一致。
并且，通过上述分析可知，在第M+1行及M+1行之后的各行TFT预导通时，源极驱动器都是根据与其同时导通行的实际数据信号，对各行上的存储电容进行了预充电，如第M+1行预充电电压为第一行的最终充电电压，而第M+2行的充电电压为第二行的最终充电电压等等。由于，在第N+1个STV 信号到来前，Tcon可能向源极驱动器发送了数据信号，也可能未发送数据信号，相应的，在第M行之前所有行的存储电容可能进行了预充电，也可能未进行预充电。为了尽量使所有行的存储电容都至少进行两次充电，本实施例中，液晶显示时序控制装置还包括：第四发送模块105，用于向源极驱动器发送所述帧画面对应的预处理数据信号，以使所述源极驱动器根据所述预处理数据信号，对所述液晶面板前M行的存储电容进行N次预充电。其中，预处理数据信号可以是与帧画面对应的数据信号相同的信号，也可以是不同的数据信号。
优选地，液晶显示时序控制装置还包括：第五发送模块，用于向栅极驱动器发送第N+1个STV信号时，还同时向源极驱动器同步该帧画面对应的数据信号，以使在第M+1行及M+1行之后的各行TFT预导通时，源极驱动器根据与其同时导通行的数据信号，对各行上的存储电容进行预充电。
本实施例提供的液晶显示时序控制装置，根据当前帧画面的灰阶大小确定OE信号的宽度，实现了对各像素点的存储电容上的电量的精准控制，进一步提高了液晶显示器的画质。
另外，参照上述各液晶显示处理方法的相关描述可知，上述第二发送模块，具体用于：
确定在发送第一个垂直起始信号后，发送的垂直时钟脉冲的个数；
在所述垂直时钟脉冲个数为M时，所述时序控制器向所述栅极驱动器发送所述帧画面对应的第N+1个垂直起始信号。
本实施例中，结合图4来说，举例来说，若M为4，则Tcon在向栅极驱动器发送第一个STV信号后，即可启动计数器，开始记录发送的CPV信号的个数，当计数器计数值为4之后，Tcon就可向栅极驱动器发送第2个STV信号，结合图4可知，在第5个CPV信号到来时，栅极驱动器会同时向第5行的TFT和第一行的TFT输出高电平驱动信号，从而使第5行的TFT和第一行的TFT同时导通，之后各列的源极驱动器，分别向第5行的存储电容进行预 充电，向第1行的存储电容进行最终充电。
另外，通过图4可以得出，假设帧画面的更新频率为f，液晶面板的总行数为L，则采用本液晶显示处理方法时，在第L行的存储电容完成最终充电时，该帧画面对应的所有行的存储电容的总充电时间大于1/f，若第M行选择的距离第一行越远，则一副帧画面对应的所有行的存储电容的总充电时间越大，而由于两幅帧画面传输的时间间隔为1/f，若前一帧画面的传输，液晶面板各行的存储电容充电时间过长，会影响下一帧画面的显示，因此本发明中M小于所述液晶面板总行数的前1/3，比如，对应HD型液晶显示器，M可以在256以内选择，选择的M越小，效果越好。
结合上述图8举例来说，对于液晶面板的反转方式为帧极性反转、点极性反转或列极性反转的液晶显示设备，M可以为2、3、4等等。若选择的M为2，则当第1行TFT预导通结束前，Tcon向栅极驱动器发送第二STV信号，从而在下一个CPV到来时，栅极驱动器同时向第二行TFT和第一行TFT输出高电平驱动信号，控制第二行TFT和第一行TFT导通，从而对第二行的存储电容进行预充电，并对第一行的存储电容进行最终充电，依次类推，完成对整个液晶面板所有行的存储电容的两次充电。
或者，由图8可以看出，若所述液晶面板的极性反转方式为行极性反转，则液晶面板上的各行，每相隔一行的液晶分子的翻转方向相同，那么为达到通过两次对存储电容的充电，增加存储电容两端电压的目的，则需保证M为偶数。即，在第2行、第4行或第6行等等任意一行的TFT预导通结束前，Tcon向栅极驱动器发送第二个STV信号，从而在下一个CPV到来时，栅极驱动器同时向第3行、第5行或第7行等等任意一行TFT和第一行TFT输出高电平驱动信号，控制第3行、第5行或第7行等等任意一行TFT和第一行TFT导通，从而对第3行、第5行或第7行等等任意一行的存储电容进行充电，并对第1行的存储电容进行最终充电，依次类推，完成对整个液晶面板所有行的存储电容的两次充电。同样的，为了尽量减小帧画面间的干扰，第M行最好选择距离第一行较近的行，比如，M为2。
本实施例提供的液晶显示时序控制装置，在一帧画面显示前，对屏幕中所有行的存储电容进行至少两次充电过程，延长了对液晶面板各行的存储电容的充电时间，从而使各行存储电容两端的电量尽量满足帧画面显示的需求，提高了液晶显示器的画质。另外，通过选择距离第一行较近的行作为第M行，使得在提高液晶显示器画质的同时，不影响帧画面间的显示效果。
图13为本发明实施例八提供的一种液晶显示设备结构示意图。如图13所示，该液晶显示设备130，包括：处理器131、存储器132、栅极驱动器133、源极驱动器134、液晶面板各行的薄膜晶体管(Thin Film Transistor，简称TFT)135和液晶面板各行的存储电容136。
其中，存储器132用于存储程序；
处理器131用于执行所述存储器132中程序，向栅极驱动器133依次发送帧画面对应的N个垂直起始信号，并在液晶面板第M行的TFT第一次预导通结束前，向所述栅极驱动器133发送所述帧画面对应的第N+1个垂直起始信号；
所述栅极驱动器133用于根据所述N个垂直起始信号，依次控制液晶面板各行的TFT135预导通N次；并根据所述第N+1垂直起始信号，控制液晶面板各行的TFT135依次导通第N+1次；
所述源极驱动器134用于在各行TFT135第N+1次导通时，对各行的存储电容136进行最终充电，同时在各行TFT135预导通时，对各行的存储电容136进行预充电，其中，N和M为大于或等于1，且小于液晶面板总行数的正整数。
本实施例中，存储器存储的程序包括待显示的帧画面信息，产生与帧画面对应各垂直起始信号相关程序、产生时钟信号的程序及源极驱动器对各行存储电容进行充电需要的数据信息等等。
在液晶显示设备使用时，处理器通过执行存储器中的程序，产生图像信号、向栅极驱动器发送的垂直起始信号、及向源极驱动器发送的数据信号等。 栅极驱动器在处理器发送的垂直起始信号的控制下，依次控制液晶面板各行TFT导通，从而使源极驱动器在TFT导通时，对液晶显示面板各行的存储电容进行至少两次充电。
本实施例提供的液晶显示设备，在显示帧画面时，各部分结构的功能和详细处理流程可参照上述实施例一至实施例四提供的液晶显示处理方法的详细描述，此处不再赘述。
本实施例提供的液晶显示设备，对每一帧画面，时序控制器都会先向栅极驱动器发送该帧画面对应的N个STV信号，栅极驱动器根据N个STV信号，依次控制液晶面板各行的TFT预导通N次，之后在第M行第一次预导通结束前，向栅极驱动器发送该帧画面的第N+1个STV信号，栅极驱动器根据第N+1个STV信号，依次控制液晶面板各行的TFT导通第N+1次，以便使源极驱动器根据该帧画面对应的数据信号对各行的存储电容进行最终充电，同时对TFT预导通的各行的存储电容进行预充电，本液晶显示处理方法通过在一帧画面显示前，对屏幕中所有行的存储电容进行至少两次充电过程，延长了对液晶面板各行的存储电容的充电时间，从而使各行存储电容两端的电量尽量满足帧画面显示的需求，提高了液晶显示器的画质。
本领域普通技术人员可以理解：实现上述方法实施例的全部或部分步骤可以通过程序指令相关的硬件来完成，前述的程序可以存储于一计算机可读取存储介质中，该程序在执行时，执行包括上述方法实施例的步骤；而前述的存储介质包括：ROM、RAM、磁碟或者光盘等各种可以存储程序代码的介质。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (19)

  1. 一种液晶显示处理方法，其特征在于，包括：
    时序控制器向栅极驱动器依次发送帧画面对应的N个垂直起始信号，以使所述栅极驱动器根据所述N个垂直起始信号，依次控制液晶面板各行的薄膜晶体管TFT预导通N次，源极驱动器在各行TFT预导通时，对各行的存储电容进行预充电；
    所述时序控制器在液晶面板第M行的TFT第一次预导通结束前，向所述栅极驱动器发送所述帧画面对应的第N+1个垂直起始信号，以使所述栅极驱动器根据所述第N+1垂直起始信号，控制液晶面板各行的TFT依次导通第N+1次，以便源极驱动器在各行TFT第N+1次导通时，对各行的存储电容进行最终充电，其中，N和M为大于或等于1，且小于液晶面板总行数的正整数。
  2. 根据权利要求1所述的方法，其特征在于，所述时序控制器向栅极驱动器依次发送帧画面对应的N个垂直起始信号之后，还包括：
    所述时序控制器向栅极驱动器依次发送所述帧画面对应的N个扫描驱动输出使能信号，以使所述栅极驱动器根据所述N个扫描驱动输出使能信号，控制所述液晶面板各行TFT预导通N次的时间；
    向所述栅极驱动器发送所述帧画面对应的第N+1个垂直起始信号之后，还包括：
    所述时序控制器向栅极驱动器发送所述帧画面对应的第N+1个扫描驱动输出使能信号，以使所述栅极驱动器根据所述第N+1个扫描驱动输出使能信号，控制所述液晶面板各行TFT第N+1次导通的时间。
  3. 根据权利要求2所述的方法，其特征在于，所述时序控制器向栅极驱动器依次发送所述帧画面对应的N个扫描驱动输出使能信号之前，还包括：
    所述时序控制器根据所述帧画面的灰阶大小确定所述N个扫描驱动输出使能信号的宽度；
    所述时序控制器向栅极驱动器发送所述帧画面对应的第N+1个扫描驱动输出使能信号之前，还包括：
    所述时序控制器根据所述帧画面的灰阶大小确定所述第N+1个扫描驱动输出使能信号的宽度。
  4. 根据权利要求1-3任一所述的方法，其特征在于，所述时序控制器在液晶面板第M行的TFT第一次预导通结束前，向所述栅极驱动器发送所述帧画面对应的第N+1个垂直起始信号，包括：
    所述时序控制器确定在发送第一个垂直起始信号后，发送的垂直时钟脉冲的个数；
    在所述垂直时钟脉冲个数为M时，所述时序控制器向所述栅极驱动器发送所述帧画面对应的第N+1个垂直起始信号。
  5. 根据权利要求1-3任一所述的方法，其特征在于，所述时序控制器向栅极驱动器依次发送帧画面对应的N个垂直起始信号之后，还包括：
    所述时序控制器向源极驱动器发送所述帧画面对应的预处理数据信号，以使所述源极驱动器根据所述预处理数据信号，对所述液晶面板前M行的存储电容进行预充电。
  6. 如权利要求1-3任一所述的方法，其特征在于，时序控制器向栅极驱动器发送第N+1个STV信号时，还同时向源极驱动器同步该帧画面对应的数据信号；
    在第M+1行及M+1行之后的各行TFT预导通时，源极驱动器根据与其同时导通行的数据信号，对各行上的存储电容进行预充电。
  7. 根据权利要求5所述的方法，其特征在于，所述时序控制器向源极驱动器依次发送所述帧画面对应的预处理数据信号之前，还包括：
    所述时序控制器根据所述帧画面的灰阶大小确定所述预处理数据信号。
  8. 根据权利要求5所述的方法，其特征在于，M小于所述液晶面板总行数的1/3。
  9. 根据权利要求7或8所述的方法，其特征在于，所述液晶面板的极性 反转方式为行极性反转；
    所述M为偶数。
  10. 一种液晶显示时序控制装置，其特征在于，包括：
    第一发送模块，用于向栅极驱动器依次发送帧画面对应的N个垂直起始信号，以使所述栅极驱动器根据所述N个垂直起始信号，依次控制液晶面板各行的薄膜晶体管TFT预导通N次，以便源极驱动器在各行TFT预导通时，对各行的存储电容进行预充电；
    第二发送模块，用于在液晶面板第M行的TFT第一次预导通结束前，向所述栅极驱动器发送所述帧画面对应的N+1个垂直起始信号，以使所述栅极驱动器根据所述第N+1垂直起始信号，控制液晶面板各行的TFT依次导通第N+1次，以便源极驱动器在各行TFT第N+1次导通时，对各行的存储电容进行最终充电，其中，N和M为大于或等于1，且小于液晶面板总行数的正整数。
  11. 根据权利要求10所述的装置，其特征在于，还包括：
    第三发送模块，用于向栅极驱动器依次发送所述帧画面对应的N个扫描驱动输出使能信号，以使所述栅极驱动器根据所述N个扫描驱动输出使能信号，控制所述液晶面板各行TFT预导通N次的时间；
    所述第三发送模块，还用于向栅极驱动器发送所述帧画面对应的第N+1个扫描驱动输出使能信号，以使所述栅极驱动器根据所述第N+1个扫描驱动输出使能信号，控制所述液晶面板各行TFT第N+1次导通的时间
  12. 根据权利要求11所述的装置，其特征在于，还包括：
    确定模块，用于根据所述帧画面的灰阶大小确定所述N个扫描驱动输出使能信号的宽度；
    所述确定模块，还用于根据所述帧画面的灰阶大小确定所述第N+1个扫描驱动输出使能信号的宽度。
  13. 根据权利要求10-12任一所述的装置，其特征在于，所述第二发送模块，具体用于：
    确定在发送第一个垂直起始信号后，发送的垂直时钟脉冲的个数；
    在所述垂直时钟脉冲个数为M时，所述时序控制器向所述栅极驱动器发送所述帧画面对应的第N+1个垂直起始信号。
  14. 根据权利要求10-12任一所述的装置，其特征在于，还包括：
    第四发送模块，用于向源极驱动器发送所述帧画面对应的预处理数据信号，以使所述源极驱动器根据所述预处理数据信号，对所述液晶面板前M行的存储电容进行预充电。
  15. 如权利要求10-12任一所述的装置，其特征在于，还包括：
    第五发送模块，用于向栅极驱动器发送第N+1个STV信号时，还同时向源极驱动器同步该帧画面对应的数据信号，以使在第M+1行及M+1行之后的各行TFT预导通时，源极驱动器根据与其同时导通行的数据信号，对各行上的存储电容进行预充电。
  16. 根据权利要求14所述的装置，其特征在于，
    所述确定模块，还用于所述时序控制器根据所述帧画面的灰阶大小确定所述预处理数据信号。
  17. 根据权利要求14所述的装置，其特征在于，M小于所述液晶面板总行数的1/3。
  18. 根据权利要求16或17所述的装置，其特征在于，所述液晶面板的极性反转方式为行极性反转；
    所述M为偶数。
  19. 一种液晶显示设备，其特征在于，包括：处理器、存储器、栅极驱动器、源极驱动器、液晶面板各行的薄膜晶体管(Thin Film Transistor，简称TFT)和存储电容；
    存储器，用于存储程序；
    处理器，用于执行所述存储器中程序，向栅极驱动器依次发送帧画面对应的N个垂直起始信号，并在液晶面板第M行的TFT第一次预导通结束前，向所述栅极驱动器发送所述帧画面对应的第N+1个垂直起始信号；
    所述栅极驱动器，用于根据所述N个垂直起始信号，依次控制液晶面板各行的TFT预导通N次；并根据所述第N+1垂直起始信号，控制液晶面板各行的TFT依次导通第N+1次；
    所述源极驱动器，用于在各行TFT第N+1次导通时，对各行的存储电容进行最终充电，同时在各行TFT预导通时，对各行的存储电容进行预充电，其中，N和M为大于或等于1，且小于液晶面板总行数的正整数。
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