WO2017001890A1

WO2017001890A1 - Method for converting gerber data to finite element model for predicting printed circuit board warpage

Info

Publication number: WO2017001890A1
Application number: PCT/IB2015/054882
Authority: WO
Inventors: Pedro Daniel DA SILVA RAMÔA; José Luis DE CARVALHO MARTINS ALVES; José Pedro SANTOS SILVA DELGADO
Original assignee: Bosch Car Multimedia Portugal, S.A.; Universidade Do Minho
Priority date: 2015-06-29
Filing date: 2015-06-29
Publication date: 2017-01-05

Abstract

Method for converting a printed circuit board, PCB, gerber data to a finite element model, comprising: generating in-plane with the PCB a 2D mesh of cells; generating a stack of one or more finite elements from each 2D mesh cell, each said finite element corresponding to one or more PCB layers; calculating the geometric and material features of each finite element of each said stack from the PCB image description of the PCB layers delimited by the outline of the respective 2D mesh cell; outputting a finite element model comprising the nodes and connections of the calculated finite elements; wherein the 2D mesh of cells is delimited by the PCB shape from the PCB image description; wherein said PCB shape comprises the border of the PCB and the hole or holes of the PCB, if present; such that all finite element nodes are within the PCB shape.

Description

D E S C R I P T I O N

METHOD FOR CONVERTING GERBER DATA TO FINITE ELEMENT MODEL FOR PREDICTING PRINTED CIRCUIT BOARD WARPAGE

Technical field

[0001] The present disclosure relates to a method to convert a Printed Circuit Board, PCB, image description, in particular a PCB vector image file (e.g. Gerber file), to a finite element model (e.g. a computer-aided engineering, CAE, file), in particular a finite element model of thermo-mechanical loading. The finite element model data can be used for predicting deformation (e.g. warpage), thus being useful for preventing warpage in a PCB.

Background Art

[0002] The complex copper distribution and multi-layer structure of any real PCB (Printed Circuit Boards) leads to the occurrence of warpage. This situation occurs mainly due to the different thermomechanical behaviour of the two materials of a PCB (copper and FR4 - i.e. conductive and non-conductive layer materials of a PCB), and particularly due to their unbalanced elastic properties and CTEs (coefficient of thermal expansion), as well asymmetric behaviour resulting from the copper distribution within each layer of copper when subjected to arbitrary heating thermal loadings. Such thermal loadings can occur either on the PCB manufacturing process itself or during the assembling and soldering of the components. These conditions enhance the appearance of malfunctions and manufacturing defects.

[0003] Copper is the preferred material for embodying a conductive layer of a PCB. A copper PCB layer is mentioned interchangeably as a conductive PCB layer. [0004] FR4 (or FR-4) is an example of a non-conductive layer providing stiffness to the PCB and separating the layers of copper. FR4 usually refers to a grade designation assigned to glass-reinforced epoxy laminate sheets used in printed circuit boards (PCB). FR4 is an example of a composite material layer composed of woven fibreglass cloth with an epoxy resin binder.

[0005] FR4 is a preferred material for embodying a support dielectric layer of a PCB. A FR4 layer is mentioned interchangeably as a dielectric PCB layer.

[0006] Warpage causes a piece or PCB to bend or twist, changing its size, contours and, mainly, local curvatures. Some of these deformation patterns have their origin on the thermos-mechanical material properties: some polymers and resins are more prone to this type of events, particularly the semicrystalline ones, as they display an anisotropic behaviour. However, since these properties are inherent to each material, the problem can only be minimized by modifying the copper distribution throughout the layers of the multi-layered PCB design.

[0007] Currently, during the designing process, PCB designers do not have a direct and precise method to predict and/or quantify the warpage phenomenon on the PCBs during and afterwards the soldering and manufacturing processes. The PCB designers do not have the required knowledge and expertise on finite elements to build a finite element model as input to the CAE (Computer Aided Engineering) software. Similarly, there is no tool capable of automatically translating/converting the information generated from the design software, usually in the gerber standard file, into a finite element model that can be used by numerical simulation tools, or it may be required a too long pre-processing step and special expertise on finite elements. Thus, warpage can only usually be known/measured once the manufacturing process is over, what clearly shows that a validation step is missing during the development of the PCBs, and can lead to higher costs and development delays.

[0008] Document US 7139678 B2 describes predicting a deformation of a board by dividing the board into a plurality of areas based on wiring information on the board; and predicting by grasping a wiring pattern of an area macroscopically, calculating an equivalent physical property value equivalent to a modulus of longitudinal elasticity and a coefficient of thermal expansion by a finite element method, and predicting the deformation of the board based on the equivalent physical property value calculated for each of the areas divided by the board dividing unit.

[0009] Document US 7139678 B2 describes calculating equivalent physical properties for each PCB layer determined by whether the layer has directionality or not, or a layer which is "unrelated" to warpage - for the layers with directionality, it calculates an equivalent physical property value in each wiring direction for calculating the equivalent physical property values. It is a complex procedure as it is necessary to execute simulations for all combinations of: wiring pattern densities, moduli of longitudinal elasticity and coefficients of thermal expansion. It is stressed that all wiring directions are calculated. The speed and output precision of the overall method has shortcomings. Finally, document US 7139678 B2 does not seem to disclose examples for the "unrelated" layer, just that it is a layer not directly contributing to warp of an entire board.

[0010] In conclusion, there are several methods already known aiming to improve the PCB design, but none of them is suited to be integrated in the designing pipeline and to be used directly by the PCB designer.

[0011] These facts are disclosed in order to illustrate the technical problem addressed by the present disclosure.

General Description

[0012] The present disclosure relates to a method to prevent the warpage phenomenon in Printed Circuit Boards, by connecting automatically (and user-free) the gerber standard file data (which defines the PCB electric artworks) to a CAE model (a finite element model). More particularly, relates to a method to evaluate and estimate the PCB design in a quality and quantity manner, predicting a 3D representation of the PCB under any thermo-mechanical loading. [0013] The present disclosure comprises in a straightforward method to predict the warpage on an arbitrarily complex PCB. With this disclosure, it is possible to predict, and thus minimize/optimize, the problems appearing during the components soldering due to the warpage phenomenon. This method fills the existing gap in the development of PCBs. Presently, the warpage measurement is made by producing prototypes and running experimental tests, which replicate the manufacturing process. The methods of the disclosure have as input the gerber files, i.e. the standard files generated by any commercial PCB development software (the same files that are sent to the PCB manufacturer and contain all the detailed information about the copper electric artworks, together with all dimensions and specifications). These files preferably comply with the RS-274X standard. Apart from the gerber files, this method/disclosure does not require any other specific information and it will not require any special expertise or skills from the user to work with a finite element solver. The resultant output is a finite element model which can then be used to carry out the numerical simulations with a finite elements solver such as Ansys(tm), Abaqus(tn) or any other adequate FEM solver.

[0014] The process according to embodiments of the disclosure can be divided into three parts:

[0015] Input Information: Gerber files are lines of code that follows preferably the RS- 274X standard containing the coordinates describing the geometry of all the elements of a PCB (macro geometry, number of layers of copper and specificities and specifications of each layer of copper). The necessary information regarding the PCBs (Printed Circuit Boards) exists in the gerber files that are generated by any commercial software for development/designing of PCBs, and allows the manufacturer to have access to all the information required for the manufacture, such as: dimensions, holes, copper circuits, number of layers, among other important information.

[0016] Processing: at this stage, the methods of the disclosure will access the information enclosed in the gerber files and, after that, it will convert the gerber commands contained in those files into graphic binary structures (bitmaps). Through these bitmaps it will be generated a finite element mesh enhanced with the geometric properties of each finite element of copper such as: area fraction of copper, inertia tensor and centre of mass. The resulting and necessary data will be exported to a text file in order to run the finite elements simulation.

[0017] Information output: From the previous processing step all the necessary information for the numerical simulation will be provided in the form of: a finite element mesh (nodes, and connectivity), material properties, boundary conditions, element properties and simulation conditions, along with specific data (area fraction of copper, inertia tensor describing the layers of copper). This information is exported in a format compatible with the CAE tools such as Abaqus, Ansys or any other adequate FEM solver. Starting from these data, the CAE tools will be able to determine the displacement fields of PCB under analysis, and thus estimate the amount of warpage associated with the prescribed thermo-mechanical loadings.

[0018] The above described procedure has two main processing focus.

[0019] The first one (1st step) is reading and processing the information of the gerber files. These information is discretized and temporarily stored in high-resolution bitmaps, i.e. bitmaps are generated based on the information defining the geometric features on each layer of copper existent on the PCB. A bitmap representing the layers of FR4 (a non-conductive layer providing stiffness to the PCB and separating the layers of copper) will also be created.

[0020] The second step is the finite element mesh generation, which will be a 3D representation of the real macroscopic geometry of the PCB defined by the gerber file, i.e. overall dimensions, channels and holes, and the geometric specificities associated with the copper distribution inside each finite element describing the layers of copper. So, the finite element mesh created by this method consists of the Cartesian nodal coordinates of all nodes defining the PCB geometry, the connectivity between these nodes, as well the geometric and material features associated to each finite element. The mesh information will be preferably exported in a format compatible with a selected external CAE software. [0021] The FE mesh refinement can be adjusted by the user, between a more refined or coarser FE mesh. By default, an in-plane FE size of substantially 50% of the PCB thickness is proposed, but normally this can be 10 - 200% of the PCT thickness, in particular 25% - 100% of PCB thickness.

[0022] The algorithm is prepared to write out finite element meshes based on the following FE types: (i) full 3D finite elements, using 3D tri-linear 8-node hexahedra elements to model both FR4 and copper layers; (ii) hybrid 3D+2D finite elements, using 3D tri-linear 8-node hexahedra elements to model the FR4 layers and 2D bi-linear 4- node quadrilateral membrane elements to model the copper layers; (iii) thick-shell 2.5D finite elements, i.e. using only one layer of finite elements through-thickness to describe, in a single finite element (3D tri-linear 8-node hexahedron) all layers of both FR4 and copper; and (iV) 2D shell finite elements, using 2D bi-linear 4-node quadrilateral shell elements to model with a single shell element all layers of both FR4 and copper.

[0023] The specific data associated to each finite element describing the copper layers aims to characterize the distribution of copper inside of each finite element. These information will be used latter on a homogenization technique in order to take into account the specificities of copper distribution inside each finite element. At the element level, the following data will be computed and outputted for each finite element describing the layers of copper: (i) area fraction of copper; (ii) number of independent islands of copper inside of the finite element; (iii) inertia tensor of the largest domain of copper inside of the finite element; (iv) centre of mass of the islands of copper; (v) thickness of the layer of copper.

[0024] The inertia tensor is computed in a local frame centred on the centre of mass, with axes parallel to the axes of the global Cartesian frame. Known the inertia tensor, their eigenvectors and eigenvalues are computed: the eigenvectors determine the orientation of the copper area fraction within the finite element, and the eigenvalues (the ratio of) allow to estimate the level of anisotropy of the copper distribution within the finite element. Both eigenvectors and eigenvalues of the inertia tensor play a key role in the identification of the homogenized thermo-mechanical properties of each finite element.

[0025] The inertia tensor is computed taking into account only for the largest island of copper inside a given finite element. This is a relevant preferred embodiment for the disclosed method, because it allows to capture more accurately the real orientation of the copper inside of a given finite element.

[0026] It is disclosed a method for converting a printed circuit board, PCB, image description to a finite element model, said PCB comprising one or more conductive layers and one or more dielectric layers for insulation and support of the conductive layers, comprising the steps of:

generating in-plane with the PCB a 2D mesh of cells;

generating a stack of one or more finite elements from each 2D mesh cell, each said finite element corresponding to one or more PCB layers;

calculating the geometric and material features of each finite element of each said stack from the PCB image description of the PCB layers delimited by the outline of the respective 2D mesh cell;

outputting a finite element model comprising the nodes and connections of the calculated finite elements;

characterized in that

the 2D mesh of cells is delimited by the PCB shape from the PCB image description;

wherein said PCB shape comprises the border of the PCB and the hole or holes of the PCB, if present;

such that all finite element nodes are within the PCB shape.

[0027] A PCB hole can be a full hole (e.g. drilled) or a partial hole (e.g. a slot).

[0028] In an embodiment, each finite element is calculated having an inertia tensor defined by the largest conductive independent area of each corresponding conductive layer or layers delimited by the outline of the respective 2D mesh cell. [0029] Method according to any of the previous claims wherein the generated in- plane 2D mesh of cells is a node grid of squares or rectangles, which have been deformed or cut until the 2D mesh of cells is delimited by the PCB shape, such that all finite element nodes will be within the PCB shape.

[0030] An embodiment comprises, for deforming or splitting the square or rectangle grid cells, the step of:

if all four nodes of the grid cell are located outside the PCB shape, deleting the cell and all four nodes;

if one node of the grid cell is located outside the PCB shape, deleting the outside node and splitting the cell into three contiguous rectangular cells within the PCB shape and discarding the part of the original cell located outside the PCB shape; if two nodes of the grid cell are located outside the PCB shape, deleting the outside nodes and splitting the cell into a non-rectangular quadrilateral cell within the PCB shape and discarding the part of the original cell located outside the PCB shape;

if three nodes of the grid cell are located outside the PCB shape, deleting the outside nodes and splitting the cell into a triangular cell within the PCB shape and discarding the part of the original cell located outside the PCB shape.

[0031] An embodiment comprises, for deleting finite element nodes located outside the PCB shape, the following steps, for each node located outside the PCB shape:

calculating the distance between the node located outside the PCB shape and the nearest new node to be created by the splitting of the cell;

if the distance is below a predefined threshold distance, then the node located outside the PCB shape is moved to the position of the nearest new node that was to be created and takes its place;

if the distance is above a predefined threshold distance, the node located outside the PCB shape is deleted and a new node is created for said splitting of the cell.

[0032] In an embodiment, the predefined threshold distance is a percentage of the grid spacing, in particular substantially 20% of the grid spacing. [0033] In an embodiment, the stack is a stack of one finite element and said finite element is a bi-linear 4-node quadrilateral element calculated for all layers of the PCB delimited by the respective 2D mesh cell.

[0034] In an embodiment, the stack is a stack of one finite element and said finite element is a tri-linear 8-node hexahedron element calculated for all layers of the PCB delimited by the respective 2D mesh cell.

[0035] In an embodiment, the stack is a stack of:

a tri-linear 8-node hexahedron finite element calculated for each dielectric layer, and

a bi-linear 4-node quadrilateral element calculated for each conductive layer.

[0036] In an embodiment, the stack is a stack of:

a tri-linear 8-node hexahedron finite element calculated for each conductive layer.

[0037] In an embodiment, the 2D mesh cells have a dimension of 10 - 200% of the PCT thickness, in particular 25% - 100% of PCB thickness, further in particular substantially 50% of the PCB thickness.

[0038] The dimension of a cell can be defined as being the size of the largest line joining two periphery points of the cell. For example, in a rectangle it is the size of the larger side.

[0039] In an embodiment, the inputs of the calculation of each finite element, from the PCB image description, for the corresponding conductive layer or layers delimited by the outline of the respective 2D mesh cell, comprise:

the area fraction of conductive areas;

the number of independent conductive areas;

the centre of mass of the conductive areas; and/or

the thickness of the conductive layer or layers. [0040] In an embodiment, the inputs of the calculation of each finite element, comprise the eigenvector and eigenvalues of the respective inertia tensor.

[0041] An embodiment comprises the previous step of discretising the PCB image description into image bitmaps of each conductive layer and of each dielectric layer.

[0042] In an embodiment, a hole of the PCB is a PCB slot, a PCB cut-out, a PCB drilled hole, a PCB channel, a PCB recess, a PCB notch or a PCB rip.

[0043] In an embodiment, the PCB image description is a structured data record.

[0044] In an embodiment, the PCB image description is a gerber file.

[0045] In an embodiment, each conductive layer is a copper PCB layer.

[0046] In an embodiment, each dielectric layer is a FR4 PCB layer.

[0047] It is also described a non-transitory storage media including program instructions for implementing a converter of a printed circuit board, PCB, image description to a finite element model, the program instructions including instructions executable to carry out any of the above methods.

[0048] It is also described a converter of a printed circuit board, PCB, image description to a finite element model, comprising a data processor having a non- transitory storage media including program instructions executable by the data processor to carry out any of the above methods.

Brief Description of the Drawings

[0049] The following figures provide preferred embodiments for illustrating the description and should not be seen as limiting the scope of invention.

[0050] Figure 1: Schematic representation of an embodiment of the main data pipeline of the disclosed algorithm.

[0051] Figure 2: Schematic representation of an embodiment of one copper layer of a PCB. [0052] Figure 3: Schematic representation of an embodiment of the zoom of a copper Layer in order to show the accuracy of shape replication.

[0053] Figure 4: Schematic representation of an embodiment of the FR4 Layer before applying the flooding algorithm.

[0054] Figure 5: Schematic representation of an embodiment of the FR4 Layer after applying the flooding algorithm.

[0055] Figure 6: Schematic representation of an embodiment of the Implemented flood fill four-way stack-based recursive algorithm.

[0056] Figure 7: Schematic representation of an embodiment of the four-nodes stencil: All original nodes are in the same material.

[0057] Figure 8: Schematic representation of an embodiment of the one-node stencil: Three original nodes in FR4, one in void.

[0058] Figure 9: Schematic representation of an embodiment of the two-nodes stencil: Two original nodes for each material.

[0059] Figure 10: Schematic representation of an embodiment of the three-nodes stencil: One original node in FR4, three in void.

[0060] Figure 11: Schematic representation of an embodiment of the nodes and cutting points initial placement.

[0061] Figure 12: Schematic representation of an embodiment of the final position of nodes and cutting points.

[0062] Figure 13: Schematic representation of an embodiment of the final mesh with nodes connected.

[0063] Figure 14: Schematic representation of an embodiment of the checking nodes algorithm.

[0064] Figure 15: Schematic representation of an embodiment of the 3D model using solely 3D Solid elements. [0065] Figure 16: Schematic representation of an embodiment of the 3D model using 3D Thick-Shell elements (multi-layer).

[0066] Figure 17: Schematic representation of an embodiment of the 3D model using 2D Shell Element (multi-layer).

[0067] Figure 18: Schematic representation of an embodiment of the 3D model using 3D Solid elements for FR4 layers and 2D membrane elements for copper layers.

[0068] Figure 19: Schematic representation of an embodiment of the isometric view of a 3D model of a PCB.

[0069] Figure 20: Schematic representation of an embodiment of the mesh applied to copper layers.

[0070] Figure 21: Schematic representation of an example of a finite element with one copper trace.

[0071] Figure 22: Schematic representation of an embodiment of an example of a finite element with one copper trace with centre of mass and eigenvectors.

Detailed Description

[0072] The disclosed methods can be divided in four main processes as shown in Fig. 1. The first process is reading gerber files, sort and store the information in different type of classes (or data structures). The second process is converting the acquired information from millimetres/inches into graphic structures of pixels (Bitmaps). The third process uses the base layer of the PCB (FR4 Layer) to create a 2D mesh. The final process consists in creating the 3D model of the PCB from the 2D mesh along with copper element properties, such as: area fraction of copper, centre of mass and the inertia tensor.

[0073] The processing stage can be divided into two steps, data acquisition and image creation. In data acquisition, the information in gerber files is read, organized and stored into different types of structures (or classes) depending on the aperture shape. If aperture is a standard aperture (line or pad) can be stored in a Linear Interpolation structure, Pad structure or Circular Interpolation structure according to the type of element read from Gerber file.

[0074] After acquisition of each layer, the information is sorted, converted into pixels and printed. The bitmap creation is divided primarily by layer (or gerber file) and then divided by shape. This approach allows the creation of simple cycles of same function and also prioritizing the access to the same class instead of jumping between classes, and therefore saving processing time. The processing order of drawing the bitmaps are: Linear Interpolation, Circular Interpolation, Pad and Irregular Shapes. The results are illustrated in Fig. 2 and Fig. 3. The first image shows the entire copper layer of a real PCB. The Fig. 3 shows with more detail the geometry of a printed circuit and the accuracy of shape replication given by the disclosed methods.

[0075] Parallel to the creation of copper layers, the FR4 layer is also created. This second process is entirely independent from the first (creation of copper layers). The FR4 layer is the dielectric layer made by fibre glass and epoxy resin inserted between the copper layers, isolating electrically the layers of copper. The FR4 also represents the main physical format of the PCB. For the process of creating the FR4 layer, it is needed the milling and drilling files. These files define the drilling holes and milling slots that cross the entire PCB throughout all layers. For the creations of the FR4 layer, three types of instructions are used: Linear interpolation, Circular interpolation for milling slots and XY coordinates for drilling holes. The drawing function of this layer is similar to the function of the drawing function of copper layers. However FR4 Layer creation process has one more step: after milling and drilling tools, several small islands of material remains on bitmap as shown in Fig. 4 where the dark colour represents FR material and the black colour represents the drilled or cut areas. In order to remove the islands of (lost) material, a flooding technique is used, more specifically, the four-way stack-based recursive algorithm (Fig. 6). The Fig. 5 presents an example of a FR4 Layer after application of flooding technique. The lighter colour represents saved FR4 material and the black colour represents void area (or without material). Flooding technique successfully eliminates the material islands thus remaining the true geometry of the real PCB.

[0076] The first step of mesh creation consists in collecting the PCB dimensions: width, height and thickness. From these values the algorithm will determine the default size and number of elements and nodes across the board. Equation 1 and Equation 2 shows how PCB dimensions can define the number of elements as typical example. The number of elements in one row (E_x) is given by two times the board width divided by its thickness (Equation 1). The number of elements in one column (E_y) is given by two times the board height divided by its thickness (Equation 2). The Equation 3 and Equation 4 retrieve the number of nodes in both axis. The total number of nodes and elements of the mesh is given by Equation 5 and Equation 6. width

E_Y = x 2 heiqht

E_v =—— x 2

n_y = E_y + 1

E total— E_x X Ey

ntotal— ⁿx ^{x n}y

[0077] A regular square lattice is then superposed to the bitmap representing the layer of FR4, in order to generate the 2D mesh. Initially, all nodes are placed at same distance from neighbour ones in the XY plane. After placing all nodes, subsequent step is to compute all material transitions between nodes (or cutting points), since it is not possible to have nodes/elements in the void area according to the present disclosure. To correct the nodes/elements in void area four pre-defined stencils are applied to the mesh.

[0078] The stencil of Fig. 7 is used when all nodes are in the same material : if all four nodes are located in FR4, the element stays unchanged; if all four nodes are located in the void area both the nodes and the element are deleted. An element with three nodes in FR4 and one node in void is modified by applying the stencil of Fig. 8, this stencil delete the old element and create three new degenerated elements (as shown in Fig. 8), two elements are composed by two nodes and a cutting point (dark point) and the third element has one node and two cutting points. The third stencil is applied in elements that have two nodes in FR4 and two in void, the result is still a quadrilateral element but slightly distorted (Fig. 9), defined by two nodes and two cutting points. Fig. 10 presents a stencil applied to elements with three nodes in void, the result is a degenerated element defined by one node and two cutting points.

[0079] Another aspect is to how to eliminate lonely nodes located in void in order to have a mesh that respects the geometry of the PCB. An algorithm to solve this problem was developed and presented in Fig. 11. If a node is located in void has to be removed or moved according to its distance to the closest cutting point. If the distance to the closest cutting point is superior to a certain percentage (user-adjustable) of the distance between nodes, then the node is deleted and a new one is created in the cutting point. If the distance smaller than the prescribed one, the node will be moved to the cutting point. For instance, the node six of Fig. 11 has two cutting points with a distance smaller than the prescribed value, so the node will be moved to the closest cutting point. The downward and upward cutting points will be removed because the node number six is no longer in the void. The node seven does not have any cutting point nearby, so the node will be eliminated and replaced by the two cutting points, the first one between node seven and three and the second one between node seven and eight. Since the node seven no longer exists, the node eleven will be moved to the nearest cutting point in order to get a better replication of the hole presented in the Fig. 11. In Fig. 12 has the result of the implementation of the algorithm presented in the Fig. 14. The final mesh with nodes connected is displayed in Fig. 13.

[0080] The disclosed methods will be able to create different 3D models as presented in Fig. 15, Fig. 16, Fig. 17, Fig. 18. The first possible model is achieved by using 3D solid elements for every layer of PCB as shown in Fig. 15. In Fig. 16 the model is constructed using a single layer of elements of thick-shell 3D elements, in which are layered and stacked the different materials defining the model along the Z axis. The Fig. 17 presents a similar approach to the previous model, the sole difference lies in using 2D shell elements instead of a 3D thick shell elements. The last representative model (Fig. 18) of a PCB is made by combining 3D solid elements for FR4 with 2D membrane elements for the copper layers.

[0081] By applying the mesh to copper layers (Fig. 20), it is possible to see that most of copper elements are not fully filled with copper, but with a mixture of copper (light colour) and epoxy resin (black colour). In order to have a more realistic simulation is preferably necessary to compute and export to the solver (e.g.Ansys(tm), Abaqus(tm) or any other suitable FEM solver) more information than just the main material or the area fraction. The information will involve:

- Percentage of area copper in each element;

- Coordinates of the centre of mass of copper islands/bodies;

- Number of copper bodies in element.

- Inertia tensor of the largest copper body (To calculate eigenvalues and eigenvectors);

[0082] The information only covers X and Y axes, because the problem resides in the XY plane. Once known how copper is distributed inside each element in the XY plane the distribution will be the same through-thickness of the copper layer under analysis.

[0083] The percentage of copper contained in an element is calculated by dividing the number of pixels of copper (i.e. lighter colour in fig. 20 or 21) by the total number of pixels of the element. The centre of mass coordinates are given by Equation 7 and Equation 8. ∑i=l ^mi^xi (7)

M

∑i=i ^m yi

Vcm ^~ (8)

M

[0084] The angular moment of a given body is given by Equation 9. The angular moment is demonstrated in a matrix form. As stated before the problem resides in the XY plane, the l_xx, l_xy and I_yy are the moments of inertia needed to identify the main direction of copper material. The moments of inertia are shown in Equation 10, Equation 11 and E uation 12.

N

%i %cm) (10)

1=1

N

Ιχγ— lyx— ∑(^χί - ^xcm) {yi - y_cm) m,i (12)

1 =1

[0085] The moments of inertia per se do not give the direction of the material; it is necessary to calculate the direction of the vectors and the intensity of those vectors: it is necessary to calculate eigenvalues and eigenvectors of the inertia tensor. Solving the characteristic Equation 13 are retrieved two values, those values are the eigenvalues of the matrix. The eigenvectors are calculated by solving the system of Equation 14.

[0086] Using the example of Fig. 21 and applying all equations from Equation 7 to Equation 14 to that element the retrieved information is shown in Fig. 22. xx - λ I xy

p(X) = det (13)

/ y. x / y. y - λ

[0087] The disclosed method embodiments allows a simplified yet precise calculation, that enables higher precision over the prior art while providing the same or improved computer running times. In particular, by creating a mesh avoiding nodes located the PCB shape and by using only the inertia tensor defined by the largest conductive independent area within each finite element, precision is improved and execution time is reduced. It was surprisingly found that any element or node located outside the PCB shape, even if only by a small margin, introduces large errors in to the finite element model. This is especially true for holes or slots (partial holes) of the PCB. It was also surprisingly found that only the largest conductive independent area needs to be taken into account when calculating the direction connected with the inertia tensor for obtaining a precise finite element model.

[0088] The term "comprising" whenever used in this document is intended to indicate the presence of stated features, integers, steps, components, but not to preclude the presence or addition of one or more other features, integers, steps, components or groups thereof.

[0089] Flow diagrams of particular embodiments of the presently disclosed methods are depicted in figures. The flow diagrams do not depict any particular means, rather the flow diagrams illustrate the functional information one of ordinary skill in the art requires to perform said methods required in accordance with the present disclosure.

[0090] It will be appreciated by those of ordinary skill in the art that unless otherwise indicated herein, the particular sequence of steps described is illustrative only and can be varied without departing from the disclosure. Thus, unless otherwise stated the steps described are so unordered meaning that, when possible, the steps can be performed in any convenient or desirable order. [0091] It is to be appreciated that certain embodiments of the disclosure as described herein may be incorporated as code (e.g., a software algorithm or program) residing in firmware and/or on computer useable medium having control logic for enabling execution on a computer system having a computer processor, such as any of the servers described herein. Such a computer system typically includes memory storage configured to provide output from execution of the code which configures a processor in accordance with the execution. The code can be arranged as firmware or software, and can be organized as a set of modules, including the various modules and algorithms described herein, such as discrete code modules, function calls, procedure calls or objects in an object-oriented programming environment. If implemented using modules, the code can comprise a single module or a plurality of modules that operate in cooperation with one another to configure the machine in which it is executed to perform the associated functions, as described herein.

[0092] The disclosure should not be seen in any way restricted to the embodiments described and a person with ordinary skill in the art will foresee many possibilities to modifications thereof.

[0093] The above described embodiments are combinable.

[0094] The following claims further set out particular embodiments of the disclosure.

Claims

C L A I M S

1. Method for converting a printed circuit board, PCB, image description to a finite element model, said PCB comprising one or more conductive layers and one or more dielectric layers for insulation and support of the conductive layers, comprising the steps of:

generating in-plane with the PCB a 2D mesh of cells;

characterized in that

such that all finite element nodes are within the PCB shape.

2. Method according to claim 1 wherein each finite element is calculated having an inertia tensor defined by the largest conductive independent area of each corresponding conductive layer or layers delimited by the outline of the respective 2D mesh cell.

3. Method according to any of the previous claims wherein the generated in-plane 2D mesh of cells is a node grid of squares or rectangles, which have been deformed or cut until the 2D mesh of cells is delimited by the PCB shape, such that all finite element nodes will be within the PCB shape.

Method according to the previous claim comprising, for deforming or splitting the square or rectangle grid cells, the step of:

Method according to the previous claim, further comprising for deleting finite element nodes located outside the PCB shape, the following steps, for each node located outside the PCB shape:

6. Method according to the previous claim, wherein the predefined threshold distance is a percentage of the grid spacing, in particular substantially 20% of the grid spacing.

7. Method according to any of the claims 1 - 6 wherein the stack is a stack of one finite element and said finite element is a bi-linear 4-node quadrilateral element calculated for all layers of the PCB delimited by the respective 2D mesh cell.

8. Method according to any of the claims 1 - 6 wherein the stack is a stack of one finite element and said finite element is a tri-linear 8-node hexahedron element calculated for all layers of the PCB delimited by the respective 2D mesh cell.

9. Method according to any of the claims 1 - 6 wherein the stack is a stack of:

a bi-linear 4-node quadrilateral element calculated for each conductive layer.

10. Method according to any of the claims 1 - 6 wherein the stack is a stack of:

11. Method according to any of the previous claims wherein the 2D mesh cells have a dimension of 10 - 200% of the PCT thickness, in particular 25% - 100% of PCB thickness, further in particular substantially 50% of the PCB thickness.

12. Method according to any of the previous claims wherein the inputs of the calculation of each finite element, from the PCB image description, for the corresponding conductive layer or layers delimited by the outline of the respective 2D mesh cell, comprise: the area fraction of conductive areas;

the number of independent conductive areas;

the centre of mass of the conductive areas; and/or

the thickness of the conductive layer or layers.

13. Method according to claim 2 and any of the claims 2-12 wherein the inputs of the calculation of each finite element, comprise:

the eigenvector and eigenvalues of the respective inertia tensor.

14. Method according to any of the previous claims comprising the previous step of discretising the PCB image description into image bitmaps of each conductive layer and of each dielectric layer.

15. Method according to any of the previous claims wherein a hole of the PCB is a PCB slot, a PCB cut-out, a PCB drilled hole, a PCB channel, a PCB recess, a PCB notch or a PCB rip.

16. Method according to any of the previous claims wherein the PCB image description is a structured data record.

17. Method according to any of the previous claims wherein the PCB image description is a gerber file.

18. Method according to any of the previous claims wherein each conductive layer is a copper PCB layer.

19. Method according to any of the previous claims wherein each dielectric layer is a FR4 PCB layer.

20. Non-transitory storage media including program instructions for implementing a converter of a printed circuit board, PCB, image description to a finite element model, the program instructions including instructions executable to carry out the method of any of the claims 1-19.

21. Converter of a printed circuit board, PCB, image description to a finite element model, comprising a data processor having a non-transitory storage media including program instructions executable by the data processor to carry out the method of any of the claims 1-19.