WO2016206421A1

WO2016206421A1 - Memory access processing method and device, and storage medium

Info

Publication number: WO2016206421A1
Application number: PCT/CN2016/077238
Authority: WO
Inventors: 武八一; 刘强
Original assignee: 中兴通讯股份有限公司
Priority date: 2015-06-26
Filing date: 2016-03-24
Publication date: 2016-12-29
Also published as: CN106326150A; CN106326150B

Abstract

A memory access processing method, comprising: dividing, according to a preset rule, a memory area into a first area and a second area; establishing, in a translation lookaside buffer (TLB) entry, a fixed TLB mapping entry corresponding to the first area and a dynamic TLB mapping entry corresponding to the second area, the dynamic TLB mapping entry being configured to replace, according to a preset page table, a mapping relationship; receiving a memory access request of a preset interface function, and if the memory access request requests to access the first area, accessing a memory address of the first area according to the fixed TLB mapping entry, and if the memory access request requests to access the second area, accessing a memory address of the second area according to the dynamic TLB mapping entry. Also disclosed in an embodiment of the present invention are a memory access processing device and storage medium.

Description

Memory access processing method, device and storage medium

Technical field

The present application relates to the field of computer technology, for example, to a memory access processing method, apparatus, and storage medium.

Background technique

As is known, in a 64-bit computer system, the memory supported by the CPU can theoretically reach up to 2^64 bytes. However, the TLB (Translation Lookaside Buffer) mapping entry as the actual page table cache is relatively small. Therefore, when the kernel accesses the physical address of the entire memory area, the address access is randomly distributed in the entire memory space due to different memory size requirements of different modules. In this way, in actual operation, a large number of TLB miss exceptions will inevitably occur. It is necessary to continuously load new TLB entries from the page table to complete virtual and real address translation, resulting in lower memory access performance and higher CPU usage. .

The above content is only used to assist in understanding the technical solutions of the embodiments of the present invention, and does not represent that the above is prior art.

Summary of the invention

The embodiment of the invention provides a memory access processing method, device, storage medium and device, which can improve the memory access performance of the system and reduce the occupancy rate of the CPU.

A memory access processing method provided by an embodiment of the present invention includes:

Dividing the memory area into the first area and the second area according to a preset rule;

Establishing a fixed TLB mapping entry corresponding to the first area and a dynamic TLB mapping entry corresponding to the second area in a transport backup buffer TLB entry; the dynamic TLB mapping entry is used according to a preset page table Mapping relationship replacement;

Receiving an access memory request of the preset interface function, in a case where the access memory request requests access to the first area, accessing the memory address of the first area according to the fixed TLB mapping entry, in the access memory In the case where the requested access is the second zone, the memory address of the second zone is accessed according to the dynamic TLB mapping entry.

Optionally, the method includes:

Determining, according to the preset access address range of the access memory request, whether the memory area requested to be accessed is the first area or the second area.

Optionally, after the accessing the memory address of the second area according to the dynamic TLB mapping entry, the method further includes:

Reloading the preset page table to replace the dynamic TLB mapping entry when the accessed memory address is not in the TLB entry;

The memory address of the second area is re-accessed according to the replaced dynamic TLB mapping entry.

Optionally, the dividing the memory area into the first area and the second area according to the preset rule includes:

When the system memory is initialized, a part of the NORMAL area preset in the memory area is divided into the second area; the DMA area and the NORMAL area preset in the memory area are not set to the first The portion of the second zone is set to the first zone.

Optionally, the method further includes:

Presetting a correspondence between the preset interface function and the access address interval, so that the first interface function whose memory access frequency is less than the first preset value and the access address interval of the second area in the preset interface function Correspondingly, the second interface function of the non-first interface function in the preset interface function corresponds to the access address interval of the first area.

Optionally, the memory access processing method further includes:

Presetting a correspondence between the preset interface function and the access address interval, so that the first interface function in the preset interface function corresponds to the access address interval of the second area, and the preset interface function is not The second interface function of the first interface function corresponds to the access address interval of the first area; the memory access frequency of the first interface function is less than the first preset value and the required memory amount is greater than the second preset value.

In addition, an embodiment of the present invention further provides a memory access processing apparatus, including:

The area dividing module is configured to divide the memory area into the first area and the second area according to the preset rule;

An entry establishing module, configured to establish, in a transport backup buffer TLB entry, a fixed TLB mapping entry corresponding to the first region and a dynamic TLB mapping entry corresponding to the second region; the dynamic TLB mapping entry is used according to The preset page table is replaced by a mapping relationship;

a processing module, configured to receive an access memory request of the preset interface function, and accessing the memory address of the first area according to the fixed TLB mapping entry, where the access memory request requests access to the first area, In the case that the access memory request requests access to the second zone, the memory address of the second zone is accessed according to the dynamic TLB mapping entry.

Optionally, the device further includes:

Loading a module, configured to reload the preset page table to replace the dynamic TLB mapping entry when the accessed memory address is not in the TLB entry;

The processing module is further configured to re-access the memory address of the second area according to the replaced dynamic TLB mapping entry.

Optionally, the device further includes:

The first preset module is configured to preset a correspondence between the preset interface function and the access address interval, so that the first interface function and the memory access frequency in the preset interface function are less than the first preset value The access address interval of the second area corresponds to, and the second interface function of the non-first interface function in the preset interface function corresponds to the access address range of the first area.

Optionally, the method further includes:

The second preset module is configured to preset a correspondence between the preset interface function and the access address interval, so that the first interface function in the preset interface function corresponds to the access address interval of the second region, and The second interface function of the non-first interface function in the preset interface function corresponds to the access address interval of the first area; the memory access frequency of the first interface function is less than the first preset value and accesses the memory request The corresponding amount of memory is greater than the second preset value.

Embodiments of the present invention also provide a computer storage medium storing computer executable instructions, the computer executable instructions being configured to perform the above method.

The embodiment of the invention further provides a device, the device comprising:

One or more processors;

Memory

One or more programs, the one or more programs being stored in the memory, and when executed by the one or more processors, do the following:

Receiving an access memory request of the preset interface function, in a case where the access memory request requests access to the first area, accessing the memory address of the first area according to the fixed TLB mapping entry, in the access memory In case the request is requested to access the second zone, according to the dynamic TLB mapping bar The memory address of the second area is accessed.

In the embodiment of the present invention, only the TLB dynamic entry is replaced when the page table is dynamically loaded, and when the first region is accessed, the access can be directly performed according to the fixed TLB entry, thereby reducing the probability of occurrence of the TLB miss exception, without avoiding continuous page interruption. The new TLB entries are loaded in the table, which improves the memory access performance of the system and reduces the CPU usage.

DRAWINGS

1 is a schematic flowchart of a first embodiment of a memory access processing method according to the present invention;

2 is a schematic diagram of a refinement process of accessing a memory in an embodiment of a memory access processing method according to the present invention;

3 is a schematic flowchart of a second embodiment of a memory access processing method according to the present invention;

4 is a schematic flowchart of a third embodiment of a memory access processing method according to the present invention;

FIG. 5 is a schematic flowchart diagram of a fourth embodiment of a memory access processing method according to the present invention; FIG.

6 is a schematic diagram of functional modules of a first embodiment of a memory access processing apparatus according to the present invention;

7 is a schematic structural diagram of a refinement function of the processing module of FIG. 6;

FIG. 8 is a schematic diagram of functional modules of a second embodiment of a memory access processing apparatus according to the present invention; FIG.

9 is a schematic diagram of functional modules of a third embodiment of a memory access processing apparatus according to the present invention;

10 is a schematic diagram of functional modules of a fourth embodiment of a memory access processing apparatus according to the present invention;

FIG. 11 is a schematic structural diagram of hardware of a device for performing a memory access processing method according to an embodiment of the present invention.

Implementation

The embodiment of the present invention provides a memory access processing method. Referring to FIG. 1, in the first embodiment of the memory access processing method of the present invention, the memory access processing method includes the following steps:

Step S10, dividing the memory area into the first area and the second area according to a preset rule;

The memory access processing method provided by the embodiment of the present invention can be applied to a computer system, and can be used to control memory address access. The above memory partitioning method can be set according to actual needs.

The preset rule may be a dividing rule of a memory address. In the 64-bit LINUX operating system, the memory area includes a DMA area (ZONE_DMA) and a NORMAL area (ZONE_NORMAL). The address space of the DMA area may range from 0 to 512 M. Correspondingly, the address space of the NORMAL area may be 512 M or more. In this embodiment, the memory can be divided into the first area and the second area according to the address. For example, when the system memory is initialized, a part of the NORMAL area of the memory area is divided into a second area; the remaining part of the NORMAL area that is not divided into the second area and the DMA area are set as the first area. . Since the second area is a part of the original NORMAL area, the addressing requirements of the 32-bit DMA device can be balanced. It should be noted that the starting address of the second zone can be determined based on actual memory and TLB mapping entries in the system.

Step S20, establishing a fixed TLB mapping entry corresponding to the first area and a dynamic TLB mapping entry corresponding to the second area in a transport backup buffer TLB entry; the dynamic TLB mapping entry is used according to a preset The page table is replaced by a mapping relationship;

In this embodiment, multiple TLB mapping entries exist in the TLB entry, and are used to access the memory area according to the TLB mapping entry when the preset interface function performs memory access. The TLB mapping entry includes a fixed TLB mapping entry and a dynamic TLB mapping entry, wherein the fixed TLB mapping entry is used for linear fixed mapping of the first region of the high frequency access, and the mapping relationship is not replaced; the dynamic TLB mapping entry is used for the low frequency The second zone entry of the degree access is dynamically replaced and loaded. Fixed TLB mapping entries and dynamic TLB mapping entries complete the mapping of the entire memory space. The above preset page table can be the kernel page table swapper_pg_dir. Dynamic TLB mapping entries can continuously load new TLB entries (ie, TLB mapping entries) from the page table to complete virtual and real address translation. In this embodiment, in order to comprehensively consider the actual dynamic bit width of the CPU, the space of the related address may be divided in the following manner:

Considering the actual dynamic bit width of the CPU, the relevant address space is arranged as follows:

First area memory start address (physical address): FIRST_START=0x200000000

Second area memory start address (physical address): SECOND_START=0x300000000

Kernel linear start address (virtual address): MAP_BASE=0xc000000000000000

Kernel temporary map start address (virtual address): FIXADDR_START=0xc00000fffd7bc000,

The kernel permanently maps the starting address (virtual address): PKMAP_BASE=0xc000008000000000.

Step S30, receiving an access memory request of the preset interface function, and accessing the memory address of the first area according to the fixed TLB mapping entry, where the access memory request requests access to the first area, In the case where the access memory request requests access to the second zone, according to the dynamic TLB The mapping entry accesses the memory address of the second zone.

The first zone in this embodiment may be referred to as a low end zone, and the second zone may be referred to as a high end zone.

Referring to FIG. 2, in the embodiment, the foregoing step S30 includes

Step S31, in the case that the preset interface function is accessed to access the memory request, determining whether the memory area accessed this time is the first area or the second area according to the preset access address range of the access memory request;

Step S32, determining that the memory area of the current access is the first area, performing step S34;

Step S33, determining that the memory area of the current access is not the first area, determining that the memory area of the current access is the second area, performing step S35;

Step S34, accessing the memory address of the first area according to the fixed TLB mapping entry;

Step S35, accessing the memory address of the second area according to the dynamic TLB mapping entry.

In this embodiment, the related functions involving memory access in the kernel can be modified. Fix the high frequency access interface to the first area of physical memory. The kernel is similar to kmalloc, kfree, get_free_page and other related interfaces. The kernel is used frequently and the application memory size is relatively small. It can be set in the first area. For interfaces with low memory access frequency but large memory requirements, operations need to be performed through the second area, such as kmap, kunmap, kmap_atomic, kunmap_atomic function interface and memory reservation interface for the system. When receiving the preset interface function to access the memory request, the memory area that is accessed this time may be determined to be the first area or the second area according to the preset access address range of the access memory request. For example, when the preset access address interval belongs to the first area, the first area may be directly accessed according to the mapping relationship of the fixed TLB mapping entry; when the preset access address interval belongs to the second area, the dynamic TLB mapping entry may be The mapping relationship accesses the second zone.

In the embodiment of the present invention, the memory area is divided into the first area and the second area, and the fixed TLB mapping entry and the dynamic TLB entry are set in the TLB entry, and only the TLB dynamic entry is replaced when the page table is dynamically loaded. When accessing the first area, the access can be directly accessed according to the fixed TLB entry, thereby reducing the probability of occurrence of the TLB miss exception, and avoiding constantly loading new TLB entries from the page table, thereby improving the system's memory access performance and reducing the system performance. CPU usage.

Referring to FIG. 3, based on the first embodiment of the memory access processing method of the present invention, in the second embodiment of the memory access processing method of the present invention, after step S34, the method further includes:

Step S40: When the accessed memory address is not in the TLB entry, reload the preset page table to replace the dynamic TLB mapping entry.

Step S50, re-accessing the memory area of the second area according to the replaced dynamic TLB mapping entry. site.

In this embodiment, after receiving the access memory request, if the memory address of the second area is accessed according to the memory access request, if the address is not found, a TLB miss exception is generated, and the TLB miss is abnormal according to the request. Reloading the preset page table to replace the dynamic TLB mapping entry to update the dynamic TLB mapping entry, ensuring that the corresponding memory address can be accessed according to the access memory request.

It can be understood that the access memory request type corresponding to the foregoing first area and the second area can be set according to actual needs. Optionally, the access address range of the interface function corresponding to the access memory request with a relatively low memory access frequency is limited to the second area, and the access address interval of the interface function corresponding to the memory access request with a relatively high memory access frequency is selected. Limited to the first zone.

As shown in FIG. 4, in the third embodiment of the memory access processing method of the present invention, the memory access processing method further includes:

Step S60: Presetting the correspondence between the preset interface function and the access address interval, so that the first interface function and the second area of the preset interface function whose memory access frequency is less than the first preset value The access address interval corresponds to, and the second interface function of the non-first interface function in the preset interface function corresponds to the access address interval of the first area.

In the case of sufficient memory, the amount of memory corresponding to the memory request may be considered, and the access address range of the interface function with a smaller buffer capacity may be set in the first area. In the fourth embodiment of the memory access processing method of the present invention, the difference from the third embodiment of the memory access processing method of the present invention is that the above step S60 can be replaced with step S70. As shown in FIG. 5, in the fourth embodiment of the memory access processing method of the present invention, the memory access processing method further includes:

Step S70: Presetting the correspondence between the preset interface function and the access address interval, so that the first interface function in the preset interface function corresponds to the access address interval of the second area, and the preset interface The second interface function of the non-first interface function in the function corresponds to the access address interval of the first area; the memory access frequency of the first interface function is less than the first preset value and the memory amount corresponding to the access memory request is greater than The second preset value.

In this embodiment, when processing the most frequently accessed memory space interface function, the access speed is fast because it is independent of the page table. Some functions with low frequency are used to access the memory area, and the TLB miss exception is generated. Finally, the content of the page table is loaded into the TLB by loading the dynamic TLB mapping entry, and the virtual real address translation is completed. Since the low-frequency access interface is modified according to the statistics of the kernel operation, The low frequency access interface has a low frequency of actual use and has little impact on the overall performance of the computer.

The embodiment of the present invention further provides a memory access processing apparatus. Referring to FIG. 6, in the first embodiment of the memory access processing apparatus of the present invention, the memory access processing apparatus includes: a region dividing module 10, an item establishing module 20, and a processing module 30. .

The area dividing module 10 is configured to divide the memory area into the first area and the second area according to a preset rule;

The memory access processing device provided by the embodiment of the present invention can be applied to a computer system for controlling memory address access. The above memory partitioning method can be set according to actual needs.

The preset rule may be a dividing rule of a memory address. In the 64-bit LINUX operating system, the memory area includes a DMA area (ZONE_DMA) and a NORMAL area (ZONE_NORMAL). The address space of the DMA area can range from 0 to 512 M. Correspondingly, the address space of the NORMAL area can be 512 M or more. In this embodiment, the memory can be divided into the first area and the second area according to the address. For example, when the system memory is initialized, a part of the NORMAL area of the memory area is divided into a second area; the remaining part of the NORMAL area that is not divided into the second area and the DMA area are set as the first area. . Since the second area is a part of the original NORMAL area, the addressing requirements of the 32-bit DMA device can be balanced. It should be noted that the starting address of the second zone can be determined based on actual memory and TLB mapping entries in the system.

The entry establishing module 20 is configured to establish, in the transport backup buffer TLB entry, a fixed TLB mapping entry corresponding to the first region and a dynamic TLB mapping entry corresponding to the second region; the dynamic TLB mapping entry is used according to The preset page table is replaced by a mapping relationship;

In this embodiment, multiple TLB mapping entries exist in the TLB entry, and are used to access the memory area according to the TLB mapping entry when the preset interface function performs memory access. The TLB mapping entry includes a fixed TLB mapping entry and a dynamic TLB mapping entry, wherein the fixed TLB mapping entry is used for linear fixed mapping of the first region of the high frequency access, and the mapping relationship is not replaced; the dynamic TLB mapping entry is set to the low frequency The second zone entry of the degree access is dynamically replaced and loaded. Fixed TLB mapping entries and dynamic TLB mapping entries complete the mapping of the entire memory space. The above preset page table can be the kernel page table swapper_pg_dir. Dynamic TLB mapping entries can continuously load new TLB entries (ie, TLB mapping entries) from the page table to complete virtual and real address translation. In this embodiment, in order to comprehensively consider the actual dynamic bit width of the CPU, the space of the related address may be divided in the following manner:

First area memory start address (physical address): FIRST_START=0x200000000

Second area memory start address (physical address): SECOND_START=0x300000000

Kernel linear start address (virtual address): MAP_BASE=0xc000000000000000

The processing module 30 is configured to receive an access memory request of the preset interface function, and access the memory address of the first area according to the fixed TLB mapping entry if the accessed memory request requests access to the first area, In the case that the access memory request requests access to the second zone, the memory address of the second zone is accessed according to the dynamic TLB mapping entry.

Referring to FIG. 7, the foregoing processing module 30 includes:

The determining unit 31 is configured to: when receiving the memory access request of the preset interface function, determine, according to the preset access address range of the access memory request, whether the memory area accessed this time is the first area or the second area;

The processing unit 32 is configured to: when the memory area of the current access is the first area, access the memory address of the first area according to the fixed TLB mapping entry; when the memory area of the current access is the second area, according to the The dynamic TLB map entry accesses the memory address of the second zone.

In this embodiment, the related functions involving memory access in the kernel can be modified. Fix the high frequency access interface to the first area of physical memory. The kernel is similar to kmalloc, kfree, get_free_page and other related interfaces. The kernel is used frequently and the application memory size is relatively small. It can be set in the first area. For an interface with a low memory access frequency but a large memory requirement, the second area needs to be operated. For example, kmap, kunmap, kmap_atomic, kunmap_atomic function interfaces related to file mapping and reading and writing, and memory access interfaces reserved for the system. When receiving the preset interface function to access the memory request, the memory area that is accessed this time may be determined to be the first area or the second area according to the preset access address range of the access memory request. For example, when the preset access address interval belongs to the first area, the first area may be directly accessed according to the mapping relationship of the fixed TLB mapping entry; when the preset access address interval belongs to the second area, the dynamic TLB mapping entry may be The mapping relationship accesses the second zone.

In the embodiment of the present invention, the memory area is divided into the first area and the second area, and the fixed TLB mapping entry and the dynamic TLB entry are set in the TLB entry, and only the TLB dynamic entry is replaced when the page table is dynamically loaded. When accessing the first zone, you can directly access the fixed TLB entry, thus reducing the TLB The probability of miss exceptions avoids the constant loading of new TLB entries from the page table, which improves the system's memory access performance and reduces CPU usage.

Referring to FIG. 8, in a second embodiment of the memory access processing device of the present invention, the memory access processing device further includes:

The loading module 40 is configured to reload the preset page table to replace the dynamic TLB mapping entry when the accessed memory address is not in the TLB entry;

The processing module 30 is further configured to re-access the memory address of the second area according to the replaced dynamic TLB mapping entry.

The access memory request type corresponding to the first area and the second area may be set according to actual needs. Optionally, the access address range of the interface function corresponding to the access memory request with a relatively low memory access frequency is limited to the second area, and the access address interval of the interface function corresponding to the memory access request with a relatively high memory access frequency is selected. Limited to the first zone.

As shown in FIG. 9, in the third embodiment of the memory access processing device of the present invention, the memory access processing device further includes:

The first preset module 50 is configured to preset a correspondence between the preset interface function and the access address interval, so that the first interface function in which the memory access frequency in the preset interface function is less than the first preset value is The access address interval of the second area corresponds to, and the second interface function of the non-first interface function in the preset interface function corresponds to the access address interval of the first area.

In the case of sufficient memory, the amount of memory corresponding to the memory request may be considered, and the access address range of the interface function with a smaller buffer capacity may be set in the first area. Referring to FIG. 10, in the fourth embodiment of the memory access processing device of the present invention, the memory access processing device further includes:

The second preset module 60 is configured to preset a correspondence between the preset interface function and the access address interval, so that the memory access frequency in the preset interface function is less than the first preset value and accessing the memory request pair The first interface function corresponding to the second preset value corresponds to the access address interval of the second area, and the second interface function of the non-first interface function in the preset interface function is the first interface function The access address range of the area corresponds.

In this embodiment, when processing the most frequently accessed memory space interface function, the access speed is fast because it is independent of the page table. Some functions that use less frequent access to the memory area will pass the TLB miss exception. Finally, the contents of the page table are loaded into the TLB by loading the dynamic TLB mapping entry, and the virtual and real address translation is completed. Since the low-frequency access interface is modified according to the statistics of the kernel operation, the actual frequency of the low-frequency access interface is low, which has little impact on the overall performance of the computer.

The embodiment of the invention further provides a computer storage medium storing computer executable instructions, the computer executable instructions being configured to perform any of the above memory access processing methods.

From the above description of the embodiments, those skilled in the art can clearly understand that the present invention can be implemented by software and necessary general hardware, and of course can also be implemented by hardware. Based on the understanding, the technical solution of the embodiment of the present invention may be embodied in the form of a software product, which may be stored in a computer readable storage medium, such as a computer floppy disk or a read-only memory (Read-Only Memory, ROM). ), random access memory (RAM), flash memory (FLASH), hard disk or optical disk, etc., including instructions for causing a computer device (which may be a personal computer, server, or network device, etc.) to perform the practice of the present invention The method described in the example.

It should be noted that, in the embodiment of the foregoing memory access processing device, the included units and modules are only divided according to functional logic, but are not limited to the above-mentioned division, as long as the corresponding functions can be implemented; The names of the units are also for convenience of distinguishing from each other and do not limit the scope of protection of the present invention.

The embodiment of the invention further provides a hardware structure diagram of a device for executing a memory access processing method. Referring to Figure 11, the device includes:

One or more processors 70, one processor 70 is taken as an example in FIG. 11;

Memory 71.

The apparatus may also include an input device 72 and an output device 73. The processor 70, the memory 71, the input device 72, and the output device 73 in the device may be connected by a bus or other means, as exemplified by a bus connection in FIG.

The memory 71 is a computer readable storage medium and can be used for storing software programs and computers. Executing a program, such as a program instruction/module corresponding to the memory access processing method in the embodiment of the present invention. The processor 70 executes the function application and data processing of the server by running the software program, the instruction and the module stored in the memory 71, that is, the memory access processing method in the above method embodiment.

The memory 71 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application required for at least one function; the storage data area may store data created according to usage of the terminal device, and the like. Further, the memory 71 may include a high speed random access memory, and may also include a nonvolatile memory such as at least one magnetic disk storage device, flash memory device, or other nonvolatile solid state storage device. In some examples, memory 71 can include memory remotely located relative to processor 70, which can be connected to the terminal device over a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

Input device 72 can be arranged to receive input numeric or character information and to generate key signal inputs related to user settings and function control of the terminal. The output device 73 may include a display device such as a display screen.

The one or more modules are stored in the memory 71, and when executed by the one or more processors 70, perform the following operations:

Optionally, the method further includes:

Optionally, the memory access processing method further includes:

Optionally, the method further includes:

The above are only optional embodiments of the present invention and are not intended to limit the scope of the invention.

Industrial applicability

The embodiment of the invention improves the memory access performance of the system and reduces the occupancy rate of the CPU.

Claims

A memory access processing method, including:

Dividing the memory area into the first area and the second area according to a preset rule;

Establishing a fixed TLB mapping entry corresponding to the first area and a dynamic TLB mapping entry corresponding to the second area in a transport backup buffer TLB entry; the dynamic TLB mapping entry is used according to a preset page table Mapping relationship replacement;

Receiving an access memory request of the preset interface function, in a case where the access memory request requests access to the first area, accessing the memory address of the first area according to the fixed TLB mapping entry, in the access memory In the case where the requested access is the second zone, the memory address of the second zone is accessed according to the dynamic TLB mapping entry.
The memory access processing method of claim 1, further comprising:

Determining, according to the preset access address range of the access memory request, whether the memory area requested to be accessed is the first area or the second area.
The memory access processing method of claim 2, after the accessing the memory address of the second area according to the dynamic TLB mapping entry, the method further comprises:

Reloading the preset page table to replace the dynamic TLB mapping entry when the accessed memory address is not in the TLB entry;

The memory address of the second area is re-accessed according to the replaced dynamic TLB mapping entry.
The memory access processing method according to claim 1, wherein the dividing the memory area into the first area and the second area according to the preset rule comprises:

When the system memory is initialized, a part of the NORMAL area preset in the memory area is divided into the second area; the DMA area and the NORMAL area preset in the memory area are not set to the first The portion of the second zone is set to the first zone.
The memory access processing method according to any one of claims 1 to 4, further comprising:

Presetting a correspondence between the preset interface function and the access address interval, so that the first interface function whose memory access frequency is less than the first preset value and the access address interval of the second area in the preset interface function Correspondingly, the second interface function of the non-first interface function in the preset interface function corresponds to the access address interval of the first area.
The memory access processing method according to any one of claims 1 to 4, further comprising:

Presetting a correspondence between the preset interface function and the access address interval, so that the first interface function in the preset interface function corresponds to the access address interval of the second area, and the preset interface function is not The second interface function of the first interface function corresponds to the access address interval of the first area; the memory access frequency of the first interface function is less than the first preset value and the required memory amount is greater than the second preset value.
A memory access processing device includes:

The area dividing module is configured to divide the memory area into the first area and the second area according to the preset rule;

An entry establishing module, configured to establish, in a transport backup buffer TLB entry, a fixed TLB mapping entry corresponding to the first region and a dynamic TLB mapping entry corresponding to the second region; the dynamic TLB mapping entry is used according to The preset page table is replaced by a mapping relationship;

a processing module, configured to receive an access memory request of the preset interface function, and accessing the memory address of the first area according to the fixed TLB mapping entry, where the access memory request requests access to the first area, In the case that the access memory request requests access to the second zone, the memory address of the second zone is accessed according to the dynamic TLB mapping entry.
The memory access processing device of claim 7, further comprising:

Loading a module, configured to reload the preset page table to replace the dynamic TLB mapping entry when the accessed memory address is not in the TLB entry;

The processing module is further configured to re-access the memory address of the second area according to the replaced dynamic TLB mapping entry.
The memory access processing device according to any one of claims 7 to 8, further comprising:

The first preset module is configured to preset a correspondence between the preset interface function and the access address interval, so that the first interface function and the memory access frequency in the preset interface function are less than the first preset value The access address interval of the second area corresponds to, and the second interface function of the non-first interface function in the preset interface function corresponds to the access address range of the first area.
The memory access processing device according to any one of claims 7 to 9, further comprising:

The second preset module is configured to preset a correspondence between the preset interface function and the access address interval, so that the first interface function in the preset interface function corresponds to the access address interval of the second region, and The second interface function of the non-first interface function in the preset interface function corresponds to the access address interval of the first area; the memory access frequency of the first interface function is less than the first preset value and accesses the memory request The corresponding amount of memory is greater than the second preset value.
A computer storage medium storing computer executable instructions arranged to perform the method of any of claims 1-6.