WO2016195606A1

WO2016195606A1 - Parallel and redundant voltage regulator system

Info

Publication number: WO2016195606A1
Application number: PCT/TR2015/000247
Authority: WO
Inventors: Süleyman TOPÇU
Original assignee: Topçu Süleyman
Priority date: 2015-06-03
Filing date: 2015-06-03
Publication date: 2016-12-08
Also published as: EP3117282A1; TR201907530T4; EP3117282B1

Abstract

The invention relates to a thyristor (9) controlled voltage regulator (13) system which is used in the regulation and stabilization of AC voltage, has a closed loop addressable thyristor conversion feature and operates on a parallel and redundant basis, and to the method for this system.

Description

DESCRIPTION

PARALLEL AND REDUNDANT VOLTAGE REGULATOR SYSTEM

Technical Field

The invention relates to voltage regulators and stabilizers which are used in places where line voltages are low and/or high; in all the applications where industrial or commercial electrical device and machines are required to be fed with regular and stable voltage; in all the electrical devices operating with single-phase and/or three-phase AC power; especially in high-capacity factories; in the plants where lack of electricity or voltage instability negatively affect the operation of the machines and devices or cause problems and loss of performance in the workflow; in the regulation and stabilization of AC voltage.

State of the Art

Today, voltage regulators used in the regulation of AC voltage are produced in different technologies such as mechanical, electromechanical, electronic and resonance. Voltage regulators produced with the current technology are produced up to 3000kva-4000kva as three-phase. As supplying current carrying elements such as on-off switch, protection fuse, thyristor, transistor, IGBT, and variac, which are required to produce a higher power voltage regulator, is not possible or very expensive, a regulator with a power higher than 4000kva cannot be produced. In order to use regulators in the plants with higher power, machines are required to be separated in 4000kva groups.

However, the plants with a power higher than 4000kva cannot stabilize their voltages by using a voltage regulator. The solution of a voltage regulator with higher power is not available in the mains voltage. Transformer stage converters are used in high voltage applications, but these units operate very slowly and are used to change the voltage permanently when the voltage is continuously low or high.

In the current technology, in case of a breakdown of the regulator in a plant using voltage regulator, the systems are closed and cannot be operated again until the breakdown in the regulator is solved. A product, which meets the redundant operation need of the plants which want to operate safely, continuously and without interruption, is not available. This is because regulators are required to be connected in parallel for the redundant operation. When newly established plants with a growth potential want to buy the regulator, which meets their needs at that time, and to increase the power later, they buy a new regulator and want to operate it by connecting the same in parallel, but such a solution cannot be offered with the regulators produced with the current technology.

The application No. CN102830744 encountered as a result of the technical researches relates to linear voltage regulator employing frequency compensation.

Another application encountered as a result of the technical researches, the patent No. US2009/0206804, however, relates to quasi-parallel voltage regulator embodiment. However, the current structures do not have a novelty aiming to solve the aforementioned drawbacks.

As a result, due to the drawbacks mentioned above and the inadequacy of the existing solutions regarding the subject matter, a development is deemed necessary to be made in the related technical field.

Objects of the Invention

Developed by being inspired of the present conditions, the present invention aims to eliminate the above mentioned drawbacks.

The main object of the invention is to obtain a voltage regulator which is connected in parallel, has a redundancy feature and operate synchronously, for the plants with a power higher than 4000kva.

The second main object of the invention is to obtain regulators operating simultaneously, in parallel and synchronously and in case of a breakdown in any regulator, to provide the other regulators to operate without interruption while the broken regulator is repaired.

Another object of the invention is to offer a solution of voltage regulator, the power of which can be increased and decreased by being connected in parallel for the big plants. Thereby, new companies are prevented from making a non-productive investment and expiration of the products bought without being used is prevented.

The structural and characteristic features and all the advantages of the present invention will be more clearly understood thanks to the figures below and the detailed description written with reference to those figures; therefore, the evaluation needs to be done by taking said figures and the detailed description into consideration. Figures to Facilitate Understanding of the Invention

Figure 1 illustrates the system according to the invention, which is formed by 4 regulators, as a whole.

Figure 2 illustrates one part of the inner structure of any of the regulators according to the invention. Figure 3 illustrates the other part of the inner structure of any of the regulators according to the invention.

Figure 4 illustrates the inner structure of the parallel communication management unit.

Scaling of drawings is not absolutely required and details, which are not needed for understanding the present invention, may have been neglected. Furthermore, elements, which are at least substantially identical or have at least substantially identical functions, are indicated with the same number.

Description of the Part References

1. CAVS-MB

2. PCU

3. PMU

4. Feedback transformer

5. Feed transformer

6. CBI

7. Booster transformer

8. Transformer with stage

9. Thyristor

10. SW1

11. SW2

12. PR U

13. Regulator (CAVS)

CAVS - Closed-loop Addressable Voltage Stabilizer

MB - Main Control Board

PMU - Parallel Management Unit

PCU - Parallel Communication Unit

CBI - Current Balance Inductor

SW - Switch PRMU - Parallel Regulator Management Unit

CATC - Closed-Loop Addressed Thyristor Changer

CPC - Closed_Loop Parallel Communication

TSD - Thyristor Selector Demultiplexer

TOC - Thyristor Open Circuit

TSC - Thyristor Short Circuit

Detailed Description of the Invention

In this detailed description, the preferred embodiments of the invention are described only for a better understanding of the subject without any limiting effects.

The invention relates to a parallel and redundant voltage regulator (13) system which is used in the regulation and stabilization of AC voltage. The system according to the invention consists of;

- electronic voltage regulator (13) (CAVS) which can operate on a parallel, redundant and synchronous basis, can be single-phase, two-phase or three-phase, is controlled by at least two thyristors (9) having the same features with each other;

- CAVS-MB (1) which takes the thyristor (9) addresses required for voltage regulation from PCU (2) by means of the electronic circuits and software algorithm designed for closed loop parallel communication; provides these addresses to be applied to the thyristor (9) groups (with the use of CATC algorithm); provides the thyristor (9) address change process to be performed by closed loop communication with the instructions of PCU (2) and reliable and precise information; is provided to be one for each phase (preferably 3 for three phases) in each regulator (13) for the parallel operation of the regulators (13) and provides a separate control and management for each phase (L1 , L2, L3); performs TOC and TSC controls for all the thyristors (9) simultaneously, and manages the status and breakdown information by measuring the information such as input voltage, output voltage, thyristor (9) temperature, etc.;

- PCU (2) developed for performing closed loop parallel and synchronous communication between PMU (3) and CAVS-MB (1), the management and communication unit, which provides the regulators (13) to perform an exchange of information with PRMU (12) over PMU (3): transmits the thyristor (9) addresses, which are received by CAVS-MB (1) cards provided by three on each of the regulators (13) from PMU (13), are separate for each phase but common for all the regulators (13), and the other instructions and sends the status information and application results it takes from CAVS-MB (1) cards to PMU (3); calculates the output and load voltages of each phase of the regulators (13) by means of analog information reading circuits and controls whether these values are synchronous with the common output of the parallel system; can perform parallel bidirectional communication with PMU (3) and CAVS-MBs (1) simultaneously; - management unit PRMU (12) which provides parallel redundant operation of at least 2 regulators (13); performs an exchange of information with the regulators (13) over PMU (3) provided therein; provides the entire system to run safely and synchronously;

- management and communication unit PMU (3) which calculates the independent thyristor (9) address information of each phase for each regulator (13) which is common for at least 2 regulators (13); sends the calculated address information to all of the regulators (13) simultaneously to provide operating safety and to meet rapid and synchronous operation needs using closed loop parallel communication electronic circuits and software algorithm; provides the regulators (13) to be connected to the parallel system by synchronizing the same therewith according to the voltage information measured from analog channels and the information received from regulators (13); controls the security of the data exchange performed between the regulator (13) and PRMU (12); and

- of the method steps where all these units are employed.

Inputs and outputs of at least 2 regulators (13) are short circuited. When the system is operated, PMU (3) sends the stable and same thyristor (9) address to all the regulators ( 3) and after assuring that this address is applied it tests the regulators (13) and provides the parallel connections thereof respectively. After all the regulators (13) are connected in parallel, the process of increasing and decreasing the output voitage starts for maintaining the output voltage in desired limits. The process of increasing and decreasing the voltage is performed in all the regulators (13) simultaneously.

Each regulator (13) has a structure as in Figures 2 and 3. It consists of the following parts:

- mechanical input switch SW1 (10) which is used for supplying and cutting the energy to the input of the voltage regulator (13) and is controlled by the CAVS-MB (1), PCU (2) and PMU (3) units;

- mechanical output switch SW2 (11) which is used for connecting and disconnecting the voltage regulator (13) output to and from the parallel connection terminals and is controlled by the CAVS- MB (1), PCU (2) and PMU (3) units;

- booster transformer (7), the secondary windings of which are coupled in series between the input-output, and which adds or removes the voltage proportional to the voltage applied to the primary winding to and from the output voltage in order to perform voltage regulation;

- transformer with stage (8) which provides applying different voltage values to the primary winding of said booster transformer (7);

- at least two thyristor (9) groups which form semi-conductor AC switch by connecting reversely in parallel to each other and are formed by coupling at least two thyristors (9) together (thyristors (9) arranged in 2 groups can be increased in a desired number depending on input voltage range and output voltage accuracy of the regulator (13) . In this preferred embodiment of the invention, in terms of ease of expression, 1st thyristor (9) group and 2nd thyristor (9) group, which provide selecting 25 different voltage stages, are formed by being arranged in the form of 2 groups out of the thyristors (9) provided by fives. It is also possible to form 9 different voltage stages by arranging 2 groups out of 3 pieces or 100 different voltage stages by arranging 2 groups out of 10 pieces.)

- CAVS-MB (1),

- PCU (2). (see Figures 2 and 3)

Thyristor (9) is a semi-conductor power switch which provides the current to pass between ANODE- CATHODE terminals when voltage is applied to the control terminal (gate); waits for the current, which is drawn for switching off the anode-cathode switch after the control voltage is cut, to be zero; remains in transmission as long as the anode-cathode current is not zero; and is generally used in AC voltage applications. In regulators (13) connected in parallel, semi-conductor AC current switches obtained by connecting the two thyristors (9) reversely in parallel to each other are used. These switches are turned on and off by indicating the address by CAVS-MB (1). Thyristors (9) are arranged in the form of 2 groups. When a specific voltage value is intended to be applied to the booster transformer (7), 1 thyristor from the 1st group of thyristors (9) in the big voltage stages and

1 thyristor (9) from the 2nd group of thyristors (9) in the small voltage stages are operated. For instance, if 30V is intended to be applied to the booster transformer (7), the thyristor (9) no. 2 in the 1st group and the thyristor (9) no. 6 in the 2nd group are operated. Voltages of the thyristors (9) no.

2 and 6 are 50V and 80V, respectively. The difference therebetween, 30V is applied to the booster transformer (7). When the stage is to be changed in order to apply a different voltage to the booster transformer (7), first the gate voltage of the thyristors (9) operating at that time is cut. In this case, thyristor (9) is not turned off immediately but remains in transmission until cathode-anode current becomes zero. Before operating a new thyristor (9), it is required to be assured that the thyristor (9), gate voltage of which is cut, is turned off. A specially designed electronic circuit is provided on the CAVS-MB (1) card which measures the zero state of anode-cathode current of each thyristor (9). There are 10 pieces of this electronic circuit in this design composed of 10 thyristors (9). This electronic circuit is referred to as TOC measurement circuit. This circuit measures on and off state of each thyristor (9), and sends the turn-off information of the thyristors (9), to which the turn-off command is sent, and the turn-on/operation information of the thyristors (9), to which operation command is sent, to the TSD unit and CAVS-MB (1) microprocessor. TOC information is collected from all of the 5 TOC measurement circuits disposed in the 1st group and sent to the microprocessor which is disposed on the CAVS-MB (1) card and is the management unit of the card. Upon receiving the TOC information, the microprocessor sets the permission of operation of a new thyristor (9) for the 1st group. 5 TOC circuits disposed in the 2nd group operate in a simiiar way and the microprocessor is allowed to set the permission of operation of a new thyristor (9) for the 2nd group. The process of selecting and operating the new thyristors (9) determined according to the voltage value desired to be applied to the booster transformer (7) starts. Thyristor Selector Demultiplexer (TSD) circuit is designed on said CAVS-MB (1) so as to activate only one thyristor (9) out of each thyristor (9) groups simultaneously, wherein it performs the thyristor (9) selection process according to the address information determined by the microprocessor of CAVS-MB (1). When a binary number between 1 and 5 is written in the address input of TSD, only one of the outputs between 1 and 5 is activated. 2 TSD circuits are used for 2 groups of thyristors (9). Microprocessor writes the address of thyristor (9) that it desires to select from the 1st group in the 1st TSD and the address of thyristor (9) that it desires to select from the 2nd group in the 2nd TSD. When the new thyristor (9) addresses are written in TSDs and the TSD output is activated, gate driver circuit of the selected thyristor (9) is operated and the thyristor (9) is activated. The information that the thyristor (9) is operated and the current is drawn between anode-cathode is measured by TOC circuit and sent to the microprocessor. After receiving the information that the thyristors (9) in both groups operate properly, the microprocessor completes the thyristor (9) selection process. This system, where the next step is passed upon receiving the information that the operating thyristor (9) is turned off and upon measuring the operation of the new thyristor (9) after the address of the new thyristor (9) is written, is referred to as closed loop addressing. If the 2 thyristors (9) in the same group are turned on simultaneously in the address thyristor (9) system composed of 2 groups, the thyristors (9) will be damaged as the 2 different voltage values will be short circuited. To prevent this and operate safely, electronic circuits are used which measure the turn-off state of the thyristors (9). Closed loop addressable thyristor (9) conversion system which measures the on or off state of each thyristor (9) and switches between the thyristors (9) with this precise information provides a significant advantage in terms of the safe operation of the high power regulators (13). In a regulator (13) operating in this way, CAVS-MB (1) definitely has the information that which thyristors (9) are active in the regulator (13). Thus, it is possible to activate the thyristor (9) having the same voltage value in multiple regulators (13) simultaneously. In case of a breakdown or failure of any thyristors (9) in fulfilling the command issued, CAVS-MB (1) has full and precise information about the situation. To control whether these thyristors (9) are turned off, suitable thyristors (9) are operated by using the respective address in accordance with the voltage stage desired to be selected.

For the operation of CAVS;

0V, 55V, 110V, 165V, 220V voltage stages to connect the 1st group of thyristors (9) and 88V, 99V, 110V, 121V, 132V stages to connect the 2nd group of thyristors (9) are provided on the transformer with stage (8). When the regulator (13) is started up, 3rd thyristor (9) from the 1st group and 8th thyristor (9) from the 2nd group are operated (thyristor address 38). As the two thyristors (9) have the same voltage, OV is applied to the secondary winding of the booster transformer (7). OV is generated in primary windings of the booster transformer (7), and the output voltage is equal to the input voltage.

If the output voltage is below the set value, thyristor (9) is increased by 1 and made 39. As the voltages of the 3rd and 9th thyristors (9) are 110V and 121V, respectively, 11V is applied to the secondary winding of the booster transformer (7). Conversion ratio of booster transformer (7) is 1/3, 3,5V is generated in the primary winding thereof. Output voltage and input voltage are +3,5V, thyristor (9) address is increased until the output voltage is elevated to the set value.

If the output voltage is above the set value, thyristor (9) address is decreased by 1. In every reduction of thyristor (9) address, output voltage decreases by 3,5V. All the address changes are performed according to the instructions received from PMU (3) by CATC protocol.

As each phase is managed by an independent CAVS-MB (1), full performance operation under 100% unstable voltage and 100% unstable load condition is possible.

Parallel communication connections between PMU and CAVS-MB (1) are made with the connecting connectors and parallel and synchronous communication electronic circuits specially designed for this purpose and disposed on PCU (2). Connectors which provide the connections between the devices and cards; multiplexer, demultiplexer, latch and line drivers where mutually received and sent information are taken and stored, are provided on PCU (2). Thereby, parallel communication is provided bi-directionally and simultaneously for three phases.

PMU (3) comprises electronic circuits which will perform simultaneous bidirectional communication with all the regulators (13) connected in parallel. Parallel and communication unit and connecting connector are added to the PMU (3) unit in a number equal to the number of the regulators ( 3) to be connected in parallel. Parallel communication units in PMU (3) and PCU (2) are the same.

In this preferred embodiment of the invention, 10 different voltage values are available on the transformer with stage (8). 10 thyristors (9) are arranged in a way to form 25 different voltage values by being arranged in the form of 2 groups out of the thyristors provided by fives. With the same design features, more number of voltage variations can be provided with more number of thyristors (9). For instance, 64 different voltage stages can be formed by using 16 thyristors (9). In the present invention, it is preferred to form 25 stages with 10 thyristors (9) in order to be simple and economic. There is no limitation in the number of regulators (13). The same system can be performed with the use of more number of regulators (13), as well.

CAVS-MB (1) tests whether all the thyristors (9) are turned off and closes the 1st and 2nd TSD outputs. In this case, gate pulse is not generated for any thyristor (9). Microprocessor writes the addresses of the thyristors (9) to be started up in the TSD inputs. TSDs select the thyristor (9) to be operated, but as the TSD exit permissions are closed, thyristor (9) gate drivers are not operated. TOC information is waited to be received for the activation of the thyristors (9). TOC information is sent by CAVS-MB (1) circuit. A cable from Anode-Cathode and Gate terminals of each thyristor (9) is received by CAVS-MB (1). TOC measurement circuit disposed on the CAVS-MB (1 ) follows the voltage between the Anode-Cathode of the thyristor (9). When the voltage between the anode- cathode of the thyristor (9) is higher than 10V, it decides that the thyristor (9) is not in transmission and gives the TOC information. 10 TOC test circuits are provided on CAVS-MB (1) in a way to be provided 1 for each thyristor (9). When all the TOC test circuits yield positive results, CAVS-MB (1) turns on the TSD outputs and provides the activation of pre-selected thyristors (9).

CATC is the electronic circuits which provide the thyristors (9) that cannot be turned on and off fully and simultaneously with the gate signal to be turned on and off with reliable and precise information in order to form different voltage variations and the algorithm where these circuits are managed. While performing the thyristor (9) conversion process, CATC first waits for the TOC information to come from the thyristor (9) measurement circuits. When all the thyristors (9) are turned off, TOC information is supplied. When the TOC information is received, TSD outputs are turned on and the gate circuit of the thyristor (9) selected is operated. Finally, TSC information is waited to be received from the thyristor (9) measurement circuits. This information indicates that the selected thyristor (9) is active. If the TSC information is not received within a certain period of time, the thyristor (9) conversion process is cancelled, all the thyristors (9) are turned off and error message is given. When the TSC information is received properly, thyristor transmission process is completed. When the thyristor (9) transmission process is completed, a new thyristor (9) address calculation permission is set for PMU (3). Performing the activation and deactivation processes of the thyristors (9) with the CATC algorithm is the most important component for the parallel operation of the regulators (13).

3 CAVS-MB (1) cards disposed in the regulator (13) bring the thyristor (9) groups in their management to the initial conditions with the same algorithm. CAVS-MB (1) informs the PCU (2) about the provision of initial conditions and waits for the new thyristor (9) address. PCU (2) takes the immediate information from the CAVS-MB (1) cards, informs PMU (3) about this and waits for the new address. The second important component of the invention is that parallel communication uses CPC protocol with the specially designed electronic circuits and algorithms. CPC protocol provides a secure and fast parallel communication which protects the thyristor (9) address information calculated by PMU (3) and sent to the regulators (13) connected in parallel against electrical noise and connection errors and provides equality and precision in the received and sent information between the 4 voltage regulators (13) and PRMU (12). Electronic circuits are designed in the invention in a way to provide 4 regulators (13) to be connected in parallel. To provide more number of regulators (13) to be connected in parallel, the number of these electronic circuits is required to be increased.

A total of 6 received data storage and retrieval circuits (DRL) and 6 sent data storage and transfer circuits, 3 (1 for each phase) for communicating with CAVS-MBs (1) and 3 for communicating with PMU (3), are provided on PCU (2). Thanks to the PCU (2) writing the information to be sent to CAVS-MBs (1) and PMU (3) in DSL and setting the DSO (data sent ok) signal, DRL which is disposed in each CAVS-MB (1) and PMU (3) is allowed to simultaneously receive the information sent.

12 data transfer and storage circuits (DSL) and 12 data retrieval and storage circuits (DRL) are available in PMU (3) in order to send and receive parallel information to each phase (L1 , L2, L3) of 4 regulators (13) connected in parallel. Thanks to the PMU (3) writing the information to be sent to all of the regulators (13) in DSL and setting the DSO (data sent ok) signal, DRL which is disposed in PCU (2) of each regulator (13) is allowed to simultaneously receive the information sent.

1 data transfer and storage circuit (DSL) and 1 data retrieval and storage circuit (DRL) are available in CAVS-MB (1) in order to receive and send information from PCU (2).

Depending on the algorithm, the information to be sent are written in the sent data latches, respectively. During this process, a separate information can also be written in each latch if required. These information are the thyristor (9) addresses or process instructions. When the writing process is completed, all the latches are opened simultaneously and 'Data Sent Ok' (DSO) signal is sent. In this way, CAVS-MBs (1) and PMU (3) are allowed to simultaneously receive the information. When CAVS-MB (1) and PMU (3) receive the sent data, 'Data Received Ok' (DRO) signal is sent. CAVS-MB (1) and PMU (3) write the information they will send in the sent data latch comprised therein and send the DSO signal. When PCU (2) receives the DSO signal, it reads the information in the received data latches and records the same in its memory. When the reading process is completed, it sends the DRO signal. To ensure an error-free parallel communication, information transfer protocol is repeated periodically in the following order. These steps are;

- PMU (3) measuring the output voltages of L1 , 12, L3 phases of the 1st regulator (13);

- continuing the processes by measuring the output voltages of the 2nd, 3rd, and 4th regulator (13), respectively, in case the 1 st regulator (13) is broken or closed;

- PMU (3) calculating thyristor (9) address separately for each phase according to the 1 st regulator (13) output voltage value;

- PMU (3) recording said thyristor (9) addresses so as to be sent to all of the regulators (13);

- PMU (3) performing the test processes so as to test the accuracy of the cable connections, accuracy of the phase ordering, and whether the communication is performed in an error-free and accurate manner;

- in case the tests results are accurate;

- Sending the thyristor (9) addresses, which are calculated by PMU (3) separately for L1 and/or L2 and/or L3 phases, to the PCUs (2) in all the regulators (13) disposed in the system as TEST ADDRESS in order to test the accuracy of the cable connections and the communication;

- PCU (2) sending the thyristor (9) TEST ADDRESS information of L1 phase it receives to the CAVS-MB (1) card of L1 phase disposed in the respective regulator (13), TEST ADDRESS of L2 phase to the CAVS-MB (1) card of L2 phase, and thyristor (9) TEST ADDRESS information of L3 phase to the CAVS-MB (1) of L3 phase;

- CAVS-MB (1 ) cards sending back the TEST ADDRESS information they receive to PCU (2);

- PCU (2) comparing the TEST ADDRESS information received from CAVS-MB (1) cards with the TEST ADDRESS information it sends to CAVS-MB (1);

- Unless TEST ADDRESS information controlled by PCU (2) match with each other, returning to the first step of the test processes in order to perform the communication control and to restart the processes;

- If the TEST ADDRESS information that PCU (2) compares are equal to each other,

- PCU (2) sending back the same TEST ADDRESS information to PMU (3);

- PMU (3) comparing the TEST ADDRESS information received from PCU (2) with the TEST ADDRESS information it sends to PCU (2);

- Unless TEST ADDRESS information controlled by PMU (3) match with each other, returning to the first step of the test processes in order to perform the communication control and to restart the processes;

- If the TEST ADDRESS information controlled by PMU (3) match with each other, - PMU (3) sending the REAL ADDRESS information to PCUs (2) so as to be applied to thyristors (9);

- PCU (2) sending the thyristor (9) REAL TEST ADDRESS information of L1 phase it receives to the CAVS-MB (1) card of L1 phase disposed in the respective regulator (13), REAL TEST ADDRESS of L2 phase to the CAVS- MB (1) card of L2 phase, and thyristor (9) REAL TEST ADDRESS information of L3 phase to the CAVS-MB (1) of L3 phase;

- CAVS-MB (1) cards comparing the REAL TEST ADDRESS information received thereby with the TEST ADDRESS information;

- If the TEST ADDRESS and REAL ADDRESS information compared by CAVS-MB (1) are different from each other, sending an error code to the PCU (2) by said CAVS-MB;

- If the TEST ADDRESS and REAL ADDRESS information compared by CAVS-MB (1) match with each other;

- CAVS-MB (1) determining the thyristors (9) required to be operated according to the thyristor (9) address that CAVS-MB (1) of each phase receives from PCU (2), turning off the thyristors (9) operating by using the CATC unit, and performing the thyristor (9) selection process by operating the new!y selected thyristors (9);

- CAVS-MB (1) sending the 'process completed' information to PCU (2);

- PCU (2) receiving the 'process done' information coming from CAVS- MB (1) with respect to the fact that thyristors (9) selected according to the thyristor (9) addresses of the phases are selected and operated;

- PCU (2) sending the 'process done' information to the PMU (3);

- when the 'process done' information is received from all PCUs (2), PMU (3) allowing for a new thyristor (9) address calculation for the voltage regulation;

returning to the first step of the test processes in order to initiate a new communication;

each PCU (2) evaluating the error and failure codes it receives from CAVS-MB (1) cards of the regulator (13) it commands and sending a status information to PMU (3);

- returning to the first step of the test processes in case the test results are inaccurate.

Said test processes are as follows;

- PMU (3) sending test information to the PCUs (2) in all the regulators (13) disposed in the system; - PCUs (2) in each of the regulator (13) controlling the accuracy of the test information received from PMU (3);

- If the test information controlled by PCUs (2) are inaccurate, PCUs (2) sending an error code to PMU (3);

- If the test information controlled by PCUs (2) are accurate,

- PCUs (2) sending these test information to CAVS-MB (1) cards;

- CAVS-MBs (1) in all the regulators (13) controlling the accuracy of the test information sent to CAVS-MBs (1) by PCUs (2);

- If the test information controlled by CAVS-MBs (1) are inaccurate, CAVS-MBs (1) sending an error code to the PCUs (2) related thereto;

- If the test information controlled by CAVS-MBs (1) are accurate,

- CAVS-MBs (1) sending back these test information to the respective PCUs (2) disposed in each regulator (13);

- PCU (2) controlling whether the information sent back by CAVS-MBs (1) match with the information previously sent to CAVS-MBs (1);

- Unless the test information controlled by PCUs (2) match with each other, PCUs (2) sending an error code to PMU (3);

- If the test information controlled by PCUs (2) match with each other,

PCUs (2) sending back these test information to PMU (3):

- PMU (3) controlling whether the information received from PCUs (2) match with the information previously sent to PCUs (2).

Receiving the same address information several times and comparing the sent and received addresses during the communication processes is a special algorithm which is developed for preventing activation of a different thyristor (9) than the other in any regulator (13) due to the connection errors or communication errors.

During the thyristor (9) address changes, short-time voltage instability likely to occur due to the fact that thyristor (9) conversion process is completed in a longer or a shorter period of time in any regulator (13) or output voltage differences occurring due to the production tolerances of the regulators (13) may lead to loop currents during the parallel connection. CBI (6) is used at the output of each regulator (13) in order to prevent said loop currents. CBI (6) consists of inductors coupled in series to the output of each phase of the regulator (13). As the current drawn from the output of the regulator (13) increases, voltage drop on inductor also increases. Thereby, if there is 1-2V difference between the output voltages of the two regulators (13) connected in parallel, this voltage is kept by CBI (6) and drawing loop current between the regulators (13) is prevented. Stage voltages of the transformers with stage (8) in ail the regulators (13) connected in parallel are equal to each other. Likewise, voltages of the booster transformer (7) are also equal to each other. Therefore, when the thyristors (9) having the same address are activated in all the regulators (13), output voltages of all the regulators (13) become equal.

Thanks to the invention, secure and fast voltage regulator (13) system is formed which comprises many voltage regulators (13); operates at high power and on a parallel and redundant basis, wherein the broken regulators (13) are disabled without affecting the other regulators (13) and are reactivated after being repaired without turning off the other regulators (13).

The most important and distinctive features of the parallel redundant closed loop addressable voltage regulators (13) according to the invention are as follows:

• PMU (3) calculates a separate address for each phase. Independent voltage regulation is available in the invention.

• The thyristor (9) addresses calculated independently for L1 , L2, L3 phases are sent simultaneously to all the regulators (13) connected in parallel by means of the specially designed electronic circuits and developed algorithm.

• After PCU (2) in each regulator (13) applies the address and operation commands received from PMU (3), it writes the status information of the regulator (13) in the parallel communication unit and sets the DSO signal. Upon receiving the DSO signal from all the PCUs (2), PMU (3) reads the coming information from the parallel communication unit. In this manner, simultaneous and parallel communication is performed with all the regulators (13).

• Output voltage can be increased or decreased with the different voltages applied to the booster transformer (7).

• Voltage value to be applied to the booster transformer (7) and application time are fully calculated and applied with the closed loop addressable thyristor (9) groups.

• Loop currents occurring due to the voltage differences between the regulators (13) are limited with CBI (6).

• Inconveniences and errors likely to occur during the thyristor (9) transmissions are detected within a short period of time such as 20-40 msec and eliminated thanks to the fast and parallel communication protocol.

• Each regulator (13) is connected to and disconnected from the parallel system in a controlled and sequential manner by PMU (3) and PCU (2). • Parallel communication between PMU (3), PCU (2) and CAVS-MB (1) is a closed loop feedback parallel communication protocol which is designed to eliminate the communication errors likely to occur due to electrical noise such as cable breaking and loose contact of the socket and similar reasons.

• Thanks to the high-speed communication, rapid voltage regulation is made by changing the thyristor (9) within 20-40msec.

• Performing the output voltage regulation according to the 1st regulator (13) output voltage, performing the voltage regulation according to the 2nd, 3rd and 4th regulators (13), respectively, in case the 1st regulator (13) is broke down, and calculating the thyristor (9) address are other important features.

When the voltage stage will be changed in the closed loop addressing the following process steps are performed;

- CAVS-MB (1) receiving the common thyristor (9) addresses determined by PMU (3) for all the regulators (13) and sent by means of PCU (2) from DRL units;

- When a new thyristor (9) address is received by CAVS-MB (1), CAVS-MB (1) issuing a command by means of its microprocessor that TSD turn off all the thyristor (9) gate pulses;

- TSD turning off the gate pulses by closing all the outputs;

- CAVS-MB (1) sending the new thyristor (9) addresses to TSD;

- CAVS-MB (1) waiting for the signal which gives the information that all the thyristors (9) are turned off from the thyristor (9) TOC circuits;

- Upon receiving the TOC signal, CAVS-MB (1) sending the signal which gives the permission of driving the thyristor (9) to TSD;

- TSD turning on the gate pulses of the determined thyristors (9);

- CAVS-MB (1) waiting for the signal which comprises the information to be received from TOC circuits that the selected thyristors (9) are turned on;

- Upon receiving the information that the selected thyristors (9) are turned on from the TOC circuits, CAVS-MB (1) sending the 'process completed' information to PCU (2);

- CAVS-MB (1) waiting for a new thyristor (9) address.

Claims

1. A thyristor (9) controiled voltage regulator (13) system which is used in the regulation and stabilization of AC voltage and operates on a parallel and redundant basis, characterized in comprising;

- at least 2 electronic voltage regulators (13) which can operate on a parallel, redundant and synchronous basis, can be single-phase or two-phase or three-phase, and have the same features with each other and which comprises: booster transformer (7), the secondary windings of which are coupled in series between the input-output, and which adds or removes the voltage proportional to the voltage applied to the primary winding to and from the output voltage in order to perform voltage regulation;

transformer with stage (8) which provides applying different voltage values to the primary winding of said booster transformer (7);

at least two thyristor (9) groups which form semi-conductor AC switch by connecting reversely in parallel to each other and are formed by coupling at least two thyristors (9) together;

CAVS-MB (1) which applies the thyristor (9) addresses it takes from PCU (2) to the thyristors (9) for voltage regulation, synchronously performs the process of changing the thyristor (9) address in all the regulators (13), provides an independent control and management for each phase (L1 , L2, L3), simultaneously manages the status and failure information for all the thyristors (9), and is provided to be one for each phase in each regulator (13);

PCU (2) developed for performing closed loop synchronous communication between PMU (3) and CAVS-MB (1), the management and communication unit, which provides the regulators (13) to perform an exchange of information over PMU (3), transmits the thyristor (9) addresses, which are separate for each phase but common for all the regulators ( 3), and the instructions received from PMU (3) to CAVS-MB (1) provided at a number equal to the phase number on each of the regulators (13) and sends the status information and application results it takes from CAVS-MB (1) cards to PMU (3), calculates the output and load voltages of each phase of the regulators (13) by means of analog information reading circuits and controls whether these values are synchronous with the common output of the parallel system, and can perform parallel bidirectional communication with PMU (3) and CAVS-MBs (1 ) simultaneously;

- and management and communication unit PMU (3) which calculates the thyristor (9) address information common for said regulators (13) and independent for each phase, sends the calculated address information to all of the regulators (13) simultaneously considering the operating safety and speed factors, provides the regulators (13) to be connected to the parallel system by synchronizing the same therewith according to the voltage information measured from analog channels and the information received from regulators (13), and controls the security of the data exchange performed with PCU (2).

2. The voltage regulator ( 3) system as in Claim 1 , characterized in comprising a management unit PRMU (12) which provides parallel redundant operation of at least 2 regulators (13); performs data exchange with the regulators (13) over PMU (3) provided therein; and provides the entire system to run safely and synchronously.

3. The voltage regulator (13) system as in Claim 1 , characterized in comprising a mechanical output switch SW2 (11) which is used for connecting and disconnecting the regulator (13) output of said regulator (13) to and from the parallel connection terminals and is controlled by the CAVS-MB (1), PCU (2) and PMU (3) units.

4. The voltage regulator (13) system as in Claim 1 , characterized in comprising CBI (6) at the output of each regulator (13) in order to prevent the loop currents caused by short-time voltage instability likely to occur during the thyristor (9) address changes and by output voltage differences occurring due to the production tolerances of the regulators (13) during the parallel connection.

5. The voltage regulator (13) system as in Claim 1 , characterized in comprising TSD unit on said CAVS-MB (1), which performs thyristor (9) selection process according to the address information determined by the microprocessor of CAVS-MB (1) and allows selecting only one thyristor (9) simultaneously.

6. The voltage regulator (13) system as in Claim 5, characterized in comprising a TOC unit which measures on and off state of each thyristor (9), and sends the turn-off information of the thyristors (9), to which the turn-off command is sent, and the turn-on/operation information of the thyristors (9), to which operation command is sent, to the TSD unit and CAVS-MB (1) microprocessor on said CAVS-MB (1).

7. The voltage regulator (13) system as in Claim 1, characterized in comprising CATC unit which provides the thyristors (9) that cannot be turned on and off fully and simultaneously with the gate signal to be turned on and off with reliable and precise information in order to form different voltage variations.

8. The voltage regulator (13) system as in Claim 1 , characterized in that the parallel communication performed between PMU (3) and PCU (2) is in compliance with the closed loop synchronous parallel communication protocol (CPC) which protects the thyristor (9) address information calculated by PMU (3) and sent to the regulators (3) connected in parallel against electrical noise and connection errors and provides equality and precision in the received and sent information.

9. The voltage regulator (13) system as in Claim 1 , characterized in comprising a sent data storage and transfer circuit (DSL) which provides the communication between CAVS-MBs (1) and PMU (3) and in which the information to be sent to CAVS-MBs (1) and PMU (3) is written and a received data storage and retrieval circuit (DRL) which provides the information to be received simultaneously by each CAVS-MB (1) and PMU (3) upon setting the DSO signal informing that the data is sent on PCU (2).

10. The voltage regulator (13) system as in Claim 1 , characterized in comprising a data storage and transfer circuit (DSL) in which the information to be sent to all the regulators (13) by PMU (3) is written in order to send and receive information in parallel to and from each phase of the regulator (13) and a received data storage and retrieval circuit (DRL) which provides the information to be received simultaneously by PCU (2) of each regulator (13) upon setting the DSO signal informing that data is sent on PMU (3).

11. A method for the thyristor (9) controlled voltage regulator (13) system which is used in the regulation of AC voltage and operates on a parallel and redundant basis, characterized in comprising the following process steps;

- PMU (3) calculating thyristor (9) address separately for each phase according to the 1st regulator (13) output voltage value;

- in case the tests results are accurate; - sending the thyristor (9) addresses, which are calculated by PMU (3) separately for L1 and/or L2 and/or L3 phases, to the PCUs (2) in all the regulators (13) disposed in the system as TEST ADDRESS in order to test the accuracy of the cable connections and the communication;

- CAVS-MB (1) cards sending back the TEST ADDRESS information they receive to PCU (2);

- uniess TEST ADDRESS information controlled by PCU (2) match with each other, returning to the first step of the test processes in order to perform the communication control and to restart the processes;

- PCU (2) sending back the same TEST ADDRESS information to PMU (3);

- if the TEST ADDRESS information controlled by PMU (3) match with each other,

- PMU (3) sending the REAL ADDRESS information to PCUs (2) so as to be applied to thyristors (9);

- PCU (2) sending the thyristor (9) REAL TEST ADDRESS information of L1 phase it receives to the CAVS-MB (1) card of L1 phase disposed in the respective regulator (13), REAL TEST ADDRESS of L2 phase to the CAVS-MB (1) card of L2 phase, and thyristor (9) REAL TEST ADDRESS information of L3 phase to the CAVS-MB (1) of L3 phase;

- if the TEST ADDRESS and REAL ADDRESS information compared by CAVS-MB (1) match with each other; - CAVS-MB (1) determining the thyristors (9) required to be operated according to the thyristor (9) address that CAVS-MB (1) of each phase receives from PCU (2), turning off the thyristors (9) operating by using the CATC unit, and performing the thyristor (9) selection process by operating the newly selected thyristors (9);

- CAVS-MB (1) sending the 'process completed' information to PCU (2);

- PCU (2) receiving the 'process done' information coming from CAVS-MB (1) with respect to the fact that thyristors (9) selected according to the thyristor (9) addresses of the phases are selected and operated;

- PCU (2) sending the 'process done' information to the PMU (3);

- when the 'process done' information is received from ail PCUs (2), PMU (3) allowing for a new thyristor (9) address calculation for the voltage regulation;

- returning to the first step of the test processes in order to initiate a new communication;

12. The method as in Claim 11 , characterized in that said test processes are as follows;

- PMU (3) sending test information to the PCUs (2) in all the regulators (13) disposed in the system;

- PCUs (2) in each of the regulator (13) controlling the accuracy of the test information received from PMU (3);

- if the test information controlled by PCUs (2) are accurate,

- PCUs (2) sending these test information to CAVS-MB (1) cards;

- if the test information controlled by CAVS-MBs (1) are accurate,

- CAVS-MBs (1) sending back these test information to the respective PCUs (2) disposed in each regulator (13); - PCU (2) controlling whether the information resent by CAVS-MBs (1) match with the information previously sent to CAVS-MBs (1);

- if the test information controlled by PCUs (2) match with each other,

- PCUs (2) sending back these test information to PMU (3);

13. The method as in Claim 11 , characterized in comprising the following process steps;

- each PCU (2) evaluating the error and failure codes it receives from CAVS-MB (1) cards of the regulator (13) it commands and sending a status information to PMU

(3).

14. The method as in Claim 11, characterized in that when the voltage stage will be changed in the closed loop addressing, it comprises the following process steps;

- CAVS-MB (1) receiving the common thyristor (9) addresses determined by PMU (3) for all the regulators (13) and sent by means of PCU (2) from DRL units which are the received data storage and retrieval circuits disposed on PCU (2);

- when a new thyristor (9) address is received by CAVS-MB (1), CAVS-MB (1) issuing a command by means of its microprocessor that TSD, which performs thyristor (9) selection process and allows selecting only one thyristor (9) simultaneously, turn off all the thyristor (9) gate pulses;

- TSD turning off the gate pulses by closing all the outputs;

- CAVS-MB (1) sending the new thyristor (9) addresses to TSD;

- CAVS-MB (1) waiting for the signal which gives the information that all the thyristors (9) are turned off from the thyristor (9) TOC circuits which measure the on and off state of each thyristor (9);

- TSD turning on the gate pulses of the determined thyristors (9);

- upon receiving the information that the selected thyristors (9) are turned on from the TOC circuits, CAVS-MB (1) sending the 'process completed" information to PCU (2);

- CAVS-MB (1) waiting for a new thyristor (9) address.