WO2016188063A1 - 提高ram存取效率的方法、装置和计算机存储介质 - Google Patents

提高ram存取效率的方法、装置和计算机存储介质 Download PDF

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WO2016188063A1
WO2016188063A1 PCT/CN2015/095272 CN2015095272W WO2016188063A1 WO 2016188063 A1 WO2016188063 A1 WO 2016188063A1 CN 2015095272 W CN2015095272 W CN 2015095272W WO 2016188063 A1 WO2016188063 A1 WO 2016188063A1
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random sequence
ram
address register
random
address
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PCT/CN2015/095272
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French (fr)
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肖洁
徐金林
廖智勇
刘衡祁
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深圳市中兴微电子技术有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures

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  • the present invention relates to the field of mobile terminals, and in particular, to a method, an apparatus, and a computer storage medium for improving access efficiency of a random access memory (RAM).
  • RAM random access memory
  • the cache chip has a length requirement for each access message.
  • a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) requires a read/write command of 64 bytes per transmission. Integer multiple.
  • a 65-byte message actually requires a 128-byte read/write command to send.
  • the 65-byte message is divided into two slices in a 64-byte format, one of which is 64 bytes, and the other is only 1 byte. If the fragmented message access system has two DDR SDRAM cache chips, the 65-byte message is stored in the two DDR SDRAMs according to the divided two packets. Thus, one of the DDR SDRAMs only stores a 1-byte fragmented message.
  • Embodiments of the present invention are directed to a method, apparatus, and computer storage medium for improving RAM access efficiency that are capable of at least partially improving RAM access efficiency in a fragmented message access system.
  • an embodiment of the present invention provides a method for improving random access memory RAM access efficiency, including: according to a preset first random sequence and a correspondence between an element of the first random sequence and a second random sequence. Obtaining the second random sequence; wherein, the number of elements of the first random sequence is consistent with the number of the second random sequence, each element of the first random sequence is different from each other and respectively corresponding to Different said second random sequence, the number of elements of the first random sequence is at least two; obtaining a correspondence according to the obtained second random sequence and the correspondence between the elements of the second random sequence and the RAM a RAM; wherein, the number of elements of the second random sequence is consistent with the number of the RAM, each element of the second random sequence is different from each other and respectively corresponds to different RAMs;
  • the RAM writes/reads the message fragments.
  • a first address register storing the first random sequence is set, and correspondingly, the first random sequence according to the preset and the correspondence between the element of the first random sequence and the second random sequence are correspondingly Obtaining the second random sequence, specifically: obtaining an element of the first random sequence according to a current address of the first address register; according to an element of the first random sequence and an element of the first random sequence Obtaining the second random sequence by the correspondence with the second random sequence; if the current address of the first address register is not the maximum value, the current address of the first address register is incremented by one; if the first address The current address of the register is the maximum value, and the first address register is set to zero.
  • a second address register corresponding to the number of the second random sequence and storing the second random sequence is set, and correspondingly, the obtained second random sequence and the Corresponding relationship between elements of the second random sequence and the RAM to obtain the RAM, Obtaining: obtaining, according to the current address of the second address register of the obtained second random sequence, an element of the second random sequence; according to an element of the second random sequence and an element of the second random sequence and a RAM Corresponding relationship obtains the RAM; if the current address of the second address register is not the maximum value, the current address of the second address register is incremented by one; if the current address of the second address register is the maximum value, Then the second address register is set to zero.
  • the first random sequence and the at least two second random sequences are generated by a pseudo random sequence generator set in advance.
  • an embodiment of the present invention provides an apparatus for improving access efficiency of a random access memory (RAM), wherein the apparatus includes: a first obtaining unit, a second obtaining unit, and a reading and writing unit, wherein: An obtaining unit, configured to obtain the second random sequence according to a preset first random sequence and a correspondence between an element of the first random sequence and a second random sequence; wherein, the elements of the first random sequence The number is consistent with the number of the second random sequence, each element of the first random sequence is different from each other and corresponds to a different second random sequence, and the number of elements of the first random sequence At least two; the second obtaining unit is configured to obtain the RAM according to a second random sequence obtained by the first obtaining unit and a correspondence between an element of the second random sequence and a RAM; wherein The number of elements of the second random sequence is consistent with the number of the RAM, each element of the second random sequence is different from each other and respectively corresponds to a different RAM; the read/write unit is configured For write / read
  • a first address register storing the first random sequence is set, and correspondingly, the first obtaining unit is configured to: obtain the first random according to a current address of the first address register An element of the sequence; obtaining the second random sequence according to an element of the first random sequence and a correspondence between an element of the first random sequence and a second random sequence; if a current address of the first address register is not a maximum value, the current address of the first address register is incremented by one; if the current address of the first address register is a maximum value, the first The address register is set to zero.
  • a second address register corresponding to the number of the second random sequence and storing the second random sequence is set, and the second obtaining unit is configured to obtain according to the first obtaining unit Obtaining, by the current address of the second address register of the second random sequence, an element of the second random sequence; obtaining the RAM according to an element of the second random sequence and a correspondence between an element of the second random sequence and a RAM If the current address of the second address register is not the maximum value, the current address of the second address register is incremented by one; if the current address of the second address register is the maximum value, the second address register Zero.
  • the apparatus further includes a pseudo-random sequence generator configured to generate the first random sequence and the at least two second random sequences.
  • an embodiment of the present invention further provides a computer storage medium, where the computer storage medium stores computer executable instructions, and the computer executable instructions are used to perform the foregoing method for improving random access memory RAM access efficiency. At least one of them.
  • An embodiment of the present invention provides a method and apparatus for improving RAM access efficiency, and obtaining a second random sequence according to a preset first random sequence and a correspondence between an element of the first random sequence and a second random sequence;
  • the second random sequence and the correspondence between the elements of the second random sequence and the RAM obtain the RAM;
  • the write/read operation is performed on the slice of the message in the obtained RAM, so that by randomly selecting the RAM in a period of time, the report is avoided
  • the fragmented message that cannot reach the fragment length in the end of the text is repeatedly written into one or more RAMs, so that the fragmented message at the end of the message is uniformly written into each RAM, and the bandwidth of each RAM is utilized to the utmost extent.
  • the access efficiency of the RAM in the fragmented message access system is improved.
  • FIG. 1 is a schematic flowchart of a method for improving RAM access efficiency according to an embodiment of the present invention
  • FIG. 2 is a detailed embodiment of a method for improving RAM access efficiency according to an embodiment of the present invention. Schematic diagram of the process
  • FIG. 3 is a schematic structural diagram of an apparatus for improving RAM access efficiency according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of another apparatus for improving RAM access efficiency according to an embodiment of the present invention.
  • FIG. 1 is a schematic flowchart of a method for improving RAM access efficiency according to an embodiment of the present invention, where the method includes:
  • S101 Obtain a second random sequence according to a preset first random sequence and a correspondence between an element of the first random sequence and a second random sequence; wherein, the number of elements of the first random sequence and the number of the second random sequence are one Therefore, each element of the first random sequence is different from each other and respectively corresponds to a different second random sequence, and the number of elements of the first random sequence is at least two;
  • each element of the first random sequence is the same as the number of the second random sequence, and each element of the first random sequence is different from each other and respectively corresponds to a different second random sequence, then Each element of a random sequence is cycled once, and each second random sequence is selected once. In this way, it is guaranteed that the probability of selecting each second random sequence in one cycle is the same.
  • the first random sequence has 4 elements, which are 0, 1, 2, and 3 respectively.
  • the first random sequence may be 0123 or 1203, where 4 different elements in the first random sequence There are 4 different second random sequences respectively.
  • the method further includes: setting a first address register that saves the first random sequence, and correspondingly, according to the preset first random sequence and the first random sequence element and the second random sequence Obtaining a second random sequence corresponding to the correspondence between the machine sequences is: obtaining an element of the first random sequence according to a current address of the first address register; and corresponding to an element of the first random sequence and the second random sequence according to the first random sequence The relationship obtains a second random sequence; if the current address of the first address register is not the maximum value, the current address of the first address register is incremented by one; if the current address of the first address register is the maximum value, the first address register is set to zero .
  • S102 Obtain a RAM according to the obtained second random sequence and the correspondence between the elements of the second random sequence and the RAM; wherein, the number of elements of the second random sequence is consistent with the number of RAM, and each element of the second random sequence Different from each other and corresponding to different RAMs.
  • second random sequences there are many second random sequences that meet the above requirements, and at least two second random sequences for selecting an actual RAM may be selected according to actual needs. For example, when the number of RAM is 6 pieces, according to It can be seen that there are 720 second random sequences that meet the requirements. In practical applications, the randomness requirements of the fragmented message access system and the balance of resources in the system can be accessed from the fragmented message to meet the requirements. At least two of the plurality of second random sequences are selected as the second random sequence of the selection RAM.
  • the number of second random sequences should not be too large. If the number of second random sequences is too large, the storage resources of the RAM are wasted.
  • the method further includes: the first random sequence and the at least two second random sequences are generated by using a preset pseudo random sequence generator. It should be noted that the first random sequence and the at least two second random sequences may be generated in various manners, which is not specifically limited in the embodiment of the present invention.
  • the method further includes: setting a second address register corresponding to the number of the second random sequence and storing the second random sequence, and correspondingly, according to the obtained second random sequence and the elements of the second random sequence and the RAM
  • Corresponding relationship obtaining RAM is specifically: obtaining an element of the second random sequence according to the current address of the second address register of the obtained second random sequence; obtaining the correspondence between the element of the second random sequence and the element of the second random sequence and the RAM RAM; if the current address of the second address register is not the maximum value, the current address of the second address register is incremented by one; if the current address of the second address register is the maximum value, the second address register is set to zero.
  • FIG. 2 is a schematic flowchart of a detailed embodiment of a method for improving RAM access efficiency according to an embodiment of the present invention, where the method includes:
  • the pseudo random sequence generator configures the first random sequence to be 2130, and the four second random sequences are 012345, 450123, 234510, and 231450, respectively;
  • the elements 0, 1, 2, and 3 of the first random sequence correspond to the second random sequences 012345, 450123, 234510, and 231450, respectively.
  • the first address register storing the first random sequence 2130 is L1
  • the second address registers storing the second random sequence 012345, 450123, 234510, and 231450 are respectively L20, L21, L22, L23, and the initial values of the address registers are all 0.
  • the fragment packet access system has six RAM buffer chips attached, so the number of elements of the second random sequence is 6, and each element in the second random sequence corresponds to a RAM buffer chip;
  • the number of two random sequences is set to 4, so the number of elements of the first random sequence is 4.
  • step is only performed when the fragmented message access system is powered on. After the fragmented message access system is powered on, the first random sequence and the second random sequence are not reconfigured.
  • S203 Obtain a corresponding second random sequence 234510 according to element 2 of the first random sequence
  • An embodiment of the present invention provides a method and apparatus for improving RAM access efficiency, and obtaining a second random sequence according to a preset first random sequence and a correspondence between an element of the first random sequence and a second random sequence;
  • the second random sequence and the correspondence between the elements of the second random sequence and the RAM obtain the RAM;
  • the write/read operation is performed on the message fragments in the RAM, so that the tail of the message is avoided by randomly selecting the RAM in a period of time
  • the fragmented message that cannot reach the fragment length is repeatedly written into one or more RAMs, and the fragmented message at the end of the message is uniformly written into each RAM, thereby maximizing the bandwidth of each RAM and improving the bandwidth.
  • the access efficiency of the RAM in the fragmented message access system is performed by randomly selecting the RAM in a period of time.
  • FIG. 3 is a schematic structural diagram of an apparatus 30 for improving RAM access efficiency according to an embodiment of the present invention.
  • the apparatus includes: a first obtaining unit 301, a second obtaining unit 302, and a reading and writing unit 303, where:
  • the first obtaining unit 301 is configured to obtain a second random sequence according to a preset first random sequence and a correspondence between an element of the first random sequence and the second random sequence; wherein, the first random sequence
  • the number of elements of the machine sequence is consistent with the number of the second random sequence, each element of the first random sequence is different from each other and corresponds to a different second random sequence, and the number of elements of the first random sequence is at least two One
  • the second obtaining unit 302 is configured to obtain a RAM according to the second random sequence obtained by the first obtaining unit 301 and the correspondence between the elements of the second random sequence and the RAM; wherein the number of elements of the second random sequence and the number of RAMs Consistently, each element of the second random sequence is different from each other and corresponds to a different RAM;
  • the read/write unit 303 is configured to perform a write/read operation on the message fragment in the RAM obtained by the second obtaining unit 302.
  • a first address register storing a first random sequence is set, and the first obtaining unit 301 is configured to: obtain an element of the first random sequence according to a current address of the first address register; The correspondence between the element of the first random sequence and the second random sequence obtains the second random sequence; if the current address of the first address register is not the maximum value, the current address of the first address register is incremented by one; if the first address register is When the current address is at the maximum value, the first address register is set to zero.
  • a second address register corresponding to the number of second random sequences and holding the second random sequence is set, and the second obtaining unit 302 is configured as a second according to the second random sequence obtained by the first obtaining unit 301.
  • the current address of the address register obtains an element of the second random sequence; the RAM is obtained according to the element of the second random sequence and the correspondence between the element of the second random sequence and the RAM; if the current address of the second address register is not the maximum value, then The current address of the second address register is incremented by one; if the current address of the second address register is the maximum value, the second address register is set to zero.
  • FIG. 4 is a schematic structural diagram of another apparatus 30 for improving RAM access efficiency according to an embodiment of the present invention.
  • the apparatus further includes a pseudo random sequence generator 304 configured to generate a first random sequence and at least two. The second random sequence.
  • the embodiment of the invention further provides a computer storage medium, wherein the computer storage medium stores computer executable instructions, and the computer executable instructions are used in the method for improving random access memory RAM access efficiency in the above technical solution. At least one of them; specifically at least one of the methods shown in 1 and 2.
  • the computer storage medium in this embodiment may correspond to various storage media such as an optical disk, a hard disk, a flash disk or a magnetic tape, and may be a non-transitory storage medium.
  • embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention can take the form of a hardware embodiment, a software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.

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Abstract

一种提高RAM存取效率的方法，该方法包括：根据预先设置的第一随机序列以及所述第一随机序列的元素与第二随机序列的对应关系获得所述第二随机序列(S101)；根据所述获得的第二随机序列以及所述第二随机序列的元素与RAM的对应关系获得所述RAM(S102)；在所述RAM中对报文分片进行写/读操作(S103)。同时也提供一种提高RAM存取效率的装置及计算机存储介质。

Description

提高RAM存取效率的方法、装置和计算机存储介质 技术领域
本发明涉及移动终端领域，尤其涉及一种提高随机存取存储器(random access memory，RAM)存取效率的方法、装置和计算机存储介质。
背景技术
随着网络容量与业务的不断增长，报文处理过程中报文缓存在容量和带宽上的要求越来越高。现有的分片报文存取系统使用多片缓存芯片，如RAM，来存取报文。由于每个报文的处理都是经过写入-处理-读出这样的过程，即每个报文都是写一次、读一次，为了平衡各片缓存芯片的带宽，会将同一报文分片写入不同的缓存芯片。
但是，缓存芯片每次存取报文有长度要求，例如，双倍速率同步动态随机存储器(Double Data Rate Synchronous Dynamic Random Access Memory，DDR SDRAM)每次发送的读/写命令要求为64字节的整数倍。例如，一个65字节的报文实际需要128字节的读/写命令来发送。具体来说，该65字节的报文按64字节一片分为两片，其中一片报文为64个字节，另一片报文有效字节仅为1字节。若分片报文存取系统有两片DDR SDRAM缓存芯片，那么该65字节报文按分成的两片报文分别存入上述两片DDR SDRAM。这样，其中一片DDR SDRAM仅存入1字节分片报文。
可以看出，现有的分片报文存取系统在进行读写操作时，由于需要将报文切分为固定长度的分片报文，那么当其中的一片分片报文包含的有效字节比较少时，会造成某些缓存芯片固定存入有效字节比较少的分片报文，这样浪费了较大的RAM缓存空间，降低了RAM的存取效率。
发明内容
本发明实施例期望提供一种提高RAM存取效率的方法、装置和计算机存储介质，能够至少部分提高分片报文存取系统中RAM的存取效率。
本发明实施例的技术方案是这样实现的：
第一方面，本发明实施例提供了一种提高随机存取存储器RAM存取效率的方法，包括：根据预先设置的第一随机序列以及所述第一随机序列的元素与第二随机序列的对应关系获得所述第二随机序列；其中，所述第一随机序列的元素个数与所述第二随机序列的个数一致，所述第一随机序列的每个元素互不相同且分别对应着不同的所述第二随机序列，所述第一随机序列的元素个数为至少两个；根据所述获得的第二随机序列以及所述第二随机序列的元素与RAM的对应关系获得所述RAM；其中，所述第二随机序列的元素个数与所述RAM的个数一致，所述第二随机序列的每个元素互不相同且分别对应着不同的所述RAM；在所述RAM中对报文分片进行写/读操作。
在上述实施例中，设置一个保存所述第一随机序列的第一地址寄存器，相应地，所述根据预先设置的第一随机序列以及所述第一随机序列的元素与第二随机序列的对应关系获得所述第二随机序列，具体为：根据所述第一地址寄存器的当前地址获得所述第一随机序列的元素；根据所述第一随机序列的元素以及所述第一随机序列的元素与第二随机序列的对应关系获得所述第二随机序列；若所述第一地址寄存器的当前地址不为最大值，则所述第一地址寄存器的当前地址加一；若所述第一地址寄存器的当前地址为最大值，则所述第一地址寄存器置零。
在上述实施例中，设置与所述第二随机序列的个数对应的且保存所述第二随机序列的第二地址寄存器，相应地，所述根据所述获得的第二随机序列以及所述第二随机序列的元素与RAM的对应关系获得所述RAM，具 体为：根据所述获得的第二随机序列的第二地址寄存器的当前地址获得所述第二随机序列的元素；根据所述第二随机序列的元素以及所述第二随机序列的元素与RAM的对应关系获得所述RAM；若所述第二地址寄存器的当前地址不为最大值，则所述第二地址寄存器的当前地址加一；若所述第二地址寄存器的当前地址为最大值，则所述第二地址寄存器置零。
在上述实施例中，所述第一随机序列和至少两个第二随机序列通过预先设置的伪随机序列发生器产生。
第二方面，本发明实施例提供了一种提高随机存取存储器RAM存取效率的装置，其中，所述装置包括：第一获得单元、第二获得单元及读写单元，其中：所述第一获得单元，配置为根据预先设置的第一随机序列以及所述第一随机序列的元素与第二随机序列的对应关系获得所述第二随机序列；其中，所述第一随机序列的元素个数与所述第二随机序列的个数一致，所述第一随机序列的每个元素互不相同且分别对应着不同的所述第二随机序列，所述第一随机序列的元素个数为至少两个；所述第二获得单元，配置为根据所述第一获得单元获得的第二随机序列以及所述第二随机序列的元素与RAM的对应关系获得所述RAM；其中，所述第二随机序列的元素个数与所述RAM的个数一致，所述第二随机序列的每个元素互不相同且分别对应着不同的所述RAM；所述读写单元，配置为在所述第二获得单元获得的所述RAM中对报文分片进行写/读操作。
在上述实施例中，设置一个保存所述第一随机序列的第一地址寄存器，相应地，所述第一获得单元，配置为：根据所述第一地址寄存器的当前地址获得所述第一随机序列的元素；根据所述第一随机序列的元素以及所述第一随机序列的元素与第二随机序列的对应关系获得所述第二随机序列；若所述第一地址寄存器的当前地址不为最大值，则所述第一地址寄存器的当前地址加一；若所述第一地址寄存器的当前地址为最大值，则所述第一 地址寄存器置零。
在上述实施例中，设置与所述第二随机序列的个数对应的且保存所述第二随机序列的第二地址寄存器，所述第二获得单元，配置为根据所述第一获得单元获得的第二随机序列的第二地址寄存器的当前地址获得所述第二随机序列的元素；根据所述第二随机序列的元素以及所述第二随机序列的元素与RAM的对应关系获得所述RAM；若所述第二地址寄存器的当前地址不为最大值，则所述第二地址寄存器的当前地址加一；若所述第二地址寄存器的当前地址为最大值，则所述第二地址寄存器置零。
在上述实施例中，所述装置还包括伪随机序列发生器，配置为产生第一随机序列和至少两个第二随机序列。
第三方面，本发明实施例还提供一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于执行前述提高随机存取存储器RAM存取效率的方法的至少其中之一。
本发明实施例提供了一种提高RAM存取效率的方法及装置，根据预先设置的第一随机序列以及第一随机序列的元素与第二随机序列的对应关系获得第二随机序列；根据获得的第二随机序列以及第二随机序列的元素与RAM的对应关系获得RAM；在获得的RAM中对报文分片进行写/读操作，这样，通过在一段周期内随机选择RAM，避免了将报文尾部不能达到分片长度的分片报文反复写入某一个或多个RAM中，实现了将报文尾部的分片报文均匀写入各个RAM中，最大限度的利用各个RAM的带宽，提高了分片报文存取系统中RAM的存取效率。
附图说明
图1为本发明实施例提供的一种提高RAM存取效率的方法的流程示意图；
图2为本发明实施例提供的提高RAM存取效率的方法的详细实施例的 流程示意图；
图3为本发明实施例提供的一种提高RAM存取效率的装置的结构示意图；
图4为本发明实施例提供的另一种提高RAM存取效率的装置的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，应当理解，以下所说明的优选实施例仅用于说明和解释本发明，并不用于限定本发明。
图1为本发明实施例提供的一种提高RAM存取效率的方法的流程示意图，该方法包括：
S101：根据预先设置的第一随机序列以及第一随机序列的元素与第二随机序列的对应关系获得第二随机序列；其中，第一随机序列的元素个数与第二随机序列的个数一致，第一随机序列的每个元素互不相同且分别对应着不同的第二随机序列，第一随机序列的元素个数为至少两个；
需要说明的是，由于第一随机序列的元素个数与第二随机序列的个数相同，且第一随机序列的每个元素互不相同并且分别对应着不同的第二随机序列，那么当第一随机序列的每个元素循环一次，每个第二随机序列都会被选取一次。这样，保证了在一个周期内选取每个第二随机序列的概率都是一样的。
举例来说，第一随机序列有4个元素，分别为0、1、2、3，那么，第一随机序列可以为0123，也可以为1203，其中，第一随机序列中的4个不同元素分别对应着4个不同的第二随机序列。
示例性地，还包括：设置一个保存第一随机序列的第一地址寄存器，相应地，根据预先设置的第一随机序列以及第一随机序列的元素与第二随 机序列的对应关系获得第二随机序列具体为：根据第一地址寄存器的当前地址获得第一随机序列的元素；根据第一随机序列的元素以及第一随机序列的元素与第二随机序列的对应关系获得第二随机序列；若第一地址寄存器的当前地址不为最大值，则第一地址寄存器的当前地址加一；若第一地址寄存器的当前地址为最大值，则第一地址寄存器置零。
S102：根据获得的第二随机序列以及第二随机序列的元素与RAM的对应关系获得RAM；其中，第二随机序列的元素个数与RAM的个数一致，第二随机序列的每个元素互不相同且分别对应着不同的RAM。
需要说明的是，由于第二随机序列的元素个数与RAM的个数相同，且第二随机序列的每个元素互不相同且分别对应着不同的RAM，那么，当第二随机序列的每个元素循环一次，每个RAM都会被选取一次。这样，提高了RAM选取的随机性，同时保证了在一个周期内选取每个RAM的概率都是一样的。
需要说明的是，满足上述要求的第二随机序列有很多种，可以根据实际需要，从中选择至少两个用于选择实际RAM的第二随机序列。举例来说，当RAM的数量为6片，根据
Figure PCTCN2015095272-appb-000001
可以看出，满足要求的第二随机序列有720种，在实际应用中，可以根据分片报文存取系统的随机性要求和分片报文存取系统内资源的平衡，从满足要求的多种第二随机序列中选择至少两个作为选择RAM的第二随机序列。
需要补充的是，第二随机序列的个数不宜过大。如果第二随机序列的个数过多会浪费RAM的存储资源。
示例性地，还包括：第一随机序列和至少两个第二随机序列可以通过预设的伪随机序列发生器产生得到。需要说明的是，第一随机序列和至少两个第二随机序列可以通过多种方式产生，本发明实施例对此不做具体限制。
示例性地，还包括：设置与第二随机序列的个数对应的且保存第二随机序列的第二地址寄存器，相应地，根据获得的第二随机序列以及第二随机序列的元素与RAM的对应关系获得RAM具体为：根据获得的第二随机序列的第二地址寄存器的当前地址获得第二随机序列的元素；根据第二随机序列的元素以及第二随机序列的元素与RAM的对应关系获得RAM；若第二地址寄存器的当前地址不为最大值，则第二地址寄存器的当前地址加一；若第二地址寄存器的当前地址为最大值，则第二地址寄存器置零。
S103：在获得的RAM中对报文分片进行写/读操作。
综合步骤S101-S103，可以看出，分片报文存取系统在对报文进行缓存时，首先通过第一随机序列获得第二随机序列，再根据第二随机序列获得实际的RAM缓存芯片。这样一来，避免了不能填满整个分片的报文尾部分片反复写入固定的某个RAM缓存芯片，提高了选择缓存芯片的随机性。
图2为本发明实施例提供的提高RAM存取效率的方法的详细实施例的流程示意图，方法包括：
S201：伪随机序列发生器配置第一随机序列为2130，四个第二随机序列分别为012345、450123、234510、231450；
其中，第一随机序列的元素0、1、2、3分别与第二随机序列012345、450123、234510、231450相对应。
其中，保存第一随机序列2130的第一地址寄存器为L1，保存第二随机序列012345、450123、234510、231450的第二地址寄存器分别为L20、L21、L22、L23，地址寄存器的初始值均为0。
需要说明的是，该分片报文存取系统外挂六片RAM缓存芯片，因此第二随机序列的元素个数为6，且第二随机序列内的每个元素对应一片RAM缓存芯片；由于第二随机序列的个数设置为4，因此第一随机序列的元素个数为4。
需要补充的是，该步骤仅在分片报文存取系统上电时进行，在分片报文存取系统上电后，不再重新配置第一随机序列及第二随机序列。
S202：在接收到分片报文后，根据L1地址寄存器的当前地址0，获得第一随机序列的元素2；此时，L1地址寄存器的当前地址加一即为1；
S203：根据第一随机序列的元素2获得对应的第二随机序列234510；
S204：根据保存第二随机序列234510的L22地址寄存器的当前地址0，获得第二随机序列的元素2；此时，L22地址寄存器的当前地址加一即为1；
S205：根据第二随机序列的元素2获得对应的RAM；
S206：在获得的RAM中对报文分片进行写/读操作。
综合步骤S201-S206，可以看出，在对分片报文进行处理时，不同于现有技术将分片报文顺序写入六片RAM，而是在一个周期内随机从六片RAM中选择一片进行写/读操作。
本发明实施例提供了一种提高RAM存取效率的方法及装置，根据预先设置的第一随机序列以及第一随机序列的元素与第二随机序列的对应关系获得第二随机序列；根据获得的第二随机序列以及第二随机序列的元素与RAM的对应关系获得RAM；在RAM中对报文分片进行写/读操作，这样，通过在一段周期内随机选择RAM，避免了将报文尾部不能达到分片长度的分片报文反复写入某一个或多个RAM中，实现了将报文尾部的分片报文均匀写入各个RAM中，最大限度的利用各个RAM的带宽，提高了分片报文存取系统中RAM的存取效率。
图3为本发明实施例提供的一种提高RAM存取效率的装置30的结构示意图，装置包括：第一获得单元301、第二获得单元302及读写单元303，其中：
第一获得单元301，配置为根据预先设置的第一随机序列以及第一随机序列的元素与第二随机序列的对应关系获得第二随机序列；其中，第一随 机序列的元素个数与第二随机序列的个数一致，第一随机序列的每个元素互不相同且分别对应着不同的第二随机序列，第一随机序列的元素个数为至少两个；
第二获得单元302，配置为根据第一获得单元301获得的第二随机序列以及第二随机序列的元素与RAM的对应关系获得RAM；其中，第二随机序列的元素个数与RAM的个数一致，第二随机序列的每个元素互不相同且分别对应着不同的RAM；
读写单元303，配置为在第二获得单元302获得的RAM中对报文分片进行写/读操作。
示例性地，设置一个保存第一随机序列的第一地址寄存器，第一获得单元301，配置为：根据第一地址寄存器的当前地址获得第一随机序列的元素；根据第一随机序列的元素以及第一随机序列的元素与第二随机序列的对应关系获得第二随机序列；若第一地址寄存器的当前地址不为最大值，则第一地址寄存器的当前地址加一；若第一地址寄存器的当前地址为最大值，则第一地址寄存器置零。
示例性地，设置与第二随机序列的个数对应的且保存第二随机序列的第二地址寄存器，第二获得单元302，配置为根据第一获得单元301获得的第二随机序列的第二地址寄存器的当前地址获得第二随机序列的元素；根据第二随机序列的元素以及第二随机序列的元素与RAM的对应关系获得RAM；若第二地址寄存器的当前地址不为最大值，则第二地址寄存器的当前地址加一；若第二地址寄存器的当前地址为最大值，则第二地址寄存器置零。
示例性地，图4为本发明实施例提供的另一种提高RAM存取效率的装置30的结构示意图，该装置还包括伪随机序列发生器304，配置为产生第一随机序列和至少两个第二随机序列。
本发明实施例还提供了一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于上述技术方案中提高随机存取存储器RAM存取效率的方法的至少其中之一；具体如1和图2所示方法的至少其中之一。
本实施例中所述计算机存储介质可对应于光盘、硬盘、闪盘或磁带各种存储介质，可选为非瞬间存储介质。
本领域内的技术人员应明白，本发明的实施例可提供为方法、系统、或计算机程序产品。因此，本发明可采用硬件实施例、软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器和光学存储器等)上实施的计算机程序产品的形式。
本发明是参照根据本发明实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机 实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
以上所述，仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围；凡按照本发明原理所作的修改，都应当理解为落入本发明的保护范围。

Claims (9)

  1. 一种提高随机存取存储器RAM存取效率的方法，其中，包括：
    根据预先设置的第一随机序列以及所述第一随机序列的元素与第二随机序列的对应关系获得所述第二随机序列；其中，所述第一随机序列的元素个数与所述第二随机序列的个数一致，所述第一随机序列的每个元素互不相同且分别对应着不同的所述第二随机序列，所述第一随机序列的元素个数为至少两个；
    根据所述获得的第二随机序列以及所述第二随机序列的元素与RAM的对应关系获得所述RAM；其中，所述第二随机序列的元素个数与所述RAM的个数一致，所述第二随机序列的每个元素互不相同且分别对应着不同的所述RAM；
    在所述RAM中对报文分片进行写/读操作。
  2. 根据权利要求1所述的方法，其中，设置一个保存所述第一随机序列的第一地址寄存器，相应地，所述根据预先设置的第一随机序列以及所述第一随机序列的元素与第二随机序列的对应关系获得所述第二随机序列，具体为：
    根据所述第一地址寄存器的当前地址获得所述第一随机序列的元素；
    根据所述第一随机序列的元素以及所述第一随机序列的元素与第二随机序列的对应关系获得所述第二随机序列；
    若所述第一地址寄存器的当前地址不为最大值，则所述第一地址寄存器的当前地址加一；若所述第一地址寄存器的当前地址为最大值，则所述第一地址寄存器置零。
  3. 根据权利要求2所述的方法，其中，设置与所述第二随机序列的个数对应的且保存所述第二随机序列的第二地址寄存器，相应地，所述根据 所述获得的第二随机序列以及所述第二随机序列的元素与RAM的对应关系获得所述RAM，具体为：
    根据所述获得的第二随机序列的第二地址寄存器的当前地址获得所述第二随机序列的元素；
    根据所述第二随机序列的元素以及所述第二随机序列的元素与RAM的对应关系获得所述RAM；
    若所述第二地址寄存器的当前地址不为最大值，则所述第二地址寄存器的当前地址加一；若所述第二地址寄存器的当前地址为最大值，则所述第二地址寄存器置零。
  4. 根据权利要求1至3任一项所述的方法，其中，所述第一随机序列和至少两个第二随机序列通过预先设置的伪随机序列发生器产生。
  5. 一种提高随机存取存储器RAM存取效率的装置，所述装置包括：第一获得单元、第二获得单元及读写单元，其中：
    所述第一获得单元，配置为根据预先设置的第一随机序列以及所述第一随机序列的元素与第二随机序列的对应关系获得所述第二随机序列；其中，所述第一随机序列的元素个数与所述第二随机序列的个数一致，所述第一随机序列的每个元素互不相同且分别对应着不同的所述第二随机序列，所述第一随机序列的元素个数为至少两个；
    所述第二获得单元，配置为根据所述第一获得单元获得的第二随机序列以及所述第二随机序列的元素与RAM的对应关系获得所述RAM；其中，所述第二随机序列的元素个数与所述RAM的个数一致，所述第二随机序列的每个元素互不相同且分别对应着不同的所述RAM；
    所述读写单元，配置为在所述第二获得单元获得的所述RAM中对报文分片进行写/读操作。
  6. 根据权利要求5所述的装置，其中，
    设置一个保存所述第一随机序列的第一地址寄存器，
    所述第一获得单元，配置为：根据所述第一地址寄存器的当前地址获得所述第一随机序列的元素；根据所述第一随机序列的元素以及所述第一随机序列的元素与第二随机序列的对应关系获得所述第二随机序列；若所述第一地址寄存器的当前地址不为最大值，则所述第一地址寄存器的当前地址加一；若所述第一地址寄存器的当前地址为最大值，则所述第一地址寄存器置零。
  7. 根据权利要求6所述的装置，其中，
    设置与所述第二随机序列的个数对应的且保存所述第二随机序列的第二地址寄存器，
    所述第二获得单元，配置为根据所述第一获得单元获得的第二随机序列的第二地址寄存器的当前地址获得所述第二随机序列的元素；根据所述第二随机序列的元素以及所述第二随机序列的元素与RAM的对应关系获得所述RAM；若所述第二地址寄存器的当前地址不为最大值，则所述第二地址寄存器的当前地址加一；若所述第二地址寄存器的当前地址为最大值，则所述第二地址寄存器置零。
  8. 根据权利要求5至7任一项所述的装置，其中，还包括伪随机序列发生器，配置为产生第一随机序列和至少两个第二随机序列。
  9. 一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于执行权利要求1至4所述提高随机存取存储器RAM存取效率的方法的至少其中之一。
PCT/CN2015/095272 2015-05-25 2015-11-23 提高ram存取效率的方法、装置和计算机存储介质 WO2016188063A1 (zh)

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US20140007250A1 (en) * 2012-06-15 2014-01-02 The Regents Of The University Of California Concealing access patterns to electronic data storage for privacy

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CN1971562A (zh) * 2006-11-29 2007-05-30 华中科技大学 面向对象存储系统中的对象分布方法
US20140007250A1 (en) * 2012-06-15 2014-01-02 The Regents Of The University Of California Concealing access patterns to electronic data storage for privacy

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