WO2016179968A1 - 一种队列管理方法、装置及存储介质 - Google Patents

一种队列管理方法、装置及存储介质 Download PDF

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Publication number
WO2016179968A1
WO2016179968A1 PCT/CN2015/092929 CN2015092929W WO2016179968A1 WO 2016179968 A1 WO2016179968 A1 WO 2016179968A1 CN 2015092929 W CN2015092929 W CN 2015092929W WO 2016179968 A1 WO2016179968 A1 WO 2016179968A1
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Prior art keywords
pointer
queue
chip
operation request
ram
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English (en)
French (fr)
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周谦
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Sanechips Technology Co Ltd
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Sanechips Technology Co Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/50—Queue scheduling
    • H04L47/62—Queue scheduling characterised by scheduling criteria
    • H04L47/621—Individual queue per connection or flow, e.g. per VC
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9015—Buffering arrangements for supporting a linked list
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9036—Common buffer combined with individual queues

Definitions

  • the present invention relates to a related art of queue management in the field of communication technologies, and in particular, to a queue management method, apparatus, and storage medium.
  • an implementation method of queue management adopts a fixed allocation space, that is, each queue allocates a fixed space, and address spaces of different queues cannot be shared.
  • This method is simple to implement, but since the address space of different queues cannot be shared, space waste is easily caused. And when there are a large number of queues, the space allocated by each queue is quite limited, and the anti-burst capability is weak; another implementation method is to use a shared space, to make a linked list for each queue, and to set a packet address space belonging to the same queue. Linked up, this method can improve the cache utilization, but the control is complicated, especially in the case of multi-linked list mode, and at the same time facing the instantaneous large-scale traffic of the network burst, the anti-burst capability is still insufficient.
  • the embodiment of the present invention is to provide a queue management method, device, and storage medium, which can effectively avoid packet loss under traffic bursts while improving access efficiency and reducing power consumption.
  • An embodiment of the present invention provides a queue management method, where the method includes:
  • the current operation request is an enqueue operation request of the message descriptor, according to the enqueue operation Requesting and buffering of on-chip random access memory (RAM), storing the message descriptor to an off-chip double-rate synchronous dynamic random access memory (DDR) or on-chip RAM And update the pointer list information;
  • RAM on-chip random access memory
  • the location information includes on-chip RAM location information and off-chip DDR location information.
  • the storing the message descriptor to the off-chip DDR or the on-chip RAM according to the enqueue operation request and the buffering condition of the on-chip RAM includes:
  • the queue number in the enqueue operation request is extracted, and the message descriptor is stored in the on-chip RAM according to the queue number.
  • the update pointer list information when it is determined that the current operation request is an enqueue operation request of the message descriptor, includes:
  • Extracting a queue number in the enqueue operation request Reading a corresponding queue tail pointer and a idle head pointer according to the queue number, updating the queue tail pointer to an address indicated by the idle head pointer, and then The idle header pointer points to the next address in the pointer list.
  • the updated pointer list information when it is determined that the current operation request is a dequeuing operation request of the message descriptor, the updated pointer list information includes:
  • Extracting a queue number in the enqueue operation request Reading a corresponding queue head pointer and an idle tail pointer according to the queue number, updating the idle tail pointer to an address indicated by the queue head pointer, and then The queue head pointer points to the next address in the pointer list.
  • the obtaining a queue head pointer corresponding to the dequeuing operation request is in the finger
  • the location information in the pin list, and the corresponding message descriptors are read according to the location information, including:
  • the corresponding message descriptor in the on-chip RAM is read according to the queue number.
  • the embodiment of the invention further provides a queue management device, the device comprising: a first processing module and a second processing module; wherein
  • the first processing module is configured to determine that the current operation request is an enqueue operation request of the message descriptor, and describe the message according to the enqueue operation request and the buffering condition of the on-chip random access memory RAM. Stores to the off-chip double rate synchronous dynamic random access memory DDR or on-chip RAM and updates the pointer list information;
  • the second processing module is configured to determine that the current operation request is a dequeue operation request of the message descriptor, and obtain location information of the queue head pointer corresponding to the dequeue operation request in the pointer list, according to the The location information reads the corresponding message descriptor and updates the pointer list information; wherein the location information includes on-chip RAM location information and off-chip DDR location information.
  • the first processing module is configured to calculate an off-chip DDR address when the current on-chip RAM cache has reached an upper limit according to the enqueue operation request, and the report is obtained according to the obtained off-chip DDR address.
  • the text descriptor is stored to the off-chip DDR;
  • the queue number in the enqueue operation request is extracted, and the message descriptor is stored in the on-chip RAM according to the queue number.
  • the first processing module is configured to extract a queue number in the enqueue operation request, read a corresponding queue tail pointer and a idle head pointer according to the queue number, and update the queue tail pointer to point Describe the address currently indicated by the idle head pointer, and then refer to the idle header The pin points to the next address in the list of pointers.
  • the second processing module is configured to extract a queue number in the enqueue operation request, read a corresponding queue head pointer and an idle tail pointer according to the queue number, and update the idle tail pointer to point The address currently indicated by the queue head pointer is then directed to the next address in the pointer list.
  • the second processing module is configured to extract a queue number in the enqueue operation request, read a corresponding queue head pointer according to the queue number, and determine that the queue head pointer is in the pointer list.
  • the off-chip DDR address is calculated, and the corresponding message descriptor in the off-chip DDR is read according to the obtained off-chip DDR address;
  • the corresponding message descriptor in the on-chip RAM is read according to the queue number.
  • the embodiment of the present invention further provides a computer storage medium, where the computer storage medium stores a computer program configured to execute the foregoing queue management method of the embodiment of the present invention.
  • the queue management method, device and storage medium provided by the embodiment of the present invention; determining that the current operation request is an enqueue operation request of the message descriptor, according to the enqueue operation request and the on-chip RAM cache situation,
  • the message descriptor is stored in the off-chip DDR or the on-chip RAM, and the pointer list information is updated; the current operation request is determined to be a dequeue operation request of the message descriptor, and the queue head pointer corresponding to the dequeue operation request is obtained.
  • the location information in the pointer list reads the corresponding message descriptor according to the location information, and updates the pointer list information; wherein the location information includes on-chip RAM location information and off-chip DDR location information.
  • the queue is managed by the pointer list and the on-chip plus off-chip method, and the storage location of the message descriptor is determined according to the buffer condition of the on-chip RAM, thereby effectively improving the access efficiency and reducing the power consumption while avoiding the traffic burst.
  • the packet loss situation is effectively improving the access efficiency and reducing the power consumption while avoiding the traffic burst.
  • FIG. 1 is a schematic flowchart of a queue management method according to an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of initializing a pointer list RAM according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of data relationships between respective RAMs according to an embodiment of the present invention.
  • FIG. 4 is a schematic flowchart of a queue management method according to Embodiment 2 of the present invention.
  • FIG. 5 is a schematic structural diagram of a queue management apparatus according to an embodiment of the present invention.
  • determining that the current operation request is an enqueue operation request of the message descriptor, and storing the message descriptor to the off-chip according to the enqueue operation request and the buffering condition of the on-chip RAM.
  • DDR or on-chip RAM and updating pointer list information; determining that the current operation request is a dequeue operation request of the message descriptor, and acquiring location information of the queue head pointer corresponding to the dequeue operation request in the pointer list, Reading the corresponding message descriptor according to the location information, and updating the pointer list information; wherein the location information includes on-chip RAM location information and off-chip DDR location information.
  • FIG. 1 is a schematic flowchart of a queue management method according to an embodiment of the present invention. As shown in FIG. 1 , a queue management method according to an embodiment of the present invention includes:
  • Step 101 Determine that the current operation request is an enqueue operation request of the message descriptor, and store the message descriptor to an off-chip DDR or an on-chip RAM according to the enqueue operation request and the buffering condition of the on-chip RAM. And update the pointer list information;
  • the storing the message descriptor to the off-chip DDR or the on-chip RAM according to the enqueue operation request and the buffering condition of the on-chip RAM includes:
  • the queue number in the enqueue operation request is extracted, and the message descriptor is stored in the on-chip RAM according to the queue number.
  • the determining that the current on-chip RAM has reached a maximum limit includes:
  • the preset buffer size of the on-chip RAM and the number of non-free pointers in the current pointer list recorded by the cache counter in real time it is determined whether the current on-chip RAM cache has reached the upper limit, if the number of non-free pointers in the current pointer list is less than the preset
  • the buffer size of the on-chip RAM determines that the current on-chip RAM cache has not reached the upper limit; otherwise, it determines that the current on-chip RAM cache has reached the upper limit;
  • the on-chip RAM is used to buffer message descriptor information, and its size can be set according to actual needs.
  • the size of the on-chip RAM is 4k, that is, the address of the on-chip RAM is 0. ⁇ 4k-1, that is, the depth of the on-chip RAM is 4 ⁇ 1024 addresses.
  • the calculating the off-chip DDR address comprises:
  • the off-chip DDR address may be a base address + a link intra-slice position offset; wherein The base address is a base address of the system configuration, and the message descriptor is stored in the off-chip DDR; the positional offset of the linked list is a relative address, and if the base address is 4k, the position of the linked list is offset. Move to 0. If the base address is 4k+1, the positional offset of the linked list is 1.
  • the updating the pointer list information includes:
  • the tail pointer RAM is used to store a queue tail pointer of all queues, and indicates a queue status of each queue; wherein the queue status includes: empty and non-empty; the tail pointer RAM
  • the size/depth of the tail can be set according to the actual situation.
  • the depth of the tail pointer RAM is equal to the number of queues.
  • the depth of the tail pointer RAM is 256 addresses, and the initialization is performed. The highest bit after the tail pointer RAM is 1 or all 1s, and the initialized queue state is empty;
  • a head pointer RAM for storing a queue head pointer of all queues, and indicating a queue status of each queue; wherein the queue status includes: null and non-empty; the size/depth of the head pointer RAM may be According to the actual situation, in one embodiment, the depth of the head pointer RAM is equal to the number of queues. In this embodiment, the depth of the head pointer RAM is 256 addresses, after the head pointer RAM is initialized. The highest bit is 1 or all 1s. It can be seen that the initialized queue status is empty.
  • the pointer linked list RAM is configured to store the pointer linked list, so that the queue pointer linked list and the free pointer linked list share a RAM, thereby eliminating the need for a separate first in first out queue (FIFO, First Input First Output) to store the idle pointer, thereby saving
  • FIFO First Input First Output
  • the hardware resource; the pointer list table RAM size can be set according to actual needs.
  • the on-chip RAM has a size of 4k, and the pointer list includes a pointer to the next address, which is initialized to a
  • the null pointer list as shown in Figure 2, the ptr RAM is the pointer list RAM, which is initialized.
  • the address of the ptr RAM is from 0 to 8191, and the content stored in the ptr RAM is the next address value, thereby forming a pointer list.
  • the pointer list includes a non-free pointer and a free pointer; wherein the number of the non-free pointers characterizes the total number of addresses occupied by the on-chip RAM and the message descriptor in the off-chip DDR, once for each queue entry
  • FIG. 3 is a schematic diagram of data relationships between the RAMs according to the embodiment of the present invention. ;
  • head_ptr ram is the head pointer RAM
  • tail_ptr ram is the tail pointer RAM.
  • Ptr ram is pointer list RAM
  • desc ram is on-chip RAM; among them, black in the pointer list RAM is a queue member in a queue, there are 6 queue members, for convenience of explanation, they are marked as 1 to 6 in order.
  • the address information of the latter data block is stored in the previous data block, because the label 6 is the last data of the queue, so the data in the pointer list RAM is invalid data; according to the head pointer and the tail pointer It can be seen that the queue number of the queue is 11, the address of the data block corresponding to the label 1 is determined by the value stored by the head pointer RAM address 11, and the data block address corresponding to the label 6 is determined by the value stored in the tail pointer RAM address 11.
  • Step 102 Determine that the current operation request is a dequeue operation request of the message descriptor, obtain location information of the queue head pointer corresponding to the dequeue operation request in the pointer list, and read corresponding information according to the location information.
  • Message descriptor and update pointer list information
  • the location information includes on-chip RAM location information and off-chip DDR location information
  • And acquiring the location information of the queue head pointer corresponding to the dequeuing operation request in the pointer list, and reading the corresponding message descriptor according to the location information includes:
  • the off-chip DDR address reads the corresponding message descriptor in the off-chip DDR according to the obtained off-chip DDR address;
  • the corresponding message descriptor in the on-chip RAM is read according to the queue number.
  • the updating the pointer list information includes:
  • Extracting a queue number in the enqueue operation request Reading a corresponding queue head pointer and an idle tail pointer according to the queue number, updating the idle tail pointer to an address indicated by the queue head pointer, and then The queue head pointer points to the next address in the pointer list.
  • the queue management method of the embodiment of the present invention includes:
  • Step 401 Receive an operation request and determine whether it is an enqueue operation request or a dequeue operation request of the message descriptor. If it is a enqueue operation request, step 402 is performed; if it is a dequeue operation request, step 404 is performed.
  • Step 402 Store the message descriptor into an off-chip DDR or an on-chip RAM according to the enqueue operation request and the buffering condition of the on-chip RAM;
  • the step includes: determining, according to the enqueue operation request, that the current on-chip RAM has reached the upper limit, calculating an off-chip DDR address, and storing the message descriptor to an off-chip DDR according to the obtained off-chip DDR address;
  • the queue number in the enqueue operation request is extracted, and the message descriptor is stored in the on-chip RAM according to the queue number.
  • the determining that the current on-chip RAM has reached a maximum limit includes:
  • the preset buffer size of the on-chip RAM and the number of non-free pointers in the current pointer list recorded by the cache counter in real time it is determined whether the current on-chip RAM cache has reached the upper limit, if the number of non-free pointers in the current pointer list is less than the preset
  • the buffer size of the on-chip RAM determines that the current on-chip RAM cache has not reached the upper limit; otherwise, it determines that the current on-chip RAM cache has reached the upper limit;
  • the on-chip RAM is used to buffer the message descriptor information, and the size thereof can be set according to actual needs.
  • the size of the on-chip RAM is 4k, that is, the address of the on-chip RAM is 0.
  • ⁇ 4k-1 that is, the depth of the on-chip RAM is 4 ⁇ 1024 addresses.
  • Step 403 Update the pointer list information, and perform step 406;
  • the step includes: extracting a queue number in the enqueue operation request, reading a corresponding queue tail pointer in the tail pointer RAM and a free head pointer in the pointer list table RAM according to the queue number, and updating the queue tail pointer to the location Describe the address currently indicated by the idle head pointer, and then point the free head pointer to the next address in the pointer list;
  • the tail pointer RAM is used to store a queue tail pointer of all queues, and indicates a queue status of each queue; wherein the queue status includes: empty and non-empty; the size/depth of the tail pointer RAM may be based on The actual situation is set.
  • the depth of the tail pointer RAM is equal to the number of queues.
  • the depth of the tail pointer RAM is 256 addresses, and the highest value after the tail pointer RAM is initialized. If the bit is 1 or all 1, it can be known that the initialized queue status is empty.
  • a head pointer RAM for storing a queue head pointer of all queues, and indicating a queue status of each queue; wherein the queue status includes: null and non-empty; the size/depth of the head pointer RAM may be According to the actual situation, in one embodiment, the depth of the head pointer RAM is equal to the number of queues. In this embodiment, the depth of the head pointer RAM is 256 addresses, after the head pointer RAM is initialized. The highest bit is 1 or all 1s. It can be seen that the initialized queue status is empty.
  • the pointer linked list RAM is configured to store the pointer linked list, so that the queue pointer linked list and the free pointer linked list share a RAM, thereby eliminating the need for a separate FIFO to store the free pointer, thereby saving hardware resources; the pointer linked list RAM size can be based on Actually, the setting needs to be performed.
  • the size of the on-chip RAM is 4k
  • the pointer list includes a pointer pointing to the next address, and is initialized into a list of empty pointers, as shown in FIG.
  • ptr The RAM is a pointer list RAM, which is initialized, the address of the ptr RAM is from 0 to 8191, and the content stored in the ptr RAM is the next address value, thereby forming a pointer list form; the pointer list includes non-idle pointers and a free pointer; wherein the number of non-free pointers characterizes the total number of addresses occupied by the message descriptors in the on-chip RAM and the off-chip DDR, and the number of non-idle pointers is incremented by one message descriptor per queue.
  • the on-chip RAM has a one-to-one correspondence with a part of the pointer list RAM, The RAM for packet descriptor information, the address information list pointer corresponding to the RAM; a schematic diagram of data relationships between each of Examples RAM embodiment of the present invention shown in Figure 3;
  • head_ptr ram is the head pointer RAM
  • tail_ptr ram is the tail pointer RAM
  • ptr ram is the pointer list RAM
  • desc ram is the on-chip RAM; wherein the black of the pointer list RAM is a queue member in the queue.
  • 6 queue members for convenience of explanation, are marked as 1 to 6 (all are virtual tags) in order, and the previous data block stores the address information of the latter data block, because the label 6 is the last data of the queue.
  • the data in the pointer list RAM is invalid data; according to the head pointer and the tail pointer, the queue number of the queue is 11, and the address of the data block corresponding to the label 1 is determined by the value stored by the head pointer RAM address 11, and the label 6 corresponds to The data block address is determined by the value stored in the tail pointer RAM address 11.
  • Step 404 Acquire location information of a queue head pointer corresponding to the dequeuing operation request in the pointer list, and read a corresponding message descriptor according to the location information.
  • the location information includes on-chip RAM location information and off-chip DDR location information
  • the step includes: extracting a queue number in the enqueue operation request, reading a corresponding queue head pointer in the head pointer RAM according to the queue number, and determining that the position of the queue head pointer in the pointer list is off-chip.
  • the off-chip DDR address is calculated, and the corresponding message descriptor in the off-chip DDR is read according to the obtained off-chip DDR address;
  • the corresponding message descriptor in the on-chip RAM is read according to the queue number.
  • Step 405 Update the pointer list information.
  • the step includes: extracting a queue number in the enqueue operation request, reading a corresponding queue head pointer and an idle tail pointer according to the queue number, and updating the idle tail pointer to point to an address currently indicated by the queue head pointer. And then directing the queue head pointer to the next address in the pointer list.
  • Step 406 End the current processing flow.
  • FIG. 5 is a schematic structural diagram of a queue management apparatus according to an embodiment of the present invention.
  • the configuration of the queue management device includes: a first processing module 51 and a second processing module 52;
  • the first processing module 51 is configured to determine that the current operation request is an enqueue operation request of the message descriptor, and store the message descriptor according to the enqueue operation request and the buffer condition of the on-chip RAM. Off-chip DDR or on-chip RAM, and update pointer list information;
  • the second processing module 52 is configured to determine that the current operation request is a dequeue operation request of the message descriptor, and obtain location information of the queue head pointer corresponding to the dequeue operation request in the pointer list, according to The location information reads the corresponding message descriptor and updates the pointer list information; wherein the location information includes on-chip RAM location information and off-chip DDR location information.
  • the first processing module 51 stores the message descriptor to an off-chip DDR or an on-chip RAM according to the enqueue operation request and the buffering condition of the on-chip RAM, including:
  • the first processing module 51 determines, according to the enqueue operation request, that the current on-chip RAM has reached the upper limit, calculates an off-chip DDR address, and stores the message descriptor into a slice according to the obtained off-chip DDR address.
  • External DDR
  • the first processing module 51 determines that the current upper limit of the on-chip RAM has reached the upper limit, including:
  • the first processing module 51 determines whether the current on-chip RAM cache has reached the upper limit according to the preset buffer size of the on-chip RAM and the number of non-free pointers in the current pointer list recorded by the cache counter in real time, if the current pointer list is not The number of free pointers is smaller than the preset buffer size of the on-chip RAM, and it is determined that the current on-chip RAM cache has not reached the upper limit; otherwise, it is determined that the current on-chip RAM has reached the upper limit;
  • the on-chip RAM is used to buffer message descriptor information, and its size can be set according to actual needs.
  • the size of the on-chip RAM is 4k, that is, the address of the on-chip RAM is 0. ⁇ 4k-1, that is, the depth of the on-chip RAM is 4 ⁇ 1024 addresses.
  • the first processing module 51 updates the pointer list information, including:
  • the first processing module 51 extracts the queue number in the enqueue operation request, reads the corresponding queue tail pointer and the idle head pointer according to the queue number, and updates the queue tail pointer to point to the current idle pointer. The indicated address, and then directing the free head pointer to a next address in the pointer list;
  • the tail pointer RAM is used to store the queue tail pointers of all queues, and indicates the queue status of each queue; wherein the queue status includes: empty and non-empty; the size/depth of the tail pointer RAM may be based on actual conditions.
  • the depth of the tail pointer RAM is equal to the number of queues.
  • the depth of the tail pointer RAM is 256 addresses, and the highest bit after initializing the tail pointer RAM is 1 or all 1, it can be seen that the initialized queue status is empty;
  • a head pointer RAM for storing a queue head pointer of all queues, and indicating a queue status of each queue; wherein the queue status includes: null and non-empty; the size/depth of the head pointer RAM may be According to the actual situation, in one embodiment, the depth of the head pointer RAM is equal to the number of queues. In this embodiment, the depth of the head pointer RAM is 256 addresses, after the head pointer RAM is initialized. The highest bit is 1 or all 1s. It can be seen that the initialized queue status is empty.
  • the pointer linked list RAM is used for storing the pointer linked list, so that the queue pointer linked list and the free pointer linked list share a piece of RAM, thereby eliminating the need for a separate first in first out queue (FIFO, First Input First Output) to store the idle pointer, thereby saving hardware resources.
  • the pointer list RAM size can be set according to actual needs.
  • the on-chip RAM has a size of 4k, and the pointer list includes a pointer pointing to the next address, and is initialized to a null pointer.
  • the ptr RAM is the pointer linked list RAM, which is initialized, the address of the ptr RAM is from 0 to 8191, and the content stored in the ptr RAM is the next address value, thereby forming a pointer list.
  • the pointer list includes a non-free pointer and a free pointer; wherein the number of the non-free pointers characterizes the total number of addresses occupied by the on-chip RAM and the message descriptor in the off-chip DDR, once for each queue entry
  • the text descriptor, the number of non-free pointers is incremented by one, and correspondingly, each time a message descriptor is dequeued, the number of non-free pointers is decremented by one
  • the on-chip RAM has a one-to-one correspondence with a part of the pointer list RAM.
  • the in-chip RAM is message descriptor information, and the pointer list table RAM is corresponding address information;
  • FIG. 3 is a schematic diagram of data relationships between respective RAMs according to an embodiment of the present invention
  • head_ptr ram is the head pointer RAM
  • tail_ptr ram is the tail pointer RAM
  • ptr ram is the pointer list RAM
  • desc ram is the on-chip RAM; wherein the black of the pointer list RAM is a queue member in the queue.
  • 6 queue members for convenience of explanation, are marked as 1 to 6 (all are virtual tags) in order, and the previous data block stores the address information of the latter data block, because the label 6 is the last data of the queue.
  • the data in the pointer list RAM is invalid data; according to the head pointer and the tail pointer, the queue number of the queue is 11, and the address of the data block corresponding to the label 1 is determined by the value stored by the head pointer RAM address 11, and the label 6 corresponds to The data block address is determined by the value stored in the tail pointer RAM address 11.
  • the second processing module 52 acquires location information of the queue head pointer corresponding to the dequeuing operation request in the pointer list, and reads corresponding message descriptors according to the location information, including :
  • the second processing module 52 extracts the queue number in the enqueue operation request, reads the corresponding queue head pointer according to the queue number, and determines that the position of the queue head pointer in the pointer list is off-chip DDR. Calculating an off-chip DDR address, and reading a corresponding message descriptor in the off-chip DDR according to the obtained off-chip DDR address;
  • the corresponding message descriptor in the on-chip RAM is read according to the queue number.
  • the pointer list information includes:
  • the second processing module 52 extracts the queue number in the enqueue operation request, reads the corresponding queue head pointer and the idle tail pointer according to the queue number, and updates the idle tail pointer to point to the current queue head pointer. The indicated address, and then the queue head pointer is directed to the next address in the list of pointers.
  • the first processing module 51 and the second processing module 52 proposed in the embodiments of the present invention may be implemented by a processor, and may also be implemented by a specific logic circuit; wherein the processor may be a processing on a mobile terminal or a server.
  • the processor may be a central processing unit (CPU), a microprocessor (MPU), a digital signal processor (DSP), or a field programmable gate array (FPGA).
  • the queue management method is implemented in the form of a software function module and is sold or used as a separate product, it may also be stored in a computer readable storage medium.
  • the technical solution of the embodiments of the present invention may be embodied in the form of a software product in essence or in the form of a software product stored in a storage medium, including a plurality of instructions.
  • a computer device (which may be a personal computer, server, or network device, etc.) is caused to perform all or part of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read only memory (ROM), a magnetic disk, or an optical disk.
  • program codes such as a USB flash drive, a mobile hard disk, a read only memory (ROM), a magnetic disk, or an optical disk.
  • the embodiment of the present invention further provides a computer storage medium, where the computer storage medium stores a computer program, and the computer program is used to execute the foregoing queue management method of the embodiment of the present invention.

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Abstract

本发明公开了一种队列管理方法，所述方法包括：确定当前的操作请求为报文描述符的入队操作请求，依据所述入队操作请求及片内随机存取存储器(RAM)的缓存情况，将所述报文描述符存储至片外双倍速率同步动态随机存储器(DDR)或片内RAM，并更新指针链表信息；确定当前的操作请求为报文描述符的出队操作请求，获取所述出队操作请求对应的队列头指针在所述指针链表中的位置信息，依据所述位置信息读取对应的报文描述符，并更新指针链表信息；其中，所述位置信息包括片内RAM位置信息及片外DDR位置信息。本发明还公开了一种队列管理装置及存储介质。

Description

一种队列管理方法、装置及存储介质 技术领域
本发明涉及通信技术领域中队列管理的相关技术，尤其涉及一种队列管理方法、装置及存储介质。
背景技术
随着网络中数据业务流量越来越大，流量突发的现象频频发生。目前，队列管理的一种实施方法是采用固定分配空间，即每个队列分配固定的空间，不同队列的地址空间不能共享，该方法实施简单但由于不同队列的地址空间不能共享，容易造成空间浪费，并且当队列数较多时，每个队列分配的空间相当有限，抗突发能力弱；另一种实施方法是采用共享空间，给每个队列做一个链表，把属于同一队列的报文地址空间链接起来，该方法可提高缓存利用率，但控制复杂，尤其采用多链表方式下，同时面对网络突发瞬时超大流量，抗突发能力依然不够。
因此，提供一种队列管理的技术方案，能够在提高访问效率的同时有效的避免流量突发下的丢包情况，已成为亟待解决的问题。
发明内容
有鉴于此，本发明实施例期望提供一种队列管理方法、装置及存储介质，能够在提高访问效率、降低功耗的同时有效的避免流量突发下的丢包情况。
为达到上述目的，本发明实施例的技术方案是这样实现的：
本发明实施例提供了一种队列管理方法，所述方法包括：
确定当前的操作请求为报文描述符的入队操作请求，依据所述入队操 作请求及片内随机存取存储器(RAM，Random-Access Memory)的缓存情况，将所述报文描述符存储至片外双倍速率同步动态随机存储器(DDR，Double Data Rate)或片内RAM，并更新指针链表信息；
确定当前的操作请求为报文描述符的出队操作请求，获取所述出队操作请求对应的队列头指针在所述指针链表中的位置信息，依据所述位置信息读取对应的报文描述符，并更新指针链表信息；其中，所述位置信息包括片内RAM位置信息及片外DDR位置信息。
上述方案中，所述依据所述入队操作请求及片内RAM的缓存情况，将所述报文描述符存储至片外DDR或片内RAM包括：
依据所述入队操作请求确定当前片内RAM的缓存已达上限时，计算片外DDR地址，并依据得到的片外DDR地址将所述报文描述符存储至片外DDR；
确定当前片内RAM的缓存未达到上限时，提取所述入队操作请求中的队列号，并依据所述队列号将所述报文描述符存储至片内RAM。
上述方案中，确定当前的操作请求为报文描述符的入队操作请求时，所述更新指针链表信息包括：
提取所述入队操作请求中的队列号，依据所述队列号读取对应的队列尾指针及空闲头指针，更新所述队列尾指针指向所述空闲头指针当前所指示的地址，然后将所述空闲头指针指向所述指针链表中的下一个地址。
上述方案中，确定当前的操作请求为报文描述符的出队操作请求时，所述更新指针链表信息包括：
提取所述入队操作请求中的队列号，依据所述队列号读取对应的队列头指针及空闲尾指针，更新所述空闲尾指针指向所述队列头指针当前所指示的地址，然后将所述队列头指针指向所述指针链表中的下一个地址。
上述方案中，所述获取所述出队操作请求对应的队列头指针在所述指 针链表中的位置信息，依据所述位置信息读取对应的报文描述符包括：
提取所述入队操作请求中的队列号，依据所述队列号读取对应的队列头指针，确定所述队列头指针在所述指针链表中的位置处于片外DDR时，计算片外DDR地址，依据得到的片外DDR地址读取片外DDR中对应的报文描述符；
确定所述队列头指针在所述指针链表中的位置处于片内RAM时，依据所述队列号读取片内RAM中对应的报文描述符。
本发明实施例还提供了一种队列管理装置，所述装置包括：第一处理模块及第二处理模块；其中，
所述第一处理模块，配置为确定当前的操作请求为报文描述符的入队操作请求，依据所述入队操作请求及片内随机存取存储器RAM的缓存情况，将所述报文描述符存储至片外双倍速率同步动态随机存储器DDR或片内RAM，并更新指针链表信息；
所述第二处理模块，配置为确定当前的操作请求为报文描述符的出队操作请求，获取所述出队操作请求对应的队列头指针在所述指针链表中的位置信息，依据所述位置信息读取对应的报文描述符，并更新指针链表信息；其中，所述位置信息包括片内RAM位置信息及片外DDR位置信息。
上述方案中，所述第一处理模块，配置为依据所述入队操作请求确定当前片内RAM的缓存已达上限时，计算片外DDR地址，并依据得到的片外DDR地址将所述报文描述符存储至片外DDR；
确定当前片内RAM的缓存未达到上限时，提取所述入队操作请求中的队列号，并依据所述队列号将所述报文描述符存储至片内RAM。
上述方案中，所述第一处理模块，配置为提取所述入队操作请求中的队列号，依据所述队列号读取对应的队列尾指针及空闲头指针，更新所述队列尾指针指向所述空闲头指针当前所指示的地址，然后将所述空闲头指 针指向所述指针链表中的下一个地址。
上述方案中，所述第二处理模块，配置为提取所述入队操作请求中的队列号，依据所述队列号读取对应的队列头指针及空闲尾指针，更新所述空闲尾指针指向所述队列头指针当前所指示的地址，然后将所述队列头指针指向所述指针链表中的下一个地址。
上述方案中，所述第二处理模块，配置为提取所述入队操作请求中的队列号，依据所述队列号读取对应的队列头指针，确定所述队列头指针在所述指针链表中的位置处于片外DDR时，计算片外DDR地址，依据得到的片外DDR地址读取片外DDR中对应的报文描述符；
确定所述队列头指针在所述指针链表中的位置处于片内RAM时，依据所述队列号读取片内RAM中对应的报文描述符。
本发明实施例还提供了一种计算机存储介质，所述计算机存储介质存储有计算机程序，该计算机程序配置为执行本发明实施例的上述队列管理方法。
本发明实施例所提供的队列管理方法、装置及存储介质；确定当前的操作请求为报文描述符的入队操作请求，依据所述入队操作请求及片内RAM的缓存情况，将所述报文描述符存储至片外DDR或片内RAM，并更新指针链表信息；确定当前的操作请求为报文描述符的出队操作请求，获取所述出队操作请求对应的队列头指针在所述指针链表中的位置信息，依据所述位置信息读取对应的报文描述符，并更新指针链表信息；其中，所述位置信息包括片内RAM位置信息及片外DDR位置信息。如此，采用指针链表及片内加片外的方式对队列进行管理，并依据片内RAM的缓存情况决定报文描述符的存储位置，在提高访问效率、降低功耗的同时有效的避免流量突发下的丢包情况。
附图说明
图1为本发明实施例一队列管理方法流程示意图；
图2为本发明实施例指针链表RAM初始化示意图；
图3为本发明实施例各个RAM间数据关系示意图；
图4为本发明实施例二队列管理方法流程示意图；
图5为本发明实施例队列管理装置组成结构示意图。
具体实施方式
在在本发明实施例中，确定当前的操作请求为报文描述符的入队操作请求，依据所述入队操作请求及片内RAM的缓存情况，将所述报文描述符存储至片外DDR或片内RAM，并更新指针链表信息；确定当前的操作请求为报文描述符的出队操作请求，获取所述出队操作请求对应的队列头指针在所述指针链表中的位置信息，依据所述位置信息读取对应的报文描述符，并更新指针链表信息；其中，所述位置信息包括片内RAM位置信息及片外DDR位置信息。
实施例一
图1所示为本发明实施例一队列管理方法流程示意图；如图1所示，本发明实施例队列管理方法包括：
步骤101：确定当前的操作请求为报文描述符的入队操作请求，依据所述入队操作请求及片内RAM的缓存情况，将所述报文描述符存储至片外DDR或片内RAM，并更新指针链表信息；
这里，所述依据所述入队操作请求及片内RAM的缓存情况，将所述报文描述符存储至片外DDR或片内RAM包括：
依据所述入队操作请求确定当前片内RAM的缓存已达上限时，计算片外DDR地址，并依据得到的片外DDR地址将所述报文描述符存储至片外DDR；
确定当前片内RAM的缓存未达到上限时，提取所述入队操作请求中的队列号，并依据所述队列号将所述报文描述符存储至片内RAM。
在一实施例中，所述确定当前片内RAM的缓存已达上限包括：
依据预设的片内RAM的缓存大小及缓存计数器实时记录的当前指针链表中非空闲指针的数量确定当前片内RAM的缓存是否已达上限，如果当前指针链表中非空闲指针的数量小于预设的片内RAM的缓存大小，确定当前片内RAM的缓存未达到上限，否则，确定当前片内RAM的缓存已达上限；
这里，所述片内RAM用于缓存报文描述符信息，其大小可依据实际需要进行设定，在一实施例中，所述片内RAM的大小为4k，即片内RAM的地址为0～4k-1，即所述片内RAM的深度为4×1024个地址。
在一实施例中，所述计算片外DDR地址包括：
依据所述片内RAM的大小及缓存计数器记录的当前指针链表中非空闲指针的数量计算片外DDR地址；所述片外DDR地址可以为基地址+链表片内位置偏移；其中，所述基地址为系统配置的、报文描述符存储在片外DDR中的基地址；所述链表片内位置偏移为一个相对地址，若所述基地址为4k，则所述链表片内位置偏移为0，如果所述基地址为4k+1，则所述链表片内位置偏移为1。
在一实施例中，所述更新指针链表信息包括：
提取所述入队操作请求中的队列号，依据所述队列号读取尾指针RAM中对应的队列尾指针及指针链表RAM中的空闲头指针，更新所述队列尾指针指向所述空闲头指针当前所指示的地址，然后将所述空闲头指针指向所述指针链表中的下一个地址；
这里，所述尾指针RAM用于存储所有队列的队列尾指针，并指示每个队列的队列状态；其中，所述队列状态包括：空和非空；所述尾指针RAM 的大小/深度可依据实际情况进行设定，在一实施例中，所述尾指针RAM的深度等于队列数，在本实施例中，所述尾指针RAM的深度为256个地址，初始化所述尾指针RAM后的最高比特为1或全为1，可知初始化的队列状态为空；
相应的，还存在头指针RAM用于存储所有队列的队列头指针，并指示每个队列的队列状态；其中，所述队列状态包括：空和非空；所述头指针RAM的大小/深度可依据实际情况进行设定，在一实施例中，所述头指针RAM的深度等于队列数，在本实施例中，所述头指针RAM的深度为256个地址，初始化所述头指针RAM后的最高比特为1或全为1，可知初始化的队列状态为空；
所述指针链表RAM用于存储所述指针链表，使队列指针链表及空闲指针链表共享一块RAM，由此可以不用单独的先入先出队列(FIFO，First Input First Output)来存储空闲指针，节省了硬件资源；所述指针链表RAM大小可依据实际需要进行设定，在一实施例中，所述片内RAM的大小为4k，所述指针链表包括了指向下一个地址的指针，初始化为一张空指针链表，如图2所示，ptr RAM为指针链表RAM，对其进行初始化，ptr RAM的地址从0～8191，ptr RAM中存储的内容是下一个地址值，由此形成一张指针链表形式；所述指针链表包括非空闲指针及空闲指针；其中，所述非空闲指针的数目表征了片内RAM及片外DDR中报文描述符所占用的地址的总数目，每入队一次报文描述符，非空闲指针的数目加一，相应的，每出队一次报文描述符，非空闲指针的数目减一；所述片内RAM与所述指针链表RAM的一部分存在一一对应关系，所述片内RAM中为报文描述符信息，所述指针链表RAM中为对应的地址信息；如图3所示为本发明实施例各个RAM间数据关系示意图；
在图3中，head_ptr ram为头指针RAM，tail_ptr ram为尾指针RAM， ptr ram为指针链表RAM，desc ram为片内RAM；其中，指针链表RAM中黑色的为一个队列中的队列成员，共有6个队列成员，为了便于说明，按顺序分别标记为1至6(均为虚拟标记)，前一个数据块中存储的是后一个数据块的地址信息，因为标号6是该队列的最后一个数据，因此该指针链表RAM中的数据为无效数据；根据头指针及尾指针可知该队列的队列号为11，标号1对应的数据块的地址由头指针RAM地址11存储的值确定，标号6对应的数据块地址由尾指针RAM地址11中存储的值确定。
步骤102：确定当前的操作请求为报文描述符的出队操作请求，获取所述出队操作请求对应的队列头指针在所述指针链表中的位置信息，依据所述位置信息读取对应的报文描述符，并更新指针链表信息；
这里，所述位置信息包括片内RAM位置信息及片外DDR位置信息；
所述获取所述出队操作请求对应的队列头指针在所述指针链表中的位置信息，依据所述位置信息读取对应的报文描述符包括：
提取所述入队操作请求中的队列号，依据所述队列号读取头指针RAM中对应的队列头指针，确定所述队列头指针在所述指针链表中的位置处于片外DDR时，计算片外DDR地址，依据得到的片外DDR地址读取片外DDR中对应的报文描述符；
确定所述队列头指针在所述指针链表中的位置处于片内RAM时，依据所述队列号读取片内RAM中对应的报文描述符。
在一实施例中，所述更新指针链表信息包括：
提取所述入队操作请求中的队列号，依据所述队列号读取对应的队列头指针及空闲尾指针，更新所述空闲尾指针指向所述队列头指针当前所指示的地址，然后将所述队列头指针指向所述指针链表中的下一个地址。
实施例二
图4所示为本发明实施例二队列管理方法流程示意图；如图4所示， 本发明实施例队列管理方法包括：
步骤401：接收操作请求并判断是报文描述符的入队操作请求还是出队操作请求，如果是入队操作请求，执行步骤402；如果是出队操作请求，执行步骤404。
步骤402：依据所述入队操作请求及片内RAM的缓存情况，将所述报文描述符存储至片外DDR或片内RAM；
本步骤包括：依据所述入队操作请求确定当前片内RAM的缓存已达上限时，计算片外DDR地址，并依据得到的片外DDR地址将所述报文描述符存储至片外DDR；
确定当前片内RAM的缓存未达到上限时，提取所述入队操作请求中的队列号，并依据所述队列号将所述报文描述符存储至片内RAM。
在一实施例中，所述确定当前片内RAM的缓存已达上限包括：
依据预设的片内RAM的缓存大小及缓存计数器实时记录的当前指针链表中非空闲指针的数量确定当前片内RAM的缓存是否已达上限，如果当前指针链表中非空闲指针的数量小于预设的片内RAM的缓存大小，确定当前片内RAM的缓存未达到上限，否则，确定当前片内RAM的缓存已达上限；
这里，所述片内RAM用于缓存报文描述符信息，其大小可依据实际需要进行设定，在本实施例中，所述片内RAM的大小为4k，即片内RAM的地址为0～4k-1，即所述片内RAM的深度为4×1024个地址。
步骤403：更新指针链表信息，并执行步骤406；
本步骤包括：提取所述入队操作请求中的队列号，依据所述队列号读取尾指针RAM中对应的队列尾指针及指针链表RAM中的空闲头指针，更新所述队列尾指针指向所述空闲头指针当前所指示的地址，然后将所述空闲头指针指向所述指针链表中的下一个地址；
这里，所述尾指针RAM用于存储所有队列的队列尾指针，并指示每个队列的队列状态；其中，所述队列状态包括：空和非空；所述尾指针RAM的大小/深度可依据实际情况进行设定，在一实施例中，所述尾指针RAM的深度等于队列数，在本实施例中，所述尾指针RAM的深度为256个地址，初始化所述尾指针RAM后的最高比特为1或全为1，可知初始化的队列状态为空；
相应的，还存在头指针RAM用于存储所有队列的队列头指针，并指示每个队列的队列状态；其中，所述队列状态包括：空和非空；所述头指针RAM的大小/深度可依据实际情况进行设定，在一实施例中，所述头指针RAM的深度等于队列数，在本实施例中，所述头指针RAM的深度为256个地址，初始化所述头指针RAM后的最高比特为1或全为1，可知初始化的队列状态为空；
所述指针链表RAM用于存储所述指针链表，使队列指针链表及空闲指针链表共享一块RAM，由此可以不用单独的FIFO来存储空闲指针，节省了硬件资源；所述指针链表RAM大小可依据实际需要进行设定，在本实施例中，所述片内RAM的大小为4k，所述指针链表包括了指向下一个地址的指针，初始化为一张空指针链表，如图2所示，ptr RAM为指针链表RAM，对其进行初始化，ptr RAM的地址从0～8191，ptr RAM中存储的内容是下一个地址值，由此形成一张指针链表形式；所述指针链表包括非空闲指针及空闲指针；其中，所述非空闲指针的数目表征了片内RAM及片外DDR中报文描述符所占用的地址的总数目，每入队一次报文描述符，非空闲指针的数目加一，相应的，每出队一次报文描述符，非空闲指针的数目减一；所述片内RAM与所述指针链表RAM的一部分存在一一对应关系，所述片内RAM中为报文描述符信息，所述指针链表RAM中为对应的地址信息；如图3所示为本发明实施例各个RAM间数据关系示意图；
在图3中，head_ptr ram为头指针RAM，tail_ptr ram为尾指针RAM，ptr ram为指针链表RAM，desc ram为片内RAM；其中，指针链表RAM中黑色的为一个队列中的队列成员，共有6个队列成员，为了便于说明，按顺序分别标记为1至6(均为虚拟标记)，前一个数据块中存储的是后一个数据块的地址信息，因为标号6是该队列的最后一个数据，因此该指针链表RAM中的数据为无效数据；根据头指针及尾指针可知该队列的队列号为11，标号1对应的数据块的地址由头指针RAM地址11存储的值确定，标号6对应的数据块地址由尾指针RAM地址11中存储的值确定。
步骤404：获取所述出队操作请求对应的队列头指针在所述指针链表中的位置信息，依据所述位置信息读取对应的报文描述符；
这里，所述位置信息包括片内RAM位置信息及片外DDR位置信息；
本步骤包括：提取所述入队操作请求中的队列号，依据所述队列号读取头指针RAM中对应的队列头指针，确定所述队列头指针在所述指针链表中的位置处于片外DDR时，计算片外DDR地址，依据得到的片外DDR地址读取片外DDR中对应的报文描述符；
确定所述队列头指针在所述指针链表中的位置处于片内RAM时，依据所述队列号读取片内RAM中对应的报文描述符。
步骤405：更新指针链表信息；
本步骤包括：提取所述入队操作请求中的队列号，依据所述队列号读取对应的队列头指针及空闲尾指针，更新所述空闲尾指针指向所述队列头指针当前所指示的地址，然后将所述队列头指针指向所述指针链表中的下一个地址。
步骤406：结束本次处理流程。
实施例三
图5为本发明实施例队列管理装置组成结构示意图；如图5所示，本 发明实施例队列管理装置组成包括：第一处理模块51及第二处理模块52；其中，
所述第一处理模块51，配置为确定当前的操作请求为报文描述符的入队操作请求，依据所述入队操作请求及片内RAM的缓存情况，将所述报文描述符存储至片外DDR或片内RAM，并更新指针链表信息；
所述第二处理模块52，配置为确定当前的操作请求为报文描述符的出队操作请求，获取所述出队操作请求对应的队列头指针在所述指针链表中的位置信息，依据所述位置信息读取对应的报文描述符，并更新指针链表信息；其中，所述位置信息包括片内RAM位置信息及片外DDR位置信息。
在一实施例中，所述第一处理模块51依据所述入队操作请求及片内RAM的缓存情况，将所述报文描述符存储至片外DDR或片内RAM，包括：
所述第一处理模块51依据所述入队操作请求确定当前片内RAM的缓存已达上限时，计算片外DDR地址，并依据得到的片外DDR地址将所述报文描述符存储至片外DDR；
确定当前片内RAM的缓存未达到上限时，提取所述入队操作请求中的队列号，并依据所述队列号将所述报文描述符存储至片内RAM；
其中，所述第一处理模块51确定当前片内RAM的缓存已达上限包括：
所述第一处理模块51依据预设的片内RAM的缓存大小及缓存计数器实时记录的当前指针链表中非空闲指针的数量确定当前片内RAM的缓存是否已达上限，如果当前指针链表中非空闲指针的数量小于预设的片内RAM的缓存大小，确定当前片内RAM的缓存未达到上限，否则，确定当前片内RAM的缓存已达上限；
这里，所述片内RAM用于缓存报文描述符信息，其大小可依据实际需要进行设定，在一实施例中，所述片内RAM的大小为4k，即片内RAM的地址为0～4k-1，即所述片内RAM的深度为4×1024个地址。
在一实施例中，确定当前的操作请求为报文描述符的入队操作请求时，所述第一处理模块51更新指针链表信息包括：
所述第一处理模块51提取所述入队操作请求中的队列号，依据所述队列号读取对应的队列尾指针及空闲头指针，更新所述队列尾指针指向所述空闲头指针当前所指示的地址，然后将所述空闲头指针指向所述指针链表中的下一个地址；
这里，尾指针RAM用于存储所有队列的队列尾指针，并指示每个队列的队列状态；其中，所述队列状态包括：空和非空；所述尾指针RAM的大小/深度可依据实际情况进行设定，在一实施例中，所述尾指针RAM的深度等于队列数，在本实施例中，所述尾指针RAM的深度为256个地址，初始化所述尾指针RAM后的最高比特为1或全为1，可知初始化的队列状态为空；
相应的，还存在头指针RAM用于存储所有队列的队列头指针，并指示每个队列的队列状态；其中，所述队列状态包括：空和非空；所述头指针RAM的大小/深度可依据实际情况进行设定，在一实施例中，所述头指针RAM的深度等于队列数，在本实施例中，所述头指针RAM的深度为256个地址，初始化所述头指针RAM后的最高比特为1或全为1，可知初始化的队列状态为空；
指针链表RAM用于存储所述指针链表，使队列指针链表及空闲指针链表共享一块RAM，由此可以不用单独的先入先出队列(FIFO，First Input First Output)来存储空闲指针，节省了硬件资源；所述指针链表RAM大小可依据实际需要进行设定，在一实施例中，所述片内RAM的大小为4k，所述指针链表包括了指向下一个地址的指针，初始化为一张空指针链表，如图2所示，ptr RAM为指针链表RAM，对其进行初始化，ptr RAM的地址从0～8191，ptr RAM中存储的内容是下一个地址值，由此形成一张指针链表 形式；所述指针链表包括非空闲指针及空闲指针；其中，所述非空闲指针的数目表征了片内RAM及片外DDR中报文描述符所占用的地址的总数目，每入队一次报文描述符，非空闲指针的数目加一，相应的，每出队一次报文描述符，非空闲指针的数目减一；所述片内RAM与所述指针链表RAM的一部分存在一一对应关系，所述片内RAM中为报文描述符信息，所述指针链表RAM中为对应的地址信息；如图3所示为本发明实施例各个RAM间数据关系示意图；
在图3中，head_ptr ram为头指针RAM，tail_ptr ram为尾指针RAM，ptr ram为指针链表RAM，desc ram为片内RAM；其中，指针链表RAM中黑色的为一个队列中的队列成员，共有6个队列成员，为了便于说明，按顺序分别标记为1至6(均为虚拟标记)，前一个数据块中存储的是后一个数据块的地址信息，因为标号6是该队列的最后一个数据，因此该指针链表RAM中的数据为无效数据；根据头指针及尾指针可知该队列的队列号为11，标号1对应的数据块的地址由头指针RAM地址11存储的值确定，标号6对应的数据块地址由尾指针RAM地址11中存储的值确定。
在一实施例中，所述第二处理模块52获取所述出队操作请求对应的队列头指针在所述指针链表中的位置信息，依据所述位置信息读取对应的报文描述符，包括：
所述第二处理模块52提取所述入队操作请求中的队列号，依据所述队列号读取对应的队列头指针，确定所述队列头指针在所述指针链表中的位置处于片外DDR时，计算片外DDR地址，依据得到的片外DDR地址读取片外DDR中对应的报文描述符；
确定所述队列头指针在所述指针链表中的位置处于片内RAM时，依据所述队列号读取片内RAM中对应的报文描述符。
在一实施例中，确定当前的操作请求为报文描述符的出队操作请求时， 所述第二处理模块52更新指针链表信息包括：
所述第二处理模块52提取所述入队操作请求中的队列号，依据所述队列号读取对应的队列头指针及空闲尾指针，更新所述空闲尾指针指向所述队列头指针当前所指示的地址，然后将所述队列头指针指向所述指针链表中的下一个地址。
本发明实施例中提出的第一处理模块51及第二处理模块52都可以通过处理器来实现，当然也可通过具体的逻辑电路实现；其中所述处理器可以是移动终端或服务器上的处理器，在实际应用中，处理器可以为中央处理器(CPU)、微处理器(MPU)、数字信号处理器(DSP)或现场可编程门阵列(FPGA)等。
本发明实施例中，如果以软件功能模块的形式实现上述队列管理方法，并作为独立的产品销售或使用时，也可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明实施例的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机、服务器、或者网络设备等)执行本发明各个实施例所述方法的全部或部分。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read Only Memory，ROM)、磁碟或者光盘等各种可以存储程序代码的介质。这样，本发明实施例不限制于任何特定的硬件和软件结合。
相应地，本发明实施例还提供一种计算机存储介质，该计算机存储介质中存储有计算机程序，该计算机程序用于执行本发明实施例的上述队列管理方法。
以上所述仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围。

Claims (11)

  1. 一种队列管理方法，所述方法包括：
    确定当前的操作请求为报文描述符的入队操作请求，依据所述入队操作请求及片内随机存取存储器RAM的缓存情况，将所述报文描述符存储至片外双倍速率同步动态随机存储器DDR或片内RAM，并更新指针链表信息；
    确定当前的操作请求为报文描述符的出队操作请求，获取所述出队操作请求对应的队列头指针在所述指针链表中的位置信息，依据所述位置信息读取对应的报文描述符，并更新指针链表信息；其中，所述位置信息包括片内RAM位置信息及片外DDR位置信息。
  2. 根据权利要求1所述方法，其中，所述依据所述入队操作请求及片内RAM的缓存情况，将所述报文描述符存储至片外DDR或片内RAM包括：
    依据所述入队操作请求确定当前片内RAM的缓存已达上限时，计算片外DDR地址，并依据得到的片外DDR地址将所述报文描述符存储至片外DDR；
    确定当前片内RAM的缓存未达到上限时，提取所述入队操作请求中的队列号，并依据所述队列号将所述报文描述符存储至片内RAM。
  3. 根据权利要求1或2所述方法，其中，确定当前的操作请求为报文描述符的入队操作请求时，所述更新指针链表信息包括：
    提取所述入队操作请求中的队列号，依据所述队列号读取对应的队列尾指针及空闲头指针，更新所述队列尾指针指向所述空闲头指针当前所指示的地址，然后将所述空闲头指针指向所述指针链表中的下一个地址。
  4. 根据权利要求1或2所述方法，其中，确定当前的操作请求为报文描述符的出队操作请求时，所述更新指针链表信息包括：
    提取所述入队操作请求中的队列号，依据所述队列号读取对应的队列头指针及空闲尾指针，更新所述空闲尾指针指向所述队列头指针当前所指示的地址，然后将所述队列头指针指向所述指针链表中的下一个地址。
  5. 根据权利要求1或2所述方法，其中，所述获取所述出队操作请求对应的队列头指针在所述指针链表中的位置信息，依据所述位置信息读取对应的报文描述符包括：
    提取所述入队操作请求中的队列号，依据所述队列号读取对应的队列头指针，确定所述队列头指针在所述指针链表中的位置处于片外DDR时，计算片外DDR地址，依据得到的片外DDR地址读取片外DDR中对应的报文描述符；
    确定所述队列头指针在所述指针链表中的位置处于片内RAM时，依据所述队列号读取片内RAM中对应的报文描述符。
  6. 一种队列管理装置，所述装置包括：第一处理模块及第二处理模块；其中，
    所述第一处理模块，配置为确定当前的操作请求为报文描述符的入队操作请求，依据所述入队操作请求及片内随机存取存储器RAM的缓存情况，将所述报文描述符存储至片外双倍速率同步动态随机存储器DDR或片内RAM，并更新指针链表信息；
    所述第二处理模块，配置为确定当前的操作请求为报文描述符的出队操作请求，获取所述出队操作请求对应的队列头指针在所述指针链表中的位置信息，依据所述位置信息读取对应的报文描述符，并更新指针链表信息；其中，所述位置信息包括片内RAM位置信息及片外DDR位置信息。
  7. 根据权利要求6所述装置，其中，所述第一处理模块，配置为依据所述入队操作请求确定当前片内RAM的缓存已达上限时，计算片外DDR地址，并依据得到的片外DDR地址将所述报文描述符存储至片外DDR；
    确定当前片内RAM的缓存未达到上限时，提取所述入队操作请求中的队列号，并依据所述队列号将所述报文描述符存储至片内RAM。
  8. 根据权利要求6或7所述装置，其中，所述第一处理模块，配置为提取所述入队操作请求中的队列号，依据所述队列号读取对应的队列尾指针及空闲头指针，更新所述队列尾指针指向所述空闲头指针当前所指示的地址，然后将所述空闲头指针指向所述指针链表中的下一个地址。
  9. 根据权利要求6或7所述装置，其中，所述第二处理模块，配置为提取所述入队操作请求中的队列号，依据所述队列号读取对应的队列头指针及空闲尾指针，更新所述空闲尾指针指向所述队列头指针当前所指示的地址，然后将所述队列头指针指向所述指针链表中的下一个地址。
  10. 根据权利要求6或7所述装置，其中，所述第二处理模块，配置为提取所述入队操作请求中的队列号，依据所述队列号读取对应的队列头指针，确定所述队列头指针在所述指针链表中的位置处于片外DDR时，计算片外DDR地址，依据得到的片外DDR地址读取片外DDR中对应的报文描述符；
    确定所述队列头指针在所述指针链表中的位置处于片内RAM时，依据所述队列号读取片内RAM中对应的报文描述符。
  11. 一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，该计算机可执行指令用于执行权利要求1至5任一项所述的队列管理方法。
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