Classifications

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  • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
  • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
  • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
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• • G—PHYSICS
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  • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
  • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
  • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
  • G11C29/38—Response verification devices
  • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
• • G—PHYSICS
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  • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
  • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
  • G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
• • G—PHYSICS
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  • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
  • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
  • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
  • G06F11/1016—Error in accessing a memory location, i.e. addressing error
• • G—PHYSICS
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  • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
  • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
  • G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F11/00—Error detection; Error correction; Monitoring
  • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
  • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
  • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
  • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
  • G06F11/1072—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in multilevel memories
• • G—PHYSICS
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  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F11/00—Error detection; Error correction; Monitoring
  • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
  • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
  • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
  • G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• • G—PHYSICS
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  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
  • G06F12/02—Addressing or allocation; Relocation
  • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
  • G06F12/023—Free address space management
  • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
  • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
  • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
  • G06F3/0601—Interfaces specially adapted for storage systems
  • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
  • G06F3/0614—Improving the reliability of storage systems
  • G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
  • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
  • G06F3/0601—Interfaces specially adapted for storage systems
  • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
  • G06F3/0638—Organizing or formatting or addressing of data
  • G06F3/064—Management of blocks
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
  • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
  • G06F3/0601—Interfaces specially adapted for storage systems
  • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
  • G06F3/0671—In-line storage system
  • G06F3/0673—Single storage device
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/10—Programming or data input circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
  • G11C29/52—Protection of memory contents; Detection of errors in memory contents
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
  • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
  • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
  • H03M13/13—Linear codes

Definitions

• Computer systems include processors that are operable to retrieve, process, and store data in memory devices.
• the memory devices used in computer systems include different kinds of memory devices, where the different types of memory devices typically have different capabilities and operating characteristics.
• the type of memory device used in a particular system is typically selected in accordance with the requirements of a particular application of the computer system. For example, some system designs require the ability to write and read data to and from non-volatile memory locations. However, some memory device solutions (such as electrically erasable read-only memories) are unsuited for some applications, because of increased cost and decreased performance characteristics.
• a host processor is arranged to send a data word that is to be stored in a WOM (write-only memory) device.
• a host interface is arranged to receive the first data word for processing by a WOM controller and an ECC controller.
• the WOM controller is for generating a first WOM-encoded word in response to an original symbol of the first data word, while the ECC controller is for generating a first set of ECC bits in response to the original symbol of the first data word.
• a memory device interface is for writing the first WOM-encoded word and the first set of ECC bits to the WOM device in accordance with the memory address associated with the first data word.
• FIG. 1 shows an illustrative computing system in accordance with example embodiments.
• FIG. 2 is a block diagram of a processing system including an ECC-managed WOM in accordance with example embodiments.
• FIG. 3 illustrates symbol-level WOM encoding in an example memory system.
• FIG. 4 is a coding diagram of an example two-stage Reed-Solomon and WOM coding scheme in accordance with example embodiments.
• FIG. 5 is a coding diagram of an example two-stage BCH coding and WOM coding scheme in accordance with example embodiments.
• FIG. 6 is a coding diagram of an example two-stage WOM coding and ECC coding scheme in accordance with example embodiments.
• FIG. 7 is an example process flow diagram in accordance with example embodiments. DETAILED DESCRIPTION OF EXAMPLE EMB ODFMENT S
• Various names may refer to a component or system.
• a system can be a sub-system of yet another system. If a first device couples to a second device, that connection can be made through a direct electrical connection, or through an indirect electrical connection via other devices and connections.
• FIG. 1 shows an illustrative computing system 100 in accordance with example embodiments.
• the computing system 100 is, or is incorporated into, an electronic system 129, such as a computer, electronics control "box” or display, communications equipment (including transmitters), or any other type of electronic system arranged to generate radio-frequency signals.
• an electronic system 129 such as a computer, electronics control "box” or display, communications equipment (including transmitters), or any other type of electronic system arranged to generate radio-frequency signals.
• the computing system 100 includes a megacell or a system-on- chip (SoC), which includes control logic such as a CPU 112 (central processing unit), a storage 114 (such as random access memory (RAM)) and a power supply 110.
• the CPU 112 can be a CISC-type (complex instruction set computer) CPU, RISC-type CPU (reduced instruction set computer), MCU-type (microcontroller unit), or a digital signal processor (DSP).
• the storage 114 (which can be memory such as on-processor cache, off-processor cache, RAM, flash memory or disk storage) stores one or more software applications 130 (such as embedded applications) that, when executed by the CPU 112, perform any suitable function associated with the computing system 100.
• the CPU 112 includes memory and logic that store information frequently accessed from the storage 114.
• the computing system 100 is often controlled by a user using a UI (user interface) 116, which provides output to and receives input from the user during the execution the software application 130.
• the output is provided using the display 118, indicator lights, a speaker, vibrations and other possible ways.
• the input is received using audio and/or video inputs (such as using voice or image recognition) and electrical and/or mechanical devices, such as keypads, switches, proximity detectors, gyros and accelerometers.
• the CPU 112 is coupled to I/O (input-output) port 128, which provides an interface that is configured to receive input from (and/or provide output to) networked devices 131.
• the networked devices 131 can include any device capable of point-to-point and/or networked communications with the computing system 100.
• the computing system 100 can also be coupled to peripherals and/or computing devices, including tangible, non-transitory media (such as flash memory) and/or cabled or wireless media. These and other input and output devices are selectively coupled to the computing system 100 by external devices using wireless or cabled connections.
• the storage 114 can be accessed by the networked devices 131.
• the CPU 1 12 is coupled to I/O (input-output) port 128, which provides an interface that is configured to receive input from (and/or provide output to) peripherals and/or computing devices 131, including tangible (such as non-transitory) media (such as flash memory) and/or cabled or wireless media (such as a Joint Test Action Group (JTAG) interface).
• I/O input-output
• computing devices 131 including tangible (such as non-transitory) media (such as flash memory) and/or cabled or wireless media (such as a Joint Test Action Group (JTAG) interface).
• JTAG Joint Test Action Group
• the CPU 112, storage 114 and power supply 110 can be coupled to an external power supply (not shown) or coupled to a local power source (such as a battery, solar cell, alternator, inductive field, fuel cell or capacitor).
• the computing system 100 includes a memory 138, which is suitable for relatively quick memory accesses and is usually formed using solid state memory devices.
• solid-state memory devices include the ECC-managed (electronic correction code-managed) write-once memory (WOM) 140.
• the WOM 140 is memory that is usually written once (or a relatively small number of times), such as before being discarded or erased.
• the use of WOM-codes enables certain systems to write and read data to and from non-volatile memory.
• ECC electronic correction code-managed
• WOM write-once memory
• the use of WOM-codes enables certain systems to write and read data to and from non-volatile memory.
• the use of ECC in WOM applications is problematic (such as discussed with respect to FIG. 3).
• the ECC-managed WOM 140 write accesses are usually faster than ECC-managed WOM 140 erase cycles (if any).
• the write accesses are capable of changing a bit location in the ECC-managed WOM 140 from an erased state to a written state (such as a "0" to a "1").
• the erased state usually depends on a technology selected, and accordingly can be either a "0" to a "1,” while the written state is usually the opposite of the erased state.
• Some memory devices may store multiple bits of information in a single memory cell, in which case the written bits include one of more bits of information that have a state opposite the erased state.
• the ECC-managed WOM 140 is written using a WOM code for efficiently writing to WOM, such that the written-to WOM can be written to multiple times without erasure.
• the ECC-managed WOM 140 is useful to provide cost-efficient non-volatile memory (NVM) having a limited reprograming capability and/or an enhanced number of write/erase cycles (such as compared with conventional NVM solutions).
• NVM non-volatile memory
• FIG. 2 is a block diagram of a processing system including an ECC-managed WOM in accordance with example embodiments.
• a processing system 200 includes an MCU 204 and a memory controller 210.
• the MCU 204 and the memory controller 210 are usually arranged on a common substrate 202.
• the memory controller 210 is communicatively coupled to the MCU 204 and is operable to manage memory accesses to memory devices to (at least) the ECC-managed WOM 140 and memory devices, such as RAM 292, PROM (programmable read-only memory) 294 and optional EEPROM (electrically erasable read-only memory) 296 (which is optionally formed using a substrate that is different from the substrate 202).
• RAM 292 random access memory
• PROM programmable read-only memory
• EEPROM electrically erasable read-only memory
• memory accesses serviced by the memory controller 210 include write operations and read operations.
• the data of write operations is transmitted in a top-to- bottom direction as illustrated in FIG. 2, while the data of read operations is transmitted in a bottom-to-top direction as illustrated in FIG. 2.
• the host interface 220 is arranged to select (such as in response to a system address supplied with a memory access command) a memory device to write data to or read data from.
• the memory controller 210 includes an ECC controller such as ECC-manager 250.
• ECC-manager 250 is operable to apply an error correction code to data for writing to the ECC-managed WOM 140.
• the ECC-manager 250 is operable to evaluate the retrieved data and, if indicated, the ECC-controller is operable to execute a corrective action in response to the evaluation.
• the corrective action is operable to correct the retrieved data using ECC-encoded data read from the ECC-managed WOM 140 via the WOM-manager 260.
• the memory controller 210 includes the WOM-manager 260.
• the WOM-manager 260 is operable to encode data (such as data encoded by the ECC-manager 260 using an ECC encoding) using a WOM code for writing the WOM (and ECC) encoded data to the ECC-managed WOM 140.
• the WOM-manager 260 is operable to decode the WOM-encoded data from the ECC-managed WOM 140. After the WOM-encoded data is decoded, the decoded data is transmitted to the ECC-manager 250 to be further decoded in accordance with the ECC-encoding that was used to originally encode the data written to the ECC-managed WOM 140.
• the memory controller 210 includes the memory device interface 270.
• the memory device interface 270 is operable to write the encoded data (such as data encoded by the ECC-manager 260 using an ECC encoding and by the WOM-manager 260 using a WOM code) to the ECC-managed WOM 140.
• the memory device interface 270 is operable to read the encoded data from the ECC-managed WOM 140.
• the memory device interface 270 is also operable to perform block initialization routines on the ECC-managed WOM 140 (such as to block erase the ECC-managed WOM 140, such that addressed memory locations are all erased to a logic-zero state).
• the block initialization routines require more time to execute than the execution time required by normal read or write cycles to the ECC-managed WOM 140.
• the WOM manager-260 is operable to encode payload data as WOM-encoded data such that the ECC-manager 250 encodes the WOM-encoded data.
• the ECC-manager 250 is operable to decode ECC-encoded data retrieved from memory such that the WOM-manager 260 decodes the WOM-encoded data to retrieve the originally encoded payload data.
• WOM encoding can be accomplished using n-bit (such as any integer number of bits that is greater than or equal to 2) symbols that are written to WOM memory a limited number of times.
• n-bit such as any integer number of bits that is greater than or equal to 2
• TABLE 1 illustrates WOM encoding for 2-bit symbols that can be written to WOM twice (such as before memory erasure is required) in a particular memory location.
• values for m W 0M can be any integer greater than or equal to 2.
• the WOM-manager 260 is able to determine the number of writes to a WOM location (for storing a WOM-encoded symbol) by reading the data stored in the location (without having to rely upon a separate counter for each memory location).
• the symbol 310 is encoded in accordance with TABLE 1 to generate an encoded symbol 320.
• the WOM code encoded memory 304 includes a 3-bit value ("000") 320 for storing the encoded symbol 320 (for example, the default erased bit value "0" for the WOM code encoded memory 304 is used for simplicity of illustration).
• the WOM code encoded memory 304 is subject to bit errors, which can lead to data loss.
• an error occurs in the least significant bit of the memory location 320.
• the strength of the error correction codes determines the degree to which errors in the encoded data appear in the decoded data. Accordingly, the 3-bit value 320 is erroneously changed to the 3-bit value ("001") 330, which represents a one-bit error (such as in the WOM code encoded memory 304).
• the 3-bit value (“001") 330 is read and decoded in accordance with TABLE 1 such that the two-bit symbol 340 (representing the decoded 3-bit value 330) has the value "11.”
• the value "1" in the example represents a two-bit error in the symbol, notwithstanding that only a 1-bit error occurred in the WOM code encoded memory 304.
• a 1-bit error in a WOM-encoded symbol can result in errors in all bits of the WOM symbol.
• this disclosure includes two-stage concatenated coding schemes that provide low processing latencies and/or reduced layout requirements for symbol-level protection of data stored in WOM-encoded memory devices.
• the two-stage concatenated coding schemes include: a first stage in which the payload data is encoded using electronic correction codes (ECC) to produce ECC-protected payload data; and a second stage in which the ECC-protected payload data is encoded using WOM-encoding.
• ECC electronic correction codes
• FIG. 4 is coding diagram of an example two-stage Reed-Solomon and WOM coding scheme in accordance with example embodiments.
• data flow diagram 400 includes word 410, ECC-encoded word 420, and WOM-encoded word 430 (having ECC-encoding).
• the ECC-encoding 480 of the ECC-encoded word 420 is preserved within the WOM-encoding 490 of the WOM-encoded word 430.
• Word 410 includes a number of "k" symbols where each symbol is stored in a symbol field such as symbol fields 412 and 414.
• the symbol fields include groups of one or more bits each group represents a symbol to be encoded.
• word 410 includes symbol field 412 (for encoding a first symbol) and symbol field 414 (for encoding a second symbol), where each symbol field is to be encoded in encoding operation 402.
• symbol field 412 includes the value "10”
• symbol filed 414 includes the value "11.”
• Encoding operation 402 is a first-stage operation that is operable to encode the (e.g., non-encoded) symbol fields of word 410 using a symbol -based error-correcting code scheme such as a Reed-Solomon code.
• a symbol -based error-correcting code scheme such as a Reed-Solomon code.
• the parity symbols are used for detecting and optionally correcting errors in an encoded word (where the number of errors that can be corrected depends on how many parity symbols are used).
• the number of parity symbols used in each RS code is given by 2*T (which is in total 2*m R s*T bits), where m R s is the bit-width of each symbol to be encoded and T is the number of correctable errors in the encoded symbol.
• m R s is selected to be an integer multiple of m W 0M-
• the encapsulated error-correction codes are capable of correcting multiple bit errors (such as where each WOM-stored word is capable of correcting for 2 or more errors in the WOM-stored word).
• the ECC-encoded words 420 include symbol field 422 for the first RS code (e.g., which is a direct copy of symbol field 412) and symbol field 426 for the second RS code (e.g., which is a direct copy of symbol field 414).
• the parity field 428 is 4-bits long and is used to protect the symbol field 426.
• the symbol field 422 includes the value "10”
• the parity field 424 includes the value "1010” (which is an example RS encoding of the symbol field 422)
• the symbol field 426 includes the value "11”
• the parity field 428 includes the value "1011” (which is an example RS encoding of the symbol field 426).
• Encoding operation 404 is a second-stage operation WOM-encoding operation (such as discussed above with respect to FIG. 3) and is operable to encode the output of the first-stage operation 402 (e.g., which is an ECC-encoded word) as a WOM-encoded word.
• encoding operation 404 encodes the ECC-encoded word 420 as a WOM-encoded word 430 (e.g., which maintains the information of the original ECC-encoded word 420).
• WOM-encoded word 430 includes WOM fields 432, 434, 436, and 438, where the WOM field 432 is the WOM code for symbol field 422, the WOM field 434 is the WOM code for symbol field 424, the WOM field 436 is the WOM code for symbol field 426, and the WOM field 438 is the WOM code for symbol field 428.
• the WOM field 432 includes the value "010”
• the WOM field 434 includes the value "010001,”
• the WOM field 436 includes the value "100”
• the WOM field 438 includes the value "000100.”
• the WOM encoding allows the WOM-encoded word (such as stored in a WOM memory) to be over-written multiple times such that execution of relatively slow (and lifecycle-limited) block initialization routines can be reduced, if not avoided all together.
• the block initialization routines include routines such as a block erasure operation (writing all "zeros" to a nonvolatile memory block or a block presetting operation (writing all "ones" to a nonvolatile block of memory).
• the type of block operation is usually determined in accordance with the technology of the memory cells used.
• Decoding operation 406 is a WOM-decoding operation (such as discussed above with respect to FIG. 3) and is operable to decode a WOM-encoded word of an ECC-encoded word as the (e.g., ideally) original ECC-encoded word.
• operation 406 is a "second stage” operation that "reverses” the encoding of the "second stage” operation 404.
• Decoding operation 406 decodes the WOM-encoded word 430 to (e.g., ideally) retrieve the ECC-encoded word 420 encoded within the WOM-encoded word 430.
• the parity fields 424 and 428 are respectively used to validate (such as restore) the symbol fields 422 and 426.
• Decoding operation 408 is an ECC-decoding operation operable to decode ECC-encoded data as validated data.
• operation 408 is a "first stage” operation that "reverses” the encoding of the "first stage” operation 402.
• the parity fields 424 and 428 are respectively used to validate (such as restore) the symbol fields 422 and 426.
• the strength (such as determined by type of ECC and the number of correction bits used) of the ECC-encoding is sufficient to correct for the error such that the data of word 410 is restorable.
• bit-error such as single bit-error
• a bit-error in a WOM-encoded field is correctable after the stored WOM-encoded words are retrieved from memory.
• an example one-bit error in the WOM-encoded word (as described above with respect to FIG. 3) can lead to a 2-bit error in a symbol.
• FIG. 5 is coding diagram of an example two-stage BCH coding and WOM coding scheme in accordance with example embodiments.
• data flow diagram 500 includes word 510, ECC-encoded word 520, and WOM-encoded word 530 (having ECC-encoding).
• the ECC-encoding 580 of the ECC-encoded word 520 is preserved within the WOM-encoding 590 of the WOM-encoded word 530.
• Word 510 includes a number of "k” symbols where each symbol is stored in a symbol field such as symbol fields 512 and 514. Accordingly, word 510 includes 2 symbols, where each symbol is respectively stored in symbol field 512 and 514.
• the symbol fields are to be encoded in encoding operation 502. As illustrated, the symbol field 512 includes the value "10" and the symbol filed 514 includes the value "11."
• Encoding operation 502 is a first-stage operation that is operable to encode the (e.g., non-encoded) symbol fields of word 510 using a non-binary cyclic error-correcting code scheme such as a BCH code.
• a non-binary cyclic error-correcting code scheme such as a BCH code.
• the number of parity symbols used is given by m W 0M (which includes m B cH *m W 0M bits) where m B cH is the bit-width of each symbol to be BCH encoded and ra WO M is equal to the width of symbol field 522 (which is 2-bits wide).
• Encoding operation 502 generates an ECC-encoded word 520.
• the ECC-encoded words 520 includes symbol field 522 (e.g., which is a direct copy of symbol field 512) for first BCH code and symbol field 524 (e.g., which is a direct copy of symbol field 514) for second BCH code.
• the parity field 528 is 4-bits long and is used to protect the symbol of symbol field 524.
• the symbol field 522 includes the value "10”
• the parity field 526 includes the value "0110” (which is a BCH encoding of the symbol field 522)
• the symbol field 524 includes the value "11”
• the parity field 528 includes the value "0010” (which is an BCH encoding of the symbol field 524).
• Encoding operation 504 is a second-stage operation WOM-encoding operation (such as discussed above with respect to FIG. 3) and is operable to encode the output of the first-stage operation 502 (e.g., which is an ECC-encoded word) as a WOM-encoded word.
• encoding operation 504 encodes the ECC-encoded word 520 as a WOM-encoded word 530 (e.g., which maintains the information of the original ECC-encoded word 520).
• the WOM-encoded word 530 includes WOM fields 532, 536, 534, and 538, where the WOM field 532 is the WOM code for symbol field 522, the WOM field 536 is the WOM code for symbol field 526, the WOM field 534 is the WOM code for symbol field 524, and the WOM field 538 is the WOM code for symbol field 528.
• the WOM field 532 includes the value "010”
• the WOM field 536 includes the value " 100010”
• the WOM field 534 includes the value "100”
• the WOM field 538 includes the value "000010.”
• the width of the parity fields 526 and 528 is 4 bits each, such that a 6-bit field (such as WOM fields 536 and 538) is used to store each of the WOM-encoded values of the parity fields 526 and 528.
• Decoding operation 506 is a WOM-decoding operation (such as discussed above with respect to FIG. 3) and is operable to decode a WOM-encoded word of an ECC-encoded word as the (e.g., ideally) original ECC-encoded word.
• decoding operation 506 decodes the WOM-encoded word 530 to (e.g., ideally) retrieve the ECC-encoded word 520 encoded within the WOM-encoded word 530.
• Decoding operation 508 is an ECC-decoding operation operable to decode ECC-encoded data as validated data.
• the parity fields 526 and 528 are respectively used to validate (such as restore) the symbol fields 522 and 524.
• the strength (such as determined by type of ECC and the number of correction bits used) of the ECC-encoding is sufficient to correct for the error such that the data of word 510 is restorable.
• FIG. 6 is coding diagram of an example two-stage WOM coding and ECC coding scheme in accordance with example embodiments.
• data flow diagram 600 includes word 610, WOM-encoded word 620, and ECC-encoded word 630 (having ECC-encoding).
• the WOM-encoding 690 of the WOM-encoded word 620 is preserved within the ECC-encoding 680 of the ECC-encoded word 630.
• Word 610 includes a number of "k" WOM symbols where each symbol is stored in a symbol field such as symbol fields 612 and 614. Accordingly, word 610 includes 2 symbols, where each symbol is respectively stored in symbol field 612 and 614. Accordingly, word 610 includes symbol field 612 (for encoding a first symbol) and symbol field 614 (for encoding a second symbol), where each symbol field is to be encoded in encoding operation 602. As illustrated, the symbol field 612 includes the value "10" and the symbol filed 614 includes the value "11."
• Encoding operation 602 is a first-stage operation that is operable to encode the (e.g., non-encoded) symbol fields of word 610 using a WOM-encoding operation (such as discussed above with respect to FIG. 3) and is operable to output the encoded symbols as a WOM-encoded word.
• encoding operation 602 encodes the word 610 as a WOM-encoded word 620 (e.g., which maintains the information of the word 610).
• WOM-encoded word 620 includes WOM fields 622 and 624, where the WOM field 622 is the WOM code for symbol field 612 and the WOM field 624 is the WOM code for symbol field 614. As illustrated, the WOM field 622 includes the value "010" and the WOM field 624 includes the value "100.”
• Encoding operation 604 is a second-stage operation that is operable to encode the WOM-encoded fields of word 620 using linear error-correcting code scheme such as a Hamming or SECDED (single-error correction, double-error detection) code.
• the example encoding operation 604 operates in accordance with an extended Hamming code. For 6 WOM-coded data bits, a (16,11) extended Hamming code is indicated and accordingly 5 parity bits are used for each write operation. Given the 2-times write capability of the WOM code, 2 sets of 5-bit parity bits are provided, where a different set of 5 parity bits is used for each write operation.
• Encoding operation 604 generates an ECC-encoded word 630.
• the ECC-encoded word 630 includes WOM field 632 (e.g., which is a direct copy of WOM field 622) and WOM field 634 (e.g., which is a direct copy of WOM field 624).
• Parity field 636 is 5-bits long and is used to protect (and, for example, correct) the symbol of WOM fields 632 and 634 in a first write operation written a particular location of the WOM device.
• the parity field 638 is 5-bits long and is used to protect the symbol of WOM fields 632 and 634 for the second write.
• the WOM field 632 includes the value "010” and the WOM field 634 includes the value "100.”
• the parity field 636 includes the value "XXXXX” (which is a first SECDED encoding of the first set of contents of WOM fields 632 and 634).
• the parity field 638 would include an (e.g., as-of-yet) undetermined value (“YYYYY”) that is a second SECDED encoding of the (e.g., arbitrarily) new values of symbol fields 632 and 634.
• the parity fields 636 and 638 are written using an encoding (such as "plain” binary) that is different from a WOM-encoding that is used to encode WOM fields 632 and 634.
• Decoding operation 606 is an ECC-decoding operation operable to decode ECC-encoded data as validated data.
• the parity field 636 is used to validate (such as restore) the WOM fields 632 and 634 after a first write operation
• the parity field 638 is used to validate (such as restore) the WOM fields 632 and 634 after a first write operation. Accordingly, the selection of which parity field to use is made in accordance with a logical analysis of the retrieved contents of the WOM fields 632 and 634 (such as discussed above with respect to Table 1), such as to determine whether the particular memory location was written to once or twice. In the event of a one-bit error in the WOM field 632 or the parity fields, 636, the strength of the ECC-encoding is sufficient to correct for the error such that the correct data of WOM field 632 is restorable.
• Decoding operation 608 is a WOM-decoding operation (such as discussed above with respect to FIG. 3) and is operable to decode a WOM-encoded word of an ECC-encoded word to retrieve the (e.g., ideally) original ECC-encoded word.
• decoding operation 608 decodes the WOM-encoded word 620 to (e.g., ideally) retrieve the original data encoded within the WOM-encoded word 620 in encoding operation 602.
• FIG. 7 is an example process flow diagram in accordance with example embodiments.
• Process flow begins in terminal 702 where process flow proceeds to operation 710.
• operation 710 a data word for storing in a WOM device is received.
• the first data word includes at least one original symbol encoded as at least two bits, and is associated with a memory address to be written to and read from.
• Program flow proceeds to step 720.
• a first stage of encoding is applied to the received data word.
• the first stage of encoding is an encoding operation that is a selected one of ECC encoding and WOM encoding.
• Program flow proceeds to step 730.
• a second stage of encoding is applied to the received data word.
• the second stage of encoding is an encoding operation that is the other operation than the selected one of ECC encoding and WOM encoding.
• the first stage operation is a WOM-encoding operation
• the second stage is an ECC-encoding operation.
• the first stage operation is an ECC-encoding operation
• the second stage is a WOM-encoding operation.
• Program flow proceeds to step 740.
• the twice-encoded word (e.g., which is encoded in stage one and stage two, such that the stage-one encoding is encapsulated by the state-two encoding) is stored in the WOM device.
• the WOM device is block initialized (with each and every WOM bit set or cleared to the same logic state) and is written to by changing a bit from the block-initialization state to a programmed state (that is the opposite of the block-initialization state).
• a particular WOM memory location can be overwritten at least once through the use of WOM encoding.
• Program flow proceeds to step 750.
• word stored in the WOM is retrieved, decoded, and the decoded word evaluated. For example, when the WOM-decoded symbol and the ECC bits read from the WOM device indicates an error, an ECC controller is operable to execute a corrective action (such as correct a bit error, generate a system interrupt, or replace the defective location of the WOM device with a spare storage location) in response to the evaluation. Program flow proceeds to terminal 799 where program flow terminates.
• a corrective action such as correct a bit error, generate a system interrupt, or replace the defective location of the WOM device with a spare storage location

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