WO2016171461A1 - Semiconductor device and manufacturing method therefor - Google Patents

Semiconductor device and manufacturing method therefor Download PDF

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Publication number
WO2016171461A1
WO2016171461A1 PCT/KR2016/004100 KR2016004100W WO2016171461A1 WO 2016171461 A1 WO2016171461 A1 WO 2016171461A1 KR 2016004100 W KR2016004100 W KR 2016004100W WO 2016171461 A1 WO2016171461 A1 WO 2016171461A1
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layer
stuffing
diffusion barrier
graphene
semiconductor device
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PCT/KR2016/004100
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French (fr)
Korean (ko)
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김기범
이상훈
김기주
김민수
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서울대학교산학협력단
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table

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  • the present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device including a diffusion barrier layer and a method for manufacturing the same.
  • Carbon atoms include fullerene, carbon nanotube, graphene, graphite, diamond, and the like.
  • graphene has a two-dimensional structure of a honeycomb structure composed of one layer or a plurality of layers of carbon atoms.
  • Graphene has excellent thermal, mechanical, and chemical stability, and has high mobility of carriers, thereby enabling high-speed electronic devices.
  • the thin thickness and high light transmittance make it applicable to flat panel display devices, transistors, energy storages, and nano-sized electronic devices.
  • One of the technical problems of the present invention is to provide a semiconductor device having improved reliability and electrical characteristics and a method of manufacturing the same.
  • a semiconductor device may include a diffusion barrier layer including a graphene layer and a stuffing layer positioned on at least a portion of the graphene layer, and a conductive layer on the diffusion barrier layer.
  • the stuffing layer may be deposited and disposed in an island form on the graphene layer.
  • the islands forming the stuffing layer may have a single crystal structure.
  • the graphene layer may include a plurality of defect regions, and the stuffing layer may be located on the defect regions.
  • the graphene layer may include a plurality of defect regions, and the stuffing layer may have a single crystal structure on the defect regions and a polycrystal structure on other regions.
  • the diffusion barrier layer may further include a catalyst metal layer disposed under the graphene layer.
  • the stuffing layer may be positioned on a surface of the diffusion barrier layer facing the conductive layer.
  • the stuffing layer is tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), molybdenum nitride (MoN), tungsten (W), tungsten nitride (WN) It may include at least one of, ruthenium (Ru), cobalt (Co).
  • the diffusion barrier layer may have a carrier concentration in the range of 5 ⁇ 10 13 / cm 2 to 9 ⁇ 10 16 / cm 2 .
  • the thickness of the diffusion barrier layer may be less than 5 nm.
  • a method of manufacturing a semiconductor device includes forming a diffusion barrier layer including a graphene layer and a stuffing layer covering at least a portion of the graphene layer, and forming a conductive layer on the stuffing layer. It may comprise the step of forming.
  • the stuffing layer may be deposited in an island form on the graphene layer.
  • the graphene layer may include a plurality of defect regions, and the stuffing layer may be formed on the defect regions.
  • the stuffing layer may be formed by atomic layer deposition (ALD).
  • ALD atomic layer deposition
  • the carrier concentration of the diffusion barrier layer may be increased by forming the stuffing layer.
  • FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment.
  • FIGS. 2-5 are schematic views of a diffusion barrier layer in accordance with an exemplary embodiment.
  • 6 to 8 are schematic views according to a process sequence to explain a method of manufacturing a semiconductor device according to an exemplary embodiment.
  • 9A to 9E are electron micrographs for explaining characteristics of the diffusion barrier layer according to an exemplary embodiment.
  • 10 to 12 are graphs for explaining the characteristics of the diffusion barrier layer according to an exemplary embodiment.
  • Embodiments of the present invention may be modified in various other forms or various embodiments may be combined, but the scope of the present invention is not limited to the embodiments described below.
  • the embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Accordingly, the shape and size of elements in the drawings may be exaggerated for clarity, and the elements denoted by the same reference numerals in the drawings are the same elements.
  • FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment.
  • the semiconductor device 10 may include a substrate 100, a first conductive layer 110, an insulating layer 120, a diffusion barrier layer 130, and a second conductive layer 140. .
  • the substrate 100 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI oxide semiconductor.
  • the substrate 100 may include a bulk wafer or an epitaxial layer.
  • the substrate 100 may include a silicon on insulator (SOI) substrate.
  • SOI silicon on insulator
  • the substrate 100 may include another region of the semiconductor device 100 (not illustrated), for example, a transistor region.
  • the first and second conductive layers 110 and 140 represent two regions electrically connected to each other, and may include a conductive material.
  • the first conductive layer 110 may be a doped region formed in the substrate 100 or a conductive region formed on the substrate 100, and the second conductive layer 140 may include a contact plug. It may be an area of the structure.
  • the first and second conductive layers 110 and 140 may be, for example, doped silicon (Si), copper (Cu), aluminum (Al), nickel (Ni), silver (Ag), gold (Au), or platinum. At least one selected from the group consisting of (Pt), tin (Sn), lead (Pb), titanium (Ti), chromium (Cr), palladium (Pd), indium (In), zinc (Zn) and carbon (C) It may include a metal, a metal alloy or a metal oxide.
  • the first and second conductive layers 110 and 140 may be formed using electroplating, physical vapor deposition (PVD), or chemical vapor deposition (CVD).
  • the insulating layer 120 may include an insulating material, such as a low- k material.
  • the low dielectric material may have a dielectric constant of less than about four.
  • the low dielectric material may be, for example, silicon carbide (SiC), silicon oxide (SiO 2 ), fluorine-containing silicon oxide (SiOF), or fluorine-containing oxide.
  • the diffusion barrier layer 130 may be used as an adhesive layer for forming the diffusion barrier layer and / or the second conductive layer 140 with respect to the material of the second conductive layer 140.
  • the diffusion barrier layer 130 may be formed of a graphene-containing film according to an embodiment of the present invention.
  • the diffusion barrier layer 130 may include a graphene layer 132 and a stuffing layer 134.
  • the graphene layer 132 may be formed of one or more two-dimensional graphene layers.
  • the stuffing layer 134 may be located on at least a portion of the graphene layer 132.
  • the stuffing layer 134 may be a layer for stuffing the defect region of the graphene layer 132 and doping the graphene layer 132.
  • the structure of the diffusion barrier layer 130 will be described in more detail with reference to FIGS. 2 to 5 below.
  • the thickness Td of the diffusion barrier layer 130 may be 5 nm or less, for example, in a range of 0.5 nm to 5 nm.
  • the diffusion barrier layer 130 may have a carrier concentration in the range of 5 ⁇ 10 13 / cm 2 to 9 ⁇ 10 16 / cm 2 . This is higher than the concentration of a single carrier of the graphene layer 132, whereby the contact resistance of the diffusion barrier layer 130 may be reduced.
  • the diffusion barrier layer 130 may have excellent diffusion barrier properties even in a relatively thin thickness. The electrical characteristics of the diffusion barrier layer 130 will be described in more detail with reference to FIGS. 10 to 12 below.
  • FIGS. 2-5 are schematic views of a diffusion barrier layer in accordance with an exemplary embodiment.
  • the diffusion barrier layer 130 may include a graphene layer 132 and a stuffing layer 134 formed on at least a portion of the graphene layer 132.
  • the graphene layer 132 may include a plurality of crystal grains (G) in two dimensions.
  • the term 'crystal grains' forms a graphene layer 132 and is used as a term referring to a two-dimensional region made of hexagonal carbons arranged in the same direction. Therefore, one grain (G) may be composed of carbons of hexagonal structure arranged in one direction.
  • the shape and arrangement of the crystal grains G itself are not limited to those shown.
  • a grain boundary GB is formed between the plurality of grains G.
  • the grain boundary GB is a kind of two-dimensional defects.
  • the carbons forming the grains G are not bonded in a hexagonal structure, but are bonded in a deformed structure such as a pentagon, a hexagon, and the like.
  • other defects such as point defects, may be present inside the grains G.
  • FIG. These defects may be formed during manufacture of the graphene layer 132, and the materials of the second conductive layer 140 (see FIG. 1) may be relatively easily diffused through the defects. Defects can also affect the mobility of the carrier, reducing the mobility of the carrier.
  • the stuffing layer 134 is disposed on a surface of the diffusion barrier layer 130 facing the second conductive layer 140 and may be formed in an island shape on the graphene layer 132.
  • the stuffing layer 134 may be formed on defect regions such as defects in grain boundaries GB and grains G of the graphene layer 132 to fill or stuff the defect regions.
  • This structure can be formed by controlling the growth conditions of the stuffing layer 134 so that the defect regions are relatively thermodynamically unstable, so that the source material is preferentially bonded to these defect regions to allow the stuffing layer 134 to grow. have. Since the stuffing layer 134 is formed on the defect region, the diffusion of the material through the defect region may be effectively prevented, so that the characteristics of the diffusion barrier layer 130 may be improved.
  • the stuffing layer 134 is grown spaced apart from each other in a plurality of island shapes, but at least some of the stuffing layers 134 may be connected to each other during growth.
  • the specific shape and size of the stuffing layer 134 is not limited to that shown in the drawings.
  • the islands constituting the stuffing layer 134 may have a single crystal structure, and thus may not include grain boundaries therein. Thus, it is possible to more effectively prevent the diffusion of the material through the defects.
  • the stuffing layer 134 may be made of a conductive material, and may include tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), molybdenum nitride (MoN), tungsten (W), and tungsten nitride (WN). ), Ruthenium (Ru), cobalt (Co) may include at least one, but is not limited thereto.
  • the stuffing layer 134 may be selected as a material capable of preventing diffusion and / or adhering to the second conductive layer 140 according to the kind of the material forming the second conductive layer 140.
  • the diffusion barrier layer 130a may include a graphene layer 132 and a stuffing layer 134a formed on at least a portion of the graphene layer 132.
  • the stuffing layer 134a of the present embodiment is not only formed on the defect regions such as the grain boundary GB of the graphene layer 132, but may also be formed on the grain G inside the grain G.
  • the formation of the stuffing layer 134a may be controlled according to deposition conditions such as deposition temperature, time, and the number of times of input of the source material.
  • the stuffing layer 134a may be preferentially formed on the defect regions as in the embodiment of FIG. 2, but may be additionally formed in the island shape on the grains G in the grains G.
  • FIG. 4B shows a cross section taken along cut line X-X ′ of FIG. 4A.
  • the diffusion barrier layer 130b may include a graphene layer 132 and a stuffing layer 134b formed on the graphene layer 132.
  • the stuffing layer 134b of the present embodiment may be formed on the entire region of the graphene layer 132.
  • the stuffing layer 134b may include first and second regions R1 and R2, where the first region R1 is a region on the defective region and the second region R2 is a crystal grain of the graphene layer 132 ( G) may be a region on.
  • the stuffing layer 134b constituting the second region R2 may include a plurality of crystal grains as shown, and the size thereof is not limited thereto.
  • the enlarged view in FIG. 4A shows the crystal direction in each of the regions R1 and R2.
  • the stuffing layer 134b may have a single crystal structure in the first region R1 and a polycrystalline structure in the second region R2.
  • the stuffing layer 134b is formed on a relatively small size of the defect, so that the stuffing layer 134b may grow in the form of an island of a single crystal, and in the second region R2, it grows on a relatively large grain G. It can grow into a polycrystalline structure having a plurality of crystal grains.
  • each of the islands constituting the first region R1 may be regarded as one grain.
  • the stuffing layer 134b may be described as having a smaller grain size in the first region R1 than a grain size in the second region R2.
  • the diffusion barrier layer 130c may further include a catalyst metal layer 131 in addition to the graphene layer 132 and the stuffing layer 134.
  • the catalytic metal layer 131 is disposed under the graphene layer 132, and may be a graphitization catalyst for depositing the graphene layer 132.
  • the catalytic metal layer 131 may be formed of, for example, copper (Cu), nickel (Ni), cobalt (Co), palladium (Pd), iron (Fe), platinum (Pt), ruthenium (Ru), iridium (Ir), and the like. It may include at least one of rhodium (Rh).
  • the diffusion barrier layer 130c includes the graphene layer 132 and the stuffing layer 134 having a relatively small thickness, the diffusion barrier layer 130c may be formed to have a relatively small thickness even if the catalyst metal layer 131 is further included. In addition, by including the catalyst metal layer 131, the graphene layer 132 may be more easily formed.
  • the coverage of the grains G constituting the graphene layer 132 is not limited to that shown in the drawing.
  • the plurality of crystal grains G is shown to completely cover the catalyst metal layer 131, but such coverage may be variously changed.
  • at least a portion of the graphene layer 132 may be formed of multiple layers instead of a single layer.
  • 6 to 8 are schematic views according to a process sequence to explain a method of manufacturing a semiconductor device according to an exemplary embodiment.
  • the first conductive layer 110 and the insulating layer 120 may be formed on the substrate 100.
  • the first conductive layer 110 represents a lower wiring layer or a lower conductive region, and may include a conductive material.
  • the first conductive layer 110 may be deposited using electroplating, PVD, or CVD.
  • an opening OP may be formed in the insulating layer 120 to expose a portion of the first conductive layer 110.
  • the opening OP may be formed by an etching process, and a separate etching stop layer may be used. Vias may be formed in the narrow area of the lower portion of the opening OP, and wiring lines may be formed in the wide area of the upper portion of the opening OP, but are not limited thereto.
  • the graphene layer 132 forming the diffusion barrier layer 130 may be formed in the opening OP of the insulating layer 120.
  • the graphene layer 132 may be formed using various methods.
  • the graphene layer 132 is formed by depositing directly in the opening OP using, for example, CVD, molecular beam epitaxy, or by applying graphene flakes. Can be formed.
  • the prepared graphene sheet may be formed by a method of transferring.
  • the catalytic metal layer 131 may be further disposed below the graphene layer 132, and the graphene layer 132 may be formed using the same.
  • the carbon source in a gaseous state may be supplied onto the catalyst metal layer 131, and the graphene layer 132 may be formed by decomposing the carbon source.
  • the carbon source may be any one of carbon monoxide, methane, ethane, ethylene, ethanol, acetylene, propane, propylene, butane, butadiene, pentane, pentene, cyclopentadiene, hexane, cyclohexane, benzene and toluene.
  • a stuffing layer 134 may be formed on the graphene layer 132.
  • the stuffing layer 134 may be formed using atomic layer deposition (ALD).
  • ALD atomic layer deposition
  • the method of forming the stuffing layer 134 is not limited thereto, and CVD, PVD, or the like may be used.
  • ALD atomic layer deposition
  • deposition of a film uniform in high aspect ratio patterns is possible.
  • one cycle in which the precursor, the purge gas, the reactant gas, and the purge gas are sequentially injected may be repeated a plurality of times to form the stuffing layer 134 having a desired thickness and coverage.
  • the defect region of the graphene layer 132 is thermodynamically unstable so that the source material is preferentially adsorbed on the defect region and thus the stuffing layer 134 is formed. Nucleation may occur.
  • the island-shaped stuffing layer 134 grown from the nucleus may be grown along the defect area. Since the size of the defect region is relatively small, the stuffing layer 134 formed thereon may have a single crystal structure.
  • the diffusion barrier layer 130 including the graphene layer 132 and the stuffing layer 134 may be formed.
  • the diffusion barrier layer 130 is illustrated in detail by dividing the graphene layer 132 and the stuffing layer 134.
  • the diffusion barrier layer 130 of the present embodiment may secure electrical characteristics while being formed in a relatively thin thickness.
  • the stuffing layer 134 on the graphene layer 132, it is possible to improve the diffusion prevention function and reduce the contact resistance.
  • a second conductive layer 140 may be formed on the diffusion barrier layer 130.
  • the second conductive layer 140 may include a conductive material, and for example, may include copper (Cu).
  • the second conductive layer 140 may be deposited using, for example, CVD, ALD, or electrolytic plating.
  • the diffusion barrier layer 130 and the second conductive layer 140 deposited on the insulating layer 120 may be removed using a planarization process. As a result, the semiconductor device 10 including the wiring structure according to the exemplary embodiment of the present invention is finally formed.
  • the diffusion barrier layer 130 is used in the wiring structure of the semiconductor device, but the use of the stacked structure of the graphene layer 132 and the stuffing layer 134 according to the present invention is not limited thereto. It may be applied to semiconductor devices for various purposes.
  • 9A to 9E are electron micrographs for explaining characteristics of the diffusion barrier layer according to an exemplary embodiment.
  • the deposition cycle changes to 20, 50, 100, 200, 400, the coverage of the stuffing layer appearing in bright colors increases.
  • the stuffing layer was preferentially deposited in defect areas such as the wrinkle of the graphene layer, but also in other areas as the cycle increased. Therefore, by adjusting the deposition cycle, it is possible to make the stuffing layer mainly formed on the defect area, thereby minimizing the deterioration of the electrical characteristics due to the defect.
  • a stuffing layer may be formed in a region other than the defect region to improve other electrical characteristics such as sheet resistance.
  • 10 to 12 are graphs for describing the electrical characteristics of the diffusion barrier layer according to an exemplary embodiment.
  • the sheet resistance decreased and the carrier concentration tended to increase. Specifically, as shown in FIG. 10, the sheet resistance had a value of about 550 mA / ⁇ on average before the deposition of the stuffing layer, but as the stuffing layer was formed, about 180 mA / ⁇ at 20 cycles and about 120 mA / 50 at 50 cycles. Gradually decreased to ⁇ . This decrease in sheet resistance may be due to an increase in carrier concentration.
  • the carrier concentration is before deposition of the stuffing layer on average about 2 ⁇ 10 13 / cm 2 degree yieoteuna, from about 6 ⁇ 10 13 / cm 2, 50 cycles at 20 cycles as to form a stuffing layer of about 8 ⁇ 10 13 / cm 2 Increased.
  • This increase in carrier concentration may be considered to be because the work function of ruthenium (Ru) used as the stuffing layer is larger than the work function of the graphene layer so that the graphene layer is doped with p-type.
  • the electron mobility did not change significantly until 50 cycles and then decreased. Therefore, when the deposition cycle is 100 or less, it can be interpreted that the electron mobility decreases relatively, while the carrier concentration greatly increases, thereby improving the electrical characteristics.
  • the diffusion barrier layer of the present embodiment includes a graphene layer and a stuffing layer, whereby the carrier concentration is relatively increased and the electron mobility is relatively reduced, so that the sheet resistance can be reduced. Accordingly, when the diffusion barrier layer of the present embodiment is used in the semiconductor device, the contact resistance can be reduced as compared with the case where only the graphene layer is used as the diffusion barrier layer.

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Abstract

The present invention provides a semiconductor device and a manufacturing method therefor. The semiconductor device according to one embodiment of the present invention comprises: an anti-diffusion layer including a graphene layer and a stuffing layer positioned on at least a partial area of the graphene layer; and a conductive layer on the anti-diffusion layer.

Description

반도체 소자 및 그 제조 방법Semiconductor device and manufacturing method thereof
본 발명은 반도체 소자 및 그 제조 방법에 관한 것으로, 보다 상세하게는, 확산 방지층을 포함하는 반도체 소자 및 그 제조 방법에 관한 것이다.The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device including a diffusion barrier layer and a method for manufacturing the same.
탄소 원자들로 구성된 물질로는 풀러렌(fullerene), 탄소나노튜브(carbon nanotube), 그래핀(graphene), 흑연(graphite), 다이아몬드(diamond) 등이 있다. 이 중, 그래핀은 탄소 원자 한 층 또는 복수의 층으로 이루어진 벌집 구조의 2차원 구조를 갖는다. 그래핀은 열적, 기계적 및 화학적 안정성이 뛰어나며, 캐리어(carrier)의 이동도(mobility)가 커서 고속 전자 소자를 구현할 수 있다. 또한, 두께가 얇고 투광성이 높아, 평판 표시 소자, 트랜지스터, 에너지 저장체 및 나노 크기의 전자 소자로의 응용성이 크다. Materials composed of carbon atoms include fullerene, carbon nanotube, graphene, graphite, diamond, and the like. Of these, graphene has a two-dimensional structure of a honeycomb structure composed of one layer or a plurality of layers of carbon atoms. Graphene has excellent thermal, mechanical, and chemical stability, and has high mobility of carriers, thereby enabling high-speed electronic devices. In addition, the thin thickness and high light transmittance make it applicable to flat panel display devices, transistors, energy storages, and nano-sized electronic devices.
본 발명의 기술적 사상이 이루고자 하는 기술적 과제 중 하나는, 신뢰성 및 전기적 특성이 향상된 반도체 소자 및 그 제조 방법을 제공하는 것이다.One of the technical problems of the present invention is to provide a semiconductor device having improved reliability and electrical characteristics and a method of manufacturing the same.
본 발명의 일 실시예에 따른 반도체 소자는, 그래핀층 및 상기 그래핀층의 적어도 일부 영역 상에 위치하는 스터핑(stuffing)층을 포함하는 확산 방지층, 및 상기 확산 방지층 상의 도전층을 포함할 수 있다.A semiconductor device according to an embodiment of the present invention may include a diffusion barrier layer including a graphene layer and a stuffing layer positioned on at least a portion of the graphene layer, and a conductive layer on the diffusion barrier layer.
본 발명의 일부 실시예에서, 상기 스터핑층은 상기 그래핀층 상에 아일랜드 형태로 증착되어 배치될 수 있다.In some embodiments of the present invention, the stuffing layer may be deposited and disposed in an island form on the graphene layer.
본 발명의 일부 실시예에서, 상기 스터핑층을 이루는 아일랜드들은 단결정 구조를 가질 수 있다.In some embodiments of the present invention, the islands forming the stuffing layer may have a single crystal structure.
본 발명의 일부 실시예에서, 상기 그래핀층은 복수의 결함 영역들을 포함하고, 상기 스터핑층은 상기 결함 영역들 상에 위치할 수 있다.In some embodiments of the present invention, the graphene layer may include a plurality of defect regions, and the stuffing layer may be located on the defect regions.
본 발명의 일부 실시예에서, 상기 그래핀층은 복수의 결함 영역들을 포함하고, 상기 스터핑층은 상기 결함 영역들 상에서 단결정 구조를 가지고, 그 외의 영역 상에서 다결정 구조를 가질 수 있다.In some embodiments of the present invention, the graphene layer may include a plurality of defect regions, and the stuffing layer may have a single crystal structure on the defect regions and a polycrystal structure on other regions.
본 발명의 일부 실시예에서, 상기 확산 방지층은, 상기 그래핀층 하부에 배치되는 촉매 금속층을 더 포함할 수 있다.In some embodiments of the present disclosure, the diffusion barrier layer may further include a catalyst metal layer disposed under the graphene layer.
본 발명의 일부 실시예에서, 상기 스터핑층은 상기 확산 방지층이 상기 도전층과 마주하는 면에 위치할 수 있다.In some embodiments of the present disclosure, the stuffing layer may be positioned on a surface of the diffusion barrier layer facing the conductive layer.
본 발명의 일부 실시예에서, 상기 스터핑층은 탄탈륨(Ta), 탄탈륨 질화물(TaN), 티타늄(Ti), 티타늄 질화물(TiN), 몰리브덴 질화물(MoN), 텅스텐(W), 텅스텐 질화물(WN), 루테늄(Ru), 코발트(Co) 중 적어도 하나를 포함할 수 있다.In some embodiments of the present invention, the stuffing layer is tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), molybdenum nitride (MoN), tungsten (W), tungsten nitride (WN) It may include at least one of, ruthenium (Ru), cobalt (Co).
본 발명의 일부 실시예에서, 상기 확산 방지층은 5×1013/cm2 내지 9×1016/cm2 범위의 캐리어 농도를 가질 수 있다.In some embodiments of the present invention, the diffusion barrier layer may have a carrier concentration in the range of 5 × 10 13 / cm 2 to 9 × 10 16 / cm 2 .
본 발명의 일부 실시예에서, 상기 확산 방지층의 두께는 5 nm보다 작을 수 있다.In some embodiments of the present invention, the thickness of the diffusion barrier layer may be less than 5 nm.
본 발명의 일 실시예에 따른 반도체 소자의 제조 방법은, 그래핀층 및 상기 그래핀층의 적어도 일부를 덮는 스터핑(stuffing)층을 포함하는 확산 방지층을 형성하는 단계, 및 상기 스터핑층 상에 도전층을 형성하는 단계를 포함할 수 있다.A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a diffusion barrier layer including a graphene layer and a stuffing layer covering at least a portion of the graphene layer, and forming a conductive layer on the stuffing layer. It may comprise the step of forming.
본 발명의 일부 실시예에서, 상기 스터핑층은 상기 그래핀층 상에 아일랜드 형태로 증착될 수 있다.In some embodiments of the present invention, the stuffing layer may be deposited in an island form on the graphene layer.
본 발명의 일부 실시예에서, 상기 그래핀층은 복수의 결함 영역들을 포함하고, 상기 스터핑층은 상기 결함 영역들 상에 형성될 수 있다.In some embodiments of the present invention, the graphene layer may include a plurality of defect regions, and the stuffing layer may be formed on the defect regions.
본 발명의 일부 실시예에서, 상기 스터핑층은 원자층 증착법(ALD)에 의해 형성할 수 있다.In some embodiments of the present invention, the stuffing layer may be formed by atomic layer deposition (ALD).
본 발명의 일부 실시예에서, 상기 스터핑층을 형성함으로써, 상기 확산 방지층의 캐리어 농도가 증가할 수 있다.In some embodiments of the present disclosure, the carrier concentration of the diffusion barrier layer may be increased by forming the stuffing layer.
그래핀층 상에 스터핑층을 형성한 확산 방지층으로 이용함으로써, 신뢰성 및 전기적 특성이 향상된 반도체 소자 및 그 제조 방법이 제공될 수 있다.By using it as a diffusion barrier layer having a stuffing layer formed on the graphene layer, a semiconductor device having improved reliability and electrical characteristics and a method of manufacturing the same can be provided.
본 발명의 다양하면서도 유익한 장점과 효과는 상술한 내용에 한정되지 않으며, 본 발명의 구체적인 실시형태를 설명하는 과정에서 보다 쉽게 이해될 수 있을 것이다.Various and advantageous advantages and effects of the present invention are not limited to the above description, and will be more readily understood in the course of describing specific embodiments of the present invention.
도 1은 예시적인 실시예에 따른 반도체 소자의 개략적인 단면도이다.1 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment.
도 2 내지 도 5는 예시적인 실시예에 따른 확산 방지층의 개략적인 도면들이다.2-5 are schematic views of a diffusion barrier layer in accordance with an exemplary embodiment.
도 6 내지 도 8은 예시적인 실시예에 따른 반도체 소자의 제조 방법을 설명하기 위하여 공정 순서에 따라 도시한 개략도들이다.6 to 8 are schematic views according to a process sequence to explain a method of manufacturing a semiconductor device according to an exemplary embodiment.
도 9a 내지 도 9e는 예시적인 실시예에 따른 확산 방지층의 특징을 설명하기 위한 전자현미경 사진들이다. 9A to 9E are electron micrographs for explaining characteristics of the diffusion barrier layer according to an exemplary embodiment.
도 10 내지 도 12는 예시적인 실시예에 따른 확산 방지층의 특성을 설명하기 위한 그래프들이다.10 to 12 are graphs for explaining the characteristics of the diffusion barrier layer according to an exemplary embodiment.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예들을 다음과 같이 설명한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.
본 발명의 실시예는 여러 가지 다른 형태로 변형되거나 여러 가지 실시예가 조합될 수 있으며, 본 발명의 범위가 이하 설명하는 실시예로 한정되는 것은 아니다. 또한, 본 발명의 실시예는 당해 기술분야에서 평균적인 지식을 가진 자에게 본 발명을 더욱 완전하게 설명하기 위해서 제공되는 것이다. 따라서, 도면에서의 요소들의 형상 및 크기 등은 보다 명확한 설명을 위해 과장될 수 있으며, 도면 상의 동일한 부호로 표시되는 요소는 동일한 요소이다.Embodiments of the present invention may be modified in various other forms or various embodiments may be combined, but the scope of the present invention is not limited to the embodiments described below. In addition, the embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Accordingly, the shape and size of elements in the drawings may be exaggerated for clarity, and the elements denoted by the same reference numerals in the drawings are the same elements.
도 1은 예시적인 실시예에 따른 반도체 소자의 개략적인 단면도이다.1 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment.
도 1을 참조하면, 반도체 소자(10)는, 기판(100), 제1 도전층(110), 절연층(120), 확산 방지층(130) 및 제2 도전층(140)을 포함할 수 있다.Referring to FIG. 1, the semiconductor device 10 may include a substrate 100, a first conductive layer 110, an insulating layer 120, a diffusion barrier layer 130, and a second conductive layer 140. .
기판(100)은 반도체 물질, 예컨대 Ⅳ족 반도체, Ⅲ-Ⅴ족 화합물 반도체, 또는 Ⅱ-Ⅵ족 산화물 반도체를 포함할 수 있다. 기판(100)은 벌크 웨이퍼(bulk wafer) 또는 에피텍셜(epitaxial)층을 포함할 수 있다. 또한, 기판(100)은 SOI(Silicon On Insulator) 기판을 포함할 수 있다. 기판(100)에는 도시하지 않은 반도체 소자(100)의 다른 영역, 예를 들어 트랜지스터 영역 등이 포함될 수 있다.The substrate 100 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI oxide semiconductor. The substrate 100 may include a bulk wafer or an epitaxial layer. In addition, the substrate 100 may include a silicon on insulator (SOI) substrate. The substrate 100 may include another region of the semiconductor device 100 (not illustrated), for example, a transistor region.
제1 및 제2 도전층(110, 140)은 서로 전기적으로 연결되는 두 영역을 나타내는 것으로, 도전성 물질을 포함할 수 있다. 일 실시예에서, 제1 도전층(110)은 기판(100) 내에 형성된 도핑 영역이거나, 기판(100) 상에 형성된 도전 영역일 수 있으며, 제2 도전층(140)은 콘택 플러그를 포함하는 배선 구조의 일 영역일 수 있다.The first and second conductive layers 110 and 140 represent two regions electrically connected to each other, and may include a conductive material. In one embodiment, the first conductive layer 110 may be a doped region formed in the substrate 100 or a conductive region formed on the substrate 100, and the second conductive layer 140 may include a contact plug. It may be an area of the structure.
제1 및 제2 도전층(110, 140)은 예를 들어, 도핑된 실리콘(Si), 구리(Cu), 알루미늄(Al), 니켈(Ni), 은(Ag), 금(Au), 백금(Pt), 주석(Sn), 납(Pb), 티타늄(Ti), 크롬(Cr), 팔라듐(Pd), 인듐(In), 아연(Zn) 및 탄소(C)로 구성된 그룹으로부터 선택된 적어도 하나의 금속, 금속 합금 또는 금속 산화물을 포함할 수 있다. 제1 및 제2 도전층(110, 140)은 전해 도금법(electroplating), 물리 기상 증착법(Physical Vapor Deposition, PVD) 또는 화학 기상 증착법(Chemical Vapor Deposition, CVD) 방식을 이용하여 형성할 수 있다.The first and second conductive layers 110 and 140 may be, for example, doped silicon (Si), copper (Cu), aluminum (Al), nickel (Ni), silver (Ag), gold (Au), or platinum. At least one selected from the group consisting of (Pt), tin (Sn), lead (Pb), titanium (Ti), chromium (Cr), palladium (Pd), indium (In), zinc (Zn) and carbon (C) It may include a metal, a metal alloy or a metal oxide. The first and second conductive layers 110 and 140 may be formed using electroplating, physical vapor deposition (PVD), or chemical vapor deposition (CVD).
절연층(120)은 절연 물질, 예컨대 저유전(low-k) 물질을 포함할 수 있다. 상기 저유전 물질은 약 4 미만의 유전 상수(dielectric constant)를 가질 수 있다. 상기 저유전 물질은 예를 들어, 실리콘 탄화물(SiC), 실리콘 산화물(SiO2), 불소 함유 실리콘 산화물(SiOF) 또는 불소 함유 산화물일 수 있다. The insulating layer 120 may include an insulating material, such as a low- k material. The low dielectric material may have a dielectric constant of less than about four. The low dielectric material may be, for example, silicon carbide (SiC), silicon oxide (SiO 2 ), fluorine-containing silicon oxide (SiOF), or fluorine-containing oxide.
확산 방지층(130)은 제2 도전층(140) 물질에 대한 확산 방지층 및/또는 제2 도전층(140)의 형성을 위한 접착층으로서 이용될 수 있다. 확산 방지층(130)은 본 발명의 일 실시예에 따른 그래핀 함유막으로 형성될 수 있다. 확산 방지층(130)은 그래핀층(132) 및 스터핑층(134)을 포함할 수 있다. 그래핀층(132)은 하나 이상의 2차원 그래핀층으로 이루어질 수 있다. 스터핑층(134)은 그래핀층(132)의 적어도 일부 영역 상에 위치할 수 있다. 스터핑층(134)은 그래핀층(132)의 결함 영역을 스터핑하고, 그래핀층(132)을 도핑하는 층일 수 있다. 확산 방지층(130)의 구조에 대해서는 하기에 도 2 내지 도 5를 참조하여 더욱 상세히 설명한다.The diffusion barrier layer 130 may be used as an adhesive layer for forming the diffusion barrier layer and / or the second conductive layer 140 with respect to the material of the second conductive layer 140. The diffusion barrier layer 130 may be formed of a graphene-containing film according to an embodiment of the present invention. The diffusion barrier layer 130 may include a graphene layer 132 and a stuffing layer 134. The graphene layer 132 may be formed of one or more two-dimensional graphene layers. The stuffing layer 134 may be located on at least a portion of the graphene layer 132. The stuffing layer 134 may be a layer for stuffing the defect region of the graphene layer 132 and doping the graphene layer 132. The structure of the diffusion barrier layer 130 will be described in more detail with reference to FIGS. 2 to 5 below.
확산 방지층(130)의 두께(Td)는 5 nm 이하, 예를 들어, 0.5 nm 내지 5 nm의 범위일 수 있다. 또한, 확산 방지층(130)은 5×1013/cm2 내지 9×1016/cm2 범위의 캐리어 농도를 가질 수 있다. 이는 그래핀층(132) 단일의 캐리어 농도보다 높은 값으로, 이에 의해 확산 방지층(130)의 접촉 저항이 감소될 수 있다.The thickness Td of the diffusion barrier layer 130 may be 5 nm or less, for example, in a range of 0.5 nm to 5 nm. In addition, the diffusion barrier layer 130 may have a carrier concentration in the range of 5 × 10 13 / cm 2 to 9 × 10 16 / cm 2 . This is higher than the concentration of a single carrier of the graphene layer 132, whereby the contact resistance of the diffusion barrier layer 130 may be reduced.
반도체 소자(100)의 디자인 룰이 감소함에 따라, 반도체 소자(100)를 이루는 구성 요소들의 고집적화가 요구된다. 이에 따라, 배선 구조 및 이를 이루는 확산 방지층(130)의 두께도 감소될 것이 요구된다. 본 발명의 실시예에 따른 확산 방지층(130)은 상대적으로 얇은 두께에서도 우수한 확산 방지 특성을 가질 수 있다. 확산 방지층(130)의 전기적 특성에 대해서는 하기에 도 10 내지 도 12를 참조하여 더욱 상세히 설명한다. As the design rule of the semiconductor device 100 decreases, high integration of components constituting the semiconductor device 100 is required. Accordingly, the thickness of the wiring structure and the diffusion barrier layer 130 constituting the wiring structure is also required. The diffusion barrier layer 130 according to the embodiment of the present invention may have excellent diffusion barrier properties even in a relatively thin thickness. The electrical characteristics of the diffusion barrier layer 130 will be described in more detail with reference to FIGS. 10 to 12 below.
도 2 내지 도 5는 예시적인 실시예에 따른 확산 방지층의 개략적인 도면들이다.2-5 are schematic views of a diffusion barrier layer in accordance with an exemplary embodiment.
도 2의 평면도를 참조하면, 확산 방지층(130)은 그래핀층(132) 및 그래핀층(132)의 적어도 일부 영역 상에 형성된 스터핑층(134)을 포함할 수 있다.Referring to the plan view of FIG. 2, the diffusion barrier layer 130 may include a graphene layer 132 and a stuffing layer 134 formed on at least a portion of the graphene layer 132.
그래핀층(132)은 2차원의 복수의 결정립들(crystal grains)(G)을 포함할 수 있다. 본 명세서에서, '결정립'은 그래핀층(132)을 이루며, 동일한 방향으로 배열된 육각형 구조의 탄소들로 이루어진 2차원 영역을 지칭하는 용어로 사용된다. 따라서, 하나의 결정립(G)은 일 방향으로 배열된 육각형 구조의 탄소들로 이루어질 수 있다. 다만, 결정립들(G) 자체의 형상 및 배열은 도시된 것에 한정되지 않는다. 복수의 결정립들(G)의 사이에는, 결정립계(grain boundary)(GB)가 형성된다. 결정립계(GB)는 일종의 2차원 결함(defect)으로서, 결정립계(GB)에서는 결정립들(G)을 이루는 탄소들이 육각형 구조로 결합되지 못하고, 오각형, 칠각형 등과 같은 변형된 구조로 결합된다. 또한, 결정립들(G) 내부에는 점 결함 등과 같은 다른 결함들이 더 존재할 수 있다. 이러한 결함들은 그래핀층(132)의 제조 중에 형성될 수 있으며, 결함들을 통해 제2 도전층(140)(도 1 참조)의 물질이 상대적으로 용이하게 확산될 수 있다. 또한, 결함들은 캐리어의 이동성에 영향을 주어 캐리어의 이동성을 감소시킬 수 있다.The graphene layer 132 may include a plurality of crystal grains (G) in two dimensions. In the present specification, the term 'crystal grains' forms a graphene layer 132 and is used as a term referring to a two-dimensional region made of hexagonal carbons arranged in the same direction. Therefore, one grain (G) may be composed of carbons of hexagonal structure arranged in one direction. However, the shape and arrangement of the crystal grains G itself are not limited to those shown. Between the plurality of grains G, a grain boundary GB is formed. The grain boundary GB is a kind of two-dimensional defects. In the grain boundary GB, the carbons forming the grains G are not bonded in a hexagonal structure, but are bonded in a deformed structure such as a pentagon, a hexagon, and the like. In addition, other defects, such as point defects, may be present inside the grains G. FIG. These defects may be formed during manufacture of the graphene layer 132, and the materials of the second conductive layer 140 (see FIG. 1) may be relatively easily diffused through the defects. Defects can also affect the mobility of the carrier, reducing the mobility of the carrier.
스터핑층(134)은 확산 방지층(130)이 제2 도전층(140)과 마주하는 면에 위치하며, 그래핀층(132) 상에 아일랜드 형태로 형성될 수 있다. 특히, 본 실시예에서 스터핑층(134)은 그래핀층(132)의 결정립계(GB) 및 결정립(G) 내의 결함과 같은 결함 영역 상에 형성되어, 결함 영역을 충전 또는 스터핑할 수 있다. 이러한 구조는 상기 결함 영역들이 상대적으로 열역학적으로 불안정한 상태이므로, 스터핑층(134)의 성장 조건을 제어함으로써 이러한 결함 영역들에 우선적으로 소스 물질이 결합되어 스터핑층(134)이 성장되게 함으로써 형성될 수 있다. 스터핑층(134)이 결함 영역 상에 형성됨으로써, 결함 영역을 통한 물질의 확산을 효과적으로 저지할 수 있어, 확산 방지층(130)의 특성이 향상될 수 있다.The stuffing layer 134 is disposed on a surface of the diffusion barrier layer 130 facing the second conductive layer 140 and may be formed in an island shape on the graphene layer 132. In particular, in the present embodiment, the stuffing layer 134 may be formed on defect regions such as defects in grain boundaries GB and grains G of the graphene layer 132 to fill or stuff the defect regions. This structure can be formed by controlling the growth conditions of the stuffing layer 134 so that the defect regions are relatively thermodynamically unstable, so that the source material is preferentially bonded to these defect regions to allow the stuffing layer 134 to grow. have. Since the stuffing layer 134 is formed on the defect region, the diffusion of the material through the defect region may be effectively prevented, so that the characteristics of the diffusion barrier layer 130 may be improved.
스터핑층(134)은 복수의 아일랜드 형태로 서로 이격되어 성장되지만, 성장 중에 적어도 일부는 서로 연결될 수도 있다. 스터핑층(134)의 구체적인 형상 및 크기는 도면에 도시된 것에 한정되지 않는다. 스터핑층(134)을 이루는 아일랜드들은 각각이 단결정 구조를 가질 수 있으며, 따라서 내부에 결정립계를 포함하지 않을 수 있다. 따라서, 결함들을 통한 물질의 확산을 더욱 효과적으로 저지할 수 있다.The stuffing layer 134 is grown spaced apart from each other in a plurality of island shapes, but at least some of the stuffing layers 134 may be connected to each other during growth. The specific shape and size of the stuffing layer 134 is not limited to that shown in the drawings. The islands constituting the stuffing layer 134 may have a single crystal structure, and thus may not include grain boundaries therein. Thus, it is possible to more effectively prevent the diffusion of the material through the defects.
스터핑층(134)은 도전성 물질로 이루어질 수 있으며, 탄탈륨(Ta), 탄탈륨 질화물(TaN), 티타늄(Ti), 티타늄 질화물(TiN), 몰리브덴 질화물(MoN), 텅스텐(W), 텅스텐 질화물(WN), 루테늄(Ru), 코발트(Co) 중 적어도 하나를 포함할 수 있으나, 이에 한정되지 않는다. 스터핑층(134)은 제2 도전층(140)을 이루는 물질의 종류에 따라, 이에 대한 확산 방지 및/또는 접착 기능을 할 수 있는 물질로 선택될 수 있다.The stuffing layer 134 may be made of a conductive material, and may include tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), molybdenum nitride (MoN), tungsten (W), and tungsten nitride (WN). ), Ruthenium (Ru), cobalt (Co) may include at least one, but is not limited thereto. The stuffing layer 134 may be selected as a material capable of preventing diffusion and / or adhering to the second conductive layer 140 according to the kind of the material forming the second conductive layer 140.
도 3의 평면도를 참조하면, 확산 방지층(130a)은 그래핀층(132) 및 그래핀층(132)의 적어도 일부 영역 상에 형성된 스터핑층(134a)을 포함할 수 있다.Referring to the plan view of FIG. 3, the diffusion barrier layer 130a may include a graphene layer 132 and a stuffing layer 134a formed on at least a portion of the graphene layer 132.
본 실시예의 스터핑층(134a)은 그래핀층(132)의 결정립계(GB)와 같은 결함 영역들 상에만 형성되지 않고, 결정립(G)의 내부에서 결정립(G) 상에도 형성될 수 있다. 이와 같은 스터핑층(134a)의 형성은 증착 온도, 시간 및 소스 물질의 투입 횟수와 같은 증착 조건에 따라 조절될 수 있다. 스터핑층(134a) 도 2의 실시예에서와 같이 결함 영역들 상에 우선적으로 형성될 수 있으나, 추가적으로 결정립(G)의 내부에서 결정립(G) 상에도 아일랜드 형태로 형성될 수 있다.The stuffing layer 134a of the present embodiment is not only formed on the defect regions such as the grain boundary GB of the graphene layer 132, but may also be formed on the grain G inside the grain G. The formation of the stuffing layer 134a may be controlled according to deposition conditions such as deposition temperature, time, and the number of times of input of the source material. The stuffing layer 134a may be preferentially formed on the defect regions as in the embodiment of FIG. 2, but may be additionally formed in the island shape on the grains G in the grains G.
도 4a의 평면도 및 도 4b의 단면도를 참조하면, 도 4b는 도 4a의 절단선 X-X'를 따라 절단한 단면을 도시한다. 확산 방지층(130b)은 그래핀층(132) 및 그래핀층(132) 상에 형성된 스터핑층(134b)을 포함할 수 있다.Referring to the plan view of FIG. 4A and the cross-sectional view of FIG. 4B, FIG. 4B shows a cross section taken along cut line X-X ′ of FIG. 4A. The diffusion barrier layer 130b may include a graphene layer 132 and a stuffing layer 134b formed on the graphene layer 132.
본 실시예의 스터핑층(134b)은 그래핀층(132)의 전체 영역 상에 형성될 수 있다. 스터핑층(134b)은 제1 및 제2 영역(R1, R2)을 포함할 수 있으며, 제1 영역(R1)은 결함 영역 상의 영역이고 제2 영역(R2)은 그래핀층(132)의 결정립(G) 상의 영역일 수 있다. 제2 영역(R2)을 이루는 스터핑층(134b)은 도시된 것과 같이 복수의 결정립들을 포함할 수 있으며, 그 크기는 도시된 것에 한정되지 않는다.The stuffing layer 134b of the present embodiment may be formed on the entire region of the graphene layer 132. The stuffing layer 134b may include first and second regions R1 and R2, where the first region R1 is a region on the defective region and the second region R2 is a crystal grain of the graphene layer 132 ( G) may be a region on. The stuffing layer 134b constituting the second region R2 may include a plurality of crystal grains as shown, and the size thereof is not limited thereto.
도 4a 내의 확대도는 각 영역들(R1, R2)에서의 결정 방향을 도시한다. 스터핑층(134b)은 제1 영역(R1)에서는 단결정 구조를 가지고, 제2 영역(R2)에서는 다결정 구조를 가질 수 있다. 제1 영역(R1)에서는 상대적으로 작은 크기의 결함 상에 스터핑층(134b)이 형성되므로 단결정의 아일랜드 형태로 성장할 수 있으며, 제2 영역(R2)에서는 상대적으로 넓은 결정립(G) 상에 성장하므로 복수의 결정립들을 갖는 다결정 구조로 성장할 수 있다. 넓은 의미에서는, 제1 영역(R1)을 이루는 복수의 아일랜드들 각각을 하나의 결정립으로 생각할 수도 있을 것이다. 이 경우, 스터핑층(134b)은 제1 영역(R1)에서의 결정립의 크기가 제2 영역(R2)에서의 결정립의 크기보다 작은 것으로 설명될 수 있다.The enlarged view in FIG. 4A shows the crystal direction in each of the regions R1 and R2. The stuffing layer 134b may have a single crystal structure in the first region R1 and a polycrystalline structure in the second region R2. In the first region R1, the stuffing layer 134b is formed on a relatively small size of the defect, so that the stuffing layer 134b may grow in the form of an island of a single crystal, and in the second region R2, it grows on a relatively large grain G. It can grow into a polycrystalline structure having a plurality of crystal grains. In a broad sense, each of the islands constituting the first region R1 may be regarded as one grain. In this case, the stuffing layer 134b may be described as having a smaller grain size in the first region R1 than a grain size in the second region R2.
도 5의 사시도를 참조하면, 확산 방지층(130c)은 그래핀층(132) 및 스터핑층(134) 외에 촉매 금속층(131)을 더 포함할 수 있다. Referring to the perspective view of FIG. 5, the diffusion barrier layer 130c may further include a catalyst metal layer 131 in addition to the graphene layer 132 and the stuffing layer 134.
촉매 금속층(131)은 그래핀층(132)의 하부에 배치되며, 그래핀층(132)을 증착하기 위한 그래파이트(graphite)화 촉매일 수 있다. 촉매 금속층(131)은 예를 들어, 구리(Cu), 니켈(Ni), 코발트(Co), 팔라듐(Pd), 철(Fe), 백금(Pt), 루테늄(Ru), 이리듐(Ir) 및 로듐(Rh) 중 적어도 하나를 포함할 수 있다.The catalytic metal layer 131 is disposed under the graphene layer 132, and may be a graphitization catalyst for depositing the graphene layer 132. The catalytic metal layer 131 may be formed of, for example, copper (Cu), nickel (Ni), cobalt (Co), palladium (Pd), iron (Fe), platinum (Pt), ruthenium (Ru), iridium (Ir), and the like. It may include at least one of rhodium (Rh).
본 실시예의 확산 방지층(130c)은 상대적으로 작은 두께의 그래핀층(132) 및 스터핑층(134)을 포함하므로, 촉매 금속층(131)을 더 포함하여도 상대적으로 작은 두께로 형성이 가능할 수 있다. 또한, 촉매 금속층(131)을 포함함으로써, 그래핀층(132)의 형성을 더욱 용이하게 할 수 있다.Since the diffusion barrier layer 130c includes the graphene layer 132 and the stuffing layer 134 having a relatively small thickness, the diffusion barrier layer 130c may be formed to have a relatively small thickness even if the catalyst metal layer 131 is further included. In addition, by including the catalyst metal layer 131, the graphene layer 132 may be more easily formed.
촉매 금속층(131) 상에서, 그래핀층(132)을 이루는 결정립들(G)의 커버리지(coverage)는 도면에 도시된 것에 한정되지 않는다. 도 5에서는 복수의 결정립들(G)이 촉매 금속층(131)을 완전히 덮는 것으로 도시되었으나, 이와 같은 커버리지는 다양하게 변경될 수 있다. 또한, 일 실시예에서, 그래핀층(132)은 적어도 일부가 단일층이 아닌 다중층으로 형성될 수도 있다.On the catalytic metal layer 131, the coverage of the grains G constituting the graphene layer 132 is not limited to that shown in the drawing. In FIG. 5, the plurality of crystal grains G is shown to completely cover the catalyst metal layer 131, but such coverage may be variously changed. In addition, in one embodiment, at least a portion of the graphene layer 132 may be formed of multiple layers instead of a single layer.
도 6 내지 도 8은 예시적인 실시예에 따른 반도체 소자의 제조 방법을 설명하기 위하여 공정 순서에 따라 도시한 개략도들이다.6 to 8 are schematic views according to a process sequence to explain a method of manufacturing a semiconductor device according to an exemplary embodiment.
도 6을 참조하면, 기판(100) 상에 제1 도전층(110) 및 절연층(120)이 형성될 수 있다. Referring to FIG. 6, the first conductive layer 110 and the insulating layer 120 may be formed on the substrate 100.
제1 도전층(110)은 하부 배선층 또는 하부의 도전 영역을 나타내는 것으로, 도전성 물질을 포함할 수 있다. 제1 도전층(110)은 전해 도금법(electroplating), PVD 또는 CVD 방식을 이용하여 증착할 수 있다.The first conductive layer 110 represents a lower wiring layer or a lower conductive region, and may include a conductive material. The first conductive layer 110 may be deposited using electroplating, PVD, or CVD.
제1 도전층(110) 상에 절연층(120)을 형성한 후, 제1 도전층(110)의 일부가 노출되도록 절연층(120)에 개구부(OP)를 형성할 수 있다. 개구부(OP)는 식각 공정에 의해 형성될 수 있으며, 별도의 식각 정지층을 이용할 수도 있다. 개구부(OP)에서 하부의 폭이 좁은 영역에는 비아(via)가 형성되고, 상부의 폭이 넓은 영역에는 배선 라인이 형성될 수 있으나, 이에 한정되지는 않는다.After the insulating layer 120 is formed on the first conductive layer 110, an opening OP may be formed in the insulating layer 120 to expose a portion of the first conductive layer 110. The opening OP may be formed by an etching process, and a separate etching stop layer may be used. Vias may be formed in the narrow area of the lower portion of the opening OP, and wiring lines may be formed in the wide area of the upper portion of the opening OP, but are not limited thereto.
도 7을 참조하면, 절연층(120)의 개구부(OP) 내에 확산 방지층(130)을 이루는 그래핀층(132)을 형성할 수 있다.Referring to FIG. 7, the graphene layer 132 forming the diffusion barrier layer 130 may be formed in the opening OP of the insulating layer 120.
그래핀층(132)은 다양한 방법을 이용하여 형성할 수 있다. 그래핀층(132)은 예를 들어, CVD, 분자 빔 에피텍시(molecular beam epitaxy, MBE) 등을 이용하여 직접 개구부(OP) 내에 증착하여 형성하거나, 그래핀 플레이크(flake)를 도포하는 방식으로 형성될 수 있다. 또는, 제조된 그래핀 시트를 전사하는 방법으로 형성할 수도 있다.The graphene layer 132 may be formed using various methods. The graphene layer 132 is formed by depositing directly in the opening OP using, for example, CVD, molecular beam epitaxy, or by applying graphene flakes. Can be formed. Alternatively, the prepared graphene sheet may be formed by a method of transferring.
실시예에 따라, 도 5를 참조하여 상술한 실시예에서와 같이, 그래핀층(132)의 하부에 촉매 금속층(131)(도 5 참조)이 더 배치될 수도 있으며, 이를 이용하여 그래핀층(132)을 형성할 수 있다. 이 경우, 촉매 금속층(131) 상에 가스 상태의 탄소 공급원 공급하고, 상기 탄소 공급원을 분해시켜 그래핀층(132)을 형성할 수 있다. 상기 탄소 공급원은 일산화탄소, 메탄, 에탄, 에틸렌, 에탄올, 아세틸렌, 프로판, 프로필렌, 부탄, 부타디엔, 펜탄, 펜텐, 사이클로펜타디엔, 헥산, 사이클로헥산, 벤젠 및 톨루엔 중 어느 하나일 수 있다.According to an embodiment, as in the above-described embodiment with reference to FIG. 5, the catalytic metal layer 131 (see FIG. 5) may be further disposed below the graphene layer 132, and the graphene layer 132 may be formed using the same. ) Can be formed. In this case, the carbon source in a gaseous state may be supplied onto the catalyst metal layer 131, and the graphene layer 132 may be formed by decomposing the carbon source. The carbon source may be any one of carbon monoxide, methane, ethane, ethylene, ethanol, acetylene, propane, propylene, butane, butadiene, pentane, pentene, cyclopentadiene, hexane, cyclohexane, benzene and toluene.
도 8을 참조하면, 그래핀층(132) 상에 스터핑층(134)을 형성할 수 있다.Referring to FIG. 8, a stuffing layer 134 may be formed on the graphene layer 132.
스터핑층(134)은 원자층 증착법(Atomic Layer Deposition, ALD)을 이용하여 형성할 수 있다. 다만, 스터핑층(134)의 형성 방법은 이에 한정되지 않으며, CVD, PVD 등을 이용할 수도 있다. ALD를 이용하는 경우, 높은 종횡비의 패턴에도 균일성 있는 막의 증착이 가능하다. 또한, ALD를 이용하는 경우, 전구체, 퍼지 가스, 반응 가스 및 퍼지 가스가 순차적으로 주입되는 하나의 사이클이 복수 회 반복되어 원하는 두께 및 커버리지(coverage)의 스터핑층(134)을 형성할 수 있다.The stuffing layer 134 may be formed using atomic layer deposition (ALD). However, the method of forming the stuffing layer 134 is not limited thereto, and CVD, PVD, or the like may be used. In the case of using ALD, deposition of a film uniform in high aspect ratio patterns is possible. In addition, when ALD is used, one cycle in which the precursor, the purge gas, the reactant gas, and the purge gas are sequentially injected may be repeated a plurality of times to form the stuffing layer 134 having a desired thickness and coverage.
스터핑층(134)의 형성 시, 도 2 내지 도 5를 참조하여 상술한 것과 같이, 그래핀층(132)의 결함 영역은 열역학적으로 불안정하여 결함 영역 상에 소스 물질이 우선적으로 흡착되어 스터핑층(134)의 핵생성(nucleation)이 이루어질 수 있다. 이 경우, 핵으로부터 성장된 아일랜드 형태의 스터핑층(134)이 결함 영역을 따라 성장될 수 있다. 결함 영역의 크기가 상대적으로 작으므로, 그 상부에 형성되는 스터핑층(134)은 단결정 구조를 가질 수 있다.In the formation of the stuffing layer 134, as described above with reference to FIGS. 2 to 5, the defect region of the graphene layer 132 is thermodynamically unstable so that the source material is preferentially adsorbed on the defect region and thus the stuffing layer 134 is formed. Nucleation may occur. In this case, the island-shaped stuffing layer 134 grown from the nucleus may be grown along the defect area. Since the size of the defect region is relatively small, the stuffing layer 134 formed thereon may have a single crystal structure.
본 단계에 의해, 그래핀층(132) 및 스터핑층(134)을 포함하는 확산 방지층(130)이 형성될 수 있다. 도 8에서, 확산 방지층(130)은 그래핀층(132) 및 스터핑층(134)으로 나누어 구체적으로 도시되었다. 본 실시예의 확산 방지층(130)은 그래핀층(132)을 이용함으로써 상대적으로 얇은 두께로 형성되면서도 전기적 특성을 확보할 수 있다. 또한, 그래핀층(132) 상에 스터핑층(134)을 형성함으로써 확산 방지 기능을 향상시키고 접촉 저항을 감소시킬 수 있다.In this step, the diffusion barrier layer 130 including the graphene layer 132 and the stuffing layer 134 may be formed. In FIG. 8, the diffusion barrier layer 130 is illustrated in detail by dividing the graphene layer 132 and the stuffing layer 134. By using the graphene layer 132, the diffusion barrier layer 130 of the present embodiment may secure electrical characteristics while being formed in a relatively thin thickness. In addition, by forming the stuffing layer 134 on the graphene layer 132, it is possible to improve the diffusion prevention function and reduce the contact resistance.
다음으로, 도 1을 함께 참조하면, 확산 방지층(130) 상에 제2 도전층(140)을 형성할 수 있다.Next, referring to FIG. 1, a second conductive layer 140 may be formed on the diffusion barrier layer 130.
제2 도전층(140)은 도전성 물질을 포함할 수 있으며, 예를 들어, 구리(Cu)를 포함할 수 있다. 제2 도전층(140)은 예를 들어, CVD, ALD 또는 전해 도금법을 이용하여 증착할 수 있다. The second conductive layer 140 may include a conductive material, and for example, may include copper (Cu). The second conductive layer 140 may be deposited using, for example, CVD, ALD, or electrolytic plating.
절연층(120)의 상부에 증착된 확산 방지층(130) 및 제2 도전층(140)은 평탄화 공정을 이용하여 제거될 수 있다. 이에 의해 최종적으로, 본 발명의 일 실시예에 따른 배선 구조를 포함하는 반도체 소자(10)가 형성된다.The diffusion barrier layer 130 and the second conductive layer 140 deposited on the insulating layer 120 may be removed using a planarization process. As a result, the semiconductor device 10 including the wiring structure according to the exemplary embodiment of the present invention is finally formed.
본 실시예에서, 확산 방지층(130)은 반도체 소자의 배선 구조에서 사용하는 경우를 나타내었으나, 본 발명에 따른 그래핀층(132) 및 스터핑층(134)의 적층 구조의 용도는 이에 한정되지 않으며, 다양한 용도로 반도체 소자에 적용될 수 있을 것이다.In the present embodiment, the diffusion barrier layer 130 is used in the wiring structure of the semiconductor device, but the use of the stacked structure of the graphene layer 132 and the stuffing layer 134 according to the present invention is not limited thereto. It may be applied to semiconductor devices for various purposes.
도 9a 내지 도 9e는 예시적인 실시예에 따른 확산 방지층의 특징을 설명하기 위한 전자현미경 사진들이다.9A to 9E are electron micrographs for explaining characteristics of the diffusion barrier layer according to an exemplary embodiment.
도 9a 내지 도 9e를 참조하면, ALD에 의해 그래핀층 상에 루테늄(Ru)의 스터핑층을 형성하면서, 증착 사이클에 따른 변화를 주사 전자현미경(Scanning Electron Microscopy, SEM)에 의해 분석하였다. 9A to 9E, while forming a stuffing layer of ruthenium (Ru) on the graphene layer by ALD, the change according to the deposition cycle was analyzed by Scanning Electron Microscopy (SEM).
증착 사이클이 20, 50, 100, 200, 400으로 변화함에 따라, 밝은 색으로 나타나는 스터핑층의 커버리지가 증가함을 알 수 있다. 초기에는 스터핑층이 그래핀층의 링클(wrinkle)과 같은 결함 영역에 우선적으로 증착되지만, 사이클이 증가함에 따라 다른 영역에도 증착되었다. 따라서, 증착 사이클을 조절함으로써, 결함 영역 상에 주로 스터핑층이 형성되게 할 수 있어, 결함으로 인한 전기적 특성의 저하를 최소화할 수 있다. 또한, 상대적으로 증착 사이클을 증가시키는 경우, 결함 영역 이외의 영역에도 스터핑층이 형성되어 면저항과 같은 다른 전기적 특성을 향상시킬 수 있다.It can be seen that as the deposition cycle changes to 20, 50, 100, 200, 400, the coverage of the stuffing layer appearing in bright colors increases. Initially, the stuffing layer was preferentially deposited in defect areas such as the wrinkle of the graphene layer, but also in other areas as the cycle increased. Therefore, by adjusting the deposition cycle, it is possible to make the stuffing layer mainly formed on the defect area, thereby minimizing the deterioration of the electrical characteristics due to the defect. In addition, when the deposition cycle is relatively increased, a stuffing layer may be formed in a region other than the defect region to improve other electrical characteristics such as sheet resistance.
도 10 내지 도 12는 예시적인 실시예에 따른 확산 방지층의 전기적 특성을 설명하기 위한 그래프들이다.10 to 12 are graphs for describing the electrical characteristics of the diffusion barrier layer according to an exemplary embodiment.
도 10 내지 도 12를 참조하면, 그래핀층 상에 스터핑층을 형성하기 전의 비교예들과 각 비교예들의 그래핀층에 ALD에 의해 루테늄(Ru)의 스터핑층을 형성한 실시예들에 대하여, ALD의 증착 사이클에 따라 각각 면저항(sheet resistance)(Rs), 캐리어 농도 및 전자 이동도의 변화를 측정하였다.10 to 12, for the comparative examples before forming the stuffing layer on the graphene layer and the embodiments in which the stuffing layer of ruthenium (Ru) was formed by ALD on the graphene layer of each comparative example, ALD The sheet resistance (Rs), the carrier concentration and the electron mobility were measured according to the deposition cycle of.
증착 사이클이 증가함에 따라, 면저항이 감소하고 캐리어 농도가 증가되는 경향을 나타내었다. 구체적으로, 도 10과 같이, 면저항은 스터핑층의 증착 전에는 평균적으로 약 550 Ω/□의 값을 가졌으나, 스터핑층을 형성함에 따라 20 사이클에서 약 180 Ω/□, 50 사이클에서 약 120 Ω/□로 점차 감소하였다. 이러한 면저항의 감소는 캐리어 농도의 증가에 기인하는 것일 수 있다. As the deposition cycles increased, the sheet resistance decreased and the carrier concentration tended to increase. Specifically, as shown in FIG. 10, the sheet resistance had a value of about 550 mA / □ on average before the deposition of the stuffing layer, but as the stuffing layer was formed, about 180 mA / □ at 20 cycles and about 120 mA / 50 at 50 cycles. Gradually decreased to □. This decrease in sheet resistance may be due to an increase in carrier concentration.
캐리어 농도는, 도 11과 같이 증착 사이클에 비례하여 증가하였다. 캐리어 농도는 스터핑층의 증착 전에는 평균적으로 약 2×1013/cm2 정도이었으나, 스터핑층을 형성함에 따라 20 사이클에서 약 6×1013/cm2, 50 사이클에서 약 8×1013/cm2으로 증가하였다. 이러한 캐리어 농도의 증가는, 스터핑층으로 사용한 루테늄(Ru)의 일함수(work function)가 그래핀층의 일함수보다 커서 그래핀층이 p-type으로 도핑되기 때문인 것으로 생각할 수 있다.Carrier concentration increased in proportion to the deposition cycle as shown in FIG. The carrier concentration is before deposition of the stuffing layer on average about 2 × 10 13 / cm 2 degree yieoteuna, from about 6 × 10 13 / cm 2, 50 cycles at 20 cycles as to form a stuffing layer of about 8 × 10 13 / cm 2 Increased. This increase in carrier concentration may be considered to be because the work function of ruthenium (Ru) used as the stuffing layer is larger than the work function of the graphene layer so that the graphene layer is doped with p-type.
도 12와 같이, 전자 이동도는 50 사이클까지 크게 변화하지 않다가 그 이후에 감소하였다. 따라서, 증착 사이클이 100 이하인 경우, 상대적으로 전자 이동도는 적게 감소하는 반면, 캐리어 농도가 큰 폭으로 증가하여 전기적 특성이 향상되는 것으로 해석할 수 있다.As shown in FIG. 12, the electron mobility did not change significantly until 50 cycles and then decreased. Therefore, when the deposition cycle is 100 or less, it can be interpreted that the electron mobility decreases relatively, while the carrier concentration greatly increases, thereby improving the electrical characteristics.
따라서, 본 실시예의 확산 방지층은 그래핀층 및 스터핑층을 포함함으로써, 캐리어 농도가 상대적으로 크게 증가하고 전자 이동도가 상대적으로 적게 감소하여, 면저항이 감소될 수 있다. 이에 따라, 본 실시예의 확산 방지층을 반도체 소자에 이용하는 경우, 그래핀층만을 확산 방지층으로 이용하는 경우에 비하여 접촉 저항이 감소될 수 있다.Therefore, the diffusion barrier layer of the present embodiment includes a graphene layer and a stuffing layer, whereby the carrier concentration is relatively increased and the electron mobility is relatively reduced, so that the sheet resistance can be reduced. Accordingly, when the diffusion barrier layer of the present embodiment is used in the semiconductor device, the contact resistance can be reduced as compared with the case where only the graphene layer is used as the diffusion barrier layer.
본 발명은 상술한 실시형태 및 첨부된 도면에 의해 한정되는 것이 아니며 첨부된 청구범위에 의해 한정하고자 한다. 따라서, 청구범위에 기재된 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 당 기술분야의 통상의 지식을 가진 자에 의해 다양한 형태의 치환, 변형 및 변경이 가능할 것이며, 이 또한 본 발명의 범위에 속한다고 할 것이다.It is intended that the invention not be limited by the foregoing embodiments and the accompanying drawings, but rather by the claims appended hereto. Accordingly, various forms of substitution, modification, and alteration may be made by those skilled in the art without departing from the technical spirit of the present invention described in the claims, which are also within the scope of the present invention. something to do.

Claims (15)

  1. 그래핀층 및 상기 그래핀층의 적어도 일부 영역 상에 위치하는 스터핑(stuffing)층을 포함하는 확산 방지층; 및A diffusion barrier layer including a graphene layer and a stuffing layer positioned on at least a portion of the graphene layer; And
    상기 확산 방지층 상의 도전층을 포함하는 반도체 소자.A semiconductor device comprising a conductive layer on the diffusion barrier layer.
  2. 제1 항에 있어서,According to claim 1,
    상기 스터핑층은 상기 그래핀층 상에 아일랜드 형태로 증착되어 배치되는 반도체 소자.The stuffing layer is a semiconductor device is disposed on the graphene layer deposited in an island form.
  3. 제2 항에 있어서,The method of claim 2,
    상기 스터핑층을 이루는 아일랜드들은 단결정 구조를 가지는 반도체 소자.The islands forming the stuffing layer have a single crystal structure.
  4. 제1 항에 있어서,According to claim 1,
    상기 그래핀층은 복수의 결함 영역들을 포함하고,The graphene layer includes a plurality of defect regions,
    상기 스터핑층은 상기 결함 영역들 상에 위치하는 반도체 소자.The stuffing layer is disposed on the defect regions.
  5. 제1 항에 있어서,According to claim 1,
    상기 그래핀층은 복수의 결함 영역들을 포함하고,The graphene layer includes a plurality of defect regions,
    상기 스터핑층은 상기 결함 영역들 상에서 단결정 구조를 가지고, 그 외의 영역 상에서 다결정 구조를 가지는 반도체 소자.The stuffing layer has a single crystal structure on the defect regions and a polycrystal structure on the other regions.
  6. 제1 항에 있어서,According to claim 1,
    상기 확산 방지층은, 상기 그래핀층 하부에 배치되는 촉매 금속층을 더 포함하는 반도체 소자.The diffusion barrier layer further comprises a catalyst metal layer disposed below the graphene layer.
  7. 제1 항에 있어서,According to claim 1,
    상기 스터핑층은 상기 확산 방지층이 상기 도전층과 마주하는 면에 위치하는 반도체 소자.The stuffing layer is a semiconductor device located on the surface of the diffusion barrier layer facing the conductive layer.
  8. 제1 항에 있어서,According to claim 1,
    상기 스터핑층은 탄탈륨(Ta), 탄탈륨 질화물(TaN), 티타늄(Ti), 티타늄 질화물(TiN), 몰리브덴 질화물(MoN), 텅스텐(W), 텅스텐 질화물(WN), 루테늄(Ru), 코발트(Co) 중 적어도 하나를 포함하는 반도체 소자.The stuffing layer is tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), molybdenum nitride (MoN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), cobalt ( Co) at least one of the semiconductor device.
  9. 제1 항에 있어서,According to claim 1,
    상기 확산 방지층은 5×1013/cm2 내지 9×1016/cm2 범위의 캐리어 농도를 가지는 반도체 소자.The diffusion barrier layer has a carrier concentration in the range of 5 × 10 13 / cm 2 to 9 × 10 16 / cm 2 .
  10. 제1 항에 있어서,According to claim 1,
    상기 확산 방지층의 두께는 5 nm보다 작은 반도체 소자.And the thickness of the diffusion barrier layer is less than 5 nm.
  11. 그래핀층 및 상기 그래핀층의 적어도 일부를 덮는 스터핑(stuffing)층을 포함하는 확산 방지층을 형성하는 단계; 및Forming a diffusion barrier layer comprising a graphene layer and a stuffing layer covering at least a portion of the graphene layer; And
    상기 스터핑층 상에 도전층을 형성하는 단계를 포함하는 반도체 소자의 제조 방법.Forming a conductive layer on the stuffing layer.
  12. 제11 항에 있어서,The method of claim 11, wherein
    상기 스터핑층은 상기 그래핀층 상에 아일랜드 형태로 증착되는 반도체 소자의 제조 방법.The stuffing layer is a semiconductor device manufacturing method is deposited on the graphene layer in the form of an island.
  13. 제11 항에 있어서,The method of claim 11, wherein
    상기 그래핀층은 복수의 결함 영역들을 포함하고,The graphene layer includes a plurality of defect regions,
    상기 스터핑층은 상기 결함 영역들 상에 형성되는 반도체 소자의 제조 방법.The stuffing layer is formed on the defect regions.
  14. 제11 항에 있어서,The method of claim 11, wherein
    상기 스터핑층은 원자층 증착법(ALD)에 의해 형성하는 반도체 소자의 제조 방법.And the stuffing layer is formed by atomic layer deposition (ALD).
  15. 제11 항에 있어서,The method of claim 11, wherein
    상기 스터핑층을 형성함으로써, 상기 확산 방지층의 캐리어 농도가 증가하는 반도체 소자의 제조 방법.The method for manufacturing a semiconductor device in which the carrier concentration of the diffusion barrier layer is increased by forming the stuffing layer.
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