WO2016167021A1

WO2016167021A1 - Solid-state imaging element, electronic apparatus, and method for controlling solid-state imaging element

Info

Publication number: WO2016167021A1
Application number: PCT/JP2016/054987
Authority: WO
Inventors: 洋子寺戸
Original assignee: ソニー株式会社
Priority date: 2015-04-13
Filing date: 2016-02-22
Publication date: 2016-10-20

Abstract

The present invention improves the picture quality of image data in a solid-state imaging element provided with transistors in which a thinned reading is performed by controlling the transistors. A selection unit selects, from all lines comprising pixels arranged along prescribed directions in a pixel array unit, some lines as thinned lines and the remaining lines after thinning as read lines. A read line transfer signal supply unit supplies a transfer signal to the read lines and thereby controls the transfer transistors of the read lines so that these transistors are placed in a conduction state over a fixed period after a prescribed time. A read unit reads out pixel signals that correspond to the amount of charges from the read lines. A thinned line transfer signal supply unit controls the cumulative time of the conduction state and/or the number of times of transition to the conduction state in the transfer transistors of the thinned lines the same way as for the read lines by supplying a transfer signal to the thinned lines.

Description

Solid-state image sensor, electronic device, and control method for solid-state image sensor

The present technology relates to a solid-state imaging device, an electronic device, and a control method for the solid-state imaging device. Specifically, the present invention relates to a solid-state imaging device provided with a transistor, an electronic device, and a method for controlling the solid-state imaging device.

Conventionally, in an electronic device having an imaging function, a solid-state imaging device is used to capture image data. The method for exposing the solid-state imaging device is classified into a global shutter method in which all of a plurality of lines are exposed simultaneously and a rolling shutter method in which those lines are exposed in order. In particular, a rolling shutter system is often used in a solid-state image pickup device of CMOS (Complementary Metal Oxide） Semiconductor). When this rolling shutter system is used, thinning readout may be performed in which some lines are thinned out in order to shorten the readout period. For example, thinning-out reading is performed when capturing a moving image or displaying an image on a monitor in real time.

When performing thinning readout, the scanning circuit in the solid-state imaging device supplies a transfer signal to the readout line to be read at the start of exposure and at the end of exposure. As a result, the transfer transistor in the readout line to which the transfer signal is supplied transitions to a conductive state and transfers charges from the photodiode to the floating diffusion layer. Here, although it is not necessary to supply a transfer signal to the thinning line to be thinned out, if the transfer signal is not supplied to the thinning line, the charge of the photodiode on the thinning line overflows from the pixel and the image data is white. May occur. This phenomenon is called blooming. In order to prevent this blooming, a solid-state imaging device has been proposed in which the potential of the transfer signal is fixed at a high level and the transfer transistor in the thinning line is kept in a conductive state (see, for example, Patent Document 1). .

JP 2008-172607 A

In the above-described solid-state imaging device, since the driving conditions of the transfer transistor in the thinning line are different from those in the readout line, the transfer transistor may be deteriorated at different speeds in these lines. Due to this difference in the deterioration speed, when the deterioration level of each transfer transistor in the readout line and the thinning line becomes different, streak noise appears along the line in the image data when all lines are read out, and the image quality There is a problem that the remarkably decreases.

The present technology has been developed in view of such a situation, and an object thereof is to improve the image quality of image data in a solid-state imaging device in which thinning-out reading is performed by transistor control.

The present technology has been made to solve the above-described problems. The first aspect of the present technology is the transition to a conductive state by a transfer signal instructing transfer of charges from a photodiode to a charge storage unit. A plurality of pixels each provided with a transfer transistor for transferring charges are arranged in a two-dimensional lattice, and all lines including the pixels arranged along a predetermined direction in the pixel array unit. A selection unit that selects a remaining line obtained by thinning a part of the lines as a thinning line, and the transfer of the read line over a predetermined period from a predetermined timing by supplying the transfer signal to the read line. Read line transfer signal supply unit for controlling the transistor to the conductive state, and a pixel signal corresponding to the amount of charge from the read line At least one of the reading unit for reading and the accumulated time of the conduction state in the transfer transistor of the thinning line and the number of transitions to the conduction state is substantially the same as the reading line by supplying the transfer signal to the thinning line. A solid-state imaging device including a thinning line transfer signal supply unit to be controlled, and a control method thereof. This brings about the effect that at least one of the accumulation time of the conduction state and the number of transition times to the conduction state in the transfer transistor of the thinning line is controlled substantially the same as that of the readout line.

In this first aspect, the thinning line transfer signal supply unit may supply the same number of transfer signals as the number transferred by the read line transfer signal supply unit to the thinning line. As a result, the same number of transfer signals as those transferred by the read line transfer signal supply unit are supplied to the thinning line.

Further, in this first aspect, the thinning line transfer signal supply unit substantially reduces the accumulated time of the conduction state by the predetermined number of transfer signals each time the predetermined number of transfer signals are transferred to the read line. The transfer signal may be supplied to the thinning line over a matching period. As a result, every time a predetermined number of transfer signals are transferred to the read line, the transfer signal is supplied to the thinning line over a period of time approximately equal to the accumulation time of the conduction state by the predetermined number of transfer signals. Bring.

In the first aspect, when a set signal is input, an output signal having a specific value is output. When a reset signal is input, an output signal having a value different from the specific value is output. Each of the lines further includes a latch circuit and an OR gate that outputs one of the two input signals to the transfer transistor, and the read line transfer signal supply unit includes the logic corresponding to the read line. The transfer signal to the read line is input to the sum gate and the transfer signal is input to the latch circuit as the reset signal corresponding to the read line, and the thinned line transfer signal supply unit corresponds to the thinned line A signal of the logical product of the output signal of the latch circuit and a predetermined additional shutter signal is used as the transfer signal to the thinning line. Form and input to the OR gate corresponding to the thinned line. As a result, the logical product of the output signal of the latch circuit corresponding to the thinning line and the predetermined additional shutter signal is generated as the transfer signal to the thinning line.

In the first aspect, the selection unit switches a position and the number of lines to be selected as the read line among the plurality of lines according to a predetermined mode signal, and the latch circuit receives the mode signal based on the mode signal. The set signal may be input every time the position and number of read lines are switched. As a result, the set signal is input to the latch circuit every time the position and number of read lines are switched by the mode signal.

In the first aspect, the selection unit may select each of the plurality of lines arranged at regular intervals in a direction perpendicular to the predetermined direction as the read line. This brings about the effect that each of the lines arranged at regular intervals in the direction perpendicular to the predetermined direction is selected as a read line.

In the first aspect, the selection unit may select lines adjacent to each other in the direction perpendicular to the predetermined direction as the readout line among the plurality of lines. Thereby, there is an effect that lines adjacent to each other in a direction perpendicular to the predetermined direction are selected as read lines.

In the first aspect, the read line transfer signal supply unit supplies the transfer signal to each of some of the pixels of the read line and the remaining pixels at different timings, and The thinning line transfer signal supply unit may supply the transfer signal to a part of the pixels of the thinning line and a remaining pixel at different timings. As a result, a transfer signal is supplied to some of the pixels and the remaining pixels at different timings.

In the first aspect, a pair of pixels adjacent to each other in a direction perpendicular to the predetermined direction among the plurality of pixels share the charge accumulation unit, and the thinning line transfer signal supply unit The transfer signal may be supplied to the thinning line during a period in which the transfer signal is not supplied to any of the lines. As a result, the transfer signal is supplied to the thinning-out line during a period in which no transfer signal is supplied to any of the read lines.

A second aspect of the present technology provides a plurality of pixels each provided with a transfer transistor that is transferred to a conductive state by a transfer signal instructing transfer of charge from the photodiode to the charge storage unit and transfers the charge. Is a pixel array unit arranged in a two-dimensional lattice, and the remaining lines obtained by thinning out some lines from all the lines composed of the pixels arranged in a predetermined direction in the pixel array unit as thinning lines. A selection unit that selects as a read line, and a read line transfer signal supply unit that controls the transfer transistor of the read line to the conductive state over a certain period from a predetermined timing by supplying the transfer signal to the read line; A readout unit that reads out a pixel signal corresponding to the amount of charge from the readout line, and the transfer of the thinning line A thinning line transfer signal supply unit for controlling at least one of the accumulated time of the conductive state in the transistor and the number of transitions to the conductive state to be substantially the same as the readout line by supplying the transfer signal to the thinning line; And an electronic device including a processing unit that processes the read pixel signal. This brings about the effect that at least one of the accumulation time of the conduction state and the number of transition times to the conduction state in the transfer transistor of the thinning line is controlled substantially the same as that of the readout line.

According to the present technology, it is possible to achieve an excellent effect that the image quality of the image data can be improved in the solid-state imaging device in which thinning-out reading is performed by controlling the transistors. Note that the effects described here are not necessarily limited, and may be any of the effects described in the present disclosure.

1 is a block diagram illustrating a configuration example of an imaging apparatus according to a first embodiment. It is a block diagram which shows one structural example of the solid-state image sensor in 1st Embodiment. FIG. 3 is a circuit diagram illustrating a configuration example of a pixel according to the first embodiment. 1 is a block diagram illustrating a configuration example of a vertical scanning circuit according to a first embodiment. FIG. It is a figure which shows an example of the decoding signal in 1st Embodiment. It is a block diagram which shows one structural example of the timing generation part in 1st Embodiment. 6 is a table showing an example of the operation of the read transfer signal generation circuit in the first embodiment. 6 is a table illustrating an example of an operation of the shutter transfer signal generation circuit according to the first embodiment. 6 is a table illustrating an example of an operation of the reset signal generation circuit according to the first embodiment. 6 is a table showing an example of the operation of the selection signal generation circuit in the first embodiment. FIG. 3 is a circuit diagram illustrating a configuration example of a transfer signal generation circuit according to the first embodiment. 3 is a table showing an example of the operation of the latch circuit in the first embodiment. 3 is a table illustrating an example of an operation of a transfer signal generation circuit according to the first embodiment. 6 is a timing chart illustrating an example of an operation in a normal reading mode of the vertical scanning circuit according to the first embodiment. 6 is a timing chart illustrating an example of an operation in a normal reading mode of the solid-state imaging device according to the first embodiment. 5 is a timing chart illustrating an example of an operation in a 1/3 decimation readout mode of the vertical scanning circuit according to the first embodiment. 3 is a timing chart illustrating an example of an operation in a 1/3 decimation readout mode of the solid-state imaging device according to the first embodiment. It is a timing chart which shows an example of operation | movement of 1/3 thinning-out reading mode of the solid-state image sensor in a comparative example. It is a flowchart which shows an example of operation | movement of the solid-state image sensor in 1st Embodiment. 6 is a flowchart illustrating an example of a normal read process in the first embodiment. It is a flowchart which shows an example of the 1/3 thinning-out reading process in 1st Embodiment. 6 is a timing chart illustrating an example of an operation in a 1/3 decimation readout mode of the solid-state imaging device according to the first modification of the first embodiment. It is a timing chart which shows an example of operation | movement of 1/3 thinning-out reading mode of the solid-state image sensor in the 2nd modification of 1st Embodiment. It is a circuit diagram which shows one structural example of the pixel array part in the 3rd modification of 1st Embodiment. It is a figure which shows an example of the decoding signal in 2nd Embodiment. 12 is a timing chart illustrating an example of an operation in a 1/5 decimation readout mode of the vertical scanning circuit according to the second embodiment. It is a figure which shows an example of the decoding signal in 3rd Embodiment. 12 is a timing chart illustrating an example of operation in a thinning readout mode of a vertical scanning circuit in a third embodiment. It is a figure which shows an example of the decoding signal in 4th Embodiment. 16 is a timing chart illustrating an example of an operation in a window reading mode of the vertical scanning circuit in the fourth embodiment.

Hereinafter, modes for carrying out the present technology (hereinafter referred to as embodiments) will be described. The description will be made in the following order.
1. 1st Embodiment (example which controls the accumulation time of the conduction | electrical_connection state of each line equally)
2. Second embodiment (an example in which the accumulated time of the conduction state of each line is controlled to be the same in the 1/5 thinning readout mode)
3. Third Embodiment (Example of switching the thinning readout mode and controlling the accumulated time of the conduction state of each line to be the same)
4). Fourth Embodiment (Example in which the accumulated time of the conduction state of each line is controlled to be the same in the window readout mode)

<1. First Embodiment>
[Configuration example of imaging device]
FIG. 1 is a block diagram illustrating a configuration example of the imaging apparatus 100 according to the first embodiment. The imaging device 100 captures image data, and includes an imaging lens 110, a solid-state imaging device 200, an image processing unit 120, a recording unit 130, a control unit 140, and a display unit 150.

The imaging lens 110 collects light and guides it to the solid-state imaging device 200. The solid-state imaging device 200 generates image data by converting light from the imaging lens 110 into an electrical signal under the control of the control unit 140. For example, a CMOS sensor is used as the solid-state image sensor 200. The solid-state imaging device 200 supplies image data to the image processing unit 120 via the signal line 209.

Here, it is assumed that the solid-state imaging device 200 has a plurality of pixels arranged in a two-dimensional grid. Hereinafter, in the solid-state imaging device 200, a plurality of pixels arranged in a predetermined direction is referred to as “row” or “line”, and a plurality of pixels arranged in a direction perpendicular to the row (line) is referred to as “column”. The solid-state imaging device 200 is controlled by the control unit 140 in either a normal reading mode in which pixel signals are read from all lines or a 1/3 decimation reading mode in which pixel signals are read from 1/3 of all lines. The 1/3 decimation readout mode is used, for example, when displaying image data on the display unit 150 in real time. On the other hand, the normal reading mode is used when, for example, a still image or a moving image is captured with a higher resolution than the 1/3 decimation reading mode.

The image processing unit 120 performs various types of image processing such as AD (Analog-to-Digital) conversion processing, noise removal processing, demosaic processing, and white balance processing on the image data under the control of the control unit 140. Further, for the image data generated in the 1/3 thinning readout mode, a process of thinning out 2/3 pixels in each line is further performed in order to make the aspect ratio the same as in the normal readout mode. The image processing unit 120 supplies the image data after the image processing generated in the normal reading mode to the recording unit 130 via the signal line 128. Further, the image processing unit 120 supplies the image data after the image processing generated in the 1/3 thinning-out reading mode to the display unit 150 via the signal line 129. The image processing unit 120 is an example of a processing unit described in the claims.

The recording unit 130 records image data. The display unit 150 displays image data. The control unit 140 controls the entire imaging apparatus 100. The control unit 140 generates various control signals according to user operations. For example, as a control signal, an imaging control signal for instructing the start or end of imaging and a mode signal for instructing a normal reading mode or a 1/3 decimation reading mode are generated. The control unit 140 supplies these control signals to the solid-state imaging device 200 via the signal line 149 to start or end imaging. The control unit 140 also supplies the control signal to the image processing unit 120 via the signal line 148 to perform image processing.

The control unit 140 controls to the 1/3 thinning readout mode when displaying the image data in real time, but is not limited to this configuration. For example, the control unit 140 may be configured to control the normal reading mode when capturing a still image and to control to the 1/3 decimation reading mode when capturing a moving image. Further, the solid-state imaging device 200 reads 1/3 of all lines at the time of thinning-out reading, but the reading ratio is not limited to 1/3, and 1/2 line or 1/5 line is read. Also good. The imaging apparatus 100 may further include an external interface and output image data to an external apparatus.

Further, although the imaging lens 110, the solid-state imaging device 200, the image processing unit 120, the recording unit 130, the control unit 140, and the display unit 150 are provided in the same device, they may be provided in different devices. For example, the imaging lens 110 and the solid-state imaging device 200 may be provided in the imaging device, and the image processing unit 120 and the like may be provided in the image processing device. Further, although the solid-state imaging device 200 is provided in the imaging device 100, it may be provided in an electronic device other than the imaging device such as a mobile phone or a tablet terminal. The imaging device 100 is an example of an electronic device in the claims.

[Configuration example of solid-state image sensor]
FIG. 2 is a block diagram illustrating a configuration example of the solid-state imaging device 200 according to the first embodiment. The solid-state imaging device 200 includes a pixel array unit 210, a column CDS unit 260, a timing signal generation circuit 270, an output circuit 280, a horizontal scanning circuit 290, and a vertical scanning circuit 300. In the pixel array unit 210, a plurality of lines are arranged, among which a plurality of pixels 220 are arranged on the 2m (m is an integer of 0 or more) line, and a plurality of pixels 230 are arranged on the 2m + 1th line. The The column CDS unit 260 is provided with a CDS circuit 261 for each column composed of pixels (220 or 230) arranged in a direction perpendicular to the line.

The timing signal generation circuit 270 generates timing signals such as a vertical synchronization signal and a horizontal synchronization signal. For example, when an imaging control signal instructing the start of imaging is supplied from the control unit 140, the timing signal generation circuit 270 generates a vertical synchronization signal, a clock signal, and a horizontal synchronization signal as timing signals. Here, the vertical synchronizing signal is a constant frequency synchronizing signal indicating the timing of reading out the pixel signal (in other words, scanning) in the direction perpendicular to the line, and the horizontal synchronizing signal is scanned in the direction horizontal to the line. It is a constant frequency synchronization signal indicating the timing to be performed. The frequency of the horizontal synchronizing signal is higher than that of the vertical synchronizing signal. The timing signal generation circuit 270 supplies a vertical synchronization signal to the vertical scanning circuit 300, supplies a clock signal to the column CDS unit 260, and supplies a horizontal synchronization signal to the horizontal scanning circuit 290. Further, for example, when an imaging control signal instructing to stop imaging is supplied, the timing signal generating circuit 270 stops generating the timing signal.

The

pixels

220 and 230 convert light into an electrical signal under the control of the vertical scanning circuit 300 and output it as a pixel signal.

The vertical scanning circuit 300 selects a line composed of the

pixels

220 or 230 in order, and outputs a pixel signal to the selected line. In the normal reading mode, the vertical scanning circuit 300 sequentially selects all lines in synchronization with the vertical synchronization signal from the timing signal generation circuit 270. On the other hand, in the 1/3 thinning readout mode, the vertical scanning circuit 300 sequentially selects 1/3 of all lines as readout lines in synchronization with the vertical synchronization signal.

The CDS circuit 261 reads out a pixel signal from a pixel via a vertical signal line 219, and performs correlated double sampling (CDS: Correlated Double Sampling) processing in synchronization with a clock signal. The CDS circuit 261 reads a pixel signal from the corresponding column and performs CDS processing on the pixel signal. Then, the CDS circuit 261 supplies the pixel signal after the CDS process to the output circuit 280 according to the control of the horizontal scanning circuit 290. The column CDS unit 260 is an example of a reading unit described in the claims.

The horizontal scanning circuit 290 causes the CDS circuit 261 to sequentially output pixel signals in synchronization with the horizontal synchronization signal. The output circuit 280 outputs a pixel signal to the recording unit 130 or the like.

The CDS circuit 261 performs only the CDS process, but may perform an AD conversion process in addition to the CDS process. In this case, the subsequent image processing unit 120 does not need to perform AD conversion processing, and performs image processing other than AD conversion processing.

[Pixel configuration example]
FIG. 3 is a circuit diagram illustrating a configuration example of the

pixels

220 and 230 according to the first embodiment. The pixel 220 includes a transfer transistor 221 and a photodiode 222. The pixel 230 includes a transfer transistor 231, a photodiode 232, a reset transistor 233, a floating diffusion layer 234, an amplification transistor 235, and a selection transistor 236. For example, N-type field effect transistors are used as the transfer transistor 221, the transfer transistor 231, the reset transistor 233, the amplification transistor 235, and the selection transistor 236. In addition, one horizontal signal line 229 is connected to the pixel 220 as a transfer signal line. A horizontal signal line 239 including a transfer signal line, a reset signal line, and a selection signal line is connected to the pixel 230. Here, the pixel 220 is arranged in the 0th row, and the pixel 230 is arranged in the 1st row.

The gate of the transfer transistor 221 is connected to the horizontal signal line 229 (transfer signal line), the source is connected to the photodiode 222, and the drain is connected to the floating diffusion layer 234. The transfer transistor 231 has a gate connected to the transfer signal line, a source connected to the photodiode 232, and a drain connected to the floating diffusion layer 234.

The gate of the reset transistor 233 is connected to the reset signal line, the source is connected to the floating diffusion layer 234, and the drain is connected to the power source. The gate of the amplification transistor 235 is connected to the floating diffusion layer 234, the source is connected to the selection transistor 236, and the drain is connected to the power source. The gate of the selection transistor 236 is connected to the selection signal line, the source is connected to the vertical signal line 219, and the drain is connected to the amplification transistor 235.

The

photodiodes

222 and 232 generate charges from light by photoelectric conversion. The transfer transistor 221 transfers charges from the photodiode 222 to the floating diffusion layer 234 in accordance with the transfer signal Tx0. The transfer transistor 231 transfers charges from the photodiode 232 to the floating diffusion layer 234 in accordance with the transfer signal Tx1.

The floating diffusion layer 234 accumulates the transferred charge and generates an electric signal having a voltage corresponding to the amount of the accumulated charge. The floating diffusion layer 234 is an example of a charge storage unit described in the claims.

When the reset signal RST0 is supplied, the reset transistor 233 discharges the floating diffusion layer 234 and resets the charge amount to an initial value. The amplification transistor 235 amplifies the electric signal generated in the floating diffusion layer 234. When the selection signal SEL0 is supplied, the selection transistor 236 supplies the amplified electrical signal as a pixel signal to the column CDS unit 260.

Note that a pair of

pixels

220 and 230 adjacent in the vertical direction share the reset transistor 233, the floating diffusion layer 234, the amplification transistor 235, and the selection transistor 236, but the configuration is not limited thereto. For example, four adjacent pixels may share the floating diffusion layer 234 and the like. In addition, the floating diffusion layer 234 and the like may be provided for each pixel without being shared.

[Configuration example of vertical scanning circuit]
FIG. 4 is a block diagram illustrating a configuration example of the vertical scanning circuit 300 according to the first embodiment. The vertical scanning circuit 300 includes a transfer signal generation unit 310, a level shifter 330, a timing generation unit 340, an address decoder 350, and a timing control unit 360.

The transfer signal generator 310 generates transfer signals for all lines. The transfer signal generation unit 310 includes a transfer signal generation circuit 320 for each line. The additional shutter signal SH_Add and the latch set signal LT_Set are commonly input to all the transfer signal generation circuits 320 by the level shifter 330. In addition, the read transfer signal RD_Rn and the shutter transfer signal SH_Rn are input to the transfer signal generation circuit 320 corresponding to the nth (n is an integer of 0 or more) line.

Here, the additional shutter signal SH_Add is a signal indicating a timing for generating a transfer signal to the thinning line to be thinned. The latch set signal LT_Set is a signal for causing the latch circuit in the transfer signal generation circuit 320 to hold a high level signal. The latch circuit will be described later. The read transfer signal RD_Rn is a signal indicating the timing at which the exposure of the nth line is finished and the pixel signal is read out. The shutter transfer signal SH_Rn is a signal indicating timing for starting exposure of the nth line.

The transfer signal generation circuit 320 generates a transfer signal to the corresponding line. The transfer signal generation circuit 320 generates a transfer signal Txn from the additional shutter signal SH_Add, the latch set signal LT_Set, the read transfer signal RD_Rn, and the shutter transfer signal SH_Rn, and supplies it to the corresponding line.

The timing control unit 360 controls the entire vertical scanning circuit 300. When the supply of the vertical synchronization signal is started, the timing control unit 360 generates a pulse signal obtained by multiplying the vertical synchronization signal and supplies the pulse signal to the timing generation unit 340. Further, the timing control unit 360 generates address data indicating the address of the read line from the mode signal. In the normal read mode, address data indicating all lines is generated, and in the 1/3 decimation read mode, address data indicating 1/3 of all lines is generated. The timing control unit 360 supplies the generated address data to the address decoder 350.

Also, the timing control unit 360 generates an additional shutter signal SH_Add in the 1/3 decimation readout mode and supplies the additional shutter signal SH_Add to the level shifter 330. In the 1/3 decimation readout mode, the timing control unit 360 generates an average of two additional shutter signals SH_Add per frame. Each additional shutter signal SH_Add is, for example, a signal that is at a high level over a certain pulse period W1.

Furthermore, the timing control unit 360 generates a latch set signal LAT_Set and supplies it to the level shifter 330 when the mode is switched or when imaging is started.

The address decoder 350 decodes address data. For each line, the address decoder 350 generates a decode signal DECn indicating whether or not the line is a read line from the address data and supplies it to the timing generator 340. The address decoder 350 is an example of a selection unit described in the claims.

The timing generation unit 340 generates a read transfer signal RD_Rn, a shutter transfer signal SH_Rn, a reset signal RSTm, and a selection signal SELm. Here, m is an integer greater than or equal to 0, and the reset signal RSTm is a signal indicating the timing at which the reset transistor 233 of the (2m + 1) th line is reset. The selection signal SELm is a signal indicating the timing at which the pixel signal is output to the selection transistor 236 on the 2m + 1st line.

The timing generation unit 340 generates a signal such as a read transfer signal RD_Rn from the pulse signal and the decode signal, and supplies the signal to the level shifter 330. Here, the read transfer signal RD_Rn and the shutter transfer signal SH_Rn are generated for each line. In addition, the reset signal RSTm and the selection signal SELm are generated for each of the 2m + 1th line among all the lines. For example, the read transfer signal RD_R0 and the shutter transfer signal SH_R0 are generated for the 0th line. For the first line, a read transfer signal RD_R1, a shutter transfer signal SH_R1, a reset signal RST0, and a selection signal SEL0 are generated.

The level shifter 330 boosts the voltage such as the latch set signal LAT_Set from the timing control unit 360 and the timing generation unit 340 to a voltage sufficient to drive the transfer signal generation unit 310 or the driver in the subsequent stage. A driver is arranged between the transfer signal generation unit 310 and the pixel array unit 210, but this driver is omitted in FIG.

FIG. 5 is a diagram illustrating an example of the decode signal in the first embodiment. It is assumed that data A is input as address data in the normal read mode, and data B is input in the 1/3 decimation read mode.

When the data A is input (normal read mode), the address decoder 350 sets “1” indicating the read line to the decode signal of all lines and outputs it. On the other hand, when data B is input (1/3 decimation read mode), the address decoder 350 sets “1” (read line) to 1/3 of the decode signals of all lines, and the remaining decimation lines. Is set to “0”. For example, “1” is set to the decode signal DEC0 of the 0th line, and “0” is set to the decode signals DEC1 and DEC2 of the first and second lines. Further, “1” is set to the third decode signal DEC3, and “0” is set to the fourth and fifth decode signals DEC4 and DEC5. Similarly thereafter, one of the three lines is set as a read line.

[Configuration example of timing generator]
FIG. 6 is a block diagram illustrating a configuration example of the timing generation unit 340 according to the first embodiment. The timing generation unit 340 includes a read transfer signal generation circuit 341 and a shutter transfer signal generation circuit 342 for each 2m-th line. Further, the timing generation unit 340 includes a read transfer signal generation circuit 343, a shutter transfer signal generation circuit 344, a reset signal generation circuit 345, and a selection signal generation circuit 346 for each of the 2m + 1th lines.

The read transfer signal generation circuit 341 generates a read transfer signal RD_Rn for the 2m (= n) th line and supplies it to the level shifter 330. The read transfer signal RD_Rn is, for example, a signal that is at a high level over a certain pulse period W1. If the decode signal DECn from the address decoder 350 is “1”, the read transfer signal generation circuit 341 uses the pulse signal from the timing control unit 360 to read the read transfer signal RD_Rn at a preset exposure end timing. Is generated. For example, the read transfer signal generation circuit 341 counts the number of pulses of the pulse signal, generates the read transfer signal RD_Rn at the timing when the count value reaches a predetermined value (that is, the exposure end timing), and calculates the count value. Repeat the initial value operation. The exposure end timing is set by an exposure control unit (not shown) that sets the exposure time according to the light metering amount, or by a user operation.

The shutter transfer signal generation circuit 342 generates a shutter transfer signal SH_Rn for the 2m (= n) th line and supplies it to the level shifter 330. The shutter transfer signal SH_Rn is, for example, a signal that is at a high level over a certain pulse period W1. If the decode signal DECn from the address decoder 350 is “1”, the shutter transfer signal generation circuit 342 uses the pulse signal from the timing control unit 360 to set the shutter transfer signal SH_Rn at a preset exposure end timing. Is generated. For example, the shutter transfer signal generation circuit 342 counts the number of pulses, generates the shutter transfer signal SH_Rn at the timing when the count value reaches a predetermined value (that is, the exposure start timing), and sets the count value to the initial value. Repeat the operation. The exposure start timing is set by an exposure control unit that sets an exposure time according to the light metering amount or by a user operation.

The configuration of the read transfer signal generation circuit 343 is the same as that of the read transfer signal generation circuit 341 except that the read transfer signal RD_Rn for the 2m + 1 (= n) th line is generated. The configuration of the shutter transfer signal generation circuit 344 is the same as that of the shutter transfer signal generation circuit 342 except that the read transfer signal SH_Rn to the 2m + 1 (= n) th line is generated.

The reset signal generation circuit 345 generates a reset signal RSTm for the reset transistor 233 shared by the 2mth and 2m + 1th lines and supplies the reset signal RSTm to the level shifter 330. When the decode signal DECn of the 2m-th line is “1”, the reset signal generation circuit 345 uses the pulse signal to set the reset signal line to the low level before the read transfer of the 2m-th line and reset after the read transfer. Set the signal line to high level. When the decode signal DECn to the 2m + 1st line is “1”, the reset signal generation circuit 345 uses the pulse signal to set the reset signal line to the low level before the read transfer of the 2m + 1th line, and read the read signal. After transfer, the reset signal line is set to high level. By such control, a high level reset signal RSTm is supplied.

The selection signal generation circuit 346 generates a selection signal SELm to the selection transistor 236 shared by the 2m-th and 2m + 1-th lines and supplies the selection signal SELm to the level shifter 330. When the decode signal DECn of the 2m-th line is “1”, the selection signal generation circuit 346 uses the pulse signal to set the selection signal line to the high level before the read transfer of the 2m-th line and select after the read transfer. Set the signal line to low level. When the decode signal DECn of the 2m + 1-th line is “1”, the selection signal generation circuit 346 uses the pulse signal to set the selection signal line to the high level before the read transfer of the 2m + 1-th line and perform the read transfer. Later, the selection signal line is set to the low level. By such control, the high level selection signal SELm is supplied.

[Operation example of timing generator]
FIG. 7 is a table showing an example of the operation of the read transfer signal generation circuit 341 in the first embodiment. If the decode signal DECn is “1”, the read transfer signal generation circuit 341 corresponding to the n-th line has an exposure end timing every time the period of the vertical synchronization signal elapses (in other words, every frame). A read transfer signal RD_Rn is generated.

FIG. 8 is a table showing an example of the operation of the shutter transfer signal generation circuit 342 in the first embodiment. If the decode signal DECn is “1”, the shutter transfer signal generation circuit 342 corresponding to the nth line generates the shutter transfer signal SH_Rn at the exposure start timing for each frame.

FIG. 9 is a table showing an example of the operation of the reset signal generation circuit 345 in the first embodiment. When only DEC1 among the decode signals DEC0 and DEC1 is “1” (read line), the reset signal generation circuit 345 sets the reset signal line to the low level before the read transfer of the first row, and the reset signal after the read transfer. Make the line high. Further, when only the decode signal DEC0 is “1” (read line), the reset signal generation circuit 345 sets the reset signal line to the low level before the read transfer of the 0th row, and sets the reset signal line after the read transfer. Set to high level. When both of the decode signals DEC0 and DEC1 are “1” (read line), the reset signal generation circuit 345 sets the reset signal line to the low level before the read transfer of the 0th and 1st rows and reads them. After transfer, the reset signal line is set to high level. By such control, a high level reset signal RTS0 is supplied. Similarly, the reset signals RSTm in the second and subsequent rows are generated from the 2m-th and 2m + 1-th decoded signals.

FIG. 10 is a table showing an example of the operation of the selection signal generation circuit 346 in the first embodiment. When only DEC1 among the decode signals DEC0 and DEC1 is “1” (read line), the selection signal generation circuit 346 sets the selection signal line to the high level before the read transfer of the first row, and the selection signal after the read transfer. Make the line high. When only the decode signal DEC0 is “1” (read line), the selection signal generation circuit 346 sets the selection signal line to the high level before the read transfer of the 0th row, and sets the selection signal line to the low level after the read transfer. To do. When both the decode signals DEC0 and DEC1 are “1” (read line), the selection signal generation circuit 346 sets the selection signal line to the high level before the read transfer of the 0th row and the 1st row, and the read transfer of them. Later, the selection signal line is set to the low level. By such control, the high level selection signal SEL0 is supplied. Similarly, the selection signals SELm in the second and subsequent rows are generated from the 2m-th and 2m + 1-th decoded signals.

[Configuration example of transfer signal generation circuit]
FIG. 11 is a circuit diagram illustrating a configuration example of the transfer signal generation circuit 320 according to the first embodiment. The transfer signal generation circuit 320 includes OR (logical sum)

gates

321 and 324, an AND (logical product) gate 322, and a latch circuit 323.

The latch circuit 323 holds 1-bit data. The latch circuit 323 includes a set terminal S, a reset terminal R, and an output terminal Q. A latch set signal LT_Set from the level shifter 330 is input to the set terminal S of the latch circuit 323. The reset terminal R of the latch circuit 323 is connected to the output terminal of the OR gate 324, and the output terminal Q is connected to the input terminal of the AND gate 322.

When the latch set signal LT_Set is input from the set terminal S, the latch circuit 323 outputs a high level signal as the latch output signal LAT_Qn. When a high level signal is input from the reset terminal R as a reset signal, the latch circuit 323 outputs a low level signal. In addition, when neither the latch set signal LT_Set nor the reset signal is input, the latch circuit 323 holds the state.

The OR gate 324 outputs a logical sum of input values. The read transfer signal RD_Rn is input to one of the two input terminals of the OR gate 324, and the shutter transfer signal SH_Rn is input to the other. The OR gate 324 outputs a logical sum of the values of the two input terminals to the latch circuit 323 as a reset signal.

Also, a high level signal from the OR gate 324 is input to the OR gate 321 as a transfer signal to the readout line. The OR gate 324 is an example of a read line transfer signal supply unit described in the claims.

The AND gate 322 outputs a logical product of input values. The additional shutter signal SH_Add is input to one of the two input terminals of the AND gate 322, and the latch output signal LAT_Qn from the latch circuit 323 is input to the other. The AND gate 322 outputs the logical product of the values of the two input terminals to the input terminal of the OR gate 321.

The high level signal from the AND gate 322 is input to the OR gate 321 as a transfer signal to the thinning line. The AND gate 322 is an example of a thinned line transfer signal supply unit described in the claims.

The OR gate 321 outputs a logical sum of input values. The OR gate 321 outputs either the transfer signal from the AND gate 322 or the transfer signal from the OR gate 324 to the pixel array unit 210 as an n-line transfer signal Txn. The OR gate 321 is an example of an OR gate described in the claims.

With this configuration, when the latch set signal LT_Set is input, the latch circuit 323 is held at a high level (in other words, set). When the read transfer signal RD_Rn or the shutter transfer signal SH_Rn is input, the low level is held in the latch circuit 323 (in other words, reset), and the transfer signal generation circuit 320 outputs the transfer signal Txn. Since these read transfer signal RD_Rn or shutter transfer signal SH_Rn is not generated in the thinning line, the latch circuit 323 remains set in the thinning line.

Here, when the additional shutter signal SH_Add is input, the transfer signal generation circuit 320 including the set latch circuit 323 outputs the transfer signal Txn. Therefore, the transfer signal Txn can be output to the transfer signal generation circuit 320 corresponding to the thinning-out line by inputting the additional shutter signal SH_Add.

Also, the number of transfer signals Txn of the thinning line per unit time is set to be the same as that of the readout line. As a result, the accumulated time during which the transfer transistor 221 is in the conductive state and the number of transitions to the conductive state are the same in the thinning line and the readout line. Note that the accumulation time of the thinning line in the conductive state and the number of transitions to the conductive state are not completely the same as those in the readout line, and the difference may be substantially the same value within a predetermined allowable value.

[Operation example of transfer signal generation circuit]
FIG. 12 is a table showing an example of the operation of the latch circuit 323 according to the first embodiment. When the values of both the set terminal S and the reset terminal R are “0”, the latch circuit 323 holds the state. When the set terminal S is “0” and the reset terminal R is “1”, the latch circuit 323 is reset and outputs a signal “0” from the output terminal Q. When the set terminal S is “1” and the reset terminal R is “0”, the latch circuit 323 is set and outputs a signal “1”.

FIG. 13 is a table showing an example of the operation of the transfer signal generation circuit 320 in the first embodiment. When the latch set signal LT_Set is input, the transfer signal generation circuit 320 for all lines sets the latch circuit 323 to generate the latch output signal LAT_Qn.

When the read transfer signal RD_Rn is input at the end of exposure, the transfer signal generation circuit 320 on the n-th line resets the latch circuit 323 and outputs the transfer signal Txn. When the shutter transfer signal SH_Rn is input at the start of exposure, the transfer signal generation circuit 320 in the nth line resets the latch circuit 323 and outputs the transfer signal Txn.

When none of the latch set signal LT_Set, the read transfer signal RD_Rn, and the shutter transfer signal SH_Rn is input, the transfer signal generation circuit 320 of the nth line holds the state of the latch circuit 323. When the additional shutter signal SH_Add is input with the latch circuit 323 set, the transfer signal generation circuit 320 outputs the transfer signal Txn. Since the thinning line latch circuit 323 is set, the transfer signal Txn is output to the thinning line by the additional shutter signal SH_Add. On the other hand, even if the additional shutter signal SH_Add is input in a state where the latch circuit 323 is reset, the transfer signal generation circuit 320 does not output the transfer signal Txn. Since the readout line latch circuit 323 is reset after the first frame readout, the transfer signal Txn is not output to the readout line even if the additional shutter signal SH_Add is inputted.

[Operation example of solid-state image sensor]
FIG. 14 is a timing chart illustrating an example of an operation in the normal reading mode of the vertical scanning circuit 300 according to the first embodiment. When imaging starts in the normal readout mode at timing T11, the timing control unit 360 in the vertical scanning circuit 300 generates a latch set signal LT_Set. As a result, the latch circuits 323 for all lines are set. The timing generation unit 340 generates the read transfer signal RD_R0 at the exposure end timing T12. As a result, the latch circuit 323 corresponding to the 0th line is reset, and the OR gate 321 in the transfer signal generation circuit 320 corresponding to the 0th line generates the transfer signal Tx0.

The timing generation unit 340 generates the read transfer signal RD_R1 at the timing T13 when the period of the horizontal synchronization signal has elapsed from the timing T12. As a result, the latch circuit 323 corresponding to the first line is reset, and the OR gate 321 corresponding to the first line generates the transfer signal Tx1. At timing T13, the timing generation unit 340 generates the shutter transfer signal SH_R0. As a result, the OR gate 321 corresponding to the 0th line generates the transfer signal Tx0. By this transfer signal Tx0, exposure of the 0th line is started. Then, the exposure of the first and subsequent lines is started in order.

The timing generation unit 340 generates a read transfer signal RD_R0 at timing T22 when the exposure period of the 0th line has elapsed. As a result, the OR gate 321 corresponding to the 0th generates the transfer signal Tx1. With this transfer signal Tx0, the exposure of the 0th line is completed and the pixel signal is read from the 0th line. Then, the exposure of each of the first and subsequent lines ends in order.

FIG. 15 is a timing chart showing an example of the operation in the normal readout mode of the solid-state imaging device 200 according to the first embodiment. When the timing signal generation circuit 270 starts generating the vertical synchronization signal XVS at the timing T11, the timing generation unit 340 generates the latch set signal LT_Set. Then, immediately before the timing T12 synchronized with the vertical synchronization signal XVS, the timing generation unit 340 sets the selection signal line to the high level and sets the reset signal line to the low level. At timing T12, the OR gate 321 generates the transfer signal Tx0, and after generating the transfer signal Tx0, the timing generation unit 340 sets the reset signal line to high level and the selection signal line to low level.

Then, immediately before the timing T13, the timing generation unit 340 sets the selection signal line to the high level and sets the reset signal line to the low level. At timing T13, the OR gate 321 generates the transfer signal Tx1, and after generating the transfer signal Tx1, the timing generation unit 340 sets the reset signal line to high level and the selection signal line to low level. Thereby, the exposure of the 0th line is started. Then, in the first and subsequent lines, the exposure is sequentially started in the same procedure.

The timing signal generation circuit 270 generates the vertical synchronization signal XVS at the timing T21 when the cycle of the vertical synchronization signal XVS has elapsed from the timing T11. Immediately before the timing T22 synchronized with the vertical synchronization signal XVS, the timing generation unit 340 sets the selection signal line to high level and the reset signal line to low level. At timing T22, the OR gate 321 generates the transfer signal Tx0. Thereby, the exposure of the 0th line is completed and the pixel signal is read out. In the first and subsequent lines, the exposure is sequentially completed in the same procedure. As described above, in the normal readout mode, all lines are sequentially exposed to read out pixel signals.

FIG. 16 is a timing chart showing an example of operation in the 1/3 decimation readout mode of the vertical scanning circuit 300 according to the first embodiment. It is assumed that the normal reading mode is switched to the 1/3 decimation reading mode at timing T11. At this timing T11, the timing control unit 360 generates a latch set signal LT_Set. As a result, the latch circuits 323 for all lines are set. At timing T12 synchronized with the vertical synchronization signal XVS, the timing generation unit 340 generates a read transfer signal RD_R0. As a result, the latch circuit 323 corresponding to the 0th line is reset, and the OR gate 321 corresponding to the 0th line generates the transfer signal Tx0.

The timing generation unit 340 generates the read transfer signal RD_R3 at the timing T13 when the period of the horizontal synchronization signal has elapsed from the timing T12. As a result, the latch circuit 323 corresponding to the third line is reset, and the OR gate 321 corresponding to the third line generates the transfer signal Tx3. At timing T13, the timing generation unit 340 generates the shutter transfer signal SH_R0. As a result, the OR gate 321 corresponding to the 0th line generates the transfer signal Tx0. By this transfer signal Tx0, exposure of the 0th line is started. Then, the exposure of the first and subsequent read lines is started in order.

Then, at timing T21 when the cycle of the vertical synchronization signal XVS has elapsed from timing T11, the timing control unit 360 generates four additional shutter signals SH_Add in order. As a result, four transfer signals Txn are generated in the line in which the latch circuit 323 is set (that is, the thinning line).

Here, it is desirable that the additional shutter signal SH_Add is supplied during a period in which the transfer signal Txn to the readout line is not generated. This is because when the transfer signal is supplied to the thinning line during the period for reading out the pixel signal, the characteristic conditions such as the power supply, ground, and signal line fluctuations change, resulting in a difference from the period in which no additional shutter signal is supplied. This is because noise may occur in the image. In addition, when the floating diffusion layer 234 is not shared by a plurality of pixels, the power supply, the ground, and the signal line are less likely to fluctuate and the characteristic conditions are not affected. The timing for supplying the additional shutter signal SH_Add is arbitrarily set. can do.

Further, the reason that the additional shutter signal SH_Add is not generated at the first timing T11 is that the latch circuits 323 of all the lines are set at this time, and the transfer signal cannot be supplied only to the thinned lines.

After the output of the four additional shutter signals SH_Add, the timing generation unit 340 generates the read transfer signal RD_R0 at the timing T22. Thereby, the exposure of the 0th line is completed and the pixel signal is read out. Then, the exposure of the first and subsequent read lines is finished in order.

At timing T31 when the cycle of the vertical synchronization signal XVS has elapsed from timing T21, the timing control unit 360 generates two additional shutter signals SH_Add in order. As a result, two transfer signals Txn are generated in the thinning line. Thereafter, every time the period of the vertical synchronization signal XVS elapses, two additional shutter signals SH_Add are generated, and two transfer signals Txn are generated in the thinning line.

As described above, every time the period of the vertical synchronization signal XVS elapses, two transfer signals Txn are generated in the read line. On the other hand, in the thinning line, the transfer signal Txn is not generated in the first cycle, four transfer signals Txn are generated in the second cycle, and thereafter, two transfer signals Txn are generated in each cycle. For this reason, the number of transfer signals Txn per cycle is two on average. In this way, since the same number of transfer signals are generated in the readout line and the thinning-out line, the accumulation time of the conduction states of the

transfer transistors

221 and 231 in those lines and the number of transitions to the conduction state are the same. . As a result, the progress rates of the deterioration of the transfer transistors (221 and the like) for each line become the same.

FIG. 17 is a timing chart showing an example of an operation in the 1/3 thinning readout mode of the solid-state imaging device 200 according to the first embodiment. When the timing signal generation circuit 270 starts generating the vertical synchronization signal XVS at the timing T11, the timing control unit 360 generates the latch set signal LT_Set. Immediately before the timing T12 synchronized with the vertical synchronization signal XVS, the timing generation unit 340 sets the selection signal line to high level and the reset signal line to low level. At timing T12, the OR gate 321 generates the transfer signal Tx0, and then the timing generation unit 340 sets the reset signal line to high level and the selection signal line to low level.

The OR gate 321 corresponding to the 0 line generates the transfer signal Tx0 at the timing T13 when the period of the horizontal synchronization signal has elapsed from the timing T12. By this transfer signal Tx0, exposure of the 0th line is started. Then, the exposure of the first and subsequent read lines is started in order.

At timing T22 when the cycle of the vertical synchronization signal XVS has elapsed from timing T11, the timing generator 340 sequentially generates four additional shutter signals SH_Add. As a result, four transfer signals Txn are generated in the line in which the latch circuit 323 is set (that is, the thinning line).

The timing generation unit 340 generates the read transfer signal RD_R0 at the timing T22 after the output of the four additional shutter signals SH_Add. Thereby, the exposure of the 0th line is completed and the pixel signal is read out. Then, the exposure of the first and subsequent read lines is finished in order. Thus, in the 1/3 thinning readout mode, 1/3 of all lines are sequentially exposed and read.

FIG. 18 is a timing chart showing an example of operation in the 1/3 thinning readout mode of the solid-state imaging device in the comparative example. In this comparative example, as described in Patent Document 1, the transfer line of the thinning line is fixed at a high level. In this case, the accumulation time of the transfer transistor in the conductive state and the number of transitions to the conductive state are not the same between the thinning line and the readout line. For this reason, the deterioration of the transfer transistor proceeds at different speeds in the thinning line and the readout line, and the degree of deterioration of the transfer transistor becomes different. Due to the difference in the degree of deterioration, when all lines are read out, streak noise is generated in the image data.

If the blooming is not a problem, the transfer line of the thinning line can be fixed at a low level. However, in this case as well, the driving conditions of the transfer transistors of the thinning line and the readout line are not the same, and similar noise is generated.

On the other hand, the vertical scanning circuit 300 supplies the same number of transfer signals to each of the thinning line and the readout line. For this reason, in these lines, the accumulation time of the conduction state of the transfer transistor and the number of transitions to the conduction state are the same, and the deterioration proceeds at the same speed. As a result, streak noise does not occur in the image data, and the image quality can be improved.

FIG. 19 is a flowchart showing an example of the operation of the solid-state imaging device 200 according to the first embodiment. This operation starts when, for example, the start of imaging is instructed by the imaging control signal. The solid-state imaging device 200 determines whether or not the mode signal indicates the 1/3 decimation readout mode (step S901). When the normal reading mode is set (step S901: No), the solid-state imaging device 200 executes normal reading processing for sequentially reading all lines (step S910). On the other hand, when the mode is the 1/3 decimation readout mode (step S901: Yes), the solid-state imaging device 200 executes 1 / decimation readout processing for sequentially reading 1/3 of all lines (step S920).

After step S910 or S920, the solid-state imaging device 200 performs predetermined image processing on the read image data (step S902). Then, the solid-state imaging device 200 determines whether or not the end of imaging is instructed by the imaging control signal (step S903). When the end of imaging is not instructed (step S903: No), the solid-state imaging device 200 repeatedly executes step S901 and subsequent steps. On the other hand, when the end of imaging is instructed (step S903: Yes), the solid-state imaging device 200 ends imaging.

FIG. 20 is a flowchart showing an example of the normal reading process in the first embodiment. The vertical scanning circuit 300 selects the 2m line, sets the corresponding selection signal line to the high level, and sets the corresponding reset signal line to the low level (step S911). The vertical scanning circuit 300 supplies a read transfer signal to the 2m line (step S912). When m is 1 or more, a shutter transfer signal to the 2m-1 line is simultaneously supplied. After the read transfer, the vertical scanning circuit 300 sets the corresponding reset signal line to the high level and sets the corresponding selection signal line to the low level (step S913). Next, the vertical scanning circuit 300 selects the 2m + 1 line, sets the corresponding selection signal line to the high level, and sets the corresponding reset signal line to the low level (step S914). The vertical scanning circuit 300 supplies the read transfer signal to the 2m + 1 line together with the shutter transfer signal to the 2m line (step S915). After the read transfer, the vertical scanning circuit 300 sets the corresponding reset signal line to the high level and sets the corresponding selection signal line to the low level (step S916). The vertical scanning circuit 300 determines whether the 2m + 1 line is the last line (step S917). When it is not the last line (step S917: No), the vertical scanning circuit 300 repeats step S911 and subsequent steps. On the other hand, if it is the last line (step S917: Yes), the vertical scanning circuit 300 supplies a shutter transfer signal to that line (step S918), and the normal reading process is terminated.

FIG. 21 is a flowchart illustrating an example of 1/3 decimation readout processing according to the first embodiment. The vertical scanning circuit 300 determines whether or not it is the time immediately after the start of imaging (T11 or the like) in the 1/3 decimation readout mode (step S921). If not immediately after the start of imaging (step S922: No), the vertical scanning circuit 300 supplies a predetermined number of transfer signals to the thinning lines (step S922).

Immediately after the start of imaging (step S921: Yes) or after step S922, the vertical scanning circuit 300 pays attention to any line and determines whether the line is a readout line (step S923). If it is a readout line (step S923: Yes), the vertical scanning circuit 300 sets the corresponding selection signal line to high level and the corresponding reset signal line to low level (step S924). The vertical scanning circuit 300 transmits a read transfer signal and outputs a pixel signal (step S925). After the read transfer, the vertical scanning circuit 300 sets the corresponding reset signal line to the high level and sets the corresponding selection signal line to the low level (step S926). Subsequently, the vertical scanning circuit 300 starts exposure by transmitting a shutter transfer signal (step S927). When the focused line is a thinning line (step S923: No) or after step S927, the vertical scanning circuit 300 determines whether reading of all the reading lines is completed (step S928).

When reading of all the reading lines has not been completed (step S928: No), the vertical scanning circuit 300 repeats step S923 and subsequent steps. On the other hand, when reading of all the reading lines is completed (step S928: Yes), the vertical scanning circuit 300 ends the 1/3 thinning-out reading process.

As described above, according to the first embodiment of the present technology, the vertical scanning circuit 300 makes the accumulated time of the conduction state of the transfer transistor of the thinning line and the number of transitions to the conduction state the same as those of the readout line. Therefore, the degree of deterioration of these lines can be made comparable. As a result, no streak noise is generated in the image data when all lines are read out, and the image quality can be improved.

[First Modification]
In the first embodiment described above, the vertical scanning circuit 300 generates the additional shutter signal SH_Add before the end of exposure of the first line (T22), but the additional shutter signal after the start of exposure of the last line. SH_Add may be generated. The vertical scanning circuit 300 according to the first modification of the first embodiment is different from the first embodiment in that the additional shutter signal SH_Add is generated after the exposure of the last line is started.

FIG. 22 is a timing chart showing an example of operation in the 1/3 decimation readout mode of the solid-state imaging device 200 in the first modification of the first embodiment. It is assumed that the exposure of the last readout line is started immediately before the timing T14. At this timing T14, since the latch circuits 323 of all the readout lines are reset, the vertical scanning circuit 300 can supply a transfer signal only to the thinning lines. Therefore, the timing control unit 360 generates two additional shutter signals SH_Add in order. As a result, the OR gates 321 of all the thinning lines generate two transfer signals Txn. Similarly, after the timing T14, two transfer signals Txn are generated every time the exposure of the last readout line is started.

As described above, according to the first modification of the first embodiment of the present technology, the vertical scanning circuit 300 sequentially supplies two transfer signals to the thinning line after the exposure of the last line is started. The number of transfer signals to each thinning line can be made two. This makes it easier to control the vertical scanning circuit 300 than in the first embodiment in which only the second frame needs to supply four transfer signals to the thinning line.

[Second Modification]
In the first embodiment described above, the vertical scanning circuit 300 controls the accumulated time of the transfer transistor in the conductive state and the number of transitions to the conductive state in the thinning line in the same manner as in the readout line. It is not limited to this configuration. Depending on the configuration of the transfer transistor, the cumulative time of the conductive state may have a greater influence on the progress of the deterioration than the number of transitions to the conductive state. In this case, it is not necessary to make the number of transitions the same, and if only the accumulation time of the conduction state is the same, the progress speed of the deterioration can be made the same. The vertical scanning circuit 300 according to the second modification of the first embodiment is different from the first embodiment in that only the accumulation time of the conduction state of the transfer transistor is controlled in the thinning line in the same manner as the readout line. Different.

FIG. 23 is a timing chart showing an example of the operation in the 1/3 decimation readout mode of the solid-state imaging device 200 in the second modification of the first embodiment. The vertical scanning circuit 300 of the second modification example of the first embodiment generates one additional shutter signal SH_Add instead of four at the timing T21. The pulse width W2 of the additional shutter signal SH_Add is four times the pulse width W1 of the transfer signal Txn to the readout line. Further, the vertical scanning circuit 300 generates one additional shutter signal SH_Add having a pulse width W2 that is twice W1 at timing T31. Thereafter, each time the period of the vertical synchronization signal XVS elapses, one additional shutter signal SH_Add having a pulse width W2 is generated. Thereby, in the thinning-out line, the accumulated time of the conduction state of the transfer transistor becomes the same as that of the reading line.

As described above, according to the second modification of the first embodiment of the present technology, the vertical scanning circuit 300 controls the accumulated time of the conduction state of the transfer transistor in the thinning line to be the same as that in the readout line. The degree of deterioration of these lines can be made comparable.

[Third Modification]
In the first embodiment described above, one transfer line is wired for each line, but two transfer lines can be wired for each line. If a part of pixels (R pixel, B pixel, etc.) in the line is connected to one of the two transfer lines, and the remaining pixel (G pixel, etc.) is connected to the other, the vertical scanning circuit 300 has an R pixel. In addition, the exposure control of the B pixel and the G pixel can be performed at different timings. Here, the R pixel indicates a pixel that receives red visible light, and the G pixel indicates a pixel that receives green visible light. The B pixel indicates a pixel that receives blue visible light. The solid-state imaging device 200 of the third modification example of the first embodiment is different from the first embodiment in that two transfer lines are wired for each line.

FIG. 24 is a circuit diagram illustrating a configuration example of the pixel array unit 210 according to the third modification of the first embodiment. The pixel array unit 210 of the third modification example of the first embodiment is different from the first embodiment in that the pixel array unit 210 further includes

pixels

240 and 250 in addition to the

pixels

220 and 230.

The pixel 220 is an R pixel on the 2m-th line, and the pixel 230 is a Gb pixel on the 2m + 1-th line. The pixel 240 is a Gr pixel on the 2m-th line, and the pixel 250 is a B pixel on the 2m + 1-th line. Here, the Gr pixel is a G pixel arranged on the same line as the R pixel, and the Gb pixel is a G pixel arranged on the same line as the B pixel.

The configuration of the pixel 240 is the same as that of the pixel 220, and the configuration of the pixel 250 is the same as that of the pixel 230. In addition, each of the R, Gr, B, and Gb pixels is arranged according to a Bayer array.

Also, two transfer lines are arranged for each line. In the 2m-th line, one of the two transfer lines is connected to the transfer transistor 221 of the R pixel (220), and the other is connected to the transfer transistor 221 of the Gr pixel (240). In the 2m + 1th line, one of the two transfer lines is connected to the transfer transistor 231 of the Gb pixel (230), and the other is connected to the transfer transistor 231 of the B pixel (250). Further, the transfer signal Txbn is supplied to the R pixel (220) of the 2m (= n) th line, and the transfer signal Txan is supplied to the Gr pixel (240) of the 2mth line. The transfer signal Txbn is supplied to the Gb pixel (230) of the 2m + 1 (= n) th line, and the transfer signal Txan is supplied to the B pixel (250) of the first line.

By these transfer signals, the vertical scanning circuit 300 supplies transfer signals to the R, Gr, B, and Gb pixels at different timings, and individually controls the exposure start timing and the exposure end timing of those pixels. Can do. Thereby, the vertical scanning circuit 300 can control the exposure times of the R, Gr, B, and Gb pixels to different values.

As described above, according to the third modification example of the first embodiment of the present technology, the vertical scanning circuit 300 supplies transfer signals to the R, Gr, B, and Gb pixels at different timings. The exposure times of these pixels can be controlled to different values.

<2. Second Embodiment>
In the first embodiment described above, the vertical scanning circuit 300 selects 1/3 of all the lines as a readout line at the time of thinning readout. However, a line having a ratio other than 1/3 may be selected. . For example, the vertical scanning circuit 300 may select 1/5 of all lines as a readout line. The vertical scanning circuit 300 according to the second embodiment is different from the first embodiment in that 1/5 of all the lines is selected as a readout line.

FIG. 25 is a diagram illustrating an example of a decoded signal according to the second embodiment. In the second embodiment, data A is input as address data in the normal read mode, and data C is input in the 1/5 decimation read mode for selecting 1/5 of all the lines. .

When data C is input (1/5 decimation read mode), the address decoder 350 sets “1” (read line) to 1/5 of the decode signals of all the lines and “0” (decimation) for the rest. Line) is set and output. For example, “0” is set to the 0th decode signal DEC0, and “0” is set to all the 1st to 4th decode signals DEC1 to DEC4. Further, “1” is set to the fifth decode signal DEC5. In the same manner, one line out of every five lines is set as a readout line.

FIG. 26 is a timing chart showing an example of the operation in the 1/5 thinning readout mode of the vertical scanning circuit 300 according to the second embodiment. It is assumed that the normal reading mode is switched to the 1/5 decimation reading mode at timing T11. At this timing T11, the timing control unit 360 generates a latch set signal LT_Set. At timing T12 synchronized with the vertical synchronization signal XVS, the timing generation unit 340 generates a read transfer signal RD_R0. The timing generation unit 340 generates the read transfer signal RD_R0 at timing T13 when the period of the horizontal synchronization signal has elapsed from timing T12.

At timing T21 when the cycle of the vertical synchronization signal XVS has elapsed from timing T11, the timing control unit 360 sequentially generates four additional shutter signals SH_Add. As a result, four transfer signals Txn are supplied to the thinning lines such as the first to fourth lines. Since the transfer signal Txn is simultaneously supplied to all the thinned lines by one additional shutter signal SH_Add, the supply timing of the additional shutter signal SH_Add can be changed even if the number of thinned lines is changed as illustrated in FIG. There is no need to change.

As described above, according to the second embodiment of the present technology, since the vertical scanning circuit 300 selects 1/5 of all lines, the image data data is more than the case of selecting 1/3 of all lines. The amount can be reduced.

<3. Third Embodiment>
In the first embodiment described above, the solid-state imaging device 200 performs reading by switching to one of two modes of the normal reading mode and the 1/3 thinning-out reading mode. However, a 1/5 decimation readout mode may be added, and the solid-state imaging device 200 may perform readout by switching to any of the three modes. The solid-state imaging device 200 according to the third embodiment is different from the first embodiment in that reading is performed by switching to any one of the normal reading mode, the 1/3 thinning readout mode, and the 1/5 thinning readout mode. .

FIG. 27 is a diagram illustrating an example of a decode signal according to the third embodiment. In the third embodiment, data A is input as address data in the normal read mode, data B is input in the 1/3 decimation read mode, and data C is input in the 1/5 decimation read mode. Shall be entered. When data A or B is input, a decode signal similar to that of the first embodiment is generated, and when data C is input, a decode signal similar to that of the second embodiment is generated. Is done.

FIG. 28 is a timing chart showing an example of the operation in the thinning readout mode of the vertical scanning circuit 300 in the third embodiment. Until the timing T11, it is assumed that the 1/3 thinning-out reading mode is set and the timing 21 thereafter is switched to the 1/5 thinning-out reading mode. At this timing T21, the timing control unit 360 supplies the latch set signal LT_Set. The operation of the vertical scanning circuit 300 before the timing T21 is the same as that in the 1/3 decimation readout mode of the first embodiment. The operation of the vertical scanning circuit 300 after the timing T21 is the same as in the 1/5 decimation readout mode of the second embodiment.

As described above, according to the third embodiment of the present technology, the solid-state imaging device 200 can switch between the 1/3 decimation readout mode and the 1/5 decimation readout mode. The amount of data can be changed according to the user's operation.

<4. Fourth Embodiment>
In the first embodiment described above, the vertical scanning circuit 300 selects lines arranged with a certain interval in the direction perpendicular to the line (that is, the column direction) as the readout line. A plurality of continuous lines may be selected as read lines. Such thinning readout is also called window readout. This window reading is used when a part of an image is cut out without reducing the resolution. The vertical scanning circuit 300 of the fourth embodiment differs from the first embodiment in that window reading is performed.

FIG. 29 is a diagram illustrating an example of a decoded signal according to the fourth embodiment. In the fourth embodiment, data A is input as address data in the normal reading mode, data B is input in the 1/3 decimation reading mode, and data D is input in the window reading mode for performing window reading. Shall be entered.

When data D is input (window read mode), the address decoder 350 sets “1” (read line) to the decode signals of a plurality of lines continuous in the column direction, and the remaining “0” (decimation line). ) Is set and output. For example, “0” is set in the 0th, 1st and 2nd decode signals DEC0, DEC1 and DEC2. Further, “1” is set to the third, fourth and fifth decode signals DEC3, DEC4 and DEC5. “0” is set to the sixth and subsequent decode signals. With these decode signals, only the third to fifth lines are read out.

FIG. 30 is a timing chart showing an example of the window reading mode operation of the vertical scanning circuit 300 according to the fourth embodiment. It is assumed that the normal reading mode is switched to the window reading mode at timing T11. At this timing T11, the timing control unit 360 generates a latch set signal LT_Set. At timing T12 synchronized with the vertical synchronization signal XVS, the timing generation unit 340 generates a read transfer signal RD_R3. Then, the timing generation unit 340 generates the read transfer signal RD_R4 at the timing T13 when the period of the horizontal synchronization signal has elapsed from the timing T12.

At timing T21 when the cycle of the vertical synchronization signal XVS has elapsed from timing T11, the timing control unit 360 sequentially generates four additional shutter signals SH_Add. As a result, four transfer signals Txn are supplied to each of the 0th to 2nd thinning lines.

As described above, according to the fourth embodiment of the present technology, the vertical scanning circuit 300 selects a plurality of continuous lines in the column direction as readout lines, so that a part of the image is not reduced without reducing the resolution. Can be cut out.

The above-described embodiment shows an example for embodying the present technology, and the matters in the embodiment and the invention-specific matters in the claims have a corresponding relationship. Similarly, the invention specific matter in the claims and the matter in the embodiment of the present technology having the same name as this have a corresponding relationship. However, the present technology is not limited to the embodiment, and can be embodied by making various modifications to the embodiment without departing from the gist thereof.

Further, the processing procedure described in the above embodiment may be regarded as a method having a series of these procedures, and a program for causing a computer to execute these series of procedures or a recording medium storing the program. You may catch it. As this recording medium, for example, a CD (Compact Disc), an MD (MiniDisc), a DVD (Digital Versatile Disc), a memory card, a Blu-ray disc (Blu-ray (registered trademark) Disc), or the like can be used.

It should be noted that the effects described here are not necessarily limited, and may be any of the effects described in the present disclosure.

In addition, this technique can also take the following structures.
(1) A plurality of pixels, each of which is provided with a transfer transistor for transferring the charge by transitioning to a conductive state by a transfer signal instructing transfer of the charge from the photodiode to the charge storage unit, is arranged in a two-dimensional lattice. A pixel array unit,
A selection unit that selects, as a readout line, a remaining line obtained by thinning out some lines as thinning lines from all of the pixels arranged in a predetermined direction in the pixel array unit;
A read line transfer signal supply unit configured to control the transfer transistor of the read line to the conductive state over a certain period from a predetermined timing by supplying the transfer signal to the read line;
A readout unit that reads out a pixel signal corresponding to the amount of the charge from the readout line;
Thinning line transfer for controlling at least one of the accumulated time of the conducting state in the transfer transistor of the thinning line and the number of transitions to the conducting state to be substantially the same as the readout line by supplying the transfer signal to the thinning line A solid-state imaging device comprising a signal supply unit.
(2) The solid-state imaging device according to (1), wherein the thinning line transfer signal supply unit supplies the same number of transfer signals to the thinning line as the number transferred by the read line transfer signal supply unit.
(3) The decimation line transfer signal supply unit extends over a period substantially equal to the accumulated time of the conduction state by the predetermined number of transfer signals each time a predetermined number of the transfer signals are transferred to the read line. The solid-state imaging device according to (1), wherein the transfer signal is supplied to the thinning line.
(4) a latch circuit that outputs an output signal having a specific value when a set signal is input, and outputs an output signal having a value different from the specific value when a reset signal is input;
An OR gate that outputs either of the two input signals to the transfer transistor is further provided for each line.
The read line transfer signal supply unit inputs the transfer signal to the read line to the OR gate corresponding to the read line and uses the transfer signal as the reset signal corresponding to the read line to the latch circuit. Input,
The thinning line transfer signal supply unit generates a logical product signal of the output signal of the latch circuit corresponding to the thinning line and a predetermined additional shutter signal as the transfer signal to the thinning line, and supplies the signal to the thinning line. The solid-state imaging device according to any one of (1) to (3), which is input to the corresponding OR gate.
(5) The selection unit switches a position and the number of lines to be selected as the readout line among the plurality of lines according to a predetermined mode signal.
The solid-state imaging device according to (4), wherein the set signal is input to the latch circuit every time the position and number of the readout lines are switched by the mode signal.
(6) In any one of (1) to (5), the selection unit selects, as the read line, each of the lines arranged at regular intervals in a direction perpendicular to the predetermined direction among the plurality of lines. The solid-state imaging device described.
(7) The solid-state imaging device according to any one of (1) to (6), wherein the selection unit selects lines adjacent to each other in the direction perpendicular to the predetermined direction among the plurality of lines as the readout line. .
(8) The read line transfer signal supply unit supplies the transfer signal to each of some of the pixels of the read line and the remaining pixels at different timings,
The thinning line transfer signal supply unit supplies any of the transfer signals to the pixels of the thinning line and the remaining pixels at timings different from each other. The solid-state image sensor described in 1.
(9) A pair of pixels adjacent in the direction perpendicular to the predetermined direction among the plurality of pixels share the charge accumulation unit,
The thinning line transfer signal supply unit according to any one of (1) to (8), wherein the transfer signal is supplied to the thinning line during a period in which the transfer signal is not supplied to any of the read lines. Solid-state image sensor.
(10) A plurality of pixels each provided with a transfer transistor for transferring the charge by transitioning to a conductive state by a transfer signal instructing transfer of the charge from the photodiode to the charge storage unit are arranged in a two-dimensional lattice pattern A pixel array unit,
A selection unit that selects, as a readout line, a remaining line obtained by thinning out some lines as thinning lines from all of the pixels arranged in a predetermined direction in the pixel array unit;
A read line transfer signal supply unit configured to control the transfer transistor of the read line to the conductive state over a certain period from a predetermined timing by supplying the transfer signal to the read line;
A readout unit that reads out a pixel signal corresponding to the amount of the charge from the readout line;
Thinning line transfer for controlling at least one of the accumulated time of the conducting state in the transfer transistor of the thinning line and the number of transitions to the conducting state to be substantially the same as the readout line by supplying the transfer signal to the thinning line A signal supply unit;
An electronic apparatus comprising: a processing unit that processes the read pixel signal.
(11) A plurality of pixels, each of which is provided with a transfer transistor for transferring the charge by transitioning to a conductive state by a transfer signal instructing transfer of the charge from the photodiode to the charge storage unit, is arranged in a two-dimensional lattice. A selection procedure for selecting, as a readout line, a remaining line obtained by thinning out some lines as thinning lines from all of the pixels arranged along a predetermined direction in the pixel array unit;
A read line transfer signal supply procedure for controlling the transfer transistor of the read line to the conductive state over a certain period from a predetermined timing by supplying the transfer signal to the read line;
A reading procedure for reading out a pixel signal corresponding to the amount of the charge from the reading line;
Thinning line transfer for controlling at least one of the accumulation time of the conduction state in the transfer transistor of the thinning line and the number of transitions to the conduction state to be substantially the same as the readout line by supplying the transfer signal to the thinning line. A control method of a solid-state imaging device comprising a signal supply procedure.

DESCRIPTION OF SYMBOLS 100 Image pick-up device 110 Imaging lens 120 Image processing part 130 Recording part 140 Control part 150 Display part 200 Solid-state image sensor 210

Pixel array part

220, 230, 240, 250 Pixel 221,231 Transfer transistor 222,232 Photodiode 233 Reset transistor 234 Floating Diffusion layer 235 Amplifying transistor 236 Select transistor 260 Column CDS section 261 CDS circuit 270 Timing signal generating circuit 280 Output circuit 290 Horizontal scanning circuit 300 Vertical scanning circuit 310 Transfer signal generating section 320 Transfer signal generating circuit 321 324 OR (logical sum) gate 322 AND (logical product) gate 323 latch circuit 330 level shifter 340 timing generation unit 341, 343 read transfer

signal generation circuit

342, 344 Transfer signal generation circuit 345 reset signal generation circuit 346 selection signal generation circuit 350 address decoder 360 timing control unit

Claims

A pixel array in which a plurality of pixels, each of which is provided with a transfer transistor that is transferred to a conductive state by a transfer signal instructing transfer of charge from a photodiode to a charge storage unit and transfers the charge, are arranged in a two-dimensional lattice pattern And
A selection unit that selects, as a readout line, a remaining line obtained by thinning out some lines as thinning lines from all of the pixels arranged in a predetermined direction in the pixel array unit;
A read line transfer signal supply unit configured to control the transfer transistor of the read line to the conductive state over a certain period from a predetermined timing by supplying the transfer signal to the read line;
A readout unit that reads out a pixel signal corresponding to the amount of the charge from the readout line;
Thinning line transfer for controlling at least one of the accumulated time of the conducting state in the transfer transistor of the thinning line and the number of transitions to the conducting state to be substantially the same as the readout line by supplying the transfer signal to the thinning line A solid-state imaging device comprising a signal supply unit.
The solid-state imaging device according to claim 1, wherein the thinning line transfer signal supply unit supplies the same number of transfer signals to the thinning line as the number transferred by the read line transfer signal supply unit.
The thinning line transfer signal supply unit is configured to transfer the transfer signal over a period of time approximately equal to the accumulated time of the conduction state by the predetermined number of transfer signals each time a predetermined number of transfer signals are transferred to the read line. The solid-state imaging device according to claim 1, wherein the is supplied to the thinning line.
A latch circuit that outputs an output signal of a specific value when a set signal is input, and outputs an output signal of a value different from the specific value when a reset signal is input;
An OR gate that outputs either of the two input signals to the transfer transistor is further provided for each line.
The read line transfer signal supply unit inputs the transfer signal to the read line to the OR gate corresponding to the read line and uses the transfer signal as the reset signal corresponding to the read line to the latch circuit. Input,
The thinning line transfer signal supply unit generates a logical product signal of the output signal of the latch circuit corresponding to the thinning line and a predetermined additional shutter signal as the transfer signal to the thinning line, and supplies the signal to the thinning line. The solid-state imaging device according to claim 1, wherein the solid-state imaging element is input to the corresponding logical sum gate.
The selection unit switches the position and the number of lines to be selected as the readout line among the plurality of lines according to a predetermined mode signal,
The solid-state imaging device according to claim 4, wherein the set signal is input to the latch circuit every time the position and the number of the readout lines are switched by the mode signal.
2. The solid-state imaging device according to claim 1, wherein the selection unit selects each of the plurality of lines arranged at regular intervals in a direction perpendicular to the predetermined direction as the readout line.
The solid-state imaging device according to claim 1, wherein the selection unit selects lines adjacent to each other in the direction perpendicular to the predetermined direction among the plurality of lines as the readout line.
The read line transfer signal supply unit supplies the transfer signal to each of some of the pixels of the read line and the remaining pixels at different timings,
2. The solid-state imaging device according to claim 1, wherein the thinning line transfer signal supply unit supplies the transfer signal to a part of the pixels of the thinning line and a remaining pixel at different timings.
A pair of pixels adjacent in the direction perpendicular to the predetermined direction among the plurality of pixels share the charge storage unit,
The solid-state imaging device according to claim 1, wherein the thinning line transfer signal supply unit supplies the transfer signal to the thinning line during a period in which the transfer signal is not supplied to any of the read lines.
A pixel array in which a plurality of pixels, each of which is provided with a transfer transistor that is transferred to a conductive state by a transfer signal instructing transfer of charge from a photodiode to a charge storage unit and transfers the charge, are arranged in a two-dimensional lattice pattern And
A selection unit that selects, as a readout line, a remaining line obtained by thinning out some lines as thinning lines from all of the pixels arranged in a predetermined direction in the pixel array unit;
A read line transfer signal supply unit configured to control the transfer transistor of the read line to the conductive state over a certain period from a predetermined timing by supplying the transfer signal to the read line;
A readout unit that reads out a pixel signal corresponding to the amount of the charge from the readout line;
Thinning line transfer for controlling at least one of the accumulated time of the conducting state in the transfer transistor of the thinning line and the number of transitions to the conducting state to be substantially the same as the readout line by supplying the transfer signal to the thinning line A signal supply unit;
An electronic apparatus comprising: a processing unit that processes the read pixel signal.
A pixel array in which a plurality of pixels, each of which is provided with a transfer transistor that is transferred to a conductive state by a transfer signal instructing transfer of charge from a photodiode to a charge storage unit and transfers the charge, are arranged in a two-dimensional lattice pattern A selection procedure for selecting, as a readout line, a remaining line obtained by thinning out some lines as thinning lines from all of the pixels arranged along a predetermined direction in the unit;
A read line transfer signal supply procedure for controlling the transfer transistor of the read line to the conductive state over a certain period from a predetermined timing by supplying the transfer signal to the read line;
A reading procedure for reading out a pixel signal corresponding to the amount of the charge from the reading line;
Thinning line transfer for controlling at least one of the accumulated time of the conducting state in the transfer transistor of the thinning line and the number of transitions to the conducting state to be substantially the same as the readout line by supplying the transfer signal to the thinning line A control method of a solid-state imaging device comprising a signal supply procedure.