WO2016162778A1 - Display device and electronic equipment - Google Patents

Abstract

Provided is a display device with low power consumption. A light resonance plate is used in a backlight unit for the display device. The light resonance plate can extract and output any wavelength region of light from incident white light. The light resonance plate reuses the remaining components that have not been output from the light resonance plate out of the incident white light without generating colored light by absorption. The light resonance plate can, for example, output each of red light, green light, and blue light.

Description

Display device and electronic device

One embodiment of the present invention relates to a transistor, a semiconductor device, and a manufacturing method thereof.

Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter).

Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A display device (a liquid crystal display device, a light-emitting display device, or the like), an illumination device, an electro-optical device, a power storage device, a memory device, a semiconductor circuit, an imaging device, an electronic device, or the like may include a semiconductor device.

In a liquid crystal display device, in order to obtain a high-quality image, an active matrix liquid crystal display device in which pixel electrodes are arranged in a matrix and a transistor is connected to each pixel electrode as a switching element has attracted attention.

For example, an active matrix liquid crystal display device in which a transistor having a metal oxide channel formation region as a switching element is connected to each pixel electrode is already known (Patent Document 1 and Patent Document 2).

Active matrix liquid crystal display devices are roughly classified into two types, a transmission type and a reflection type. In the case of a transmissive liquid crystal display device, the power consumption of the backlight greatly affects the power consumption of the entire liquid crystal display device, so how to reduce the light loss inside the panel is an important point for reducing power consumption. It becomes. Light loss inside the panel is caused by light refraction in the interlayer insulating film, light absorption by the color filter, and the like.

In general, a color filter has a function of transmitting light in a specific wavelength range by utilizing light absorption by a pigment. For this reason, when colored light is generated from white light using a color filter, the loss of light increases in principle. Actually, 70% or more of the light emitted from the backlight may be absorbed by the color filter. Therefore, it can be said that the generation of colored light by the color filter is one of the factors hindering the reduction in power consumption of the liquid crystal display device.

JP 2007-123861 A JP 2007-96055 A

An object is to provide a display device with low power consumption. Another object is to provide a display device with favorable color reproducibility. Another object is to provide a display device with high display quality. Another object is to provide a display device with favorable reliability. Another object is to provide a novel display device.

Note that the description of these problems does not disturb the existence of other problems. Note that one embodiment of the present invention does not have to solve all of these problems. Issues other than these will be apparent from the description of the specification, drawings, claims, etc., and other issues can be extracted from the descriptions of the specification, drawings, claims, etc. It is.

One embodiment of the present invention includes a light source, an optical resonance plate, and a liquid crystal element. The light source and the liquid crystal element overlap with each other through the optical resonance plate, and the light source emits first light having a first wavelength range. The optical resonance plate is a display device having a function of extracting the second light having the second wavelength region from the first light and a function of making the second light incident on the liquid crystal element. .

Alternatively, one embodiment of the present invention includes a light source, an optical resonance plate, and a liquid crystal element, the light source and the liquid crystal element overlap with each other through the optical resonance plate, and the light source emits the first light having the first wavelength range. The optical resonance plate has a function of emitting light, the first light, the second light having the second wavelength range, the third light having the third wavelength range, and the fourth wavelength having the fourth wavelength range. The display device has a function of extracting the second light and a function of causing the second to fourth lights to enter the liquid crystal element.

Another embodiment of the present invention is an electronic device including any of the above display devices and an antenna, a battery, a housing, a speaker, a microphone, an operation switch, or an operation button.

The second light may be light having a red wavelength range, the third light may be light having a green wavelength range, and the fourth light is light having a blue wavelength range. May be.

Alternatively, the second light may have a center wavelength of 610 nm to 750 nm, the third light may have a center wavelength of 500 nm to 560 nm, and the fourth light has a center wavelength of 435 nm to 480 nm. It may be.

Further, the color temperature of the first light is preferably 3000 K or more and 12000 K or less.

The liquid crystal element may be a horizontal electric field type liquid crystal element.

A display device with low power consumption can be provided. Alternatively, a display device with favorable color reproducibility can be provided. Alternatively, a display device with favorable display quality can be provided. Alternatively, a display device with favorable reliability can be provided. Alternatively, a novel display device can be provided.

Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention need not have all of these effects. It should be noted that the effects other than these are naturally obvious from the description of the specification, drawings, claims, etc., and it is possible to extract the other effects from the descriptions of the specification, drawings, claims, etc. It is.

FIG. 14 is a perspective view illustrating a display device. FIG. 14 is a perspective view illustrating a display device. Sectional drawing explaining an optical resonance board. The perspective view explaining a light emission part. Sectional drawing explaining the preparation methods of an optical resonance board. Sectional drawing explaining the preparation methods of an optical resonance board. Sectional drawing explaining the preparation methods of an optical resonance board. Sectional drawing explaining a display apparatus. Sectional drawing explaining a display apparatus. Sectional drawing explaining a display apparatus. FIG. 6 illustrates a configuration example of a pixel. FIG. 9 is a block diagram illustrating a structure example of a display device. FIG. 9 is a block diagram illustrating a structure example of a display device. 4A and 4B are a circuit portion and a top view illustrating a structure example of a pixel according to an embodiment. Sectional drawing explaining the structural example of an element substrate. FIG. 6 is a cross-sectional view illustrating a structure example of a display device according to an embodiment. FIG. 6 is a cross-sectional view illustrating a structure example of a display device according to an embodiment. FIG. 6 is a Cs-corrected high-resolution TEM image in a cross section of a CAAC-OS and a schematic cross-sectional view of the CAAC-OS. The Cs correction | amendment high-resolution TEM image in the plane of CAAC-OS. 6A and 6B illustrate structural analysis by XRD of a CAAC-OS and a single crystal oxide semiconductor. The figure which shows the electron diffraction pattern of CAAC-OS. FIG. 6 shows changes in crystal parts of an In—Ga—Zn oxide due to electron irradiation. FIG. 10 is a cross-sectional view illustrating an example of a transistor. FIG. 10 is a cross-sectional view illustrating an example of a transistor. FIG. 10 is a cross-sectional view illustrating an example of a transistor. 4A and 4B are a top view and cross-sectional views illustrating an example of a transistor. 4A and 4B are a top view and cross-sectional views illustrating an example of a transistor. 4A and 4B are a top view and cross-sectional views illustrating an example of a transistor. 4A and 4B are a top view and cross-sectional views illustrating an example of a transistor. 4A and 4B are a top view and cross-sectional views illustrating an example of a transistor. The figure explaining an energy band structure. The expanded view explaining an example of a display module. FIG. 14 is a perspective view illustrating an example of an electronic device.

Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated.

In addition, the position, size, range, and the like of each component illustrated in the drawings and the like may not represent the actual position, size, range, or the like in order to facilitate understanding of the invention. Therefore, the disclosed invention is not necessarily limited to the position, size, range, or the like disclosed in the drawings and the like. For example, in an actual manufacturing process, a layer or a resist mask may be lost unintentionally by a process such as etching, but may be omitted for easy understanding.

In the drawings, some components may be omitted for easy understanding of the invention. Moreover, description of some hidden lines may be omitted.

In the present specification and the like, ordinal numbers such as “first” and “second” are used to avoid confusion between components, and do not indicate any order or order such as process order or stacking order. In addition, even in terms that do not have an ordinal number in this specification and the like, an ordinal number may be added in the claims to avoid confusion between the constituent elements. Further, even terms having an ordinal number in this specification and the like may have different ordinal numbers in the claims. Even in the present specification and the like, terms with ordinal numbers are sometimes omitted in the claims.

Further, in this specification and the like, the terms “electrode” and “wiring” do not functionally limit these components. For example, an “electrode” may be used as part of a “wiring” and vice versa. Furthermore, the terms “electrode” and “wiring” include a case where a plurality of “electrodes” and “wirings” are integrally formed.

In the present specification and the like, the terms “upper” and “lower” do not limit that the positional relationship between the components is directly above or directly below and is in direct contact. For example, the expression “electrode B on the insulating layer A” does not require the electrode B to be formed in direct contact with the insulating layer A, and another configuration between the insulating layer A and the electrode B. Do not exclude things that contain elements.

In addition, the functions of the source and drain of the transistor are switched with each other depending on operating conditions such as when transistors with different polarities are used or when the direction of current changes in circuit operation. It is difficult to limit. Therefore, in this specification, the terms source and drain can be used interchangeably.

In this specification and the like, when “X and Y are connected” is described, X and Y are electrically connected, and X and Y are functionally connected. The case where they are connected and the case where X and Y are directly connected are disclosed in this specification and the like. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or text, and anything other than the connection relation shown in the figure or text is also described in the figure or text.

In this specification and the like, the term “electrically connected” includes a case where the terminals are connected via an element having some electrical action. Here, the “thing having some electric action” is not particularly limited as long as it can exchange electric signals between connection targets. Therefore, even in the case of being expressed as “electrically connected”, in an actual circuit, there is a case where there is no physical connection portion and the wiring is merely extended.

Note that the channel length refers to, for example, a region where a semiconductor (or a portion where current flows in the semiconductor when the transistor is on) and a gate electrode overlap with each other in a top view of the transistor, or a region where a channel is formed (Also referred to as “channel formation region”) refers to the distance between the source (source region or source electrode) and the drain (drain region or drain electrode). Note that in one transistor, the channel length is not necessarily the same in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

The channel width is, for example, a region in which a semiconductor (or a portion in which a current flows in the semiconductor when the transistor is on) and a gate electrode overlap each other, or a source and a drain in a region where a channel is formed. This is the length of the part. Note that in one transistor, the channel width is not necessarily the same in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in this specification, the channel width is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

Note that depending on the structure of the transistor, the channel width in a region where a channel is actually formed (also referred to as “effective channel width”) and the channel width (“apparent channel width” shown in the top view of the transistor) May also be different. For example, when the gate electrode covers the side surface of the semiconductor layer, the effective channel width may be larger than the apparent channel width, and the influence may not be negligible. For example, in a fine transistor whose gate electrode covers a side surface of a semiconductor, the ratio of a channel region formed on the side surface of the semiconductor may increase. In that case, the effective channel width becomes larger than the apparent channel width.

In such a case, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, it is difficult to accurately measure the effective channel width when the shape of the semiconductor is not accurately known.

Therefore, in this specification, the apparent channel width may be referred to as “surrounded channel width (SCW)”. In this specification, in the case where the term “channel width” is simply used, it may denote an enclosed channel width or an apparent channel width. Alternatively, in this specification, in the case where the term “channel width” is simply used, it may denote an effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, enclosed channel width, and the like can be determined by analyzing a cross-sectional TEM image or the like.

Note that in the case where the field-effect mobility of a transistor, the current value per channel width, and the like are calculated and calculated, the calculation may be performed using the enclosed channel width. In that case, the value may be different from that calculated using the effective channel width.

Note that the impurity of the semiconductor means, for example, a component other than the main component constituting the semiconductor. For example, an element having a concentration of less than 0.1 atomic% can be said to be an impurity. When impurities are included, for example, DOS (Density of State) of the semiconductor may increase, carrier mobility may decrease, and crystallinity may decrease. In the case where the semiconductor is an oxide semiconductor, examples of the impurity that changes the characteristics of the semiconductor include a Group 1 element, a Group 2 element, a Group 13 element, a Group 14 element, a Group 15 element, and an oxide semiconductor. There are transition metals other than the main components of, for example, hydrogen (also included in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen and the like. In the case of an oxide semiconductor, oxygen vacancies may be formed by mixing impurities such as hydrogen, for example. In the case where the semiconductor is silicon, examples of impurities that change the characteristics of the semiconductor include group 1 elements, group 2 elements, group 13 elements, and group 15 elements excluding oxygen and hydrogen.

Further, in this specification and the like, “parallel” means a state in which two straight lines are arranged at an angle of −10 ° to 10 °. Therefore, the case of −5 ° to 5 ° is also included. Further, “substantially parallel” means a state in which two straight lines are arranged at an angle of −30 ° to 30 °. “Vertical” and “orthogonal” mean a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included. Further, “substantially vertical” means a state in which two straight lines are arranged at an angle of 60 ° to 120 °.

In addition, in this specification, etc., the terms “same”, “same”, “equal”, “uniform” (including these synonyms), etc. with respect to the count value and the measured value, unless otherwise specified. And an error of plus or minus 20%.

In this specification and the like, in the case where an etching step is performed after a photolithography step, the resist mask formed in the photolithography step is removed after the etching step is finished unless otherwise specified.

In this specification and the like, the high power supply potential VDD (hereinafter, also simply referred to as “VDD” or “H potential”) indicates a power supply potential higher than the low power supply potential VSS. The low power supply potential VSS (hereinafter also simply referred to as “VSS” or “L potential”) indicates a power supply potential lower than the high power supply potential VDD. Alternatively, the ground potential can be used as VDD or VSS. For example, when VDD is a ground potential, VSS is a potential lower than the ground potential, and when VSS is a ground potential, VDD is a potential higher than the ground potential.

Note that the terms “film” and “layer” can be interchanged with each other depending on the case or circumstances. For example, the term “conductive layer” may be changed to the term “conductive film”. Alternatively, for example, the term “insulating film” may be changed to the term “insulating layer” in some cases.

In this specification, when a crystal is trigonal or rhombohedral, it is represented as a hexagonal system.

(Embodiment 1)
In this embodiment, a structural example of the liquid crystal display device 100 of one embodiment of the present invention will be described with reference to drawings.

The liquid crystal display device 100 includes a liquid crystal panel 110 to which an FPC 111 (Flexible Printed Circuit) is connected, and a backlight unit 120. FIG. 1A is a perspective view of the liquid crystal display device 100. FIG. 1B is a perspective view showing a state where the liquid crystal display device 100 is separated into a liquid crystal panel 110 and a backlight unit 120. 1A and 1B are provided with arrows indicating the X-axis direction, the Y-axis direction, and the Z-axis direction. The X axis direction, the Y axis direction, and the Z axis direction are directions orthogonal to each other.

The liquid crystal panel 110 includes a display area 141, a circuit 142, and a circuit 143. The display area 141 includes a plurality of pixels 114 (not shown in FIG. 1). The circuit 142 and the circuit 143 are composed of a plurality of transistors. The circuit 142 and the circuit 143 have a function of determining which pixel 114 in the display region 141 is supplied with the signal supplied through the FPC 111.

For example, when the pixels 114 are arranged in a 1920 × 1080 matrix, a display device that can display at a resolution of so-called full high-definition (also referred to as “2K resolution”, “2K1K”, “2K”, or the like) can be realized. it can. For example, when the pixels 114 are arranged in a matrix of 3840 × 2160 (or 4096 × 2160), so-called ultra high vision (“4K resolution”, “4K2K”, “4K”, “4K UHD”, “4K UHDTV”). ”,“ QFHD ”,“ 4K Ultra HD ”, etc.). Further, for example, when the pixels 114 are arranged in a 7680 × 4320 (or 8192 × 4320) matrix, so-called super high vision (“8K resolution”, “8K4K”, “8K”, “8K UHD”, “8K UHDTV”). It is also possible to realize a display device capable of displaying at a resolution of “. By increasing the number of pixels, it is possible to realize a display device capable of displaying at a resolution of 16K or 32K.

The backlight unit 120 includes a light emitting unit 122 and an optical resonance plate 121. The light emitting unit 122 and the optical resonance plate 121 are provided so as to overlap each other. In FIG. 1B, the light emitting unit 122 is provided below the optical resonance plate 121. The liquid crystal panel 110 is disposed on the optical resonance plate 121 side of the backlight unit 120.

FIG. 2A1 is a perspective view of the liquid crystal panel 110 to which the FPC 111 is connected. 2A2 is an enlarged view of the portion 115 in the display region 141. FIG. In the liquid crystal panel 110, a plurality of pixels 114 are arranged in a matrix in the display region 141. The pixel 114 includes a sub-pixel 113R that emits red light, a sub-pixel 113G that emits green light, and a sub-pixel 113B that emits blue light. In addition, the subpixel 113R, the subpixel 113G, and the subpixel 113B of each pixel 114 are arranged in the Y-axis direction. Note that in this specification and the like, when describing any or all subpixels of the liquid crystal panel 110, they are simply referred to as “subpixels 113”.

FIG. 2B1 is a perspective view of the backlight unit 120. FIG. In FIG. 2 (B1), the optical resonance plate 121 and the light emitting portion 122 are shown separately. FIG. 2B2 is an enlarged view of the portion 125 in the optical resonance plate 121. 2B2 illustrates the substrate 126 and the structure 127 among the components of the optical resonance plate 121. FIG. The structure 127 has a convex portion in the cross section in the Y-axis direction. The structure 127 is provided on the substrate 126 so as to extend in the X-axis direction.

Next, the structure and function of the light emitting unit 122 and the optical resonance plate 121 will be described. FIG. 3A is a cross-sectional view of the light-emitting portion 122 and the optical resonance plate 121 corresponding to the portion Y1-Y2 shown in FIG.

<Light emitting part>
The light emitting unit 122 includes a light guide layer 149, a light source 123, and a reflective layer 124. The light source 123 is provided in the light guide layer 149. The reflective layer 124 is provided on one surface side of the light guide layer 149. A part of the light 135 emitted from the light source 123 is emitted in the Z-axis direction from the other surface side of the light guide layer 149. In this specification and the like, a surface from which light is emitted is referred to as an “emission surface”. Further, another part of the light 135 emitted from the light source 123 is reflected by the reflective layer 124 and emitted from the emission surface in the Z-axis direction.

The light guide layer 149 is formed using a material with high visible light transmittance. The light guide layer 149 can be formed using, for example, an inorganic material such as silicon oxide, or an organic material such as polyimide resin or acrylic resin. Further, as the light guide layer 149, a gas such as air, nitrogen, or a rare gas may be used.

The reflective layer 124 is formed using a material with a high visible light reflectance. The reflective layer 124 can be formed using a material containing, for example, silver (Ag), aluminum (Al), or the like.

As the light source 123, a cold cathode tube (CCFL: Cold Cathode Fluorescent Lamp), an LED (Light Emitting Diode), or the like can be used. As the LED, a white LED, a red LED, a green LED, a blue LED, or the like may be used alone or in combination. Further, an organic EL (Electro Luminescence) element, an inorganic EL element, or the like may be used as the light source 123.

Note that the light source 123 may be provided outside the light guide layer 149 as illustrated in the perspective views of FIGS. FIG. 4A illustrates an example in which the light source 123 is provided along one side surface of the light guide layer 149 in the X-axis direction. The light 135 emitted from the light source 123 enters the light guide layer 149 from the side surface, is reflected in the light guide layer 149, and is emitted in the Z-axis direction. FIG. 4B illustrates an example in which the light source 123 is provided along one side surface of the light guide layer 149 in the Y-axis direction. The light source 123 may be provided on both side surfaces in the X-axis direction of the light guide layer 149 or on both side surfaces in the Y-axis direction. In addition, as illustrated in FIG. 4C, the light source 123 may be provided on all side surfaces of the light guide layer 149.

Further, a functional member such as a polarizing plate, a phase difference plate, or a prism sheet may be provided on the light emitting surface side of the light guide layer 149.

<Optical resonance plate>
The optical resonance plate 121 has a structure 127 on a substrate 126 and a semi-transmissive layer 128 on the substrate 126 and the structure 127. In addition, the light guide layer 129 having a flat surface is provided on the semi-transmissive layer 128, and the semi-transmissive layer 131 is provided on the light guide layer 129. In addition, the protective layer 132 is provided over the semi-transmissive layer 131.

As the substrate 126, a light-transmitting substrate can be used. For example, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used. As the substrate 126, for example, a flexible substrate such as a resin may be used.

The structure 127 is formed using a light-transmitting material. The light-transmitting material may be an insulating material, a conductive material, or a semiconductor material. For example, the structure 127 may be formed using an insulating material such as silicon oxide or silicon nitride, or may be formed using a conductive material such as indium tin oxide (ITO) or zinc oxide. . Alternatively, the structure 127 may be formed using a resin material. Alternatively, the structure 127 may be formed by combining these materials.

The semi-transmissive layer 128 and the semi-transmissive layer 131 transmit a certain proportion of incident light and reflect a certain proportion of light. As the semi-transmissive layer 128 and the semi-transmissive layer 131, for example, a material containing silver (Ag) or a material containing aluminum (Al) can be used. The ratio of the transmitted light to the incident light (transmittance) can be determined by the thickness of these materials.

The transflective layer 128 preferably has the same or larger visible light transmittance as the transflective layer 131. Specifically, the visible light transmittance of the semi-transmissive layer 128 is preferably 30% to 80%, and more preferably 20% to 80%. Further, the visible light transmittance of the semi-transmissive layer 131 is preferably 0.1% or more and 30% or less, and more preferably 0.1% or more and 20% or less.

The light guide layer 129 is formed using a material with high visible light transmittance. Specifically, a material having a visible light transmittance of 50% to 100%, preferably 70% to 100% is used. For example, an inorganic material such as silicon oxide or an organic material such as polyimide resin or acrylic resin can be used for the light guide layer 129.

After the formation of the light guide layer 129, the surface of the light guide layer 129 may be planarized. The planarization treatment is not particularly limited, but can be performed by polishing treatment (for example, chemical mechanical polishing (CMP)) or dry etching treatment. In addition, the polishing process can be omitted by forming the light guide layer 129 using an insulating material having a planarization function. As a material having a planarization function, for example, an organic material such as polyimide resin or acrylic resin can be used.

Further, as the light guide layer 129, a gas such as air, nitrogen, or a rare gas may be used. In the case of using gas as the light guide layer 129, the distance between the semi-transmissive layer 131 and the semi-transmissive layer 128 can be kept constant by providing a spacer in a part of the light guide layer 129.

The protective layer 132 may be formed using a material similar to that of the light guide layer 129, for example.

In the optical resonance plate 121, the first resonance region 133 a to the third resonance region 133 c are repeatedly formed by the structure 127. In each of the first resonance region 133a to the third resonance region 133c, the semi-transmissive layer 131 overlaps the semi-transmissive layer 128 via the light guide layer 129 in each region, and the semi-transmissive layer 128 and the semi-transmissive layer 131 are mutually connected. Has parallel surfaces.

In the first resonance region 133a, the light guide layer 129 has a thickness d1. The second resonance region 133b has a light guide layer 129 thickness d2. In the third resonance region 133c, the light guide layer 129 has a thickness d3. d1 to d3 correspond to the distance from the semi-transmissive layer 128 to the semi-transmissive layer 131. The thickness d1 can be determined by the thickness of the light guide layer 129. The thickness d2 and the thickness d3 can be determined by the thickness of the light guide layer 129 and the size of the structure 127.

The light 135 emitted from the light emitting unit 122 is incident on the optical resonance plate 121 and propagates in the structure 127 and the light guide layer 129 along the Z-axis direction. A part of the light 135 that has entered the light guide layer 129 beyond the semi-transmissive layer 128 resonates between the semi-transmissive layer 128 and the semi-transmissive layer 131 and is emitted in the Z-axis direction. The color temperature of the light 135 is preferably 3000 K or more and 12000 K or less.

By setting the thicknesses d1 to d3 to arbitrary values, the wavelength of light emitted in the Z-axis direction can be determined. For example, in order to extract light having a wavelength λ from the light 135 in the first resonance region 133a and emit the light in the Z-axis direction, the product (optical path length) of the thickness d1 and the refractive index n of the light guide layer 129 has a wavelength λ. It may be set so as to be m times 1/2 (m is an integer of 1 or more). Therefore, the thickness d1 can be obtained by Equation 1.

In the present embodiment, the thickness d1 is set so that light 136R having a red wavelength region is emitted from the first resonance region 133a. In addition, the thickness d2 is set so that light 136G having a green wavelength region is emitted from the second resonance region 133b. The thickness d2 can be obtained by replacing d1 in Equation 1 with d2. Further, the thickness d3 is set so that light 136B having a blue wavelength region is emitted from the third resonance region 133c. The thickness d3 can be obtained by replacing d1 in Equation 1 with d3.

A part of the remaining component of the light 135 that has not been emitted from each resonance region propagates in the light guide layer 129 and is emitted from another resonance region. Further, a part of the remaining component of the light 135 is transmitted through the semi-transmissive layer 128 and returned to the light emitting unit 122, reflected in the light emitting unit 122, and incident on the optical resonance plate 121 again.

In this way, by using the optical resonance plate 121 to extract light in a specific wavelength region from the light 135, the light use efficiency is increased as compared with the case where the color filter absorbs light and generates colored light. be able to. Thus, power consumption of the display device can be reduced.

3B, the light 135 may be incident on the optical resonance plate 121 from the protective layer 132 side, and the light 136R, the light 136G, and the light 136B may be emitted from the substrate 126 side. FIG. 3B is a cross-sectional view of the light-emitting portion 122 and the optical resonance plate 121 corresponding to the portion Y1-Y2 illustrated in FIG.

<Method for producing optical resonance plate>
[Production Method Example 1]
Next, an example of a method for manufacturing the optical resonance plate 121 will be described. 5 and 6 are cross-sectional views of the optical resonance plate 121 corresponding to the portion Y1-Y2 of FIG. 2 (B1).

First, a layer 137 for forming the structure 127 is provided over the substrate 126 (see FIG. 5A). Next, a resist mask is formed over the layer 137 by a photolithography method, an inkjet method, or the like, and part of the layer 137 is selectively etched, so that the layer 138 is formed. After the formation of the layer 138, the resist mask is removed (see FIG. 5B).

Next, a resist mask 139 is formed over part of the layer 138 (see FIG. 5C). A part of the layer 138 is selectively removed using the resist mask 139, so that the structure 127 having a convex portion is formed (see FIG. 5D). Thereafter, the resist mask 139 is removed.

Next, the semi-transmissive layer 128 is formed over the substrate 126 and the structure 127 (see FIG. 6A).

Next, a light guide layer 129 having a flat surface is provided over the semi-transmissive layer 128 (see FIG. 6B).

Next, the semi-transmissive layer 131 is provided over the light guide layer 129, and the protective layer 132 is provided over the semi-transmissive layer 131 (see FIG. 6C).

Note that the resist mask may be formed using a halftone mask or a graytone mask.

[Production Method Example 2]
A manufacturing method example of the optical resonance plate 121 different from the manufacturing method example 1 will be described. FIG. 7 is a cross-sectional view of the optical resonance plate 121 corresponding to the portion Y1-Y2 of FIG.

First, a layer 137 for forming the structure 127a is provided over the substrate 126 (see FIG. 7A). Next, a resist mask is formed over the layer 137 by a photolithography method, an inkjet method, or the like, and part of the layer 137 is selectively etched to form the structure 127a. After the structure 127a is formed, the resist mask is removed (see FIG. 7B).

Next, a layer 145 for forming the structure 127b is provided over the structure 127a (see FIG. 7C). It is preferable to increase the selectivity of the layer 145 and the structure 127a by using a material having etching characteristics different from those of the structure 127a for the layer 145. For example, the structure 127a may be formed using a light-transmitting inorganic insulator such as silicon oxide, and the layer 145 may be formed using a light-transmitting metal oxide such as ITO. By using materials with different etching characteristics, the thicknesses of the structure 127a and the layer 145 (structure 127b) can be easily controlled.

Next, a resist mask 139 is formed over part of the layer 145 (see FIG. 7D). A part of the layer 145 is selectively removed using the resist mask 139, so that the structure 127b is formed. The structure 127a and the structure 127b are stacked to form the structure 127 having a convex portion.

Next, the semi-transmissive layer 128 is formed over the substrate 126 and the structure 127 (see FIG. 7E). The subsequent manufacturing steps can be performed in the same manner as in Manufacturing Method Example 1.

The manufacturing method of the optical resonance plate 121 is not limited to the above manufacturing method. For example, it is possible to apply a MEMS (Micro Electro Mechanical Systems) manufacturing method to the manufacturing of the optical resonance plate 121. For example, the structure 127 may be removed after the structure 127 and the semi-transmissive layer 128 are formed by applying a MEMS manufacturing method. By removing the structure 127, light 135 is not absorbed by the structure 127, so that the utilization efficiency of the light 135 can be increased.

<Arrangement of liquid crystal panel and optical resonance plate>
8 to 10 are cross-sectional views of the part M1-M2 illustrated in FIG. The liquid crystal panel 110 includes an element substrate 150 provided with a transistor 156 and a counter substrate 160.

In FIG. 8, an element substrate 150 includes a transistor 156 and an electrode 153 with an insulating layer 152 provided over a substrate 151. The electrode 153 is electrically connected to the transistor 156. An alignment film 154 is formed to cover the electrode 153. The electrode 153 can function as a pixel electrode.

The counter substrate 160 includes a light shielding layer 162 over the substrate 161, an overcoat layer 163 over the light shielding layer 162, an electrode 164 over the overcoat layer 163, and an alignment film 165 over the electrode 164. .

The element substrate 150 and the counter substrate 160 are arranged so that the electrode 153 and the electrode 164 face each other, and overlap with each other with the liquid crystal layer 155 interposed therebetween. In addition, a polarizing plate 171 is provided outside the element substrate 150, and a polarizing plate 172 is provided outside the counter substrate 160. Further, the liquid crystal element 157 is formed by the electrode 153, the alignment film 154, the liquid crystal layer 155, the alignment film 165, and the electrode 164.

The liquid crystal panel 110 and the optical resonance plate 121 (backlight unit 120) are arranged so that the sub-pixel 113R and the first resonance region 133a overlap each other. Similarly, the sub-pixel 113G and the first resonance region 133b are arranged so as to overlap each other. Further, the sub-pixel 113B and the first resonance region 133c are arranged so as to overlap each other.

The light 136 </ b> R emitted from the first resonance region 133 a of the optical resonance plate 121 enters the sub-pixel 113 </ b> R, and is emitted outside from the counter substrate 160 side through the liquid crystal element 157. Similarly, the light 136G emitted from the first resonance region 133b enters the sub-pixel 113G, and is emitted to the outside from the counter substrate 160 side via the liquid crystal element 157. Further, the light 136 </ b> B emitted from the first resonance region 133 c enters the sub-pixel 113 </ b> B, and is emitted to the outside from the counter substrate 160 side through the liquid crystal element 157. The liquid crystal element 157 controls the amount of light transmitted for each sub-pixel.

Further, as illustrated in FIG. 9, a coloring layer may be provided between the substrate 161 and the overcoat layer 163 of the counter substrate 160. In FIG. 9, a colored layer 166R that transmits light in the red wavelength range is provided in the sub-pixel 113R, a colored layer 166G that transmits light in the green wavelength range is provided in the sub-pixel 113G, and a blue wavelength range is provided in the sub-pixel 113B. In this specification and the like, when describing any colored layer or all the colored layers, the colored layer 166B is simply referred to as “colored layer 166”.

By providing the colored layer, the color reproducibility of the liquid crystal display device 100 can be further improved. Further, by providing the colored layer, reflection of external light can be suppressed and the visibility of the liquid crystal display device 100 can be further improved. Further, by providing the colored layer, the contrast ratio can be increased and the display quality of the liquid crystal display device 100 can be further improved.

In addition, as a driving method of a display device (liquid crystal display device) including the liquid crystal element 157, for example, a TN mode, an STN mode, a VA mode, an ASM (Axial Symmetrical Aligned Micro-cell) mode, an OCB (Optically Compensated Birefringence) mode, and the like. FLC (Ferroelectric Liquid Crystal) mode, AFLC (Antiferroelectric Liquid Crystal) mode, MVA mode, PVA (Patterned Vertical Alignment) mode, IPS (In-Place Switching) mode, FFSwitching mode Such as A (Transverse Bend Alignment) mode may be used. In addition to the above-described driving methods, there are ECB (Electrically Controlled Birefringence) mode, PDLC (Polymer Dispersed Liquid Crystal) mode, PNLC (Polymer Network Liquid Crystal mode), and other driving methods for the display device. . However, the present invention is not limited to this, and various liquid crystal elements and driving methods thereof can be used.

Alternatively, the liquid crystal element 157 may be formed using a liquid crystal composition including a liquid crystal exhibiting a blue phase (Blue Phase) and a chiral agent. A liquid crystal display device containing a liquid crystal exhibiting a blue phase has a response speed as short as 1 msec or less and is optically isotropic, so that alignment treatment is unnecessary and viewing angle dependency is small.

When the liquid crystal display device 100 is used in a so-called lateral electric field mode such as an IPS mode or an FFS mode, the electrode 164 on the counter substrate 160 may not be provided.

FIG. 10 is a cross-sectional view when the liquid crystal display device 100 is used in the IPS mode. In FIG. 10, an electrode 167 is formed on the element substrate 150. A common potential (common potential) is supplied to the electrode 167. In FIG. 10, the liquid crystal element 157 includes an electrode 153, an electrode 167, an alignment film 154, a liquid crystal layer 155, and an alignment film 165. In the liquid crystal element 314, the alignment of liquid crystal is controlled by an electric field generated between the electrode 153 and the electrode 167 (an electric field generated in a direction transverse to the substrate surface). FIG. 10 illustrates the case where the counter substrate 160 is not provided with the electrode 164, but the counter substrate 160 may be provided with the electrode 164.

Further, instead of the liquid crystal element 157, a display element using MEMS (Micro Electro Mechanical Systems) may be used. For example, a DMS (Digital Micro Shutter) element may be used.

<Example of Pixel Configuration of Display Device>
Here, an example of a pixel configuration for realizing color display will be described with reference to FIG. As described above, full color display can be realized by configuring the pixel 114 with sub-pixels that emit red, green, and blue light. The light emitted from the sub-pixel may be other than red, green, and blue, and may be yellow, cyan, magenta, and the like, for example.

In addition, as shown in FIG. 11A, one pixel 114 may be provided with four subpixels. For example, in addition to the subpixel 113R, the subpixel 113G, and the subpixel 113B, a subpixel 113Y that emits yellow light may be provided. By increasing the number of sub-pixels included in one pixel 114, color reproducibility can be particularly improved. Therefore, the display quality of the display device can be improved.

Further, a sub-pixel 113W that emits white light may be provided instead of the sub-pixel 113Y. By providing the sub-pixel 113W, the light emission luminance of the display area can be increased. Note that in the case where the subpixel 113W is provided, the semi-transmissive layer 131 in a region overlapping with the subpixel 113W may not be provided.

Note that the occupied area and shape of the subpixels may be the same or different. As shown in FIG. 11B, the area of the sub-pixel 113B that emits blue light may be larger than those of the sub-pixel 113R and the sub-pixel 113G.

Further, as the arrangement method, a method other than the stripe arrangement may be used. For example, a delta array, a Bayer array, a matrix array, or the like can be applied. An example in the case of applying a matrix arrangement is shown in FIG. An example in the case of applying the pen tile arrangement is shown in FIG.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 2)
In this embodiment, circuit configuration examples that can be used for the liquid crystal display device 100 and cross-sectional structure examples of the transistor 156 and the capacitor 158 that can be used for the subpixel 113 will be described.

[Block diagram of liquid crystal display device]
FIG. 12 is a block diagram for explaining the configuration of the liquid crystal display device 100. The liquid crystal display device 100 includes a display area 141, a circuit 142, and a circuit 143. The circuit 142 functions as, for example, a signal line driver circuit. The circuit 143 functions as, for example, a scanning line driver circuit.

Further, the liquid crystal display device 100 is arranged substantially in parallel with each other and m scanning lines 3135 whose potentials are controlled by the circuit 143, and each of the liquid crystal display devices 100 is arranged substantially in parallel, and the circuit 142 supplies the potential. N signal lines 3136 to be controlled. Further, the display area 141 has a plurality of sub-pixels 113 arranged in a matrix of m rows and n columns. Note that m and n are both natural numbers of 2 or more.

In the display region 141, each scanning line 3135 is electrically connected to n subpixels 113 arranged in any row among the subpixels 113. Each signal line 3136 is electrically connected to m subpixels 113 arranged in any column among the subpixels 113.

Further, as illustrated in FIG. 13A, a circuit 143a may be provided at a position facing the circuit 143 with the display region 141 interposed therebetween. Further, as illustrated in FIG. 13B, a circuit 142a may be provided at a position facing the circuit 142 with the display region 141 interposed therebetween. 13A and 13B illustrate an example in which the circuit 143a is connected to the scan line 3135 in the same manner as the circuit 143. However, the present invention is not limited to this. For example, the circuit 143 and the circuit 143a connected to the scanning line 3135 may be changed every several rows. FIG. 13B illustrates an example in which the circuit 142 a is connected to the signal line 3136 similarly to the circuit 142. However, the present invention is not limited to this. For example, the circuit 142 and the circuit 142a connected to the signal line 3136 may be changed every several rows. The circuit 142, the circuit 142a, the circuit 143, and the circuit 143a may have a function other than driving the subpixel 113.

Further, the circuit 142, the circuit 142a, the circuit 143, and the circuit 143a may be referred to as “driving circuits”. The subpixel 113 includes a pixel circuit and a display element. The pixel circuit 3137 is a circuit for driving a display element. The transistor included in the driver circuit can be formed at the same time as the transistor included in the pixel circuit 3137. Alternatively, part or all of the driver circuit may be formed over another substrate and electrically connected to the liquid crystal display device 100. For example, part or all of the driver circuit may be formed using a single crystal substrate and electrically connected to the liquid crystal display device 100.

[Pixel circuit configuration example 1]
FIG. 14A1 illustrates an example of a circuit configuration that can be used for the sub-pixel 113 of the liquid crystal display device 100. A pixel circuit 3137 illustrated in FIG. 14A1 includes a transistor 156 and a capacitor 158. In addition, the pixel circuit 3137 is electrically connected to a liquid crystal element 157 that can function as a display element.

One potential of the pair of electrodes of the liquid crystal element 157 is appropriately set in accordance with the specification of the pixel circuit 3137. The alignment state of the liquid crystal included in the liquid crystal element 157 is set by data written to the node 3436. Note that a common potential (common potential) may be applied to one of the pair of electrodes of the liquid crystal element 157. The other of the pair of electrodes of the liquid crystal element 157 is electrically connected to the node 3436.

In the pixel circuit 3137 in the m-th row and the n-th column, one of the source electrode and the drain electrode of the transistor 156 is electrically connected to the signal line DL_n, and the other is electrically connected to the node 3436. A gate electrode of the transistor 156 is electrically connected to the scan line GL_m. The transistor 156 has a function of controlling writing of a data signal to the node 3436.

One of the pair of electrodes of the capacitor 158 is electrically connected to a wiring to which a specific potential is supplied (hereinafter also referred to as “capacitance line CL”), and the other is electrically connected to a node 3436. . The other of the pair of electrodes of the liquid crystal element 157 is electrically connected to the node 3436. Note that the value of the potential of the capacitor line CL is set as appropriate in accordance with the specifications of the pixel circuit 3137. The capacitor 158 functions as a storage capacitor that stores data written to the node 3436.

Here, an example of operation of the display device including the pixel circuit 3137 in FIG. 14A1 is described. First, the pixel circuit 3137 in each row is sequentially selected by the circuit 143, the transistor 156 is turned on, and a data signal is written to the node 3436.

Next, the data signal written to the node 3436 is held with the transistor 156 turned off. The amount of light transmitted through the liquid crystal element 157 is determined in accordance with the data signal written to the node 3436. By sequentially performing this for each row, an image can be displayed in the display area 141.

In addition, as illustrated in FIG. 14A2, a transistor 156a including a back gate electrode may be used instead of the transistor 156. Note that the back gate electrode will be described in detail in another embodiment.

[Pixel circuit configuration example 2]
A pixel circuit 3137 having a structure different from that of the pixel circuit 3137 illustrated in FIG. 14A1 is described with reference to FIG. FIG. 14C is a top view illustrating a layout example of the pixel circuit 3137 illustrated in FIG. FIG. 14C is a layout example in the case where the liquid crystal element is operated in the IPS mode. FIG. 14C illustrates a layout example in the case where the node 3437 is electrically connected to the capacitor line CL.

A pixel circuit 3137 illustrated in FIG. 14B1 is different from the pixel circuit 3137 illustrated in FIG. 14A1 in that the pixel circuit 3137 includes a liquid crystal element 157a and a liquid crystal element 157b connected in parallel instead of the liquid crystal element 157. Here, different configurations are described, and the above description is used for similar configurations.

In the pixel circuit 3137 illustrated in FIG. 14B1, one electrode of the liquid crystal element 157a is electrically connected to the node 3437, and the other electrode (electrode E1) is electrically connected to the node 3436. In addition, one electrode (electrode E2) of the liquid crystal element 157b is electrically connected to the node 3436, and the other electrode is electrically connected to the node 3437.

In general, in a display device using a liquid crystal element, the polarity of a voltage applied to the liquid crystal element is switched every frame. When the liquid crystal display device 100 is used in the horizontal electric field mode, the movement of the liquid crystal element may vary depending on the polarity of the voltage applied to the liquid crystal element. In addition, a flicker phenomenon that is one of display defects may occur due to the difference. In particular, when the frame rate is slow, the flicker phenomenon is likely to occur, and the display quality is likely to deteriorate.

As shown in FIG. 14B1, the structure in which the liquid crystal element 157a and the liquid crystal element 157b are connected in parallel can cancel the difference and make the flicker phenomenon difficult to occur. Therefore, the display quality of the display device can be improved.

In addition, as illustrated in FIG. 14B2, a transistor 156a including a back gate electrode may be used instead of the transistor 156.

[Cross-sectional structure example 1 of transistor and capacitor]
The subpixel 113 includes, for example, at least one transistor 156 and one capacitor element 158 on the element substrate 150. In addition, the transistor 156 and the capacitor 158 are formed over the insulating layer 152.

FIG. 15A illustrates an example of a cross-sectional structure of part of the element substrate 150 including the transistor 156 and the capacitor 158. A transistor 156 illustrated in FIG. 15A is a channel-etched transistor which is a kind of bottom-gate transistor.

In FIG. 15A, an insulating layer 152 is formed over a substrate 151, and an electrode 201 and an electrode 211 are formed over the insulating layer 152. An insulating layer 202 is formed over the electrode 201 and the electrode 211, and a semiconductor layer 203 is formed over the insulating layer 202. An electrode 204 and an electrode 205 are provided in contact with part of the semiconductor layer 203. Part of the electrode 205 overlaps with the electrode 211 with the insulating layer 202 interposed therebetween, so that the capacitor 158 is formed. An insulating layer 206 is formed so as to cover the electrodes 204 and 205, an insulating layer 207 is formed over the insulating layer 206, and an insulating layer 208 is formed over the insulating layer 207. An electrode 153 is formed over the insulating layer 208. The electrode 153 is electrically connected to the electrode 205 through an opening provided in the insulating layer 208, the insulating layer 207, and the insulating layer 206. An alignment film 154 is formed on the electrode 153.

The electrode 201 can function as a gate electrode. The electrode 204 can function as one of a source electrode and a drain electrode. The electrode 205 can function as the other of the source electrode and the drain electrode. The electrode 211 can function as one electrode of the capacitor 158. In addition, the electrode 205 can function as the other electrode of the capacitor 158.

The electrode 201 and the electrode 211 can be formed through the same manufacturing process. The electrode 204 and the electrode 205 can be formed through the same manufacturing process.

<Board>
There is no particular limitation on the material used for the substrate 151, but it is necessary that the substrate 151 have at least light-transmitting properties and heat resistance to withstand heat treatment. For example, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used.

Note that as the substrate 151, a flexible substrate (flexible substrate), a bonded film, a base film, or the like may be used. Examples of materials such as a flexible substrate, a laminated film, and a base film include polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), polytetrafluoroethylene (PTFE), and polypropylene. Polyester, polyvinyl fluoride, polyvinyl chloride, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, aramid, epoxy resin, acrylic resin, and the like can be used.

The flexible substrate used for the substrate 151 is preferably as the linear expansion coefficient is lower because deformation due to the environment is suppressed. For the flexible substrate used for the substrate 151, for example, a material having a linear expansion coefficient of 1 × 10 ⁻³ / K or less, 5 × 10 ⁻⁵ / K or less, or 1 × 10 ⁻⁵ / K or less may be used. . In particular, since aramid has a low coefficient of linear expansion, it is suitable as a flexible substrate.

<Insulating layer>
The insulating layer 152, the insulating layer 202, the insulating layer 206, the insulating layer 207, and the insulating layer 208 include aluminum nitride, aluminum oxide, aluminum nitride oxide, aluminum oxynitride, magnesium oxide, silicon nitride, silicon oxide, silicon nitride oxide, and oxide A material selected from silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, aluminum silicate, or the like is used as a single layer or a stacked layer. Alternatively, a material obtained by mixing a plurality of materials among oxide materials, nitride materials, oxynitride materials, and nitride oxide materials may be used.

Note that in this specification, a nitrided oxide refers to a compound having a higher nitrogen content than oxygen. Further, oxynitride refers to a compound having a higher oxygen content than nitrogen. In addition, content of each element can be measured using Rutherford backscattering method (RBS: Rutherford Backscattering Spectrometry) etc., for example.

In particular, the insulating layer 152 and the insulating layer 207 are preferably formed using an insulating material which does not easily transmit impurities. For example, an insulating material including boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium or tantalum, in a single layer, or What is necessary is just to use it by lamination | stacking. For example, as an insulating material that hardly permeates impurities, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, Examples thereof include silicon nitride. Alternatively, the insulating layer 152 or the insulating layer 207 may be formed using indium tin zinc oxide (In—Sn—Zn oxide) with high insulating properties or the like.

By using an insulating material that does not easily transmit impurities for the insulating layer 152, diffusion of impurities from the substrate 151 side can be suppressed and the reliability of the transistor can be improved. By using an insulating material that does not easily transmit impurities for the insulating layer 207, diffusion of impurities from the insulating layer 208 side can be suppressed and the reliability of the transistor can be improved.

As the insulating layer 152, the insulating layer 202, the insulating layer 206, the insulating layer 207, and the insulating layer 208, a plurality of insulating layers formed using these materials may be stacked. The formation method of the insulating layer 152, the insulating layer 202, the insulating layer 206, the insulating layer 207, and the insulating layer 208 is not particularly limited, and a sputtering method, a CVD (Chemical Vapor Deposition) method, an MBE (Molecular Beam Epitaxy) method, or a PLD (PLD) method is used. Various forming methods such as a pulsed laser deposition (ALD) method, an ALD (Atomic Layer Deposition) method, and a spin coating method can be used.

For example, when an aluminum oxide film is formed using a thermal CVD method, two types of gases, a source gas obtained by vaporizing a liquid (TMA or the like) containing a solvent and an aluminum precursor compound, and H ₂ O as an oxidizing agent are used. Use gas. Note that the chemical formula of trimethylaluminum is Al (CH ₃ ) ₃ . Other material liquids include tris (dimethylamido) aluminum, triisobutylaluminum, aluminum tris (2,2,6,6-tetramethyl-3,5-heptanedionate) and the like.

In the case where an oxide semiconductor is used for the semiconductor layer 203, it is preferable to reduce the hydrogen concentration in the insulating layer in order to prevent an increase in the hydrogen concentration in the semiconductor layer 203. In particular, the hydrogen concentration in the insulating layer 202 and the insulating layer 206 in contact with the semiconductor layer 203 is preferably reduced. Specifically, the hydrogen concentration in the insulating layer is 2 × 10 ²⁰ atoms / cm ³ or less, preferably 5 × 10 ¹⁹ atoms / cm ³ or less, more preferably 1 × 10 ¹⁹ atoms / cm ³ or less in SIMS. More preferably, it is 5 × 10 ¹⁸ atoms / cm ³ or less. In order to prevent an increase in the nitrogen concentration in the semiconductor layer 203, it is preferable to reduce the nitrogen concentration in the insulating layer. In particular, the nitrogen concentration in the insulating layer 202 and the insulating layer 206 in contact with the semiconductor layer 203 is preferably reduced. Specifically, the nitrogen concentration in the insulating layer is less than 5 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less in SIMS. More preferably, it is 5 × 10 ¹⁷ atoms / cm ³ or less.

Note that the concentration measured by SIMS analysis may include a variation of plus or minus 40%.

In the case where an oxide semiconductor is used for the semiconductor layer 203, the insulating layer is preferably formed using an insulating layer from which oxygen is released by heating (also referred to as an “insulating layer containing excess oxygen”). In particular, the insulating layer 202 and the insulating layer 206 in contact with the semiconductor layer 203 are preferably insulating layers containing excess oxygen. For example, in TDS analysis performed by heat treatment at a surface temperature of the insulating layer of 100 ° C. to 700 ° C., preferably 100 ° C. to 500 ° C., the amount of released oxygen converted to oxygen atoms is 1.0 × 10 ^An insulating layer that is ¹⁸ atoms / cm ³ or more, or 3.0 × 10 ²⁰ atoms / cm ³ or more is preferable.

The insulating layer containing excess oxygen can also be formed by performing treatment for adding oxygen to the insulating layer. The treatment for adding oxygen can be performed using heat treatment in an oxygen atmosphere, an ion implantation apparatus, an ion doping apparatus, or a plasma treatment apparatus. As a gas for adding oxygen, oxygen gas such as ¹⁶ O ₂ or ¹⁸ O ₂ , nitrous oxide gas, ozone gas, or the like can be used. Note that in this specification, treatment for adding oxygen is also referred to as “oxygen doping treatment”.

Further, by forming the insulating layer by a sputtering method in an atmosphere containing oxygen, oxygen can be introduced into the formation layer.

In general, the capacitive element has a configuration in which a dielectric is sandwiched between two opposing electrodes. The thinner the dielectric (the shorter the distance between the two opposing electrodes), the more the dielectric As the dielectric constant increases, the capacitance value increases. However, if the dielectric is thinned in order to increase the capacitance value of the capacitor, the current that flows unintentionally between the two electrodes (hereinafter also referred to as “leakage current”) increases due to the tunnel effect or the like. In addition, the withstand voltage of the capacitive element is likely to decrease.

A portion where the gate electrode, the gate insulating layer, and the semiconductor layer of the transistor overlap functions as a capacitor (hereinafter also referred to as “gate capacitor”). Note that a channel is formed in the semiconductor layer in a region overlapping with the gate electrode with the gate insulating layer interposed therebetween. That is, the gate electrode and the channel formation region function as two electrodes of the capacitor. In addition, the gate insulating layer functions as a dielectric of the capacitor. Although it is preferable that the capacitance value of the gate capacitance is large, if the gate insulating layer is thinned in order to increase the capacitance value, problems such as an increase in leakage current and a decrease in dielectric strength are likely to occur.

Therefore, as the insulating layer 202, hafnium silicate (HfSi _x O _y (x> 0, y> 0)), hafnium silicate added with nitrogen (HfSi _x O _y N _z (x> 0, y> 0, z>) 0)), high-k materials such as hafnium aluminate to which nitrogen is added (HfAl _x O _y N _z (x> 0, y> 0, z> 0)), hafnium oxide, or yttrium oxide, Even if the insulating layer 202 is made thick, a sufficient capacitance value between the insulating layer 202 and the semiconductor layer 203 can be secured.

For example, when a high-k material having a high dielectric constant is used for the insulating layer 202, a capacitance value equivalent to that obtained when silicon oxide is used for the insulating layer 202 can be realized even when the insulating layer 202 is thick. Leakage current generated between the semiconductor layers 203 can be reduced. In addition, leakage current generated between a wiring formed using the same layer as the electrode 201 and another wiring overlapping with the wiring through the insulating layer 202 can be reduced. Note that the insulating layer 202 may have a stacked structure of a high-k material and another insulating material.

The insulating layer 208 is an insulating layer having a flat surface. As the insulating layer 208, in addition to the insulating material, a heat-resistant organic material such as polyimide, acrylic resin, benzocyclobutene resin, polyamide, or epoxy resin can be used. In addition to the organic material, a low dielectric constant material (low-k material), a siloxane resin, PSG (phosphorus glass), BPSG (phosphorus boron glass), or the like can be used. Note that a plurality of insulating layers formed using these materials may be stacked.

Note that the siloxane-based resin corresponds to a resin including a Si—O—Si bond formed using a siloxane-based material as a starting material. Siloxane resins may use organic groups (for example, alkyl groups and aryl groups) and fluoro groups as substituents. The organic group may have a fluoro group.

The formation method of the insulating layer 208 is not particularly limited, and depending on the material, a sputtering method, an SOG method, spin coating, dipping, spray coating, a droplet discharge method (such as an ink jet method), or a printing method (screen printing or offset). Etc.) may be used.

In addition, a CMP process may be performed on the sample surface. By performing the CMP treatment, unevenness on the surface of the sample can be reduced, and the coverage of the insulating layer and the conductive layer to be formed thereafter can be improved.

<Semiconductor layer>
As the semiconductor layer 203, a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used. As the semiconductor material, for example, silicon or germanium can be used. Alternatively, a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, an oxide semiconductor, or a nitride semiconductor, an organic semiconductor, or the like can be used.

In the case where an organic semiconductor is used for the semiconductor layer 203, a low-molecular organic material having an aromatic ring, a π-electron conjugated conductive polymer, or the like can be used. For example, rubrene, tetracene, pentacene, perylene diimide, tetracyanoquinodimethane, polythiophene, polyacetylene, polyparaphenylene vinylene, and the like can be used.

In addition, since the band gap of the oxide semiconductor is 2 eV or more, when an oxide semiconductor is used for the semiconductor layer 203, a transistor with extremely low off-state current can be realized. Specifically, the off-current per channel width of 1 μm can be less than 1 × 10 ⁻²⁰ A, less than 1 × 10 ⁻²² A, or less than 1 × 10 ⁻²⁴ A at room temperature. Thus, a transistor with low power consumption can be provided. In addition, a display device or a semiconductor device with low power consumption can be provided.

In addition, a transistor using an oxide semiconductor layer for a semiconductor layer in which a channel is formed (also referred to as an “OS transistor”) has high withstand voltage between a source and a drain. Thus, a highly reliable transistor can be provided. In addition, a display device or a semiconductor device with high reliability can be provided.

In this embodiment, the case where an oxide semiconductor is used for the semiconductor layer 203 is described. As the oxide semiconductor used for the semiconductor layer 203, for example, an oxide semiconductor containing indium (In) is preferably used. For example, when the oxide semiconductor contains indium, the carrier mobility (electron mobility) increases. The oxide semiconductor preferably contains the element M.

The element M is preferably aluminum, gallium, yttrium or tin. Other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, the element M may be a combination of a plurality of the aforementioned elements. The element M is an element having a high binding energy with oxygen, for example. The element M is an element having a function of increasing the energy gap of the oxide semiconductor, for example. The oxide semiconductor preferably contains zinc. An oxide semiconductor may be easily crystallized when it contains zinc.

Note that the oxide semiconductor used for the semiconductor layer 203 is not limited to an oxide containing indium. The oxide semiconductor may be an oxide containing zinc, an oxide containing zinc, an oxide semiconductor containing tin, or the like, which does not contain indium, such as zinc tin oxide, gallium tin oxide, and gallium oxide. Absent.

As the oxide semiconductor used for the semiconductor layer 203, for example, an oxide semiconductor with a wide energy gap is used. The energy gap of the oxide semiconductor used for the semiconductor layer 203 is, for example, 2.5 eV to 4.2 eV, preferably 2.8 eV to 3.8 eV, and more preferably 3 eV to 3.5 eV.

An oxide semiconductor includes a sputtering method, a CVD (Chemical Vapor Deposition) method (including a MOCVD (Metal Organic Chemical Deposition) method, an ALD (Atomic Layer Deposition) method, a thermal CVD method, and a PECVD (Dephemation Method). However, the film formation may be performed using an MBE (Molecular Beam Epitaxy) method or a PLD (Pulsed Laser Deposition) method. In the plasma CVD method, a high-quality film can be obtained at a relatively low temperature. When a film formation method that does not use plasma at the time of film formation, such as an MOCVD method, an ALD method, or a thermal CVD method, a film on which a surface is formed is hardly damaged and a film with few defects is obtained.

The CVD method and the ALD method are film forming methods in which a film is formed by a reaction on the surface of an object to be processed, unlike a film forming method in which particles emitted from a target or the like are deposited. Therefore, it is a film forming method that is not easily affected by the shape of the object to be processed and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, and thus is suitable for covering the surface of an opening having a high aspect ratio. However, since the ALD method has a relatively low film formation rate, it may be preferable to use it in combination with another film formation method such as a CVD method with a high film formation rate.

In the CVD method and the ALD method, the composition of the obtained film can be controlled by the flow rate ratio of the source gases. For example, in the CVD method and the ALD method, a film having an arbitrary composition can be formed depending on the flow rate ratio of the source gases. Further, for example, in the CVD method and the ALD method, a film whose composition is continuously changed can be formed by changing the flow rate ratio of the source gas while forming the film. When film formation is performed while changing the flow rate ratio of the source gas, the time required for film formation can be shortened by the time required for conveyance and pressure adjustment compared to the case where film formation is performed using a plurality of film formation chambers. it can. Therefore, the productivity of transistors and semiconductor devices may be improved.

For example, when an InGaZnO _x (X> 0) film is formed as the semiconductor layer 203 by a thermal CVD method, trimethylindium (In (CH ₃ ) ₃ ), trimethylgallium (Ga (CH ₃ ) ₃ ), and Dimethyl zinc (Zn (CH ₃ ) ₂ ) is used. The invention is not limited to these combinations, triethyl gallium instead of trimethylgallium _{(Ga (C 2 H 5)} 3) can also be used, diethylzinc in place of dimethylzinc _{(Zn (C 2 H 5)} 2) Can also be used.

For example, when an InGaZnO _x (X> 0) film is formed as the semiconductor layer 203 by the ALD method, an InO ₂ layer is formed by sequentially introducing In (CH ₃ ) ₃ gas and O ₃ gas repeatedly. Thereafter, Ga (CH ₃ ) ₃ gas and O ₃ gas are sequentially introduced repeatedly to form a GaO layer, and then Zn (CH ₃ ) ₂ gas and O ₃ gas are successively introduced to form a ZnO layer. . Note that the order of these layers is not limited to this example. Further, a mixed compound layer such as an InGaO ₂ layer, an InZnO ₂ layer, a GaInO layer, a ZnInO layer, or a GaZnO layer may be formed using these gases. Incidentally, O ₃ may be used the H _{2 O} gas was bubbled water with an inert gas such as Ar in place of the gas, but better to use an O ₃ gas containing no H are preferred. Further, In (C ₂ H ₅ ) ₃ gas or tris (acetylacetonato) indium may be used instead of In (CH ₃ ) ₃ gas. Tris (acetylacetonato) indium is also called In (acac) ₃ . Further, Ga (C ₂ H ₅ ) ₃ gas or tris (acetylacetonato) gallium may be used instead of Ga (CH ₃ ) ₃ gas. Tris (acetylacetonato) gallium is also called Ga (acac) ₃ . Further, Zn (CH ₃ ) ₂ gas or zinc acetate may be used. It is not limited to these gas types.

In the case where the oxide semiconductor layer is formed by a sputtering method, a target containing indium is preferably used to reduce the number of particles. Further, when an oxide target having a high atomic ratio of the element M is used, the conductivity of the target may be lowered. When an oxide target with a high atomic ratio of indium is used, the conductivity of the target can be increased and DC discharge and AC discharge can be easily performed, so that it is easy to deal with a large-area substrate. Therefore, the productivity of the semiconductor device can be increased.

In the case where the oxide semiconductor layer is formed by a sputtering method, the target atomic ratio is such that In: M: Zn is 3: 1: 1, 3: 1: 2, 3: 1: 4, or 1: 1. It may be 0.5, 1: 1: 1, 1: 1: 2, 1: 4: 4, 4: 2: 4.1, or the like.

Note that when the oxide semiconductor layer is formed by a sputtering method, an oxide semiconductor layer having an atomic ratio that deviates from the atomic ratio of the target may be formed. In particular, in the case of zinc, the atomic number ratio of the formed film may be smaller than the atomic ratio of the target. Specifically, the atomic ratio of zinc contained in the target may be 40 atomic% or more and 90 atomic% or less.

In addition, in order to impart stable electrical characteristics to the OS transistor, an oxide semiconductor in which the semiconductor layer 203 can be regarded as intrinsic or substantially intrinsic by reducing impurities and oxygen vacancies in the oxide semiconductor layer to achieve high purity intrinsicity. A layer is preferred. In addition, an oxide semiconductor layer in which at least a channel formation region in the semiconductor layer 203 can be regarded as intrinsic or substantially intrinsic is preferably used.

In the case where an oxide semiconductor layer is used for the semiconductor layer 203, it is preferable to use a CAAC-OS (C Axis Crystalline Oxide Semiconductor). Note that the CAAC-OS is described in detail in Embodiment 4.

In addition, in the oxide semiconductor layer used for the semiconductor layer 203, a region that is not a CAAC is preferably less than 20% of the entire oxide semiconductor layer.

The CAAC-OS has a dielectric anisotropy. Specifically, the CAAC-OS has a higher dielectric constant in the c-axis direction than that in the a-axis direction and the b-axis direction. A transistor in which a CAAC-OS is used for a semiconductor layer in which a channel is formed and a gate electrode is arranged in the c-axis direction has a large dielectric constant in the c-axis direction, so that an electric field generated from the gate electrode easily reaches the entire CAAC-OS. . Therefore, the subthreshold swing value (S value) can be reduced. Further, in a transistor in which a CAAC-OS is used for a semiconductor layer, an increase in S value due to miniaturization hardly occurs.

In addition, since the CAAC-OS has a small dielectric constant in the a-axis direction and the b-axis direction, the influence of an electric field generated between the source and the drain is reduced. Therefore, a channel length modulation effect, a short channel effect, and the like are hardly generated, and the reliability of the transistor can be improved.

Here, the channel length modulation effect refers to a phenomenon in which when the drain voltage is higher than the threshold voltage, the depletion layer spreads from the drain side, and the effective channel length is shortened. The short channel effect refers to a phenomenon in which deterioration of electrical characteristics such as a decrease in threshold voltage occurs due to a short channel length. The finer the transistor, the easier it is for electrical characteristics to deteriorate due to these phenomena.

After the formation of the oxide semiconductor layer, oxygen doping treatment may be performed. Further, heat treatment is preferably performed in order to further reduce impurities such as moisture or hydrogen contained in the oxide semiconductor layer so that the oxide semiconductor layer is highly purified.

For example, the amount of moisture when measured using a dew point meter in an inert gas atmosphere such as nitrogen or a rare gas, an oxidizing gas atmosphere, or ultra-dry air (CRDS (cavity ring down laser spectroscopy) method) under a reduced pressure atmosphere The oxide semiconductor layer is subjected to heat treatment in an atmosphere of 20 ppm (−55 ° C. in terms of dew point) or less, preferably 1 ppm or less, preferably 10 ppb or less. Note that the oxidizing gas atmosphere refers to an atmosphere containing 10 ppm or more of an oxidizing gas such as oxygen, ozone, or oxygen nitride. In addition, the inert gas atmosphere refers to an atmosphere in which the aforementioned oxidizing gas is less than 10 ppm and is filled with nitrogen or a rare gas.

Further, by performing heat treatment, oxygen contained in the insulating layer 202 can be diffused into the oxide semiconductor layer simultaneously with the release of impurities, so that oxygen vacancies contained in the oxide semiconductor layer can be reduced. Note that after heat treatment in an inert gas atmosphere, heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more in order to supplement the desorbed oxygen. Note that heat treatment may be performed at any time after the oxide semiconductor layer is formed.

There is no particular limitation on a heating device used for the heat treatment, and a device for heating an object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element may be used. For example, an RTA (Rapid Thermal Annial) apparatus such as an electric furnace, an LRTA (Lamp Rapid Thermal Anneal) apparatus, or a GRTA (Gas Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus that heats an object to be processed by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp. The GRTA apparatus is an apparatus that performs heat treatment using a high-temperature gas.

The heat treatment may be performed at 250 ° C to 650 ° C, preferably 300 ° C to 500 ° C. The processing time is within 24 hours. Heat treatment for more than 24 hours is not preferable because it causes a decrease in productivity.

<Electrode>
The conductive material for forming the electrode 201, the electrode 211, the electrode 204, and the electrode 205 includes aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, A material containing one or more metal elements selected from manganese, magnesium, zirconium, beryllium and the like can be used. Alternatively, a semiconductor with high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used. A plurality of conductive layers formed using these materials may be stacked.

In addition, as a conductive material for forming the electrode 201, the electrode 211, the electrode 204, and the electrode 205, indium tin oxide (ITO), indium oxide containing tungsten oxide, and indium zinc oxide containing tungsten oxide are used. Oxides, indium oxides containing titanium oxide, indium tin oxides containing titanium oxide, indium zinc oxides, conductive materials containing oxygen such as indium tin oxides added with silicon, nitrogen such as titanium nitride and tantalum nitride A conductive material can also be applied. Alternatively, a stacked structure in which the above-described material containing a metal element and a conductive material containing oxygen are combined can be employed. Alternatively, a stacked structure in which the above-described material containing a metal element and a conductive material containing nitrogen are combined can be used. A stacked structure in which the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen can be combined. The formation method of the conductive material is not particularly limited, and various formation methods such as an evaporation method, a CVD method, and a sputtering method can be used.

The electrode 153 is formed using a light-transmitting conductive material such as ITO or indium zinc oxide. Note that the electrode 164 formed over the counter electrode is also formed using a light-transmitting conductive material, similarly to the electrode 153.

<Alignment film>
The alignment film 154 and the alignment film 165 can be formed using an organic resin such as polyimide or polyvinyl alcohol, and the surface thereof is subjected to an alignment process such as rubbing for aligning liquid crystal molecules in a certain direction. ing. The rubbing can be performed by rotating a roller wrapped with a cloth such as nylon so as to contact the alignment film 154 and rubbing the surface of the alignment film in a certain direction. The rubbing can be performed by rotating a roller wound with a cloth such as nylon so as to contact the alignment film 165 and rubbing the surface of the alignment film in a certain direction. In addition, the alignment film 154 and the alignment film 165 can be formed using a photo-alignment technique or the like without performing rubbing. Note that it is also possible to directly form an alignment film having alignment characteristics by an evaporation method using an inorganic material such as silicon oxide without performing an alignment treatment.

[Cross-sectional structure example 2 of transistor and capacitor]
FIG. 15B shows a cross-sectional structure example different from the cross-sectional structure example 1. A cross-sectional structure example 2 shown in FIG. 15B is different from the cross-sectional structure example 1 in the structure of the capacitor 158. In the cross-sectional structure example 2, the electrode 213 formed through the same process as the semiconductor layer 203 is used as the other electrode of the capacitor 158.

After the electrode 213 is formed through the same process as the semiconductor layer 203, the conductivity is increased by adding an impurity. For example, when an oxide semiconductor is used for the semiconductor layer 203 and the electrode 213, first, part of the insulating layer 206 in a region overlapping with the electrode 213 is removed, so that the surface of the electrode 213 is exposed. Next, an insulating layer containing hydrogen is brought into contact with the surface of the electrode 213 as the insulating layer 207 to diffuse hydrogen into the electrode 213. In this way, the conductivity of the electrode 213 can be increased.

[Example 3 of cross-sectional structure of transistor and capacitor]
FIG. 15C illustrates a cross-sectional structure example different from the cross-sectional structure example 1 and the cross-sectional structure example 2. The cross-sectional structure example 3 illustrated in FIG. 15C is different from the cross-sectional structure example 1 and the cross-sectional structure example 2 in the structure of the transistor 156 and the capacitor 158.

A transistor 156 illustrated in FIG. 15C includes the electrode 209 over the insulating layer 207. The electrode 209 can be formed using a material and a method similar to those of other electrodes. In addition, the electrode 209 can function as a back gate. The back gate will be described in detail later.

Further, in the capacitor 158 illustrated in FIG. 15C, the electrode 211 and the electrode 219 are used without providing the electrode 211. The electrode 213 can be formed in the same manner as the cross-sectional structure example 3. The electrode 219 can be formed through the same process as the electrode 209.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 3)
In this embodiment, a structural example of the liquid crystal panel 110 is described with reference to drawings. The cross-sectional views shown in FIGS. 16A, 16B, 17A, and 17B are cross-sectional views of the portion N1-N2 shown in FIG.

FIG. 16A shows a configuration example in the case of using in a so-called vertical electric field mode such as a TN mode or a VA mode. In FIG. 16A, a sealant 4005 is provided so as to surround the display region 141, the circuit 142, and the circuit 143 (not shown) provided over the substrate 151. The substrate 151, the display region 141, the circuit 142, the circuit 143 (not shown), and the sealant 4005 are sealed with the substrate 161. In FIGS. 2A and 16A, a driver circuit such as the circuit 142 is formed using the transistor 4011 having the same structure as the transistor 156; however, the driver circuit is formed using a single crystal semiconductor or a polycrystalline semiconductor. May be used. Various signals and potentials supplied to the driver circuit and the display area 141 are supplied via the FPC 111.

Note that a connection method of a separately formed drive circuit is not particularly limited, and wire bonding, COG (Chip On Glass), TCP (Tape Carrier Package), COF (Chip On Film), or the like can be used.

The display device illustrated in FIG. 16A includes an electrode 4015, and the electrode 4015 is electrically connected to the FPC 111 through an anisotropic conductive layer 4019. In addition, the electrode 4015 is electrically connected to the wiring 4014 in an opening formed in the insulating layer 208, the insulating layer 207, and the insulating layer 206.

The electrode 4015 is formed using the same conductive layer as the electrode 153, and the wiring 4014 is formed using the same conductive layer as the source electrode and the drain electrode of the transistor 156.

The display region 141 and the peripheral circuit each include a plurality of transistors. FIG. 16A illustrates a transistor 156 included in the display region 141 and a transistor 4011 included in the circuit 142. In FIG. 16A, the insulating layer 208, the insulating layer 207, and the insulating layer 206 are provided over the transistor 156 and the transistor 4011.

The display device illustrated in FIG. 16A includes a capacitor 158. The capacitor 158 includes a region where the electrode 211 overlaps with part of one of the source electrode and the drain electrode of the transistor 156 with the insulating layer 202 interposed therebetween. The electrode 211 is formed using the same conductive layer as the gate electrode of the transistor 156.

The capacitance of the capacitor provided in the display region is set so that charges can be held in a predetermined period in consideration of a leakage current of a transistor arranged in the display region. The capacity of the capacitor may be set in consideration of the off-state current of the transistor.

For example, by using an OS transistor in the pixel portion of the liquid crystal display device, the capacitance of the capacitor can be reduced to 1/3 or less, more preferably 1/5 or less of the liquid crystal capacitance. By using the OS transistor, the formation of the capacitor can be omitted.

The transistor 156 provided in the display region 141 is electrically connected to the display element. FIG. 16A illustrates an example of a liquid crystal display device using a liquid crystal element as a display element. In FIG. 16A, a liquid crystal element 157 which is a display element includes an electrode 153, an electrode 164, and a liquid crystal layer 155. Note that an insulating layer 154 and an insulating layer 165 which function as alignment films are provided so as to sandwich the liquid crystal layer 155. The electrode 164 is provided on the substrate 161 side, and the electrode 153 and the electrode 164 overlap with each other with the liquid crystal layer 155 interposed therebetween.

The spacer 4035 is a columnar spacer obtained by selectively etching the insulating layer, and is provided to control the distance (cell gap) between the electrode 153 and the electrode 164. Note that a spacer 4035 may be a spherical spacer.

In this embodiment mode, a method called multi-domain or multi-domain design in which one subpixel 113 is divided into several regions and the liquid crystal is aligned in different directions can be used. .

The specific resistance of the liquid crystal material is 1 × 10 ⁹ Ω · cm or more, preferably 1 × 10 ¹¹ Ω · cm or more, and more preferably 1 × 10 ¹² Ω · cm or more. In addition, the value of the specific resistance in this specification shall be the value measured at 20 degreeC.

The OS transistor can reduce a current value in an off state (off-state current value). Therefore, when an OS transistor is used as the transistor 156, the holding time of an electric signal such as an image signal can be extended. Therefore, since the frequency of the refresh operation can be reduced, there is an effect of suppressing power consumption.

Further, the liquid crystal panel 110 may be appropriately provided with an optical member (an optical substrate or an optical film) such as a polarizing member, a retardation member, or an antireflection member. For example, a circularly polarizing plate that combines a polarizing substrate and a retardation substrate may be used.

Further, as illustrated in FIG. 16B, a light-blocking layer 162, a coloring layer 166, an overcoat layer 163, and the like may be provided on the substrate 161 side.

Note that the light-blocking layer 162 is preferably provided so as to overlap with the transistor. By providing the light-blocking layer 162 so as to overlap with the transistor, light can be prevented from entering the semiconductor layer of the transistor. Therefore, light deterioration of the semiconductor layer can be prevented and deterioration of electric characteristics of the transistor can be prevented. FIG. 16B illustrates an example in which the light-blocking layer 162 is provided over the transistor 156 and the transistor 4011.

FIG. 17A shows a configuration example in the case of using in a so-called lateral electric field mode. FIG. 17A shows a configuration example when the liquid crystal panel 110 is operated in the FFS mode. In FIG. 17A, an electrode 164 is provided over the insulating layer 208, and a comb-like electrode 153 is provided over the electrode 164 with an insulating layer 159 provided therebetween.

In addition, since the region where the electrode 164 and the electrode 153 overlap functions as a capacitor, the formation of the capacitor 158 can be omitted.

In addition, as illustrated in FIG. 17B, a light-blocking layer 162, a coloring layer 166, an overcoat layer 163, and the like may be provided on the substrate 161 side.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 4)
In this embodiment, the structure of an oxide semiconductor is described.

An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. As the non-single-crystal oxide semiconductor, a CAAC-OS (C Axis Crystalline Oxide Semiconductor), a polycrystalline oxide semiconductor, an nc-OS (Nanocrystalline Semiconductor), a pseudo-amorphous oxide semiconductor (a-liquid oxide OS) like Oxide Semiconductor) and amorphous oxide semiconductor.

From another viewpoint, oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxide semiconductors. Examples of a crystalline oxide semiconductor include a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, and an nc-OS.

As the definition of the amorphous structure, it is generally known that it is not fixed in a metastable state, isotropic and does not have a heterogeneous structure, and the like. Moreover, it can be paraphrased as a structure having a flexible bond angle and short-range order, but not long-range order.

In other words, in the case of an oxide semiconductor that is essentially stable, it cannot be called a complete amorphous oxide semiconductor. In addition, an oxide semiconductor that is not isotropic (eg, has a periodic structure in a minute region) cannot be referred to as a completely amorphous oxide semiconductor. However, although an a-like OS has a periodic structure in a minute region, it has a void (also referred to as a void) and is an unstable structure. Therefore, it can be said that it is close to an amorphous oxide semiconductor in terms of physical properties.

<CAAC-OS>
First, the CAAC-OS will be described.

The CAAC-OS is one of oxide semiconductors having a plurality of c-axis aligned crystal parts (also referred to as pellets).

A plurality of pellets can be confirmed by observing a combined analysis image (also referred to as a high-resolution TEM image) of a CAAC-OS bright field image and a diffraction pattern with a transmission electron microscope (TEM: Transmission Electron Microscope). . On the other hand, in the high-resolution TEM image, the boundary between pellets, that is, the crystal grain boundary (also referred to as grain boundary) cannot be clearly confirmed. Therefore, it can be said that the CAAC-OS does not easily lower the electron mobility due to the crystal grain boundary.

Hereinafter, a CAAC-OS observed with a TEM will be described. FIG. 18A shows a high-resolution TEM image of a cross section of the CAAC-OS which is observed from a direction substantially parallel to the sample surface. For observation of the high-resolution TEM image, a spherical aberration correction function was used. A high-resolution TEM image using the spherical aberration correction function is particularly referred to as a Cs-corrected high-resolution TEM image. Acquisition of a Cs-corrected high-resolution TEM image can be performed by, for example, an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.

FIG. 18B shows a Cs-corrected high-resolution TEM image obtained by enlarging the region (1) in FIG. FIG. 18B shows that metal atoms are arranged in a layered manner in a pellet. The arrangement of each layer of metal atoms reflects unevenness on a surface (also referred to as a formation surface) or an upper surface where a CAAC-OS film is formed, and is parallel to the formation surface or upper surface of the CAAC-OS.

As shown in FIG. 18B, the CAAC-OS has a characteristic atomic arrangement. FIG. 18C shows a characteristic atomic arrangement with auxiliary lines. 18B and 18C, the size of one pellet is 1 nm or more or 3 nm or more, and the size of the gap caused by the inclination between the pellet and the pellet is about 0.8 nm. I know that there is. Therefore, the pellet can also be referred to as a nanocrystal (nc). The CAAC-OS can also be referred to as an oxide semiconductor including CANC (C-Axis aligned nanocrystals).

Here, based on the Cs-corrected high-resolution TEM image, the layout of the CAAC-OS pellets 5100 on the substrate 5120 is schematically shown as a structure in which bricks or blocks are stacked (FIG. 18D). reference.). A portion where an inclination is generated between pellets observed in FIG. 18C corresponds to a region 5161 shown in FIG.

FIG. 19A shows a Cs-corrected high-resolution TEM image of the plane of the CAAC-OS observed from a direction substantially perpendicular to the sample surface. The Cs-corrected high-resolution TEM images obtained by enlarging the region (1), the region (2), and the region (3) in FIG. 19A are shown in FIGS. 19B, 19C, and 19D, respectively. Show. From FIG. 19B, FIG. 19C, and FIG. 19D, it can be confirmed that the pellet has a shape in which metal atoms are arranged in a triangular shape, a quadrangular shape, or a hexagonal shape. However, there is no regularity in the arrangement of metal atoms between different pellets.

Next, the CAAC-OS analyzed by X-ray diffraction (XRD: X-Ray Diffraction) will be described. For example, when structural analysis by an out-of-plane method is performed on a CAAC-OS including an InGaZnO ₄ crystal, a peak appears at a diffraction angle (2θ) of around 31 ° as illustrated in FIG. There is. Since this peak is attributed to the (009) plane of the InGaZnO ₄ crystal, the CAAC-OS crystal has c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the formation surface or the top surface. It can be confirmed.

Note that in structural analysis of the CAAC-OS by an out-of-plane method, in addition to a peak where 2θ is around 31 °, a peak may also appear when 2θ is around 36 °. A peak at 2θ of around 36 ° indicates that a crystal having no c-axis alignment is included in part of the CAAC-OS. In a more preferable CAAC-OS, in the structural analysis by the out-of-plane method, 2θ has a peak in the vicinity of 31 °, and 2θ has no peak in the vicinity of 36 °.

On the other hand, when structural analysis is performed on the CAAC-OS by an in-plane method in which X-rays are incident from a direction substantially perpendicular to the c-axis, a peak appears at 2θ of around 56 °. This peak is attributed to the (110) plane of the InGaZnO ₄ crystal. In the case of the CAAC-OS, even when 2θ is fixed at around 56 ° and analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis), FIG. A clear peak does not appear as shown. On the other hand, in the case of an InGaZnO ₄ single crystal oxide semiconductor, when φ scan is performed with 2θ fixed at around 56 °, it belongs to a crystal plane equivalent to the (110) plane as shown in FIG. 6 peaks are observed. Therefore, structural analysis using XRD can confirm that the CAAC-OS has irregular orientations in the a-axis and the b-axis.

Next, a CAAC-OS analyzed by electron diffraction will be described. For example, when an electron beam with a probe diameter of 300 nm is incident on a CAAC-OS including an InGaZnO ₄ crystal in parallel with a sample surface, a diffraction pattern (a limited-field transmission electron diffraction pattern as illustrated in FIG. 21A) is obtained. Say) may appear. This diffraction pattern includes spots caused by the (009) plane of the InGaZnO ₄ crystal. Therefore, electron diffraction shows that the pellets included in the CAAC-OS have c-axis alignment, and the c-axis is in a direction substantially perpendicular to the formation surface or the top surface. On the other hand, FIG. 21B shows a diffraction pattern obtained when an electron beam with a probe diameter of 300 nm is incident on the same sample in a direction perpendicular to the sample surface. From FIG. 21B, a ring-shaped diffraction pattern is confirmed. Therefore, electron diffraction shows that the a-axis and the b-axis of the pellet included in the CAAC-OS have no orientation. Note that the first ring in FIG. 21B is considered to originate from the (010) plane and the (100) plane of the InGaZnO ₄ crystal. Further, the second ring in FIG. 21B is considered to be caused by the (110) plane or the like.

As described above, the CAAC-OS is an oxide semiconductor with high crystallinity. Since the crystallinity of an oxide semiconductor may be deteriorated by entry of impurities, generation of defects, or the like, in reverse, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

Note that the impurity means an element other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, or a transition metal element. For example, an element such as silicon, which has a stronger bonding force with oxygen than a metal element included in an oxide semiconductor, disturbs the atomic arrangement of the oxide semiconductor by depriving the oxide semiconductor of oxygen, thereby reducing crystallinity. It becomes a factor. In addition, heavy metals such as iron and nickel, argon, carbon dioxide, and the like have large atomic radii (or molecular radii), which disturbs the atomic arrangement of the oxide semiconductor and decreases crystallinity.

In the case where an oxide semiconductor has impurities or defects, characteristics may fluctuate due to light, heat, or the like. For example, an impurity contained in the oxide semiconductor might serve as a carrier trap or a carrier generation source. In addition, oxygen vacancies in the oxide semiconductor may serve as carrier traps or may serve as carrier generation sources by capturing hydrogen.

A CAAC-OS with few impurities and oxygen vacancies is an oxide semiconductor with low carrier density. Specifically, less than 8 × ^{10 11} pieces / cm ^3, preferably 1 × ¹⁰ 11 / cm less than ^3, more preferably 1 × ^{10 10} pieces / cm ³ MatsuMitsuru, 1 × ^{10 -9} cells / cm An oxide semiconductor having a carrier density of ³ or more can be obtained. Such an oxide semiconductor is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. The CAAC-OS has a low impurity concentration and a low density of defect states. That is, it can be said that the oxide semiconductor has stable characteristics.

<Nc-OS>
Next, the nc-OS will be described.

The nc-OS has a region where a crystal part can be confirmed and a region where a clear crystal part cannot be confirmed in a high-resolution TEM image. In many cases, a crystal part included in the nc-OS has a size of 1 nm to 10 nm, or 1 nm to 3 nm. Note that an oxide semiconductor in which the size of a crystal part is greater than 10 nm and less than or equal to 100 nm is sometimes referred to as a microcrystalline oxide semiconductor. For example, the nc-OS may not be able to clearly confirm a crystal grain boundary in a high-resolution TEM image. Note that the nanocrystal may have the same origin as the pellet in the CAAC-OS. Therefore, the crystal part of nc-OS is sometimes referred to as a pellet below.

The nc-OS has periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS has no regularity in crystal orientation between different pellets. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS may not be distinguished from an a-like OS or an amorphous oxide semiconductor depending on an analysis method. For example, when an X-ray having a diameter larger than that of the pellet is used for nc-OS, a peak indicating a crystal plane is not detected in the analysis by the out-of-plane method. Further, when electron diffraction using an electron beam having a probe diameter (for example, 50 nm or more) larger than that of the pellet is performed on the nc-OS, a diffraction pattern such as a halo pattern is observed. On the other hand, spots are observed when nc-OS is subjected to nanobeam electron diffraction using an electron beam with a probe diameter that is close to the pellet size or smaller than the pellet size. Further, when nanobeam electron diffraction is performed on the nc-OS, a region with high luminance may be observed like a circle (in a ring shape). Furthermore, a plurality of spots may be observed in the ring-shaped region.

Thus, since the crystal orientation is not regular between the pellets (nanocrystals), the nc-OS has an oxide semiconductor having RANC (Random Aligned nanocrystals), or NANC (Non-Aligned nanocrystals). It can also be called an oxide semiconductor.

The nc-OS is an oxide semiconductor that has higher regularity than an amorphous oxide semiconductor. Therefore, the nc-OS has a lower density of defect states than an a-like OS or an amorphous oxide semiconductor. Note that the nc-OS does not have regularity in crystal orientation between different pellets. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

<A-like OS>
The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor.

In the a-like OS, a void may be observed in a high-resolution TEM image. Moreover, in a high-resolution TEM image, it has the area | region which can confirm a crystal part clearly, and the area | region which cannot confirm a crystal part.

Since it has a void, the a-like OS has an unstable structure. Hereinafter, in order to show that the a-like OS has an unstable structure as compared with the CAAC-OS and the nc-OS, a change in structure due to electron irradiation is shown.

As samples for electron irradiation, an a-like OS (referred to as sample A), nc-OS (referred to as sample B), and CAAC-OS (referred to as sample C) are prepared. Each sample is an In—Ga—Zn oxide.

First, a high-resolution cross-sectional TEM image of each sample is acquired. It can be seen from the high-resolution cross-sectional TEM image that each sample has a crystal part.

The determination of which part is regarded as one crystal part may be performed as follows. For example, the unit cell of an InGaZnO ₄ crystal has a structure in which three In—O layers and six Ga—Zn—O layers have a total of nine layers stacked in the c-axis direction. Are known. The spacing between these adjacent layers is about the same as the lattice spacing (also referred to as d value) of the (009) plane, and the value is determined to be 0.29 nm from crystal structure analysis. Therefore, a portion where the interval between lattice fringes is 0.28 nm or more and 0.30 nm or less can be regarded as a crystal part of InGaZnO ₄ . Note that the lattice fringes correspond to the ab plane of the InGaZnO ₄ crystal.

FIG. 22 is an example in which the average size of the crystal parts (from 22 to 45) of each sample was examined. However, the length of the lattice fringes described above is the size of the crystal part. From FIG. 22, it can be seen that in the a-like OS, the crystal part becomes larger according to the cumulative dose of electrons. Specifically, as shown by (1) in FIG. 22, the crystal portion (also referred to as initial nucleus) which was about 1.2 nm in the initial stage of observation by TEM has a cumulative irradiation dose of 4.2. It can be seen that the film grows to a size of about 2.6 nm at × 10 ⁸ e ⁻ / nm ² . On the other hand, in the case of nc-OS and CAAC-OS, it is understood that there is little change in the size of the crystal part in the range of the cumulative electron dose from the start of electron irradiation to 4.2 × 10 ⁸ e ⁻ / nm ^2. . Specifically, as indicated by (2) and (3) in FIG. 22, the sizes of the crystal parts of nc-OS and CAAC-OS are about 1.4 nm, respectively, regardless of the cumulative electron dose. And about 2.1 nm.

As described above, in the a-like OS, the crystal part may be grown by electron irradiation. On the other hand, in the nc-OS and the CAAC-OS, the crystal part is hardly grown by electron irradiation. That is, it can be seen that the a-like OS has an unstable structure as compared with the nc-OS and the CAAC-OS.

In addition, since it has a void, the a-like OS has a lower density than the nc-OS and the CAAC-OS. Specifically, the density of the a-like OS is 78.6% or more and less than 92.3% of the density of the single crystal having the same composition. Further, the density of the nc-OS and the density of the CAAC-OS are 92.3% or more and less than 100% of the density of the single crystal having the same composition. An oxide semiconductor that is less than 78% of the density of a single crystal is difficult to form.

For example, in an oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of single crystal InGaZnO ₄ having a rhombohedral structure is 6.357 g / cm ³ . Thus, for example, in an oxide semiconductor that satisfies In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of a-like OS is 5.0 g / cm ³ or more and less than 5.9 g / cm ^3. . For example, in the oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of the nc-OS and the density of the CAAC-OS is 5.9 g / cm ³ or more and 6.3 g / less than cm ³ .

Note that there may be no single crystal having the same composition. In that case, the density corresponding to the single crystal in a desired composition can be estimated by combining single crystals having different compositions at an arbitrary ratio. What is necessary is just to estimate the density corresponding to the single crystal of a desired composition using a weighted average with respect to the ratio which combines the single crystal from which a composition differs. However, the density is preferably estimated by combining as few kinds of single crystals as possible.

As described above, oxide semiconductors have various structures and various properties. Note that the oxide semiconductor may be a stacked film including two or more of an amorphous oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS, for example.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 5)
In this embodiment, an example of a transistor that can be used for the pixel circuit, the driver circuit, or the like described in the above embodiment is described.

The liquid crystal display device 100 of one embodiment of the present invention can be manufactured using various types of transistors such as a bottom-gate transistor and a top-gate transistor. Therefore, the semiconductor layer material and the transistor structure to be used can be easily replaced in accordance with an existing production line.

[Bottom gate type transistor]
FIG. 23A1 is a cross-sectional view of a channel protection transistor 410 which is a kind of bottom-gate transistor. The transistor 410 includes an electrode 246 over a substrate 271 with an insulating layer 272 interposed therebetween. In addition, the semiconductor layer 242 is provided over the electrode 246 with the insulating layer 226 interposed therebetween. The electrode 246 can function as a gate electrode. The insulating layer 226 can function as a gate insulating layer.

In addition, the insulating layer 225 is provided over the channel formation region of the semiconductor layer 242. In addition, the electrode 244 a and the electrode 244 b are provided over the insulating layer 226 in contact with part of the semiconductor layer 242. Part of the electrode 244 a and part of the electrode 244 b are formed over the insulating layer 226.

The insulating layer 225 can function as a channel protective layer. By providing the insulating layer 225 over the channel formation region, exposure of the semiconductor layer 242 that occurs when the electrodes 244a and 244b are formed can be prevented. Therefore, the channel formation region of the semiconductor layer 242 can be prevented from being etched when the electrodes 244a and 244b are formed. According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be realized.

The transistor 410 includes the insulating layer 228 over the electrode 244a, the electrode 244b, and the insulating layer 225, and includes the insulating layer 229 over the insulating layer 228.

Note that a conductive layer such as an electrode, a semiconductor layer, an insulating layer, a substrate, or the like included in the transistor disclosed in this embodiment can be formed using the materials and methods disclosed in the other embodiments. For example, the semiconductor layer 242 can be formed using a material and a method similar to those of the semiconductor layer 203.

Note that in the case where an oxide semiconductor is used for the semiconductor layer 242, a material capable of depriving oxygen from part of the semiconductor layer 242 and generating oxygen vacancies in at least a portion of the electrode 224a and the electrode 224b in contact with the semiconductor layer 242. Is preferably used. In the region where oxygen vacancies occur in the semiconductor layer 242, the carrier concentration increases, and the region becomes n-type and becomes an n-type region (n ⁺ layer). Accordingly, the region can function as a source region or a drain region. As an example of a material capable of depriving oxygen from an oxide semiconductor and causing oxygen vacancies, tungsten, titanium, and the like can be given.

When the source region and the drain region are formed in the semiconductor layer 242, contact resistance between the electrode 224a and the electrode 224b and the semiconductor layer 242 can be reduced. Thus, favorable electric characteristics of the transistor, such as field effect mobility and threshold voltage, can be obtained.

In the case where a semiconductor such as silicon is used for the semiconductor layer 242, a layer functioning as an n-type semiconductor or a p-type semiconductor is preferably provided between the semiconductor layer 242 and the electrode 224a and between the semiconductor layer 242 and the electrode 224b. A layer functioning as an n-type semiconductor or a p-type semiconductor can function as a source region or a drain region of a transistor.

The insulating layer 229 is preferably formed using a material having a function of preventing or reducing impurity diffusion from the outside to the transistor. Note that the insulating layer 229 can be omitted as necessary.

Note that in the case where an oxide semiconductor is used for the semiconductor layer 242, heat treatment may be performed before or after the insulating layer 229 is formed or before or after the insulating layer 229 is formed. By performing the heat treatment, oxygen contained in the insulating layer 229 and other insulating layers can be diffused into the semiconductor layer 242 so that oxygen vacancies in the semiconductor layer 242 can be filled. Alternatively, by forming the insulating layer 229 while heating, oxygen vacancies in the semiconductor layer 242 can be compensated.

In general, the CVD method can be classified into a plasma CVD (PECVD: Plasma Enhanced CVD) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, and the like. Furthermore, it can classify | categorize into the metal CVD (MCVD: Metal CVD) method, the organic metal CVD (MOCVD: Metal Organic CVD) method, etc. by the raw material gas to be used.

In general, the vapor deposition method includes resistance heating vapor deposition method, electron beam vapor deposition method, MBE (Molecular Beam Epitaxy) method, PLD (Pulsed Laser Deposition) method, IAD (Ion beam Assisted Deposition) method, ALD (Atomite Deposition Method). Can be classified.

In the plasma CVD method, a high-quality film can be obtained at a relatively low temperature. In addition, when a film formation method that does not use plasma at the time of film formation, such as an MOCVD method or an evaporation method, a film with less defects and a film with few defects is obtained.

In general, the sputtering method can be classified into a DC sputtering method, a magnetron sputtering method, an RF sputtering method, an ion beam sputtering method, an ECR (Electron Cyclotron Resonance) sputtering method, a counter target sputtering method, and the like.

In the facing target sputtering method, plasma is confined between the targets, so that plasma damage to the substrate can be reduced. Further, depending on the inclination of the target, the incident angle of the sputtered particles to the substrate can be made shallow, so that the step coverage can be improved.

A transistor 411 illustrated in FIG. 23A2 is different from the transistor 410 in that the transistor 411 includes an electrode 223 that can function as a back gate electrode over the insulating layer 229. The electrode 223 can be formed using a material and a method similar to those of the electrode 246.

In general, the back gate electrode is formed using a conductive layer, and the channel formation region of the semiconductor layer is sandwiched between the gate electrode and the back gate electrode. Therefore, the back gate electrode can function in the same manner as the gate electrode. The potential of the back gate electrode may be the same as that of the gate electrode, or may be a ground potential (GND potential) or an arbitrary potential. In addition, the threshold voltage of the transistor can be changed by changing the potential of the back gate electrode independently of the gate electrode.

Both the electrode 246 and the electrode 223 can function as gate electrodes. Thus, each of the insulating layer 226, the insulating layer 225, the insulating layer 228, and the insulating layer 229 can function as a gate insulating layer. Note that the electrode 223 may be provided between the insulating layer 228 and the insulating layer 229.

Note that when one of the electrode 246 and the electrode 223 is referred to as a “gate electrode”, the other is referred to as a “back gate electrode”. For example, in the transistor 411, when the electrode 223 is referred to as a “gate electrode”, the electrode 246 is referred to as a “back gate electrode”. In the case where the electrode 223 is used as a “gate electrode”, the transistor 411 can be regarded as a kind of top-gate transistor. One of the electrode 246 and the electrode 223 may be referred to as a “first gate electrode”, and the other may be referred to as a “second gate electrode”.

By providing the electrode 246 and the electrode 223 with the semiconductor layer 242 interposed therebetween, and further by setting the electrode 246 and the electrode 223 to have the same potential, a region where carriers flow in the semiconductor layer 242 becomes larger in the film thickness direction. The amount of carrier movement increases. As a result, the on-state current of the transistor 411 increases and the field-effect mobility increases.

Therefore, the transistor 411 has a large on-state current with respect to the occupied area. That is, the area occupied by the transistor 411 can be reduced with respect to the required on-state current. According to one embodiment of the present invention, the area occupied by a transistor can be reduced. Thus, according to one embodiment of the present invention, a highly integrated semiconductor device can be realized.

In addition, since the gate electrode and the back gate electrode are formed using conductive layers, they have a function of preventing an electric field generated outside the transistor from acting on a semiconductor layer in which a channel is formed (particularly, an electric field shielding function against static electricity). . Note that the electric field shielding function can be improved by forming the back gate electrode larger than the semiconductor layer and covering the semiconductor layer with the back gate electrode.

In addition, since the electrode 246 and the electrode 223 each have a function of shielding an electric field from the outside, charges such as charged particles generated on the insulating layer 272 side or above the electrode 223 do not affect the channel formation region of the semiconductor layer 242. As a result, deterioration due to a stress test (for example, a gate bias-temperature (GBT) stress test in which a negative charge is applied to the gate) is suppressed. In addition, the phenomenon that the gate voltage (rising voltage) at which the on-current begins to flow can be reduced depending on the magnitude of the drain voltage. Note that this effect occurs when the electrode 246 and the electrode 223 have the same potential or different potentials.

Note that the BT stress test is a kind of accelerated test, and it is possible to evaluate a change in characteristics (aging) of a transistor caused by long-term use in a short time. In particular, the amount of change in the threshold voltage of the transistor before and after the BT stress test is an important index for examining reliability. It can be said that the smaller the threshold voltage fluctuation amount, the higher the reliability of the transistor.

In addition, since the electrode 246 and the electrode 223 are provided and the electrode 246 and the electrode 223 are set to the same potential, the amount of fluctuation in the threshold voltage is reduced. For this reason, variation in electrical characteristics among a plurality of transistors is reduced at the same time.

In addition, a transistor having a back gate electrode also has a smaller threshold voltage variation before and after the + GBT stress test in which a positive charge is applied to the gate than a transistor having no back gate electrode.

In addition, when the back gate electrode is formed using a light-blocking conductive film, light can be prevented from entering the semiconductor layer from the back gate electrode side. Therefore, light deterioration of the semiconductor layer can be prevented, and deterioration of electrical characteristics such as shift of the threshold voltage of the transistor can be prevented.

According to one embodiment of the present invention, a highly reliable transistor can be realized. In addition, a highly reliable semiconductor device can be realized.

FIG. 23B1 is a cross-sectional view of a channel protection transistor 420 which is one of bottom-gate transistors. The transistor 420 has substantially the same structure as the transistor 410 except that the insulating layer 225 covers the semiconductor layer 242.

By providing the insulating layer 229, the semiconductor layer 242 can be prevented from being exposed when the electrode 244a and the electrode 244b are formed. Therefore, the semiconductor layer 242 can be prevented from being thinned when the electrodes 244a and 244b are formed. In addition, the semiconductor layer 242 and the electrode 244a are electrically connected to each other in an opening formed by selectively removing part of the insulating layer 225 which overlaps with the semiconductor layer 242. In addition, the semiconductor layer 242 and the electrode 244b are electrically connected to each other in an opening formed by selectively removing part of the insulating layer 225 which overlaps with the semiconductor layer 242. A region of the insulating layer 225 that overlaps with a channel formation region can function as a channel protective layer.

A transistor 421 illustrated in FIG. 23B2 is different from the transistor 420 in that the transistor 421 includes an electrode 223 that can function as a back gate electrode over the insulating layer 229.

The distance between the electrode 244a and the electrode 246 and the distance between the electrode 244b and the electrode 246 are longer in the transistor 420 and the transistor 421 than in the transistor 410 and the transistor 411. Accordingly, parasitic capacitance generated between the electrode 244a and the electrode 246 can be reduced. In addition, parasitic capacitance generated between the electrode 244b and the electrode 246 can be reduced. According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be realized.

A transistor 425 illustrated in FIG. 23C1 is a channel-etched transistor which is one of bottom-gate transistors. In the transistor 425, the electrode 244a and the electrode 244b are formed in contact with the semiconductor layer 242 without providing the insulating layer 225. For this reason, part of the semiconductor layer 242 exposed when the electrodes 244a and 244b are formed may be etched. On the other hand, since the insulating layer 229 is not provided, the productivity of the transistor can be increased.

A transistor 426 illustrated in FIG. 23C2 is different from the transistor 420 in that the transistor 426 includes an electrode 223 that can function as a back gate electrode over the insulating layer 229.

[Top gate type transistor]
FIG. 24A1 is a cross-sectional view of a transistor 430 which is a kind of top-gate transistor. The transistor 430 includes a semiconductor layer 242 over a substrate 271 with an insulating layer 272 interposed therebetween. An electrode 244 a in contact with part of the semiconductor layer 242 and a part of the semiconductor layer 242 are provided over the semiconductor layer 242 and the insulating layer 272. The semiconductor layer 242, the electrode 244a, and the electrode 244b have the insulating layer 226, and the insulating layer 226 has the electrode 246.

In the transistor 430, since the electrode 246 and the electrode 244a and the electrode 246 and the electrode 244b do not overlap with each other, the parasitic capacitance generated between the electrode 246 and the electrode 244a and the parasitic capacitance generated between the electrode 246 and the electrode 244b are reduced. be able to. In addition, after the electrode 246 is formed, the impurity region can be formed in the semiconductor layer 242 by self-alignment by introducing the impurity 255 into the semiconductor layer 242 using the electrode 246 as a mask (see FIG. FIG. 24 (A3) reference). According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be realized.

Note that the impurity 255 can be introduced using an ion implantation apparatus, an ion doping apparatus, or a plasma treatment apparatus.

As the impurity 255, for example, at least one element of a Group 13 element or a Group 15 element can be used. In the case where an oxide semiconductor is used for the semiconductor layer 242, at least one element of a rare gas, hydrogen, and nitrogen can be used as the impurity 255.

A transistor 431 illustrated in FIG. 24A2 is different from the transistor 430 in that the transistor 431 includes an electrode 223 and an insulating layer 227. The transistor 431 includes the electrode 223 formed over the insulating layer 272 and the insulating layer 227 formed over the electrode 223. The electrode 223 can function as a back gate electrode. Thus, the insulating layer 227 can function as a gate insulating layer. The insulating layer 227 can be formed using a material and a method similar to those of the insulating layer 226.

Like the transistor 411, the transistor 431 is a transistor having a large on-state current with respect to the occupied area. That is, the area occupied by the transistor 431 can be reduced with respect to the required on-state current. According to one embodiment of the present invention, the area occupied by a transistor can be reduced. Thus, according to one embodiment of the present invention, a highly integrated semiconductor device can be realized.

A transistor 440 illustrated in FIG. 24B1 is one of top-gate transistors. The transistor 440 is different from the transistor 430 in that the semiconductor layer 242 is formed after the electrodes 244a and 244b are formed. A transistor 441 illustrated in FIG. 24B2 is different from the transistor 440 in that the electrode 223 and the insulating layer 227 are included. In the transistor 440 and the transistor 441, part of the semiconductor layer 242 is formed over the electrode 244a, and the other part of the semiconductor layer 242 is formed over the electrode 244b.

Like the transistor 411, the transistor 441 is a transistor having a large on-state current with respect to the occupied area. That is, the area occupied by the transistor 441 can be reduced with respect to the required on-state current. According to one embodiment of the present invention, the area occupied by a transistor can be reduced. Thus, according to one embodiment of the present invention, a highly integrated semiconductor device can be realized.

A transistor 442 illustrated in FIG. 25A1 is one of top-gate transistors. The transistor 442 includes an electrode 244a and an electrode 244b over the insulating layer 229. The electrodes 244a and 244b are electrically connected to the semiconductor layer 242 through openings formed in the insulating layers 228 and 229.

A part of the insulating layer 226 that does not overlap with the electrode 246 is removed. In addition, part of the insulating layer 226 included in the transistor 442 extends beyond the end portion of the electrode 246.

By introducing the impurity 255 into the semiconductor layer 242 using the electrode 246 and the insulating layer 226 as a mask, an impurity region can be formed in the semiconductor layer 242 in a self-aligned manner (FIG. 25A3). reference).

At this time, the impurity 255 is not introduced into the region overlapping with the electrode 246 of the semiconductor layer 242, and the impurity 255 is introduced into a region not overlapping with the electrode 246. Further, the impurity concentration of the region where the impurity 255 is introduced through the insulating layer 226 of the semiconductor layer 242 is lower than the region where the impurity 255 is introduced without passing through the insulating layer 226. Therefore, an LDD (Lightly Doped Drain) region is formed in a region adjacent to the electrode 246 in the semiconductor layer 242.

A transistor 443 illustrated in FIG. 25A2 is different from the transistor 442 in that the transistor 443 includes an electrode 223 below the semiconductor layer 242. The electrode 223 overlaps the semiconductor layer 242 with the insulating layer 272 interposed therebetween. The electrode 223 can function as a back gate electrode.

Further, a region which does not overlap with the electrode 246 of the insulating layer 226 may be removed as in the transistor 444 illustrated in FIG. 25B1 and the transistor 445 illustrated in FIG. Further, like the transistor 446 illustrated in FIG. 25C1 and the transistor 447 illustrated in FIG. 25C2, the insulating layer 226 may be left without being removed.

The transistors 444, 445, 446, and 447 also form impurity regions in the semiconductor layer 242 in a self-aligned manner by introducing the impurity 255 into the semiconductor layer 242 using the electrode 246 as a mask after forming the electrode 246. be able to.

According to Ikkuma of the present invention, a transistor with favorable electrical characteristics can be realized. According to one embodiment of the present invention, a highly integrated semiconductor device can be realized.

[S-channel type transistor]
FIG. 26 illustrates an example of a transistor structure using an oxide semiconductor as the semiconductor layer 242. A transistor 450 illustrated in FIG. 26 has a structure in which a semiconductor layer 242b is formed over a semiconductor layer 242a, and an upper surface of the semiconductor layer 242b, a side surface of the semiconductor layer 242b, and a side surface of the semiconductor layer 242a are covered with the semiconductor layer 242c. Have. FIG. 26A is a top view of the transistor 450. FIG. 26B is a cross-sectional view (cross-sectional view in the channel length direction) of the portion indicated by the dashed-dotted line X1-X2 in FIG. FIG. 26C is a cross-sectional view (cross-sectional view in the channel width direction) of the portion indicated by the dashed-dotted line Y1-Y2 in FIG.

In addition, the transistor 450 includes an electrode 243 that functions as a gate electrode. The electrode 243 can be formed using a material and a method similar to those of the electrode 246. In this embodiment mode, the electrode 243 is a stack of two conductive layers.

The semiconductor layer 242a, the semiconductor layer 242b, and the semiconductor layer 242c are formed using a material containing one or both of In and Ga. Typically, an In—Ga oxide (an oxide containing In and Ga), an In—Zn oxide (an oxide containing In and Zn), an In—M—Zn oxide (In, the element M, Zn-containing oxide, wherein the element M is one or more elements selected from Al, Ti, Ga, Y, Zr, La, Ce, Nd, or Hf, and is a metal element having a stronger binding force to oxygen than In There is.)

The semiconductor layer 242a and the semiconductor layer 242c are preferably formed using a material containing one or more of the same metal elements among the metal elements included in the semiconductor layer 242b. When such a material is used, interface states can be hardly generated at the interface between the semiconductor layer 242a and the semiconductor layer 242b and the interface between the semiconductor layer 242c and the semiconductor layer 242b. Thus, carrier scattering and trapping at the interface are unlikely to occur, and the field-effect mobility of the transistor can be improved. In addition, variation in threshold voltage of the transistor can be reduced. Therefore, a semiconductor device having favorable electrical characteristics can be realized.

The thickness of the semiconductor layer 242a and the semiconductor layer 242c is 3 nm to 100 nm, preferably 3 nm to 50 nm. The thickness of the semiconductor layer 242b is 3 nm to 200 nm, preferably 3 nm to 100 nm, more preferably 3 nm to 50 nm.

In addition, when the semiconductor layer 242b is an In-M-Zn oxide and the semiconductor layer 242a and the semiconductor layer 242c are also In-M-Zn oxide, the semiconductor layer 242a and the semiconductor layer 242c are formed as In: M: Zn = x. ₁ : y ₁ : z ₁ [atomic number ratio] and the semiconductor layer 242b is In: M: Zn = x ₂ : y ₂ : z ₂ [atomic number ratio], y ₁ / x ₁ is y ₂ / x ₂ The semiconductor layer 242a, the semiconductor layer 242c, and the semiconductor layer 242b can be selected so as to be larger than those. Preferably, the semiconductor layer 242a, the semiconductor layer 242c, and the semiconductor layer 242b are selected so that y ₁ / x ₁ is 1.5 times or more larger than y ₂ / x ₂ . More preferably, the semiconductor layer 242a, the semiconductor layer 242c, and the semiconductor layer 242b are selected so that y ₁ / x ₁ is twice or more larger than y ₂ / x ₂ . More preferably, the semiconductor layer 242a, the semiconductor layer 242c, and the semiconductor layer 242b are selected so that y ₁ / x ₁ is three times or more larger than y ₂ / x ₂ . It is preferable that y ₁ is x ₁ or more because stable electrical characteristics can be imparted to the transistor. However, when y ₁ is 3 times or more of x ₁ , the field-effect mobility of the transistor is lowered. Therefore, y ₁ is preferably less than 3 times x ₁ . With the above structure of the semiconductor layer 242a and the semiconductor layer 242c, the semiconductor layer 242a and the semiconductor layer 242c can be a layer in which oxygen vacancies are less likely to occur than in the semiconductor layer 242b.

Note that when the semiconductor layer 242a and the semiconductor layer 242c are In-M-Zn oxides, the contents of In and the element M except for Zn and O are preferably less than 50 atomic% for In and 50 atomic% for the element M. More preferably, In is less than 25 atomic%, and the element M is 75 atomic% or more. In addition, when the semiconductor layer 242b is an In-M-Zn oxide, the contents of In and the element M except for Zn and O are preferably greater than or equal to 25 atomic%, more preferably less than 75 atomic%, and more preferably less than 75 atomic%. It is assumed that In is 34 atomic% or more and the element M is less than 66 atomic%.

For example, the semiconductor layer 242a containing In or Ga and the semiconductor layer 242c containing In or Ga include In: Ga: Zn = 1: 3: 2, 1: 3: 4, 1: 3: 6, and 1: 6: 4. Or an In—Ga—Zn oxide formed using a target having an atomic ratio of 1: 9: 6 or an In—Ga formed using a target having an atomic ratio of In: Ga = 1: 9. An oxide, gallium oxide, or the like can be used. The semiconductor layer 242b is formed using an atomic ratio target such as In: Ga: Zn = 3: 1: 2, 1: 1: 1, 5: 5: 6, or 4: 2: 4.1. In—Ga—Zn oxide can be used. Note that the atomic ratios of the semiconductor layer 242a, the semiconductor layer 242b, and the semiconductor layer 242c each include a variation of plus or minus 20% of the above atomic ratio as an error.

In order to impart stable electrical characteristics to the transistor including the semiconductor layer 242b, impurities and oxygen vacancies in the semiconductor layer 242b are reduced to high purity intrinsic, and the semiconductor layer 242b can be regarded as intrinsic or substantially intrinsic. A physical semiconductor layer is preferable. In addition, it is preferable that at least a channel formation region in the semiconductor layer 242b be a semiconductor layer that can be regarded as intrinsic or substantially intrinsic.

Note that an oxide semiconductor layer that can be regarded as substantially intrinsic means that the carrier density in the oxide semiconductor layer is less than 8 × 10 ¹¹ / cm ³ , preferably less than 1 × 10 ¹¹ / cm ³ , and more preferably 1 The oxide semiconductor layer is less than × 10 ¹⁰ pieces / cm ³ and 1 × 10 ⁻⁹ pieces / cm ³ or more.

FIG. 27 illustrates an example of a transistor structure using an oxide semiconductor as the semiconductor layer 242. In the transistor 422 illustrated in FIG. 27, the semiconductor layer 242b is formed over the semiconductor layer 242a. The transistor 422 is a kind of bottom-gate transistor having a back gate electrode. FIG. 27A is a top view of the transistor 422. FIG. FIG. 27B is a cross-sectional view (cross-sectional view in the channel length direction) of the portion indicated by the dashed-dotted line X1-X2 in FIG. FIG. 27C is a cross-sectional view (cross-sectional view in the channel width direction) of the portion indicated by the dashed-dotted line Y1-Y2 in FIG.

The electrode 223 provided over the insulating layer 229 is electrically connected to the electrode 246 through the insulating layer 226, the insulating layer 228, and the openings 247 a and 247 b provided in the insulating layer 229. Therefore, the same potential is supplied to the electrode 223 and the electrode 246. One of the openings 247a and 247b may not be provided. Further, it is not necessary to provide both the opening 247a and the opening 247b. When both the opening 247a and the opening 247b are not provided, different potentials can be supplied to the electrode 223 and the electrode 246.

[Energy band structure of oxide semiconductor]
Here, the functions and effects of the semiconductor layer 242 formed by stacking the semiconductor layer 242a, the semiconductor layer 242b, and the semiconductor layer 242c will be described with reference to energy band structure diagrams shown in FIGS. 31A and 31B. I will explain. FIG. 31A is an energy band structure diagram of the portion indicated by the dashed-dotted line D1-D2 in FIG. FIG. 31A illustrates an energy band structure of a channel formation region of the transistor 450.

In FIG. 31A, Ec382, Ec383a, Ec383b, Ec383c, and Ec386 indicate the energy at the lower end of the conduction band of the insulating layer 272, the semiconductor layer 242a, the semiconductor layer 242b, the semiconductor layer 242c, and the insulating layer 226, respectively.

Here, the difference between the vacuum level and the energy at the bottom of the conduction band (also referred to as “electron affinity”) is defined as the energy gap based on the difference between the vacuum level and the energy at the top of the valence band (also referred to as ionization potential). Subtracted value. The energy gap can be measured using a spectroscopic ellipsometer (for example, HORIBA JOBYVON UT-300). In addition, the energy difference between the vacuum level and the upper end of the valence band can be measured using an ultraviolet photoelectron spectroscopy (UPS) device (for example, Versa Probe of PHI).

Note that an In—Ga—Zn oxide formed using a target with an atomic ratio of In: Ga: Zn = 1: 3: 2 has an energy gap of approximately 3.5 eV and an electron affinity of approximately 4.5 eV. In addition, an In—Ga—Zn oxide formed using a target with an atomic ratio of In: Ga: Zn = 1: 3: 4 has an energy gap of about 3.4 eV and an electron affinity of about 4.5 eV. In addition, an In—Ga—Zn oxide formed using a target with an atomic ratio of In: Ga: Zn = 1: 3: 6 has an energy gap of about 3.3 eV and an electron affinity of about 4.5 eV. In addition, an In—Ga—Zn oxide formed using a target with an atomic ratio of In: Ga: Zn = 1: 6: 2 has an energy gap of about 3.9 eV and an electron affinity of about 4.3 eV. In addition, an In—Ga—Zn oxide formed using a target with an atomic ratio of In: Ga: Zn = 1: 6: 8 has an energy gap of approximately 3.5 eV and an electron affinity of approximately 4.4 eV. In addition, an In—Ga—Zn oxide formed using a target with an atomic ratio of In: Ga: Zn = 1: 6: 10 has an energy gap of about 3.5 eV and an electron affinity of about 4.5 eV. An In—Ga—Zn oxide formed using a target with an atomic ratio of In: Ga: Zn = 1: 1: 1 has an energy gap of about 3.2 eV and an electron affinity of about 4.7 eV. An In—Ga—Zn oxide formed using a target with an atomic ratio of In: Ga: Zn = 3: 1: 2 has an energy gap of approximately 2.8 eV and an electron affinity of approximately 5.0 eV.

Since the insulating layers 272 and 226 are insulators, Ec382 and Ec386 have a higher vacuum level (less electron affinity) than Ec383a, Ec383b, and Ec383c.

Ec383a is closer to the vacuum level than Ec383b. Specifically, Ec383a is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more or 0.15 eV or more, and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less vacuum level than Ec383b. It is preferable that it is close to.

Ec383c is closer to the vacuum level than Ec383b. Specifically, Ec383c is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more or 0.15 eV or more, and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less than Ec383b. It is preferable that it is close to.

In addition, a mixed region is formed in the vicinity of the interface between the semiconductor layer 242a and the semiconductor layer 242b and in the vicinity of the interface between the semiconductor layer 242b and the semiconductor layer 242c, and thus the energy at the lower end of the conduction band changes continuously. That is, there are almost no levels at these interfaces.

Therefore, in the stacked structure having the energy band structure, electrons move mainly in the semiconductor layer 242b. Therefore, even when a level exists at the interface between the semiconductor layer 242a and the insulating layer 224 or the interface between the semiconductor layer 242c and the insulating layer 226, the level hardly affects the movement of electrons. Further, since there are no or almost no levels at the interface between the semiconductor layer 242a and the semiconductor layer 242b and the interface between the semiconductor layer 242c and the semiconductor layer 242b, movement of electrons in the region is not hindered. Therefore, the transistor 134 having the stacked structure of the oxide semiconductor can achieve high field effect mobility.

Note that as shown in FIG. 31A, trap levels 390 due to impurities and defects can be formed in the vicinity of the interface between the semiconductor layer 242a and the insulating layer 272 and in the vicinity of the interface between the semiconductor layer 242c and the insulating layer 226. However, the presence of the semiconductor layer 242a and the semiconductor layer 242c makes it possible to keep the semiconductor layer 242b away from the trap level.

In particular, the transistor 134 illustrated in this embodiment is formed so that the upper surface and the side surface of the semiconductor layer 242b are in contact with the semiconductor layer 242c, and the lower surface of the semiconductor layer 242b is in contact with the semiconductor layer 242a. In this manner, the semiconductor layer 242b is covered with the semiconductor layer 242a and the semiconductor layer 242c, whereby the influence of the trap level can be further reduced.

However, when the energy difference between Ec383a or Ec383c and Ec383b is small, electrons in the semiconductor layer 242b may reach the trap level exceeding the energy difference. When electrons are trapped in the trap level, negative fixed charges are generated at the interface of the insulating layer, and the threshold voltage of the transistor is shifted in the positive direction.

Therefore, when the energy difference between Ec383a, Ec383c, and Ec383b is 0.1 eV or more, preferably 0.15 eV or more, variation in the threshold voltage of the transistor is reduced, and the electrical characteristics of the transistor are good. Therefore, it is preferable.

The band gap of the semiconductor layer 242a and the semiconductor layer 242c is preferably wider than the band gap of the semiconductor layer 242b.

FIG. 31B is an energy band structure diagram of a region indicated by a dashed-dotted line in FIG. 27B. FIG. 31B illustrates an energy band structure of a channel formation region of the transistor 422.

In FIG. 31B, Ec387 indicates the energy at the lower end of the conduction band of the insulating layer 228. When the semiconductor layer 242 includes the semiconductor layer 242a and the semiconductor layer 242b, the productivity of the transistor can be increased. Note that although the semiconductor layer 242c is not provided, the semiconductor layer 242 is easily affected by the trap level 390, but higher field-effect mobility can be achieved than in the case where the semiconductor layer 242 has a single-layer structure.

According to one embodiment of the present invention, a transistor with little variation in electrical characteristics can be realized. Thus, a semiconductor device with little variation in electrical characteristics can be realized. According to one embodiment of the present invention, a highly reliable transistor can be realized. Therefore, a highly reliable semiconductor device can be realized.

An oxide semiconductor has a large energy cap of 3.0 eV or more and a high transmittance with respect to visible light. In a transistor obtained by processing an oxide semiconductor under appropriate conditions, 100 zA (1 × 10 ⁻¹⁹ A) or less or 10 zA under off-state current temperature conditions (for example, 25 ° C.) (1 × 10 ⁻²⁰ A) or less, further 1 zA (1 × 10 ⁻²¹ A) or less. Therefore, a semiconductor device with low power consumption can be provided.

According to one embodiment of the present invention, a transistor with low power consumption can be realized. Thus, a semiconductor device such as a display element or a display device with low power consumption can be realized. Alternatively, a semiconductor device such as a display element or a display device with favorable reliability can be realized.

Returning to the description of the transistor 450 illustrated in FIG. By providing the semiconductor layer 242 b over the convex portion provided in the insulating layer 272, the side surface of the semiconductor layer 242 b can be covered with the electrode 243. In other words, the transistor 450 has a structure in which the semiconductor layer 242b can be electrically surrounded by the electric field of the electrode 243. In this manner, a transistor structure that electrically surrounds a semiconductor layer in which a channel is formed by an electric field of a conductive film is referred to as a surrounded channel (s-channel) structure. A transistor having an s-channel structure is also referred to as an “s-channel transistor” or an “s-channel transistor”.

In the s-channel structure, a channel can be formed in the entire semiconductor layer 242b (bulk). In the s-channel structure, the drain current of the transistor can be increased and a larger on-current can be obtained. Further, the entire region of the channel formation region formed in the semiconductor layer 242b can be depleted by the electric field of the electrode 243. Therefore, in the s-channel structure, the off-state current of the transistor can be further reduced.

Note that by increasing the protruding portion of the insulating layer 272 and decreasing the channel width, the effect of increasing on-state current, the effect of reducing off-state current, and the like by the s-channel structure can be further increased. Further, the exposed semiconductor layer 242a may be removed when the semiconductor layer 242b is formed. In this case, the side surfaces of the semiconductor layer 242a and the semiconductor layer 242b may be aligned.

Further, an electrode 223 may be provided below the semiconductor layer 242 with an insulating layer interposed therebetween as in a transistor 451 shown in FIG. FIG. 28A is a top view of the transistor 451. FIG. FIG. 28B is a cross-sectional view illustrating a portion indicated by the dashed-dotted line X1-X2 in FIG. FIG. 28C is a cross-sectional view illustrating a portion indicated by dashed-dotted line Y1-Y2 in FIG.

29, the insulating layer 275 may be provided over the electrode 243 and the layer 214 may be provided over the insulating layer 275. FIG. 29A is a top view of the transistor 452. FIG. FIG. 29B is a cross-sectional view illustrating a portion indicated by the dashed-dotted line X1-X2 in FIG. FIG. 29C is a cross-sectional view illustrating a portion indicated by dashed-dotted line Y1-Y2 in FIG.

Note that in FIG. 29, the layer 214 is provided over the insulating layer 275; however, the layer 214 may be provided over the insulating layer 228 or the insulating layer 229. When the layer 214 is formed using a light-blocking material, variation in characteristics of the transistor due to light irradiation, reduction in reliability, or the like can be prevented. Note that the above effect can be enhanced by forming the layer 214 at least larger than the semiconductor layer 242b and covering the semiconductor layer 242b with the layer 214. The layer 214 can be formed using an organic material, an inorganic material, or a metal material. In the case where the layer 214 is formed using a conductive material, a voltage may be supplied to the layer 214 or the layer 214 may be in an electrically floating (floating) state.

FIG. 30 illustrates an example of a transistor having an s-channel structure. A transistor 448 illustrated in FIG. 30 has a structure substantially similar to that of the transistor 447 described above. In the transistor 448, the semiconductor layer 242 is formed over the convex portion of the insulating layer 272. The transistor 448 is a kind of top-gate transistor having a back gate electrode. FIG. 30A is a top view of the transistor 448. FIG. 30B is a cross-sectional view illustrating a portion indicated by the dashed-dotted line X1-X2 in FIG. FIG. 30C is a cross-sectional view illustrating a portion indicated by dashed-dotted line Y1-Y2 in FIG.

FIG. 30 illustrates the case where an inorganic semiconductor layer such as silicon is used for the semiconductor layer 242 included in the transistor 448. In FIG. 30, the semiconductor layer 242 includes a semiconductor layer 242i, two semiconductor layers 242t, and two semiconductor layers 242u in a region overlapping with the gate electrode. The semiconductor layer 242i is disposed between the two semiconductor layers 242t. The semiconductor layer 242i and the two semiconductor layers 242t are disposed between the two semiconductor layers 242u.

A channel is formed in the semiconductor layer 242i when the transistor 448 is on. Thus, the semiconductor layer 242i functions as a channel formation region. The semiconductor layer 242t functions as a low concentration impurity region (LDD). In addition, the semiconductor layer 242u functions as a high concentration impurity region. Of the two semiconductor layers 242t, one or both of the semiconductor layers 242t may not be provided. Of the two semiconductor layers 242u, one semiconductor layer 242u functions as a source region, and the other semiconductor layer 242u functions as a drain region.

The electrode 244a provided over the insulating layer 229 is electrically connected to one of the semiconductor layers 242u in the insulating layer 226, the insulating layer 228, and the opening 247c provided in the insulating layer 229. The electrode 244b provided over the insulating layer 229 is electrically connected to the other of the semiconductor layers 242u in the insulating layer 226, the insulating layer 228, and the opening 247d provided in the insulating layer 229.

The electrode 243 provided over the insulating layer 226 is electrically connected to the electrode 223 through the opening 247a and the opening 247b provided in the insulating layer 226 and the insulating layer 272. Therefore, the same potential is supplied to the electrode 246 and the electrode 223. One of the openings 247a and 247b may not be provided. Further, it is not necessary to provide both the opening 247a and the opening 247b. When both the opening 247a and the opening 247b are not provided, different potentials can be supplied to the electrode 223 and the electrode 246.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 6)
In this embodiment, a display module is described as an example of a semiconductor device using the liquid crystal display device 100. A display module 6000 illustrated in FIG. 32 includes a touch sensor 6004, a liquid crystal display device 100, a frame 6009, a printed board 6010, and a battery 6011 connected to the FPC 6003 between an upper cover 6001 and a lower cover 6002. Note that the battery 6011, the touch sensor 6004, and the like may not be provided.

The shapes and dimensions of the upper cover 6001 and the lower cover 6002 can be changed as appropriate in accordance with the sizes of the touch sensor 6004, the liquid crystal display device 100, and the like.

As the touch sensor 6004, a resistive touch sensor or a capacitive touch sensor can be used by being superimposed on the liquid crystal display device 100. It is also possible to add a touch sensor function to the liquid crystal display device 100. For example, it is possible to provide a touch sensor electrode in each pixel of the liquid crystal panel 110 included in the liquid crystal display device 100 and add a capacitive touch panel function. Alternatively, an optical sensor may be provided in each pixel of the liquid crystal panel 110 to add the function of an optical touch sensor.

In addition to the protective function of the liquid crystal display device 100, the frame 6009 has a function as an electromagnetic shield for blocking electromagnetic waves generated from the printed circuit board 6010 side. The frame 6009 may have a function as a heat sink.

The printed board 6010 includes a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal, and the like. The power source for supplying power to the power supply circuit may be a battery 6011 or a commercial power source. Note that the battery 6011 can be omitted when a commercial power source is used as the power source.

Further, a member such as a polarizing plate, a retardation plate, or a prism sheet may be additionally provided in the display module 6000.

Note that this embodiment can be combined with any of the other embodiments and examples in this specification as appropriate.

(Embodiment 7)
In this embodiment, examples of electronic devices using a semiconductor device including a transistor, a display device, and the like disclosed in this specification and the like will be described.

As an electronic device using a semiconductor device according to one embodiment of the present invention, a display device such as a television or a monitor, a lighting device, a desktop or laptop personal computer, a word processor, or a DVD (Digital Versatile Disc) is stored in a recording medium Playback device for playing back still images or moving images, portable CD player, radio, tape recorder, headphone stereo, stereo, table clock, wall clock, cordless telephone cordless handset, transceiver, car phone, mobile phone, personal digital assistant, tablet Type game consoles, portable game machines, fixed game machines such as pachinko machines, calculators, electronic notebooks, electronic books, electronic translators, voice input devices, video cameras, digital still cameras, electric shavers, microwave ovens, etc. Electric cooker, electric Air conditioner such as rinsing machine, electric vacuum cleaner, water heater, electric fan, hair dryer, air conditioner, humidifier, dehumidifier, dishwasher, dish dryer, clothing dryer, futon dryer, electric refrigerator, electric freezer, electricity Examples include freezer refrigerators, DNA storage freezers, flashlights, tools such as chainsaws, medical devices such as smoke detectors and dialysis machines. Further examples include industrial equipment such as guide lights, traffic lights, belt conveyors, elevators, escalators, industrial robots, power storage systems, power storage devices for power leveling and smart grids. In addition, an electric motor using electric power from a secondary battery, a moving body driven by an engine using fuel, and the like may be included in the category of electronic devices. Examples of the moving body include an electric vehicle (EV), a hybrid vehicle (HEV) having both an internal combustion engine and an electric motor, a plug-in hybrid vehicle (PHEV), a tracked vehicle in which these tire wheels are changed to an endless track, and electric assist. Examples include motorbikes including bicycles, motorcycles, electric wheelchairs, golf carts, small or large ships, submarines, helicopters, aircraft, rockets, artificial satellites, space probes, planetary probes, and space ships.

A portable game machine 2900 illustrated in FIG. 33A includes a housing 2901, a housing 2902, a display portion 2903, a display portion 2904, a microphone 2905, a speaker 2906, operation keys 2907, and the like. Note that although the portable game machine illustrated in FIG. 29A includes two display portions 2903 and 2904, the number of display portions is not limited thereto. The display portion 2903 is provided with a touch screen as an input device and can be operated with a stylus 2908 or the like.

An information terminal 2910 illustrated in FIG. 33B includes a display portion 2912, a microphone 2917, a speaker portion 2914, a camera 2913, an external connection portion 2916, an operation button 2915, and the like in a housing 2911. The display portion 2912 includes a display panel using a flexible substrate and a touch screen. The information terminal 2910 can be used as, for example, a smartphone, a mobile phone, a tablet information terminal, a tablet personal computer, an electronic book terminal, or the like.

A laptop personal computer 2920 illustrated in FIG. 33C includes a housing 2921, a display portion 2922, a keyboard 2923, a pointing device 2924, and the like.

A video camera 2940 illustrated in FIG. 33D includes a housing 2941, a housing 2942, a display portion 2944, operation keys 2944, a lens 2945, a connection portion 2946, and the like. The operation keys 2944 and the lens 2945 are provided on the housing 2941, and the display portion 2944 is provided on the housing 2942. The housing 2941 and the housing 2942 are connected to each other by a connection portion 2946. The angle between the housing 2941 and the housing 2942 can be changed by the connection portion 2946. Depending on the angle of the housing 2942 with respect to the housing 2941, the orientation of the image displayed on the display portion 2943 can be changed, and display / non-display of the image can be switched.

FIG. 33E illustrates an example of a bangle information terminal. The information terminal 2950 includes a housing 2951, a display portion 2952, and the like. The display portion 2952 is supported by a housing 2951 having a curved surface. Since the display portion 2952 includes a display panel using a flexible substrate, an information terminal 2950 that is flexible, light, and easy to use can be provided.

FIG. 33F illustrates an example of a wristwatch-type information terminal. The information terminal 2960 includes a housing 2961, a display portion 2962, a band 2963, a buckle 2964, operation buttons 2965, an input / output terminal 2966, and the like. The information terminal 2960 can execute various applications such as mobile phone, e-mail, text browsing and creation, music playback, Internet communication, and computer games.

The display surface of the display portion 2962 is curved, and display can be performed along the curved display surface. The display portion 2962 includes a touch sensor and can be operated by touching the screen with a finger, a stylus, or the like. For example, an application can be started by touching an icon 2967 displayed on the display unit 2962. The operation button 2965 can have various functions such as power on / off operation, wireless communication on / off operation, manner mode execution / cancellation, and power saving mode execution / cancellation in addition to time setting. . For example, the function of the operation button 2965 can be set by an operating system incorporated in the information terminal 2960.

In addition, the information terminal 2960 can execute short-range wireless communication that is a communication standard. For example, it is possible to talk hands-free by communicating with a headset capable of wireless communication. Further, the information terminal 2960 includes an input / output terminal 2966, and can directly exchange data with other information terminals via a connector. Charging can also be performed via the input / output terminal 2966. Note that the charging operation may be performed by wireless power feeding without using the input / output terminal 2966.

FIG. 33G illustrates an electric refrigerator as an example of a household electric appliance. The electric refrigerator 2970 includes a housing 2971, a refrigerator door 2972, a freezer door 2993, a display portion 2974, and the like.

FIG. 33H is an external view illustrating an example of an automobile. The automobile 2980 includes a vehicle body 2981, wheels 2982, a dashboard 2983, lights 2984, and the like.

In the electronic device described in this embodiment, the above-described transistor, the above-described display device, or the like is mounted.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

100 Liquid crystal display device 110 Liquid crystal panel 111 FPC
113 Sub-pixel 114 Pixel 115 Site 120 Backlight unit 121 Optical resonance plate 122 Light emitting portion 123 Light source 124 Reflective layer 125 Site 126 Substrate 127 Structure 128 Semi-transmissive layer 129 Light guide layer 131 Semi-transmissive layer 132 Protective layer 134 Transistor 135 Light 137 Layer 138 Layer 139 Resist mask 141 Display area 142 Circuit 143 Circuit 145 Layer 149 Light guiding layer 150 Element substrate 151 Substrate 152 Insulating layer 153 Electrode 154 Alignment film 155 Liquid crystal layer 156 Transistor 157 Liquid crystal element 158 Capacitance element 159 Insulating layer 160 Counter substrate 161 Substrate 162 Light-shielding layer 163 Overcoat layer 164 Electrode 165 Alignment film 166 Colored layer 167 Electrode 171 Polarizing plate 172 Polarizing plate 201 Electrode 202 Insulating layer 203 Semiconductor layer 204 Electrode 205 Electrode 206 Insulating layer 207 Insulating layer 208 Insulating layer 209 Electrode 211 Electrode 213 Electrode 214 Layer 219 Electrode 223 Electrode 224 Insulating layer 226 Insulating layer 227 Insulating layer 228 Insulating layer 229 Insulating layer 242 Semiconductor layer 243 Electrode 246 Electrode 255 Impurity 271 Substrate 272 Insulating layer 275 Insulating layer 314 Liquid crystal element 382 Ec
386 Ec
387 Ec
390 trap level 410 transistor 411 transistor 420 transistor 421 transistor 422 transistor 425 transistor 430 transistor 431 transistor 440 transistor 441 transistor 442 transistor 443 transistor 444 transistor 445 transistor 446 transistor 447 transistor 448 transistor 450 transistor 451 transistor 452 transistor 2900 portable game machine 2901 Housing 2902 Housing 2903 Display 2904 Display 2905 Microphone 2906 Speaker 2907 Operation key 2908 Stylus 2910 Information terminal 2911 Housing 2912 Display 2913 Camera 2914 Speaker 2915 Button 2916 External connection unit 2917 Microphone 2920 Notebook personal computer 2921 Case 2922 Display unit 2923 Keyboard 2924 Pointing device 2940 Video camera 2941 Case 2294 Case 2944 Display unit 2944 Operation key 2945 Lens 2946 Connection unit 2950 Information terminal 2951 Case 2952 Display unit 2960 Information terminal 2961 Housing 2962 Display unit 2963 Band 2964 Buckle 2965 Operation button 2966 Input / output terminal 2967 Icon 2970 Electric refrigerator 2971 Housing 2972 Refrigeration room door 2972 Freezer compartment door 2974 Display unit 2980 Car 2981 Car body 2982 Wheel 2983 Dashboard 2984 Light 3135 Scanning line 3136 Signal line 3137 Pixel circuit 3436 No 3437 node 4005 sealant 4010 4011 transistors 4014 wiring 4015 electrodes 4019 anisotropic conductive layer 4032 insulating layer 4033 insulating layer 4035 spacer 5100 pellets 5120 substrate 5161 area 6000 display module 6001 top cover 6002 lower cover 6003 FPC
6004 Touch sensor 6009 Frame 6010 Printed circuit board 6011 Battery 113B Subpixel 113G Subpixel 113R Subpixel 113Y Subpixel 127a Structure 127b Structure 133a Resonance area 133b Resonance area 133c Resonance area 136B Light 136G Light 136R Light 142a Circuit 143a Circuit 156a Transistor 157 Liquid crystal element 157b Liquid crystal element 166B Colored layer 166G Colored layer 166R Colored layer 224a Electrode 224b Electrode 242a Semiconductor layer 242b Semiconductor layer 242c Semiconductor layer 242i Semiconductor layer 242t Semiconductor layer 242u Semiconductor layer 244a Electrode 244b Electrode 247c Opening 247c Opening 247c Opening 247c
383b Ec
383c Ec

Claims (9)

1. A light source, an optical resonance plate, and a liquid crystal element;
   The light source and the liquid crystal element overlap each other through the optical resonance plate,
   The light source has a function of emitting first light having a first wavelength range;
   The optical resonance plate is a display device having a function of extracting second light having a second wavelength region from the first light and causing the second light to enter the liquid crystal element.
2. A light source, an optical resonance plate, and a liquid crystal element;
   The light source and the liquid crystal element overlap each other through the optical resonance plate,
   The light source has a function of emitting first light having a first wavelength range;
   The optical resonance plate is
   The second light having the second wavelength range, the third light having the third wavelength range, and the fourth light having the fourth wavelength range are extracted from the first light, and the second light is extracted. A display device having a function of causing the fourth light to enter the liquid crystal element.
3. In claim 2,
   The second light is light having a red wavelength range,
   The third light is light having a green wavelength range,
   The display device, wherein the fourth light is light having a blue wavelength range.
4. In claim 2 or claim 3,
   A display device, wherein a center wavelength of the second light is 610 nm or more and 750 nm or less.
5. In claim 2 or claim 3,
   A display device, wherein a center wavelength of the third light is not less than 500 nm and not more than 560 nm.
6. In claim 2 or claim 3,
   A display device, wherein a center wavelength of the fourth light is not less than 435 nm and not more than 480 nm.
7. In any one of Claims 1 thru | or 3,
   The display device, wherein the color temperature of the first light is 3000K or more and 12000K or less.
8. In any one of Claims 1 thru | or 3,
   The liquid crystal element is a display device which is a horizontal electric field type liquid crystal element.
9. A display device according to any one of claims 1 to 3,
   An electronic device having an antenna, a battery, a housing, a speaker, a microphone, an operation switch, or an operation button.

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